LXR linux/arch/xtensa/include/asm/cacheasm.h

   1/*
   2 * include/asm-xtensa/cacheasm.h
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 2006 Tensilica Inc.
   9 */
  10
  11#include <asm/cache.h>
  12#include <asm/asmmacro.h>
  13#include <linux/stringify.h>
  14
  15/*
  16 * Define cache functions as macros here so that they can be used
  17 * by the kernel and boot loader. We should consider moving them to a
  18 * library that can be linked by both.
  19 *
  20 * Locking
  21 *
  22 *   ___unlock_dcache_all
  23 *   ___unlock_icache_all
  24 *
  25 * Flush and invaldating
  26 *
  27 *   ___flush_invalidate_dcache_{all|range|page}
  28 *   ___flush_dcache_{all|range|page}
  29 *   ___invalidate_dcache_{all|range|page}
  30 *   ___invalidate_icache_{all|range|page}
  31 *
  32 */
  33
  34        .macro  __loop_cache_all ar at insn size line_width
  35
  36        movi    \ar, 0
  37
  38        __loopi \ar, \at, \size, (4 << (\line_width))
  39        \insn   \ar, 0 << (\line_width)
  40        \insn   \ar, 1 << (\line_width)
  41        \insn   \ar, 2 << (\line_width)
  42        \insn   \ar, 3 << (\line_width)
  43        __endla \ar, \at, 4 << (\line_width)
  44
  45        .endm
  46
  47
  48        .macro  __loop_cache_range ar as at insn line_width
  49
  50        extui   \at, \ar, 0, \line_width
  51        add     \as, \as, \at
  52
  53        __loops \ar, \as, \at, \line_width
  54        \insn   \ar, 0
  55        __endla \ar, \at, (1 << (\line_width))
  56
  57        .endm
  58
  59
  60        .macro  __loop_cache_page ar at insn line_width
  61
  62        __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
  63        \insn   \ar, 0 << (\line_width)
  64        \insn   \ar, 1 << (\line_width)
  65        \insn   \ar, 2 << (\line_width)
  66        \insn   \ar, 3 << (\line_width)
  67        __endla \ar, \at, 4 << (\line_width)
  68
  69        .endm
  70
  71
  72#if XCHAL_DCACHE_LINE_LOCKABLE
  73
  74        .macro  ___unlock_dcache_all ar at
  75
  76        __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
  77
  78        .endm
  79
  80#endif
  81
  82#if XCHAL_ICACHE_LINE_LOCKABLE
  83
  84        .macro  ___unlock_icache_all ar at
  85
  86        __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
  87
  88        .endm
  89#endif
  90
  91        .macro  ___flush_invalidate_dcache_all ar at
  92
  93        __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
  94
  95        .endm
  96
  97
  98        .macro  ___flush_dcache_all ar at
  99
 100        __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
 101
 102        .endm
 103
 104
 105        .macro  ___invalidate_dcache_all ar at
 106
 107        __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
 108                         XCHAL_DCACHE_LINEWIDTH
 109
 110        .endm
 111
 112
 113        .macro  ___invalidate_icache_all ar at
 114
 115        __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
 116                         XCHAL_ICACHE_LINEWIDTH
 117
 118        .endm
 119
 120
 121
 122        .macro  ___flush_invalidate_dcache_range ar as at
 123
 124        __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
 125
 126        .endm
 127
 128
 129        .macro  ___flush_dcache_range ar as at
 130
 131        __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
 132
 133        .endm
 134
 135
 136        .macro  ___invalidate_dcache_range ar as at
 137
 138        __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
 139
 140        .endm
 141
 142
 143        .macro  ___invalidate_icache_range ar as at
 144
 145        __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
 146
 147        .endm
 148
 149
 150
 151        .macro  ___flush_invalidate_dcache_page ar as
 152
 153        __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
 154
 155        .endm
 156
 157
 158        .macro ___flush_dcache_page ar as
 159
 160        __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
 161
 162        .endm
 163
 164
 165        .macro  ___invalidate_dcache_page ar as
 166
 167        __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
 168
 169        .endm
 170
 171
 172        .macro  ___invalidate_icache_page ar as
 173
 174        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
 175
 176        .endm
 177