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21#include <linux/pci.h>
22#include <linux/interrupt.h>
23#include <linux/ata.h>
24#include <linux/delay.h>
25#include <linux/hdreg.h>
26#include <linux/uaccess.h>
27#include <linux/random.h>
28#include <linux/smp.h>
29#include <linux/compat.h>
30#include <linux/fs.h>
31#include <linux/module.h>
32#include <linux/genhd.h>
33#include <linux/blkdev.h>
34#include <linux/bio.h>
35#include <linux/dma-mapping.h>
36#include <linux/idr.h>
37#include <linux/kthread.h>
38#include <../drivers/ata/ahci.h>
39#include <linux/export.h>
40#include <linux/debugfs.h>
41#include "mtip32xx.h"
42
43#define HW_CMD_SLOT_SZ (MTIP_MAX_COMMAND_SLOTS * 32)
44#define HW_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (MTIP_MAX_SG * 16))
45#define HW_CMD_TBL_AR_SZ (HW_CMD_TBL_SZ * MTIP_MAX_COMMAND_SLOTS)
46#define HW_PORT_PRIV_DMA_SZ \
47 (HW_CMD_SLOT_SZ + HW_CMD_TBL_AR_SZ + AHCI_RX_FIS_SZ)
48
49#define HOST_CAP_NZDMA (1 << 19)
50#define HOST_HSORG 0xFC
51#define HSORG_DISABLE_SLOTGRP_INTR (1<<24)
52#define HSORG_DISABLE_SLOTGRP_PXIS (1<<16)
53#define HSORG_HWREV 0xFF00
54#define HSORG_STYLE 0x8
55#define HSORG_SLOTGROUPS 0x7
56
57#define PORT_COMMAND_ISSUE 0x38
58#define PORT_SDBV 0x7C
59
60#define PORT_OFFSET 0x100
61#define PORT_MEM_SIZE 0x80
62
63#define PORT_IRQ_ERR \
64 (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | PORT_IRQ_CONNECT | \
65 PORT_IRQ_PHYRDY | PORT_IRQ_UNK_FIS | PORT_IRQ_BAD_PMP | \
66 PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_NONFATAL | \
67 PORT_IRQ_OVERFLOW)
68#define PORT_IRQ_LEGACY \
69 (PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
70#define PORT_IRQ_HANDLED \
71 (PORT_IRQ_SDB_FIS | PORT_IRQ_LEGACY | \
72 PORT_IRQ_TF_ERR | PORT_IRQ_IF_ERR | \
73 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)
74#define DEF_PORT_IRQ \
75 (PORT_IRQ_ERR | PORT_IRQ_LEGACY | PORT_IRQ_SDB_FIS)
76
77
78#define MTIP_PRODUCT_UNKNOWN 0x00
79#define MTIP_PRODUCT_ASICFPGA 0x11
80
81
82static int instance;
83
84struct list_head online_list;
85struct list_head removing_list;
86spinlock_t dev_lock;
87
88
89
90
91
92static int mtip_major;
93static struct dentry *dfs_parent;
94static struct dentry *dfs_device_status;
95
96static u32 cpu_use[NR_CPUS];
97
98static DEFINE_SPINLOCK(rssd_index_lock);
99static DEFINE_IDA(rssd_index_ida);
100
101static int mtip_block_initialize(struct driver_data *dd);
102
103#ifdef CONFIG_COMPAT
104struct mtip_compat_ide_task_request_s {
105 __u8 io_ports[8];
106 __u8 hob_ports[8];
107 ide_reg_valid_t out_flags;
108 ide_reg_valid_t in_flags;
109 int data_phase;
110 int req_cmd;
111 compat_ulong_t out_size;
112 compat_ulong_t in_size;
113};
114#endif
115
116
117
118
119
120
121
122
123
124
125
126static bool mtip_check_surprise_removal(struct pci_dev *pdev)
127{
128 u16 vendor_id = 0;
129
130
131 pci_read_config_word(pdev, 0x00, &vendor_id);
132 if (vendor_id == 0xFFFF)
133 return true;
134
135 return false;
136}
137
138
139
140
141
142
143
144
145
146
147
148static void mtip_command_cleanup(struct driver_data *dd)
149{
150 int group = 0, commandslot = 0, commandindex = 0;
151 struct mtip_cmd *command;
152 struct mtip_port *port = dd->port;
153 static int in_progress;
154
155 if (in_progress)
156 return;
157
158 in_progress = 1;
159
160 for (group = 0; group < 4; group++) {
161 for (commandslot = 0; commandslot < 32; commandslot++) {
162 if (!(port->allocated[group] & (1 << commandslot)))
163 continue;
164
165 commandindex = group << 5 | commandslot;
166 command = &port->commands[commandindex];
167
168 if (atomic_read(&command->active)
169 && (command->async_callback)) {
170 command->async_callback(command->async_data,
171 -ENODEV);
172 command->async_callback = NULL;
173 command->async_data = NULL;
174 }
175
176 dma_unmap_sg(&port->dd->pdev->dev,
177 command->sg,
178 command->scatter_ents,
179 command->direction);
180 }
181 }
182
183 up(&port->cmd_slot);
184
185 set_bit(MTIP_DDF_CLEANUP_BIT, &dd->dd_flag);
186 in_progress = 0;
187}
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202static int get_slot(struct mtip_port *port)
203{
204 int slot, i;
205 unsigned int num_command_slots = port->dd->slot_groups * 32;
206
207
208
209
210
211
212
213
214
215
216 for (i = 0; i < 10; i++) {
217 slot = find_next_zero_bit(port->allocated,
218 num_command_slots, 1);
219 if ((slot < num_command_slots) &&
220 (!test_and_set_bit(slot, port->allocated)))
221 return slot;
222 }
223 dev_warn(&port->dd->pdev->dev, "Failed to get a tag.\n");
224
225 if (mtip_check_surprise_removal(port->dd->pdev)) {
226
227 mtip_command_cleanup(port->dd);
228 }
229 return -1;
230}
231
232
233
234
235
236
237
238
239
240
241static inline void release_slot(struct mtip_port *port, int tag)
242{
243 smp_mb__before_clear_bit();
244 clear_bit(tag, port->allocated);
245 smp_mb__after_clear_bit();
246}
247
248
249
250
251
252
253
254
255
256
257static int mtip_hba_reset(struct driver_data *dd)
258{
259 unsigned long timeout;
260
261
262 writel(HOST_RESET, dd->mmio + HOST_CTL);
263
264
265 readl(dd->mmio + HOST_CTL);
266
267
268 timeout = jiffies + msecs_to_jiffies(2000);
269 do {
270 mdelay(10);
271 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))
272 return -1;
273
274 } while ((readl(dd->mmio + HOST_CTL) & HOST_RESET)
275 && time_before(jiffies, timeout));
276
277 if (readl(dd->mmio + HOST_CTL) & HOST_RESET)
278 return -1;
279
280 return 0;
281}
282
283
284
285
286
287
288
289
290
291
292
293
294
295static inline void mtip_issue_ncq_command(struct mtip_port *port, int tag)
296{
297 int group = tag >> 5;
298
299 atomic_set(&port->commands[tag].active, 1);
300
301
302 spin_lock(&port->cmd_issue_lock[group]);
303 writel((1 << MTIP_TAG_BIT(tag)),
304 port->s_active[MTIP_TAG_INDEX(tag)]);
305 writel((1 << MTIP_TAG_BIT(tag)),
306 port->cmd_issue[MTIP_TAG_INDEX(tag)]);
307 spin_unlock(&port->cmd_issue_lock[group]);
308
309
310 port->commands[tag].comp_time = jiffies + msecs_to_jiffies(
311 MTIP_NCQ_COMMAND_TIMEOUT_MS);
312}
313
314
315
316
317
318
319
320
321
322
323static int mtip_enable_fis(struct mtip_port *port, int enable)
324{
325 u32 tmp;
326
327
328 tmp = readl(port->mmio + PORT_CMD);
329 if (enable)
330 writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
331 else
332 writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
333
334
335 readl(port->mmio + PORT_CMD);
336
337 return (((tmp & PORT_CMD_FIS_RX) == PORT_CMD_FIS_RX));
338}
339
340
341
342
343
344
345
346
347
348
349static int mtip_enable_engine(struct mtip_port *port, int enable)
350{
351 u32 tmp;
352
353
354 tmp = readl(port->mmio + PORT_CMD);
355 if (enable)
356 writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD);
357 else
358 writel(tmp & ~PORT_CMD_START, port->mmio + PORT_CMD);
359
360 readl(port->mmio + PORT_CMD);
361 return (((tmp & PORT_CMD_START) == PORT_CMD_START));
362}
363
364
365
366
367
368
369
370static inline void mtip_start_port(struct mtip_port *port)
371{
372
373 mtip_enable_fis(port, 1);
374
375
376 mtip_enable_engine(port, 1);
377}
378
379
380
381
382
383
384
385
386
387
388static inline void mtip_deinit_port(struct mtip_port *port)
389{
390
391 writel(0, port->mmio + PORT_IRQ_MASK);
392
393
394 mtip_enable_engine(port, 0);
395
396
397 mtip_enable_fis(port, 0);
398}
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413static void mtip_init_port(struct mtip_port *port)
414{
415 int i;
416 mtip_deinit_port(port);
417
418
419 if (readl(port->dd->mmio + HOST_CAP) & HOST_CAP_64) {
420 writel((port->command_list_dma >> 16) >> 16,
421 port->mmio + PORT_LST_ADDR_HI);
422 writel((port->rxfis_dma >> 16) >> 16,
423 port->mmio + PORT_FIS_ADDR_HI);
424 }
425
426 writel(port->command_list_dma & 0xFFFFFFFF,
427 port->mmio + PORT_LST_ADDR);
428 writel(port->rxfis_dma & 0xFFFFFFFF, port->mmio + PORT_FIS_ADDR);
429
430
431 writel(readl(port->mmio + PORT_SCR_ERR), port->mmio + PORT_SCR_ERR);
432
433
434 for (i = 0; i < port->dd->slot_groups; i++)
435 writel(0xFFFFFFFF, port->completed[i]);
436
437
438 writel(readl(port->mmio + PORT_IRQ_STAT), port->mmio + PORT_IRQ_STAT);
439
440
441 writel(readl(port->dd->mmio + HOST_IRQ_STAT),
442 port->dd->mmio + HOST_IRQ_STAT);
443
444
445 writel(DEF_PORT_IRQ, port->mmio + PORT_IRQ_MASK);
446}
447
448
449
450
451
452
453
454
455
456static void mtip_restart_port(struct mtip_port *port)
457{
458 unsigned long timeout;
459
460
461 mtip_enable_engine(port, 0);
462
463
464 timeout = jiffies + msecs_to_jiffies(500);
465 while ((readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON)
466 && time_before(jiffies, timeout))
467 ;
468
469 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
470 return;
471
472
473
474
475
476 if (readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON) {
477 dev_warn(&port->dd->pdev->dev,
478 "PxCMD.CR not clear, escalating reset\n");
479
480 if (mtip_hba_reset(port->dd))
481 dev_err(&port->dd->pdev->dev,
482 "HBA reset escalation failed.\n");
483
484
485 mdelay(30);
486 }
487
488 dev_warn(&port->dd->pdev->dev, "Issuing COM reset\n");
489
490
491 writel(readl(port->mmio + PORT_SCR_CTL) |
492 1, port->mmio + PORT_SCR_CTL);
493 readl(port->mmio + PORT_SCR_CTL);
494
495
496 timeout = jiffies + msecs_to_jiffies(1);
497 while (time_before(jiffies, timeout))
498 ;
499
500 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
501 return;
502
503
504 writel(readl(port->mmio + PORT_SCR_CTL) & ~1,
505 port->mmio + PORT_SCR_CTL);
506 readl(port->mmio + PORT_SCR_CTL);
507
508
509 timeout = jiffies + msecs_to_jiffies(500);
510 while (((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
511 && time_before(jiffies, timeout))
512 ;
513
514 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
515 return;
516
517 if ((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
518 dev_warn(&port->dd->pdev->dev,
519 "COM reset failed\n");
520
521 mtip_init_port(port);
522 mtip_start_port(port);
523
524}
525
526static int mtip_device_reset(struct driver_data *dd)
527{
528 int rv = 0;
529
530 if (mtip_check_surprise_removal(dd->pdev))
531 return 0;
532
533 if (mtip_hba_reset(dd) < 0)
534 rv = -EFAULT;
535
536 mdelay(1);
537 mtip_init_port(dd->port);
538 mtip_start_port(dd->port);
539
540
541 writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
542 dd->mmio + HOST_CTL);
543 return rv;
544}
545
546
547
548
549static void print_tags(struct driver_data *dd,
550 char *msg,
551 unsigned long *tagbits,
552 int cnt)
553{
554 unsigned char tagmap[128];
555 int group, tagmap_len = 0;
556
557 memset(tagmap, 0, sizeof(tagmap));
558 for (group = SLOTBITS_IN_LONGS; group > 0; group--)
559 tagmap_len = sprintf(tagmap + tagmap_len, "%016lX ",
560 tagbits[group-1]);
561 dev_warn(&dd->pdev->dev,
562 "%d command(s) %s: tagmap [%s]", cnt, msg, tagmap);
563}
564
565
566
567
568
569
570
571
572
573
574static void mtip_timeout_function(unsigned long int data)
575{
576 struct mtip_port *port = (struct mtip_port *) data;
577 struct host_to_dev_fis *fis;
578 struct mtip_cmd *command;
579 int tag, cmdto_cnt = 0;
580 unsigned int bit, group;
581 unsigned int num_command_slots;
582 unsigned long to, tagaccum[SLOTBITS_IN_LONGS];
583
584 if (unlikely(!port))
585 return;
586
587 if (test_bit(MTIP_DDF_RESUME_BIT, &port->dd->dd_flag)) {
588 mod_timer(&port->cmd_timer,
589 jiffies + msecs_to_jiffies(30000));
590 return;
591 }
592
593 memset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));
594 num_command_slots = port->dd->slot_groups * 32;
595
596 for (tag = 0; tag < num_command_slots; tag++) {
597
598
599
600
601 if (tag == MTIP_TAG_INTERNAL)
602 continue;
603
604 if (atomic_read(&port->commands[tag].active) &&
605 (time_after(jiffies, port->commands[tag].comp_time))) {
606 group = tag >> 5;
607 bit = tag & 0x1F;
608
609 command = &port->commands[tag];
610 fis = (struct host_to_dev_fis *) command->command;
611
612 set_bit(tag, tagaccum);
613 cmdto_cnt++;
614 if (cmdto_cnt == 1)
615 set_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
616
617
618
619
620
621
622 writel(1 << bit, port->completed[group]);
623
624
625 if (likely(command->async_callback))
626 command->async_callback(command->async_data,
627 -EIO);
628 command->async_callback = NULL;
629 command->comp_func = NULL;
630
631
632 dma_unmap_sg(&port->dd->pdev->dev,
633 command->sg,
634 command->scatter_ents,
635 command->direction);
636
637
638
639
640
641 atomic_set(&port->commands[tag].active, 0);
642 release_slot(port, tag);
643
644 up(&port->cmd_slot);
645 }
646 }
647
648 if (cmdto_cnt) {
649 print_tags(port->dd, "timed out", tagaccum, cmdto_cnt);
650 if (!test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {
651 mtip_device_reset(port->dd);
652 wake_up_interruptible(&port->svc_wait);
653 }
654 clear_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
655 }
656
657 if (port->ic_pause_timer) {
658 to = port->ic_pause_timer + msecs_to_jiffies(1000);
659 if (time_after(jiffies, to)) {
660 if (!test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {
661 port->ic_pause_timer = 0;
662 clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
663 clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
664 clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
665 wake_up_interruptible(&port->svc_wait);
666 }
667
668
669 }
670 }
671
672
673 mod_timer(&port->cmd_timer,
674 jiffies + msecs_to_jiffies(MTIP_TIMEOUT_CHECK_PERIOD));
675}
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695static void mtip_async_complete(struct mtip_port *port,
696 int tag,
697 void *data,
698 int status)
699{
700 struct mtip_cmd *command;
701 struct driver_data *dd = data;
702 int cb_status = status ? -EIO : 0;
703
704 if (unlikely(!dd) || unlikely(!port))
705 return;
706
707 command = &port->commands[tag];
708
709 if (unlikely(status == PORT_IRQ_TF_ERR)) {
710 dev_warn(&port->dd->pdev->dev,
711 "Command tag %d failed due to TFE\n", tag);
712 }
713
714
715 if (likely(command->async_callback))
716 command->async_callback(command->async_data, cb_status);
717
718 command->async_callback = NULL;
719 command->comp_func = NULL;
720
721
722 dma_unmap_sg(&dd->pdev->dev,
723 command->sg,
724 command->scatter_ents,
725 command->direction);
726
727
728 atomic_set(&port->commands[tag].active, 0);
729 release_slot(port, tag);
730
731 if (unlikely(command->unaligned))
732 up(&port->cmd_slot_unal);
733 else
734 up(&port->cmd_slot);
735}
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752static void mtip_completion(struct mtip_port *port,
753 int tag,
754 void *data,
755 int status)
756{
757 struct mtip_cmd *command = &port->commands[tag];
758 struct completion *waiting = data;
759 if (unlikely(status == PORT_IRQ_TF_ERR))
760 dev_warn(&port->dd->pdev->dev,
761 "Internal command %d completed with TFE\n", tag);
762
763 command->async_callback = NULL;
764 command->comp_func = NULL;
765
766 complete(waiting);
767}
768
769static void mtip_null_completion(struct mtip_port *port,
770 int tag,
771 void *data,
772 int status)
773{
774 return;
775}
776
777static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
778 dma_addr_t buffer_dma, unsigned int sectors);
779static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
780 struct smart_attr *attrib);
781
782
783
784
785
786
787
788
789static void mtip_handle_tfe(struct driver_data *dd)
790{
791 int group, tag, bit, reissue, rv;
792 struct mtip_port *port;
793 struct mtip_cmd *cmd;
794 u32 completed;
795 struct host_to_dev_fis *fis;
796 unsigned long tagaccum[SLOTBITS_IN_LONGS];
797 unsigned int cmd_cnt = 0;
798 unsigned char *buf;
799 char *fail_reason = NULL;
800 int fail_all_ncq_write = 0, fail_all_ncq_cmds = 0;
801
802 dev_warn(&dd->pdev->dev, "Taskfile error\n");
803
804 port = dd->port;
805
806
807 del_timer(&port->cmd_timer);
808 set_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
809
810 if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags) &&
811 test_bit(MTIP_TAG_INTERNAL, port->allocated)) {
812 cmd = &port->commands[MTIP_TAG_INTERNAL];
813 dbg_printk(MTIP_DRV_NAME " TFE for the internal command\n");
814
815 atomic_inc(&cmd->active);
816 if (cmd->comp_data && cmd->comp_func) {
817 cmd->comp_func(port, MTIP_TAG_INTERNAL,
818 cmd->comp_data, PORT_IRQ_TF_ERR);
819 }
820 goto handle_tfe_exit;
821 }
822
823
824 memset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));
825
826
827 for (group = 0; group < dd->slot_groups; group++) {
828 completed = readl(port->completed[group]);
829
830
831 writel(completed, port->completed[group]);
832
833
834 for (bit = 0; bit < 32 && completed; bit++) {
835 if (!(completed & (1<<bit)))
836 continue;
837 tag = (group << 5) + bit;
838
839
840 if (tag == MTIP_TAG_INTERNAL)
841 continue;
842
843 cmd = &port->commands[tag];
844 if (likely(cmd->comp_func)) {
845 set_bit(tag, tagaccum);
846 cmd_cnt++;
847 atomic_set(&cmd->active, 0);
848 cmd->comp_func(port,
849 tag,
850 cmd->comp_data,
851 0);
852 } else {
853 dev_err(&port->dd->pdev->dev,
854 "Missing completion func for tag %d",
855 tag);
856 if (mtip_check_surprise_removal(dd->pdev)) {
857 mtip_command_cleanup(dd);
858
859 return;
860 }
861 }
862 }
863 }
864
865 print_tags(dd, "completed (TFE)", tagaccum, cmd_cnt);
866
867
868 mdelay(20);
869 mtip_restart_port(port);
870
871
872 rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
873 dd->port->log_buf,
874 dd->port->log_buf_dma, 1);
875 if (rv) {
876 dev_warn(&dd->pdev->dev,
877 "Error in READ LOG EXT (10h) command\n");
878
879 } else {
880 buf = (unsigned char *)dd->port->log_buf;
881 if (buf[259] & 0x1) {
882 dev_info(&dd->pdev->dev,
883 "Write protect bit is set.\n");
884 set_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag);
885 fail_all_ncq_write = 1;
886 fail_reason = "write protect";
887 }
888 if (buf[288] == 0xF7) {
889 dev_info(&dd->pdev->dev,
890 "Exceeded Tmax, drive in thermal shutdown.\n");
891 set_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag);
892 fail_all_ncq_cmds = 1;
893 fail_reason = "thermal shutdown";
894 }
895 if (buf[288] == 0xBF) {
896 dev_info(&dd->pdev->dev,
897 "Drive indicates rebuild has failed.\n");
898 fail_all_ncq_cmds = 1;
899 fail_reason = "rebuild failed";
900 }
901 }
902
903
904 memset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));
905
906
907 for (group = 0; group < dd->slot_groups; group++) {
908 for (bit = 0; bit < 32; bit++) {
909 reissue = 1;
910 tag = (group << 5) + bit;
911 cmd = &port->commands[tag];
912
913
914 if (atomic_read(&cmd->active) == 0)
915 continue;
916
917 fis = (struct host_to_dev_fis *)cmd->command;
918
919
920 if (tag == MTIP_TAG_INTERNAL ||
921 fis->command == ATA_CMD_SET_FEATURES)
922 reissue = 0;
923 else {
924 if (fail_all_ncq_cmds ||
925 (fail_all_ncq_write &&
926 fis->command == ATA_CMD_FPDMA_WRITE)) {
927 dev_warn(&dd->pdev->dev,
928 " Fail: %s w/tag %d [%s].\n",
929 fis->command == ATA_CMD_FPDMA_WRITE ?
930 "write" : "read",
931 tag,
932 fail_reason != NULL ?
933 fail_reason : "unknown");
934 atomic_set(&cmd->active, 0);
935 if (cmd->comp_func) {
936 cmd->comp_func(port, tag,
937 cmd->comp_data,
938 -ENODATA);
939 }
940 continue;
941 }
942 }
943
944
945
946
947
948 if (reissue && (cmd->retries-- > 0)) {
949
950 set_bit(tag, tagaccum);
951
952
953 mtip_issue_ncq_command(port, tag);
954
955 continue;
956 }
957
958
959 dev_warn(&port->dd->pdev->dev,
960 "retiring tag %d\n", tag);
961 atomic_set(&cmd->active, 0);
962
963 if (cmd->comp_func)
964 cmd->comp_func(
965 port,
966 tag,
967 cmd->comp_data,
968 PORT_IRQ_TF_ERR);
969 else
970 dev_warn(&port->dd->pdev->dev,
971 "Bad completion for tag %d\n",
972 tag);
973 }
974 }
975 print_tags(dd, "reissued (TFE)", tagaccum, cmd_cnt);
976
977handle_tfe_exit:
978
979 clear_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
980 wake_up_interruptible(&port->svc_wait);
981
982 mod_timer(&port->cmd_timer,
983 jiffies + msecs_to_jiffies(MTIP_TIMEOUT_CHECK_PERIOD));
984}
985
986
987
988
989static inline void mtip_workq_sdbfx(struct mtip_port *port, int group,
990 u32 completed)
991{
992 struct driver_data *dd = port->dd;
993 int tag, bit;
994 struct mtip_cmd *command;
995
996 if (!completed) {
997 WARN_ON_ONCE(!completed);
998 return;
999 }
1000
1001 writel(completed, port->completed[group]);
1002
1003
1004 for (bit = 0; (bit < 32) && completed; bit++) {
1005 if (completed & 0x01) {
1006 tag = (group << 5) | bit;
1007
1008
1009 if (unlikely(tag == MTIP_TAG_INTERNAL))
1010 continue;
1011
1012 command = &port->commands[tag];
1013
1014 if (likely(command->comp_func)) {
1015 command->comp_func(
1016 port,
1017 tag,
1018 command->comp_data,
1019 0);
1020 } else {
1021 dev_warn(&dd->pdev->dev,
1022 "Null completion "
1023 "for tag %d",
1024 tag);
1025
1026 if (mtip_check_surprise_removal(
1027 dd->pdev)) {
1028 mtip_command_cleanup(dd);
1029 return;
1030 }
1031 }
1032 }
1033 completed >>= 1;
1034 }
1035
1036
1037 if (atomic_dec_return(&dd->irq_workers_active) == 0)
1038 writel(0xffffffff, dd->mmio + HOST_IRQ_STAT);
1039}
1040
1041
1042
1043
1044static inline void mtip_process_legacy(struct driver_data *dd, u32 port_stat)
1045{
1046 struct mtip_port *port = dd->port;
1047 struct mtip_cmd *cmd = &port->commands[MTIP_TAG_INTERNAL];
1048
1049 if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags) &&
1050 (cmd != NULL) && !(readl(port->cmd_issue[MTIP_TAG_INTERNAL])
1051 & (1 << MTIP_TAG_INTERNAL))) {
1052 if (cmd->comp_func) {
1053 cmd->comp_func(port,
1054 MTIP_TAG_INTERNAL,
1055 cmd->comp_data,
1056 0);
1057 return;
1058 }
1059 }
1060
1061 return;
1062}
1063
1064
1065
1066
1067static inline void mtip_process_errors(struct driver_data *dd, u32 port_stat)
1068{
1069 if (likely(port_stat & (PORT_IRQ_TF_ERR | PORT_IRQ_IF_ERR)))
1070 mtip_handle_tfe(dd);
1071
1072 if (unlikely(port_stat & PORT_IRQ_CONNECT)) {
1073 dev_warn(&dd->pdev->dev,
1074 "Clearing PxSERR.DIAG.x\n");
1075 writel((1 << 26), dd->port->mmio + PORT_SCR_ERR);
1076 }
1077
1078 if (unlikely(port_stat & PORT_IRQ_PHYRDY)) {
1079 dev_warn(&dd->pdev->dev,
1080 "Clearing PxSERR.DIAG.n\n");
1081 writel((1 << 16), dd->port->mmio + PORT_SCR_ERR);
1082 }
1083
1084 if (unlikely(port_stat & ~PORT_IRQ_HANDLED)) {
1085 dev_warn(&dd->pdev->dev,
1086 "Port stat errors %x unhandled\n",
1087 (port_stat & ~PORT_IRQ_HANDLED));
1088 }
1089}
1090
1091static inline irqreturn_t mtip_handle_irq(struct driver_data *data)
1092{
1093 struct driver_data *dd = (struct driver_data *) data;
1094 struct mtip_port *port = dd->port;
1095 u32 hba_stat, port_stat;
1096 int rv = IRQ_NONE;
1097 int do_irq_enable = 1, i, workers;
1098 struct mtip_work *twork;
1099
1100 hba_stat = readl(dd->mmio + HOST_IRQ_STAT);
1101 if (hba_stat) {
1102 rv = IRQ_HANDLED;
1103
1104
1105 port_stat = readl(port->mmio + PORT_IRQ_STAT);
1106 writel(port_stat, port->mmio + PORT_IRQ_STAT);
1107
1108
1109 if (likely(port_stat & PORT_IRQ_SDB_FIS)) {
1110 do_irq_enable = 0;
1111 WARN_ON_ONCE(atomic_read(&dd->irq_workers_active) != 0);
1112
1113
1114 for (i = 0, workers = 0; i < MTIP_MAX_SLOT_GROUPS;
1115 i++) {
1116 twork = &dd->work[i];
1117 twork->completed = readl(port->completed[i]);
1118 if (twork->completed)
1119 workers++;
1120 }
1121
1122 atomic_set(&dd->irq_workers_active, workers);
1123 if (workers) {
1124 for (i = 1; i < MTIP_MAX_SLOT_GROUPS; i++) {
1125 twork = &dd->work[i];
1126 if (twork->completed)
1127 queue_work_on(
1128 twork->cpu_binding,
1129 dd->isr_workq,
1130 &twork->work);
1131 }
1132
1133 if (likely(dd->work[0].completed))
1134 mtip_workq_sdbfx(port, 0,
1135 dd->work[0].completed);
1136
1137 } else {
1138
1139
1140
1141
1142 do_irq_enable = 1;
1143 }
1144 }
1145
1146 if (unlikely(port_stat & PORT_IRQ_ERR)) {
1147 if (unlikely(mtip_check_surprise_removal(dd->pdev))) {
1148 mtip_command_cleanup(dd);
1149
1150 return IRQ_HANDLED;
1151 }
1152 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
1153 &dd->dd_flag))
1154 return rv;
1155
1156 mtip_process_errors(dd, port_stat & PORT_IRQ_ERR);
1157 }
1158
1159 if (unlikely(port_stat & PORT_IRQ_LEGACY))
1160 mtip_process_legacy(dd, port_stat & PORT_IRQ_LEGACY);
1161 }
1162
1163
1164 if (unlikely(do_irq_enable))
1165 writel(hba_stat, dd->mmio + HOST_IRQ_STAT);
1166
1167 return rv;
1168}
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180static irqreturn_t mtip_irq_handler(int irq, void *instance)
1181{
1182 struct driver_data *dd = instance;
1183
1184 return mtip_handle_irq(dd);
1185}
1186
1187static void mtip_issue_non_ncq_command(struct mtip_port *port, int tag)
1188{
1189 atomic_set(&port->commands[tag].active, 1);
1190 writel(1 << MTIP_TAG_BIT(tag),
1191 port->cmd_issue[MTIP_TAG_INDEX(tag)]);
1192}
1193
1194static bool mtip_pause_ncq(struct mtip_port *port,
1195 struct host_to_dev_fis *fis)
1196{
1197 struct host_to_dev_fis *reply;
1198 unsigned long task_file_data;
1199
1200 reply = port->rxfis + RX_FIS_D2H_REG;
1201 task_file_data = readl(port->mmio+PORT_TFDATA);
1202
1203 if (fis->command == ATA_CMD_SEC_ERASE_UNIT)
1204 clear_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1205
1206 if ((task_file_data & 1))
1207 return false;
1208
1209 if (fis->command == ATA_CMD_SEC_ERASE_PREP) {
1210 set_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
1211 set_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1212 port->ic_pause_timer = jiffies;
1213 return true;
1214 } else if ((fis->command == ATA_CMD_DOWNLOAD_MICRO) &&
1215 (fis->features == 0x03)) {
1216 set_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
1217 port->ic_pause_timer = jiffies;
1218 return true;
1219 } else if ((fis->command == ATA_CMD_SEC_ERASE_UNIT) ||
1220 ((fis->command == 0xFC) &&
1221 (fis->features == 0x27 || fis->features == 0x72 ||
1222 fis->features == 0x62 || fis->features == 0x26))) {
1223
1224 mtip_restart_port(port);
1225 return false;
1226 }
1227
1228 return false;
1229}
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241static int mtip_quiesce_io(struct mtip_port *port, unsigned long timeout)
1242{
1243 unsigned long to;
1244 unsigned int n;
1245 unsigned int active = 1;
1246
1247 to = jiffies + msecs_to_jiffies(timeout);
1248 do {
1249 if (test_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags) &&
1250 test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
1251 msleep(20);
1252 continue;
1253 }
1254 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
1255 return -EFAULT;
1256
1257
1258
1259
1260 active = readl(port->s_active[0]) & 0xFFFFFFFE;
1261 for (n = 1; n < port->dd->slot_groups; n++)
1262 active |= readl(port->s_active[n]);
1263
1264 if (!active)
1265 break;
1266
1267 msleep(20);
1268 } while (time_before(jiffies, to));
1269
1270 return active ? -EBUSY : 0;
1271}
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291static int mtip_exec_internal_command(struct mtip_port *port,
1292 struct host_to_dev_fis *fis,
1293 int fis_len,
1294 dma_addr_t buffer,
1295 int buf_len,
1296 u32 opts,
1297 gfp_t atomic,
1298 unsigned long timeout)
1299{
1300 struct mtip_cmd_sg *command_sg;
1301 DECLARE_COMPLETION_ONSTACK(wait);
1302 int rv = 0, ready2go = 1;
1303 struct mtip_cmd *int_cmd = &port->commands[MTIP_TAG_INTERNAL];
1304 unsigned long to;
1305 struct driver_data *dd = port->dd;
1306
1307
1308 if (buffer & 0x00000007) {
1309 dev_err(&dd->pdev->dev, "SG buffer is not 8 byte aligned\n");
1310 return -EFAULT;
1311 }
1312
1313 to = jiffies + msecs_to_jiffies(timeout);
1314 do {
1315 ready2go = !test_and_set_bit(MTIP_TAG_INTERNAL,
1316 port->allocated);
1317 if (ready2go)
1318 break;
1319 mdelay(100);
1320 } while (time_before(jiffies, to));
1321 if (!ready2go) {
1322 dev_warn(&dd->pdev->dev,
1323 "Internal cmd active. new cmd [%02X]\n", fis->command);
1324 return -EBUSY;
1325 }
1326 set_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1327 port->ic_pause_timer = 0;
1328
1329 clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
1330 clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
1331
1332 if (atomic == GFP_KERNEL) {
1333 if (fis->command != ATA_CMD_STANDBYNOW1) {
1334
1335 if (mtip_quiesce_io(port, 5000) < 0) {
1336 dev_warn(&dd->pdev->dev,
1337 "Failed to quiesce IO\n");
1338 release_slot(port, MTIP_TAG_INTERNAL);
1339 clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1340 wake_up_interruptible(&port->svc_wait);
1341 return -EBUSY;
1342 }
1343 }
1344
1345
1346 int_cmd->comp_data = &wait;
1347 int_cmd->comp_func = mtip_completion;
1348
1349 } else {
1350
1351 int_cmd->comp_data = NULL;
1352 int_cmd->comp_func = mtip_null_completion;
1353 }
1354
1355
1356 memcpy(int_cmd->command, fis, fis_len*4);
1357
1358
1359 int_cmd->command_header->opts =
1360 __force_bit2int cpu_to_le32(opts | fis_len);
1361 if (buf_len) {
1362 command_sg = int_cmd->command + AHCI_CMD_TBL_HDR_SZ;
1363
1364 command_sg->info =
1365 __force_bit2int cpu_to_le32((buf_len-1) & 0x3FFFFF);
1366 command_sg->dba =
1367 __force_bit2int cpu_to_le32(buffer & 0xFFFFFFFF);
1368 command_sg->dba_upper =
1369 __force_bit2int cpu_to_le32((buffer >> 16) >> 16);
1370
1371 int_cmd->command_header->opts |=
1372 __force_bit2int cpu_to_le32((1 << 16));
1373 }
1374
1375
1376 int_cmd->command_header->byte_count = 0;
1377
1378
1379 mtip_issue_non_ncq_command(port, MTIP_TAG_INTERNAL);
1380
1381 if (atomic == GFP_KERNEL) {
1382
1383 if (wait_for_completion_interruptible_timeout(
1384 &wait,
1385 msecs_to_jiffies(timeout)) <= 0) {
1386 if (rv == -ERESTARTSYS) {
1387 dev_err(&dd->pdev->dev,
1388 "Internal command [%02X] was interrupted after %lu ms\n",
1389 fis->command, timeout);
1390 rv = -EINTR;
1391 goto exec_ic_exit;
1392 } else if (rv == 0)
1393 dev_err(&dd->pdev->dev,
1394 "Internal command did not complete [%02X] within timeout of %lu ms\n",
1395 fis->command, timeout);
1396 else
1397 dev_err(&dd->pdev->dev,
1398 "Internal command [%02X] wait returned code [%d] after %lu ms - unhandled\n",
1399 fis->command, rv, timeout);
1400
1401 if (mtip_check_surprise_removal(dd->pdev) ||
1402 test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
1403 &dd->dd_flag)) {
1404 dev_err(&dd->pdev->dev,
1405 "Internal command [%02X] wait returned due to SR\n",
1406 fis->command);
1407 rv = -ENXIO;
1408 goto exec_ic_exit;
1409 }
1410 mtip_device_reset(dd);
1411 rv = -EAGAIN;
1412 goto exec_ic_exit;
1413 }
1414 } else {
1415 u32 hba_stat, port_stat;
1416
1417
1418 timeout = jiffies + msecs_to_jiffies(timeout);
1419 while ((readl(port->cmd_issue[MTIP_TAG_INTERNAL])
1420 & (1 << MTIP_TAG_INTERNAL))
1421 && time_before(jiffies, timeout)) {
1422 if (mtip_check_surprise_removal(dd->pdev)) {
1423 rv = -ENXIO;
1424 goto exec_ic_exit;
1425 }
1426 if ((fis->command != ATA_CMD_STANDBYNOW1) &&
1427 test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
1428 &dd->dd_flag)) {
1429 rv = -ENXIO;
1430 goto exec_ic_exit;
1431 }
1432 port_stat = readl(port->mmio + PORT_IRQ_STAT);
1433 if (!port_stat)
1434 continue;
1435
1436 if (port_stat & PORT_IRQ_ERR) {
1437 dev_err(&dd->pdev->dev,
1438 "Internal command [%02X] failed\n",
1439 fis->command);
1440 mtip_device_reset(dd);
1441 rv = -EIO;
1442 goto exec_ic_exit;
1443 } else {
1444 writel(port_stat, port->mmio + PORT_IRQ_STAT);
1445 hba_stat = readl(dd->mmio + HOST_IRQ_STAT);
1446 if (hba_stat)
1447 writel(hba_stat,
1448 dd->mmio + HOST_IRQ_STAT);
1449 }
1450 break;
1451 }
1452 }
1453
1454 if (readl(port->cmd_issue[MTIP_TAG_INTERNAL])
1455 & (1 << MTIP_TAG_INTERNAL)) {
1456 rv = -ENXIO;
1457 if (!test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)) {
1458 mtip_device_reset(dd);
1459 rv = -EAGAIN;
1460 }
1461 }
1462exec_ic_exit:
1463
1464 atomic_set(&int_cmd->active, 0);
1465 release_slot(port, MTIP_TAG_INTERNAL);
1466 if (rv >= 0 && mtip_pause_ncq(port, fis)) {
1467
1468 return rv;
1469 }
1470 clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1471 wake_up_interruptible(&port->svc_wait);
1472
1473 return rv;
1474}
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489static inline void ata_swap_string(u16 *buf, unsigned int len)
1490{
1491 int i;
1492 for (i = 0; i < (len/2); i++)
1493 be16_to_cpus(&buf[i]);
1494}
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515static int mtip_get_identify(struct mtip_port *port, void __user *user_buffer)
1516{
1517 int rv = 0;
1518 struct host_to_dev_fis fis;
1519
1520 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
1521 return -EFAULT;
1522
1523
1524 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1525 fis.type = 0x27;
1526 fis.opts = 1 << 7;
1527 fis.command = ATA_CMD_ID_ATA;
1528
1529
1530 port->identify_valid = 0;
1531
1532
1533 memset(port->identify, 0, sizeof(u16) * ATA_ID_WORDS);
1534
1535
1536 if (mtip_exec_internal_command(port,
1537 &fis,
1538 5,
1539 port->identify_dma,
1540 sizeof(u16) * ATA_ID_WORDS,
1541 0,
1542 GFP_KERNEL,
1543 MTIP_INTERNAL_COMMAND_TIMEOUT_MS)
1544 < 0) {
1545 rv = -1;
1546 goto out;
1547 }
1548
1549
1550
1551
1552
1553
1554#ifdef __LITTLE_ENDIAN
1555 ata_swap_string(port->identify + 27, 40);
1556 ata_swap_string(port->identify + 23, 8);
1557 ata_swap_string(port->identify + 10, 20);
1558#else
1559 {
1560 int i;
1561 for (i = 0; i < ATA_ID_WORDS; i++)
1562 port->identify[i] = le16_to_cpu(port->identify[i]);
1563 }
1564#endif
1565
1566#ifdef MTIP_TRIM
1567
1568 if (port->identify[69] & (1 << 14) && port->identify[69] & (1 << 5))
1569 port->dd->trim_supp = true;
1570 else
1571#endif
1572 port->dd->trim_supp = false;
1573
1574
1575 port->identify_valid = 1;
1576
1577 if (user_buffer) {
1578 if (copy_to_user(
1579 user_buffer,
1580 port->identify,
1581 ATA_ID_WORDS * sizeof(u16))) {
1582 rv = -EFAULT;
1583 goto out;
1584 }
1585 }
1586
1587out:
1588 return rv;
1589}
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600static int mtip_standby_immediate(struct mtip_port *port)
1601{
1602 int rv;
1603 struct host_to_dev_fis fis;
1604 unsigned long start;
1605
1606
1607 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1608 fis.type = 0x27;
1609 fis.opts = 1 << 7;
1610 fis.command = ATA_CMD_STANDBYNOW1;
1611
1612 start = jiffies;
1613 rv = mtip_exec_internal_command(port,
1614 &fis,
1615 5,
1616 0,
1617 0,
1618 0,
1619 GFP_ATOMIC,
1620 15000);
1621 dbg_printk(MTIP_DRV_NAME "Time taken to complete standby cmd: %d ms\n",
1622 jiffies_to_msecs(jiffies - start));
1623 if (rv)
1624 dev_warn(&port->dd->pdev->dev,
1625 "STANDBY IMMEDIATE command failed.\n");
1626
1627 return rv;
1628}
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
1643 dma_addr_t buffer_dma, unsigned int sectors)
1644{
1645 struct host_to_dev_fis fis;
1646
1647 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1648 fis.type = 0x27;
1649 fis.opts = 1 << 7;
1650 fis.command = ATA_CMD_READ_LOG_EXT;
1651 fis.sect_count = sectors & 0xFF;
1652 fis.sect_cnt_ex = (sectors >> 8) & 0xFF;
1653 fis.lba_low = page;
1654 fis.lba_mid = 0;
1655 fis.device = ATA_DEVICE_OBS;
1656
1657 memset(buffer, 0, sectors * ATA_SECT_SIZE);
1658
1659 return mtip_exec_internal_command(port,
1660 &fis,
1661 5,
1662 buffer_dma,
1663 sectors * ATA_SECT_SIZE,
1664 0,
1665 GFP_ATOMIC,
1666 MTIP_INTERNAL_COMMAND_TIMEOUT_MS);
1667}
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679static int mtip_get_smart_data(struct mtip_port *port, u8 *buffer,
1680 dma_addr_t buffer_dma)
1681{
1682 struct host_to_dev_fis fis;
1683
1684 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1685 fis.type = 0x27;
1686 fis.opts = 1 << 7;
1687 fis.command = ATA_CMD_SMART;
1688 fis.features = 0xD0;
1689 fis.sect_count = 1;
1690 fis.lba_mid = 0x4F;
1691 fis.lba_hi = 0xC2;
1692 fis.device = ATA_DEVICE_OBS;
1693
1694 return mtip_exec_internal_command(port,
1695 &fis,
1696 5,
1697 buffer_dma,
1698 ATA_SECT_SIZE,
1699 0,
1700 GFP_ATOMIC,
1701 15000);
1702}
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
1716 struct smart_attr *attrib)
1717{
1718 int rv, i;
1719 struct smart_attr *pattr;
1720
1721 if (!attrib)
1722 return -EINVAL;
1723
1724 if (!port->identify_valid) {
1725 dev_warn(&port->dd->pdev->dev, "IDENTIFY DATA not valid\n");
1726 return -EPERM;
1727 }
1728 if (!(port->identify[82] & 0x1)) {
1729 dev_warn(&port->dd->pdev->dev, "SMART not supported\n");
1730 return -EPERM;
1731 }
1732 if (!(port->identify[85] & 0x1)) {
1733 dev_warn(&port->dd->pdev->dev, "SMART not enabled\n");
1734 return -EPERM;
1735 }
1736
1737 memset(port->smart_buf, 0, ATA_SECT_SIZE);
1738 rv = mtip_get_smart_data(port, port->smart_buf, port->smart_buf_dma);
1739 if (rv) {
1740 dev_warn(&port->dd->pdev->dev, "Failed to ge SMART data\n");
1741 return rv;
1742 }
1743
1744 pattr = (struct smart_attr *)(port->smart_buf + 2);
1745 for (i = 0; i < 29; i++, pattr++)
1746 if (pattr->attr_id == id) {
1747 memcpy(attrib, pattr, sizeof(struct smart_attr));
1748 break;
1749 }
1750
1751 if (i == 29) {
1752 dev_warn(&port->dd->pdev->dev,
1753 "Query for invalid SMART attribute ID\n");
1754 rv = -EINVAL;
1755 }
1756
1757 return rv;
1758}
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772static int mtip_send_trim(struct driver_data *dd, unsigned int lba,
1773 unsigned int len)
1774{
1775 int i, rv = 0;
1776 u64 tlba, tlen, sect_left;
1777 struct mtip_trim_entry *buf;
1778 dma_addr_t dma_addr;
1779 struct host_to_dev_fis fis;
1780
1781 if (!len || dd->trim_supp == false)
1782 return -EINVAL;
1783
1784
1785 WARN_ON(len > (MTIP_MAX_TRIM_ENTRY_LEN * MTIP_MAX_TRIM_ENTRIES));
1786
1787
1788 WARN_ON(len % 8 != 0);
1789
1790
1791 WARN_ON(sizeof(struct mtip_trim) > ATA_SECT_SIZE);
1792
1793
1794 buf = dmam_alloc_coherent(&dd->pdev->dev, ATA_SECT_SIZE, &dma_addr,
1795 GFP_KERNEL);
1796 if (!buf)
1797 return -ENOMEM;
1798 memset(buf, 0, ATA_SECT_SIZE);
1799
1800 for (i = 0, sect_left = len, tlba = lba;
1801 i < MTIP_MAX_TRIM_ENTRIES && sect_left;
1802 i++) {
1803 tlen = (sect_left >= MTIP_MAX_TRIM_ENTRY_LEN ?
1804 MTIP_MAX_TRIM_ENTRY_LEN :
1805 sect_left);
1806 buf[i].lba = __force_bit2int cpu_to_le32(tlba);
1807 buf[i].range = __force_bit2int cpu_to_le16(tlen);
1808 tlba += tlen;
1809 sect_left -= tlen;
1810 }
1811 WARN_ON(sect_left != 0);
1812
1813
1814 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1815 fis.type = 0x27;
1816 fis.opts = 1 << 7;
1817 fis.command = 0xfb;
1818 fis.features = 0x60;
1819 fis.sect_count = 1;
1820 fis.device = ATA_DEVICE_OBS;
1821
1822 if (mtip_exec_internal_command(dd->port,
1823 &fis,
1824 5,
1825 dma_addr,
1826 ATA_SECT_SIZE,
1827 0,
1828 GFP_KERNEL,
1829 MTIP_TRIM_TIMEOUT_MS) < 0)
1830 rv = -EIO;
1831
1832 dmam_free_coherent(&dd->pdev->dev, ATA_SECT_SIZE, buf, dma_addr);
1833 return rv;
1834}
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846static bool mtip_hw_get_capacity(struct driver_data *dd, sector_t *sectors)
1847{
1848 struct mtip_port *port = dd->port;
1849 u64 total, raw0, raw1, raw2, raw3;
1850 raw0 = port->identify[100];
1851 raw1 = port->identify[101];
1852 raw2 = port->identify[102];
1853 raw3 = port->identify[103];
1854 total = raw0 | raw1<<16 | raw2<<32 | raw3<<48;
1855 *sectors = total;
1856 return (bool) !!port->identify_valid;
1857}
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867static void mtip_dump_identify(struct mtip_port *port)
1868{
1869 sector_t sectors;
1870 unsigned short revid;
1871 char cbuf[42];
1872
1873 if (!port->identify_valid)
1874 return;
1875
1876 strlcpy(cbuf, (char *)(port->identify+10), 21);
1877 dev_info(&port->dd->pdev->dev,
1878 "Serial No.: %s\n", cbuf);
1879
1880 strlcpy(cbuf, (char *)(port->identify+23), 9);
1881 dev_info(&port->dd->pdev->dev,
1882 "Firmware Ver.: %s\n", cbuf);
1883
1884 strlcpy(cbuf, (char *)(port->identify+27), 41);
1885 dev_info(&port->dd->pdev->dev, "Model: %s\n", cbuf);
1886
1887 if (mtip_hw_get_capacity(port->dd, §ors))
1888 dev_info(&port->dd->pdev->dev,
1889 "Capacity: %llu sectors (%llu MB)\n",
1890 (u64)sectors,
1891 ((u64)sectors) * ATA_SECT_SIZE >> 20);
1892
1893 pci_read_config_word(port->dd->pdev, PCI_REVISION_ID, &revid);
1894 switch (revid & 0xFF) {
1895 case 0x1:
1896 strlcpy(cbuf, "A0", 3);
1897 break;
1898 case 0x3:
1899 strlcpy(cbuf, "A2", 3);
1900 break;
1901 default:
1902 strlcpy(cbuf, "?", 2);
1903 break;
1904 }
1905 dev_info(&port->dd->pdev->dev,
1906 "Card Type: %s\n", cbuf);
1907}
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918static inline void fill_command_sg(struct driver_data *dd,
1919 struct mtip_cmd *command,
1920 int nents)
1921{
1922 int n;
1923 unsigned int dma_len;
1924 struct mtip_cmd_sg *command_sg;
1925 struct scatterlist *sg = command->sg;
1926
1927 command_sg = command->command + AHCI_CMD_TBL_HDR_SZ;
1928
1929 for (n = 0; n < nents; n++) {
1930 dma_len = sg_dma_len(sg);
1931 if (dma_len > 0x400000)
1932 dev_err(&dd->pdev->dev,
1933 "DMA segment length truncated\n");
1934 command_sg->info = __force_bit2int
1935 cpu_to_le32((dma_len-1) & 0x3FFFFF);
1936 command_sg->dba = __force_bit2int
1937 cpu_to_le32(sg_dma_address(sg));
1938 command_sg->dba_upper = __force_bit2int
1939 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
1940 command_sg++;
1941 sg++;
1942 }
1943}
1944
1945
1946
1947
1948
1949
1950
1951static int exec_drive_task(struct mtip_port *port, u8 *command)
1952{
1953 struct host_to_dev_fis fis;
1954 struct host_to_dev_fis *reply = (port->rxfis + RX_FIS_D2H_REG);
1955
1956
1957 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1958 fis.type = 0x27;
1959 fis.opts = 1 << 7;
1960 fis.command = command[0];
1961 fis.features = command[1];
1962 fis.sect_count = command[2];
1963 fis.sector = command[3];
1964 fis.cyl_low = command[4];
1965 fis.cyl_hi = command[5];
1966 fis.device = command[6] & ~0x10;
1967
1968 dbg_printk(MTIP_DRV_NAME " %s: User Command: cmd %x, feat %x, nsect %x, sect %x, lcyl %x, hcyl %x, sel %x\n",
1969 __func__,
1970 command[0],
1971 command[1],
1972 command[2],
1973 command[3],
1974 command[4],
1975 command[5],
1976 command[6]);
1977
1978
1979 if (mtip_exec_internal_command(port,
1980 &fis,
1981 5,
1982 0,
1983 0,
1984 0,
1985 GFP_KERNEL,
1986 MTIP_IOCTL_COMMAND_TIMEOUT_MS) < 0) {
1987 return -1;
1988 }
1989
1990 command[0] = reply->command;
1991 command[1] = reply->features;
1992 command[4] = reply->cyl_low;
1993 command[5] = reply->cyl_hi;
1994
1995 dbg_printk(MTIP_DRV_NAME " %s: Completion Status: stat %x, err %x , cyl_lo %x cyl_hi %x\n",
1996 __func__,
1997 command[0],
1998 command[1],
1999 command[4],
2000 command[5]);
2001
2002 return 0;
2003}
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018static int exec_drive_command(struct mtip_port *port, u8 *command,
2019 void __user *user_buffer)
2020{
2021 struct host_to_dev_fis fis;
2022 struct host_to_dev_fis *reply;
2023 u8 *buf = NULL;
2024 dma_addr_t dma_addr = 0;
2025 int rv = 0, xfer_sz = command[3];
2026
2027 if (xfer_sz) {
2028 if (!user_buffer)
2029 return -EFAULT;
2030
2031 buf = dmam_alloc_coherent(&port->dd->pdev->dev,
2032 ATA_SECT_SIZE * xfer_sz,
2033 &dma_addr,
2034 GFP_KERNEL);
2035 if (!buf) {
2036 dev_err(&port->dd->pdev->dev,
2037 "Memory allocation failed (%d bytes)\n",
2038 ATA_SECT_SIZE * xfer_sz);
2039 return -ENOMEM;
2040 }
2041 memset(buf, 0, ATA_SECT_SIZE * xfer_sz);
2042 }
2043
2044
2045 memset(&fis, 0, sizeof(struct host_to_dev_fis));
2046 fis.type = 0x27;
2047 fis.opts = 1 << 7;
2048 fis.command = command[0];
2049 fis.features = command[2];
2050 fis.sect_count = command[3];
2051 if (fis.command == ATA_CMD_SMART) {
2052 fis.sector = command[1];
2053 fis.cyl_low = 0x4F;
2054 fis.cyl_hi = 0xC2;
2055 }
2056
2057 if (xfer_sz)
2058 reply = (port->rxfis + RX_FIS_PIO_SETUP);
2059 else
2060 reply = (port->rxfis + RX_FIS_D2H_REG);
2061
2062 dbg_printk(MTIP_DRV_NAME
2063 " %s: User Command: cmd %x, sect %x, "
2064 "feat %x, sectcnt %x\n",
2065 __func__,
2066 command[0],
2067 command[1],
2068 command[2],
2069 command[3]);
2070
2071
2072 if (mtip_exec_internal_command(port,
2073 &fis,
2074 5,
2075 (xfer_sz ? dma_addr : 0),
2076 (xfer_sz ? ATA_SECT_SIZE * xfer_sz : 0),
2077 0,
2078 GFP_KERNEL,
2079 MTIP_IOCTL_COMMAND_TIMEOUT_MS)
2080 < 0) {
2081 rv = -EFAULT;
2082 goto exit_drive_command;
2083 }
2084
2085
2086 command[0] = reply->command;
2087 command[1] = reply->features;
2088 command[2] = reply->sect_count;
2089
2090 dbg_printk(MTIP_DRV_NAME
2091 " %s: Completion Status: stat %x, "
2092 "err %x, nsect %x\n",
2093 __func__,
2094 command[0],
2095 command[1],
2096 command[2]);
2097
2098 if (xfer_sz) {
2099 if (copy_to_user(user_buffer,
2100 buf,
2101 ATA_SECT_SIZE * command[3])) {
2102 rv = -EFAULT;
2103 goto exit_drive_command;
2104 }
2105 }
2106exit_drive_command:
2107 if (buf)
2108 dmam_free_coherent(&port->dd->pdev->dev,
2109 ATA_SECT_SIZE * xfer_sz, buf, dma_addr);
2110 return rv;
2111}
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125static unsigned int implicit_sector(unsigned char command,
2126 unsigned char features)
2127{
2128 unsigned int rv = 0;
2129
2130
2131 switch (command) {
2132 case ATA_CMD_SEC_SET_PASS:
2133 case ATA_CMD_SEC_UNLOCK:
2134 case ATA_CMD_SEC_ERASE_PREP:
2135 case ATA_CMD_SEC_ERASE_UNIT:
2136 case ATA_CMD_SEC_FREEZE_LOCK:
2137 case ATA_CMD_SEC_DISABLE_PASS:
2138 case ATA_CMD_PMP_READ:
2139 case ATA_CMD_PMP_WRITE:
2140 rv = 1;
2141 break;
2142 case ATA_CMD_SET_MAX:
2143 if (features == ATA_SET_MAX_UNLOCK)
2144 rv = 1;
2145 break;
2146 case ATA_CMD_SMART:
2147 if ((features == ATA_SMART_READ_VALUES) ||
2148 (features == ATA_SMART_READ_THRESHOLDS))
2149 rv = 1;
2150 break;
2151 case ATA_CMD_CONF_OVERLAY:
2152 if ((features == ATA_DCO_IDENTIFY) ||
2153 (features == ATA_DCO_SET))
2154 rv = 1;
2155 break;
2156 }
2157 return rv;
2158}
2159static void mtip_set_timeout(struct driver_data *dd,
2160 struct host_to_dev_fis *fis,
2161 unsigned int *timeout, u8 erasemode)
2162{
2163 switch (fis->command) {
2164 case ATA_CMD_DOWNLOAD_MICRO:
2165 *timeout = 120000;
2166 break;
2167 case ATA_CMD_SEC_ERASE_UNIT:
2168 case 0xFC:
2169 if (erasemode)
2170 *timeout = ((*(dd->port->identify + 90) * 2) * 60000);
2171 else
2172 *timeout = ((*(dd->port->identify + 89) * 2) * 60000);
2173 break;
2174 case ATA_CMD_STANDBYNOW1:
2175 *timeout = 120000;
2176 break;
2177 case 0xF7:
2178 case 0xFA:
2179 *timeout = 60000;
2180 break;
2181 case ATA_CMD_SMART:
2182 *timeout = 15000;
2183 break;
2184 default:
2185 *timeout = MTIP_IOCTL_COMMAND_TIMEOUT_MS;
2186 break;
2187 }
2188}
2189
2190
2191
2192
2193
2194static int exec_drive_taskfile(struct driver_data *dd,
2195 void __user *buf,
2196 ide_task_request_t *req_task,
2197 int outtotal)
2198{
2199 struct host_to_dev_fis fis;
2200 struct host_to_dev_fis *reply;
2201 u8 *outbuf = NULL;
2202 u8 *inbuf = NULL;
2203 dma_addr_t outbuf_dma = 0;
2204 dma_addr_t inbuf_dma = 0;
2205 dma_addr_t dma_buffer = 0;
2206 int err = 0;
2207 unsigned int taskin = 0;
2208 unsigned int taskout = 0;
2209 u8 nsect = 0;
2210 unsigned int timeout;
2211 unsigned int force_single_sector;
2212 unsigned int transfer_size;
2213 unsigned long task_file_data;
2214 int intotal = outtotal + req_task->out_size;
2215 int erasemode = 0;
2216
2217 taskout = req_task->out_size;
2218 taskin = req_task->in_size;
2219
2220 if (taskin > 130560 || taskout > 130560) {
2221 err = -EINVAL;
2222 goto abort;
2223 }
2224
2225 if (taskout) {
2226 outbuf = kzalloc(taskout, GFP_KERNEL);
2227 if (outbuf == NULL) {
2228 err = -ENOMEM;
2229 goto abort;
2230 }
2231 if (copy_from_user(outbuf, buf + outtotal, taskout)) {
2232 err = -EFAULT;
2233 goto abort;
2234 }
2235 outbuf_dma = pci_map_single(dd->pdev,
2236 outbuf,
2237 taskout,
2238 DMA_TO_DEVICE);
2239 if (outbuf_dma == 0) {
2240 err = -ENOMEM;
2241 goto abort;
2242 }
2243 dma_buffer = outbuf_dma;
2244 }
2245
2246 if (taskin) {
2247 inbuf = kzalloc(taskin, GFP_KERNEL);
2248 if (inbuf == NULL) {
2249 err = -ENOMEM;
2250 goto abort;
2251 }
2252
2253 if (copy_from_user(inbuf, buf + intotal, taskin)) {
2254 err = -EFAULT;
2255 goto abort;
2256 }
2257 inbuf_dma = pci_map_single(dd->pdev,
2258 inbuf,
2259 taskin, DMA_FROM_DEVICE);
2260 if (inbuf_dma == 0) {
2261 err = -ENOMEM;
2262 goto abort;
2263 }
2264 dma_buffer = inbuf_dma;
2265 }
2266
2267
2268 switch (req_task->data_phase) {
2269 case TASKFILE_OUT:
2270 nsect = taskout / ATA_SECT_SIZE;
2271 reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
2272 break;
2273 case TASKFILE_IN:
2274 reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
2275 break;
2276 case TASKFILE_NO_DATA:
2277 reply = (dd->port->rxfis + RX_FIS_D2H_REG);
2278 break;
2279 default:
2280 err = -EINVAL;
2281 goto abort;
2282 }
2283
2284
2285 memset(&fis, 0, sizeof(struct host_to_dev_fis));
2286
2287 fis.type = 0x27;
2288 fis.opts = 1 << 7;
2289 fis.command = req_task->io_ports[7];
2290 fis.features = req_task->io_ports[1];
2291 fis.sect_count = req_task->io_ports[2];
2292 fis.lba_low = req_task->io_ports[3];
2293 fis.lba_mid = req_task->io_ports[4];
2294 fis.lba_hi = req_task->io_ports[5];
2295
2296 fis.device = req_task->io_ports[6] & ~0x10;
2297
2298 if ((req_task->in_flags.all == 0) && (req_task->out_flags.all & 1)) {
2299 req_task->in_flags.all =
2300 IDE_TASKFILE_STD_IN_FLAGS |
2301 (IDE_HOB_STD_IN_FLAGS << 8);
2302 fis.lba_low_ex = req_task->hob_ports[3];
2303 fis.lba_mid_ex = req_task->hob_ports[4];
2304 fis.lba_hi_ex = req_task->hob_ports[5];
2305 fis.features_ex = req_task->hob_ports[1];
2306 fis.sect_cnt_ex = req_task->hob_ports[2];
2307
2308 } else {
2309 req_task->in_flags.all = IDE_TASKFILE_STD_IN_FLAGS;
2310 }
2311
2312 force_single_sector = implicit_sector(fis.command, fis.features);
2313
2314 if ((taskin || taskout) && (!fis.sect_count)) {
2315 if (nsect)
2316 fis.sect_count = nsect;
2317 else {
2318 if (!force_single_sector) {
2319 dev_warn(&dd->pdev->dev,
2320 "data movement but "
2321 "sect_count is 0\n");
2322 err = -EINVAL;
2323 goto abort;
2324 }
2325 }
2326 }
2327
2328 dbg_printk(MTIP_DRV_NAME
2329 " %s: cmd %x, feat %x, nsect %x,"
2330 " sect/lbal %x, lcyl/lbam %x, hcyl/lbah %x,"
2331 " head/dev %x\n",
2332 __func__,
2333 fis.command,
2334 fis.features,
2335 fis.sect_count,
2336 fis.lba_low,
2337 fis.lba_mid,
2338 fis.lba_hi,
2339 fis.device);
2340
2341
2342 if ((fis.command == ATA_CMD_SEC_ERASE_UNIT) && outbuf &&
2343 (outbuf[0] & MTIP_SEC_ERASE_MODE)) {
2344 erasemode = 1;
2345 }
2346
2347 mtip_set_timeout(dd, &fis, &timeout, erasemode);
2348
2349
2350 if (force_single_sector)
2351 transfer_size = ATA_SECT_SIZE;
2352 else
2353 transfer_size = ATA_SECT_SIZE * fis.sect_count;
2354
2355
2356 if (mtip_exec_internal_command(dd->port,
2357 &fis,
2358 5,
2359 dma_buffer,
2360 transfer_size,
2361 0,
2362 GFP_KERNEL,
2363 timeout) < 0) {
2364 err = -EIO;
2365 goto abort;
2366 }
2367
2368 task_file_data = readl(dd->port->mmio+PORT_TFDATA);
2369
2370 if ((req_task->data_phase == TASKFILE_IN) && !(task_file_data & 1)) {
2371 reply = dd->port->rxfis + RX_FIS_PIO_SETUP;
2372 req_task->io_ports[7] = reply->control;
2373 } else {
2374 reply = dd->port->rxfis + RX_FIS_D2H_REG;
2375 req_task->io_ports[7] = reply->command;
2376 }
2377
2378
2379 if (inbuf_dma)
2380 pci_unmap_single(dd->pdev, inbuf_dma,
2381 taskin, DMA_FROM_DEVICE);
2382 if (outbuf_dma)
2383 pci_unmap_single(dd->pdev, outbuf_dma,
2384 taskout, DMA_TO_DEVICE);
2385 inbuf_dma = 0;
2386 outbuf_dma = 0;
2387
2388
2389 req_task->io_ports[1] = reply->features;
2390 req_task->io_ports[2] = reply->sect_count;
2391 req_task->io_ports[3] = reply->lba_low;
2392 req_task->io_ports[4] = reply->lba_mid;
2393 req_task->io_ports[5] = reply->lba_hi;
2394 req_task->io_ports[6] = reply->device;
2395
2396 if (req_task->out_flags.all & 1) {
2397
2398 req_task->hob_ports[3] = reply->lba_low_ex;
2399 req_task->hob_ports[4] = reply->lba_mid_ex;
2400 req_task->hob_ports[5] = reply->lba_hi_ex;
2401 req_task->hob_ports[1] = reply->features_ex;
2402 req_task->hob_ports[2] = reply->sect_cnt_ex;
2403 }
2404 dbg_printk(MTIP_DRV_NAME
2405 " %s: Completion: stat %x,"
2406 "err %x, sect_cnt %x, lbalo %x,"
2407 "lbamid %x, lbahi %x, dev %x\n",
2408 __func__,
2409 req_task->io_ports[7],
2410 req_task->io_ports[1],
2411 req_task->io_ports[2],
2412 req_task->io_ports[3],
2413 req_task->io_ports[4],
2414 req_task->io_ports[5],
2415 req_task->io_ports[6]);
2416
2417 if (taskout) {
2418 if (copy_to_user(buf + outtotal, outbuf, taskout)) {
2419 err = -EFAULT;
2420 goto abort;
2421 }
2422 }
2423 if (taskin) {
2424 if (copy_to_user(buf + intotal, inbuf, taskin)) {
2425 err = -EFAULT;
2426 goto abort;
2427 }
2428 }
2429abort:
2430 if (inbuf_dma)
2431 pci_unmap_single(dd->pdev, inbuf_dma,
2432 taskin, DMA_FROM_DEVICE);
2433 if (outbuf_dma)
2434 pci_unmap_single(dd->pdev, outbuf_dma,
2435 taskout, DMA_TO_DEVICE);
2436 kfree(outbuf);
2437 kfree(inbuf);
2438
2439 return err;
2440}
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459static int mtip_hw_ioctl(struct driver_data *dd, unsigned int cmd,
2460 unsigned long arg)
2461{
2462 switch (cmd) {
2463 case HDIO_GET_IDENTITY:
2464 {
2465 if (copy_to_user((void __user *)arg, dd->port->identify,
2466 sizeof(u16) * ATA_ID_WORDS))
2467 return -EFAULT;
2468 break;
2469 }
2470 case HDIO_DRIVE_CMD:
2471 {
2472 u8 drive_command[4];
2473
2474
2475 if (copy_from_user(drive_command,
2476 (void __user *) arg,
2477 sizeof(drive_command)))
2478 return -EFAULT;
2479
2480
2481 if (exec_drive_command(dd->port,
2482 drive_command,
2483 (void __user *) (arg+4)))
2484 return -EIO;
2485
2486
2487 if (copy_to_user((void __user *) arg,
2488 drive_command,
2489 sizeof(drive_command)))
2490 return -EFAULT;
2491
2492 break;
2493 }
2494 case HDIO_DRIVE_TASK:
2495 {
2496 u8 drive_command[7];
2497
2498
2499 if (copy_from_user(drive_command,
2500 (void __user *) arg,
2501 sizeof(drive_command)))
2502 return -EFAULT;
2503
2504
2505 if (exec_drive_task(dd->port, drive_command))
2506 return -EIO;
2507
2508
2509 if (copy_to_user((void __user *) arg,
2510 drive_command,
2511 sizeof(drive_command)))
2512 return -EFAULT;
2513
2514 break;
2515 }
2516 case HDIO_DRIVE_TASKFILE: {
2517 ide_task_request_t req_task;
2518 int ret, outtotal;
2519
2520 if (copy_from_user(&req_task, (void __user *) arg,
2521 sizeof(req_task)))
2522 return -EFAULT;
2523
2524 outtotal = sizeof(req_task);
2525
2526 ret = exec_drive_taskfile(dd, (void __user *) arg,
2527 &req_task, outtotal);
2528
2529 if (copy_to_user((void __user *) arg, &req_task,
2530 sizeof(req_task)))
2531 return -EFAULT;
2532
2533 return ret;
2534 }
2535
2536 default:
2537 return -EINVAL;
2538 }
2539 return 0;
2540}
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563static void mtip_hw_submit_io(struct driver_data *dd, sector_t sector,
2564 int nsect, int nents, int tag, void *callback,
2565 void *data, int dir, int unaligned)
2566{
2567 struct host_to_dev_fis *fis;
2568 struct mtip_port *port = dd->port;
2569 struct mtip_cmd *command = &port->commands[tag];
2570 int dma_dir = (dir == READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2571 u64 start = sector;
2572
2573
2574 nents = dma_map_sg(&dd->pdev->dev, command->sg, nents, dma_dir);
2575
2576 command->scatter_ents = nents;
2577
2578 command->unaligned = unaligned;
2579
2580
2581
2582
2583 command->retries = MTIP_MAX_RETRIES;
2584
2585
2586 fis = command->command;
2587 fis->type = 0x27;
2588 fis->opts = 1 << 7;
2589 fis->command =
2590 (dir == READ ? ATA_CMD_FPDMA_READ : ATA_CMD_FPDMA_WRITE);
2591 fis->lba_low = start & 0xFF;
2592 fis->lba_mid = (start >> 8) & 0xFF;
2593 fis->lba_hi = (start >> 16) & 0xFF;
2594 fis->lba_low_ex = (start >> 24) & 0xFF;
2595 fis->lba_mid_ex = (start >> 32) & 0xFF;
2596 fis->lba_hi_ex = (start >> 40) & 0xFF;
2597 fis->device = 1 << 6;
2598 fis->features = nsect & 0xFF;
2599 fis->features_ex = (nsect >> 8) & 0xFF;
2600 fis->sect_count = ((tag << 3) | (tag >> 5));
2601 fis->sect_cnt_ex = 0;
2602 fis->control = 0;
2603 fis->res2 = 0;
2604 fis->res3 = 0;
2605 fill_command_sg(dd, command, nents);
2606
2607 if (unaligned)
2608 fis->device |= 1 << 7;
2609
2610
2611 command->command_header->opts =
2612 __force_bit2int cpu_to_le32(
2613 (nents << 16) | 5 | AHCI_CMD_PREFETCH);
2614 command->command_header->byte_count = 0;
2615
2616
2617
2618
2619
2620 command->comp_data = dd;
2621 command->comp_func = mtip_async_complete;
2622 command->direction = dma_dir;
2623
2624
2625
2626
2627
2628 command->async_data = data;
2629 command->async_callback = callback;
2630
2631
2632
2633
2634
2635 if (port->flags & MTIP_PF_PAUSE_IO) {
2636 set_bit(tag, port->cmds_to_issue);
2637 set_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
2638 return;
2639 }
2640
2641
2642 mtip_issue_ncq_command(port, tag);
2643
2644 return;
2645}
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656static void mtip_hw_release_scatterlist(struct driver_data *dd, int tag,
2657 int unaligned)
2658{
2659 struct semaphore *sem = unaligned ? &dd->port->cmd_slot_unal :
2660 &dd->port->cmd_slot;
2661 release_slot(dd->port, tag);
2662 up(sem);
2663}
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676static struct scatterlist *mtip_hw_get_scatterlist(struct driver_data *dd,
2677 int *tag, int unaligned)
2678{
2679 struct semaphore *sem = unaligned ? &dd->port->cmd_slot_unal :
2680 &dd->port->cmd_slot;
2681
2682
2683
2684
2685
2686
2687 down(sem);
2688 *tag = get_slot(dd->port);
2689
2690 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))) {
2691 up(sem);
2692 return NULL;
2693 }
2694 if (unlikely(*tag < 0)) {
2695 up(sem);
2696 return NULL;
2697 }
2698
2699 return dd->port->commands[*tag].sg;
2700}
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712static ssize_t mtip_hw_show_status(struct device *dev,
2713 struct device_attribute *attr,
2714 char *buf)
2715{
2716 struct driver_data *dd = dev_to_disk(dev)->private_data;
2717 int size = 0;
2718
2719 if (test_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag))
2720 size += sprintf(buf, "%s", "thermal_shutdown\n");
2721 else if (test_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag))
2722 size += sprintf(buf, "%s", "write_protect\n");
2723 else
2724 size += sprintf(buf, "%s", "online\n");
2725
2726 return size;
2727}
2728
2729static DEVICE_ATTR(status, S_IRUGO, mtip_hw_show_status, NULL);
2730
2731
2732
2733static ssize_t show_device_status(struct device_driver *drv, char *buf)
2734{
2735 int size = 0;
2736 struct driver_data *dd, *tmp;
2737 unsigned long flags;
2738 char id_buf[42];
2739 u16 status = 0;
2740
2741 spin_lock_irqsave(&dev_lock, flags);
2742 size += sprintf(&buf[size], "Devices Present:\n");
2743 list_for_each_entry_safe(dd, tmp, &online_list, online_list) {
2744 if (dd->pdev) {
2745 if (dd->port &&
2746 dd->port->identify &&
2747 dd->port->identify_valid) {
2748 strlcpy(id_buf,
2749 (char *) (dd->port->identify + 10), 21);
2750 status = *(dd->port->identify + 141);
2751 } else {
2752 memset(id_buf, 0, 42);
2753 status = 0;
2754 }
2755
2756 if (dd->port &&
2757 test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2758 size += sprintf(&buf[size],
2759 " device %s %s (ftl rebuild %d %%)\n",
2760 dev_name(&dd->pdev->dev),
2761 id_buf,
2762 status);
2763 } else {
2764 size += sprintf(&buf[size],
2765 " device %s %s\n",
2766 dev_name(&dd->pdev->dev),
2767 id_buf);
2768 }
2769 }
2770 }
2771
2772 size += sprintf(&buf[size], "Devices Being Removed:\n");
2773 list_for_each_entry_safe(dd, tmp, &removing_list, remove_list) {
2774 if (dd->pdev) {
2775 if (dd->port &&
2776 dd->port->identify &&
2777 dd->port->identify_valid) {
2778 strlcpy(id_buf,
2779 (char *) (dd->port->identify+10), 21);
2780 status = *(dd->port->identify + 141);
2781 } else {
2782 memset(id_buf, 0, 42);
2783 status = 0;
2784 }
2785
2786 if (dd->port &&
2787 test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2788 size += sprintf(&buf[size],
2789 " device %s %s (ftl rebuild %d %%)\n",
2790 dev_name(&dd->pdev->dev),
2791 id_buf,
2792 status);
2793 } else {
2794 size += sprintf(&buf[size],
2795 " device %s %s\n",
2796 dev_name(&dd->pdev->dev),
2797 id_buf);
2798 }
2799 }
2800 }
2801 spin_unlock_irqrestore(&dev_lock, flags);
2802
2803 return size;
2804}
2805
2806static ssize_t mtip_hw_read_device_status(struct file *f, char __user *ubuf,
2807 size_t len, loff_t *offset)
2808{
2809 int size = *offset;
2810 char buf[MTIP_DFS_MAX_BUF_SIZE];
2811
2812 if (!len || *offset)
2813 return 0;
2814
2815 size += show_device_status(NULL, buf);
2816
2817 *offset = size <= len ? size : len;
2818 size = copy_to_user(ubuf, buf, *offset);
2819 if (size)
2820 return -EFAULT;
2821
2822 return *offset;
2823}
2824
2825static ssize_t mtip_hw_read_registers(struct file *f, char __user *ubuf,
2826 size_t len, loff_t *offset)
2827{
2828 struct driver_data *dd = (struct driver_data *)f->private_data;
2829 char buf[MTIP_DFS_MAX_BUF_SIZE];
2830 u32 group_allocated;
2831 int size = *offset;
2832 int n;
2833
2834 if (!len || size)
2835 return 0;
2836
2837 size += sprintf(&buf[size], "H/ S ACTive : [ 0x");
2838
2839 for (n = dd->slot_groups-1; n >= 0; n--)
2840 size += sprintf(&buf[size], "%08X ",
2841 readl(dd->port->s_active[n]));
2842
2843 size += sprintf(&buf[size], "]\n");
2844 size += sprintf(&buf[size], "H/ Command Issue : [ 0x");
2845
2846 for (n = dd->slot_groups-1; n >= 0; n--)
2847 size += sprintf(&buf[size], "%08X ",
2848 readl(dd->port->cmd_issue[n]));
2849
2850 size += sprintf(&buf[size], "]\n");
2851 size += sprintf(&buf[size], "H/ Completed : [ 0x");
2852
2853 for (n = dd->slot_groups-1; n >= 0; n--)
2854 size += sprintf(&buf[size], "%08X ",
2855 readl(dd->port->completed[n]));
2856
2857 size += sprintf(&buf[size], "]\n");
2858 size += sprintf(&buf[size], "H/ PORT IRQ STAT : [ 0x%08X ]\n",
2859 readl(dd->port->mmio + PORT_IRQ_STAT));
2860 size += sprintf(&buf[size], "H/ HOST IRQ STAT : [ 0x%08X ]\n",
2861 readl(dd->mmio + HOST_IRQ_STAT));
2862 size += sprintf(&buf[size], "\n");
2863
2864 size += sprintf(&buf[size], "L/ Allocated : [ 0x");
2865
2866 for (n = dd->slot_groups-1; n >= 0; n--) {
2867 if (sizeof(long) > sizeof(u32))
2868 group_allocated =
2869 dd->port->allocated[n/2] >> (32*(n&1));
2870 else
2871 group_allocated = dd->port->allocated[n];
2872 size += sprintf(&buf[size], "%08X ", group_allocated);
2873 }
2874 size += sprintf(&buf[size], "]\n");
2875
2876 size += sprintf(&buf[size], "L/ Commands in Q : [ 0x");
2877
2878 for (n = dd->slot_groups-1; n >= 0; n--) {
2879 if (sizeof(long) > sizeof(u32))
2880 group_allocated =
2881 dd->port->cmds_to_issue[n/2] >> (32*(n&1));
2882 else
2883 group_allocated = dd->port->cmds_to_issue[n];
2884 size += sprintf(&buf[size], "%08X ", group_allocated);
2885 }
2886 size += sprintf(&buf[size], "]\n");
2887
2888 *offset = size <= len ? size : len;
2889 size = copy_to_user(ubuf, buf, *offset);
2890 if (size)
2891 return -EFAULT;
2892
2893 return *offset;
2894}
2895
2896static ssize_t mtip_hw_read_flags(struct file *f, char __user *ubuf,
2897 size_t len, loff_t *offset)
2898{
2899 struct driver_data *dd = (struct driver_data *)f->private_data;
2900 char buf[MTIP_DFS_MAX_BUF_SIZE];
2901 int size = *offset;
2902
2903 if (!len || size)
2904 return 0;
2905
2906 size += sprintf(&buf[size], "Flag-port : [ %08lX ]\n",
2907 dd->port->flags);
2908 size += sprintf(&buf[size], "Flag-dd : [ %08lX ]\n",
2909 dd->dd_flag);
2910
2911 *offset = size <= len ? size : len;
2912 size = copy_to_user(ubuf, buf, *offset);
2913 if (size)
2914 return -EFAULT;
2915
2916 return *offset;
2917}
2918
2919static const struct file_operations mtip_device_status_fops = {
2920 .owner = THIS_MODULE,
2921 .open = simple_open,
2922 .read = mtip_hw_read_device_status,
2923 .llseek = no_llseek,
2924};
2925
2926static const struct file_operations mtip_regs_fops = {
2927 .owner = THIS_MODULE,
2928 .open = simple_open,
2929 .read = mtip_hw_read_registers,
2930 .llseek = no_llseek,
2931};
2932
2933static const struct file_operations mtip_flags_fops = {
2934 .owner = THIS_MODULE,
2935 .open = simple_open,
2936 .read = mtip_hw_read_flags,
2937 .llseek = no_llseek,
2938};
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950static int mtip_hw_sysfs_init(struct driver_data *dd, struct kobject *kobj)
2951{
2952 if (!kobj || !dd)
2953 return -EINVAL;
2954
2955 if (sysfs_create_file(kobj, &dev_attr_status.attr))
2956 dev_warn(&dd->pdev->dev,
2957 "Error creating 'status' sysfs entry\n");
2958 return 0;
2959}
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971static int mtip_hw_sysfs_exit(struct driver_data *dd, struct kobject *kobj)
2972{
2973 if (!kobj || !dd)
2974 return -EINVAL;
2975
2976 sysfs_remove_file(kobj, &dev_attr_status.attr);
2977
2978 return 0;
2979}
2980
2981static int mtip_hw_debugfs_init(struct driver_data *dd)
2982{
2983 if (!dfs_parent)
2984 return -1;
2985
2986 dd->dfs_node = debugfs_create_dir(dd->disk->disk_name, dfs_parent);
2987 if (IS_ERR_OR_NULL(dd->dfs_node)) {
2988 dev_warn(&dd->pdev->dev,
2989 "Error creating node %s under debugfs\n",
2990 dd->disk->disk_name);
2991 dd->dfs_node = NULL;
2992 return -1;
2993 }
2994
2995 debugfs_create_file("flags", S_IRUGO, dd->dfs_node, dd,
2996 &mtip_flags_fops);
2997 debugfs_create_file("registers", S_IRUGO, dd->dfs_node, dd,
2998 &mtip_regs_fops);
2999
3000 return 0;
3001}
3002
3003static void mtip_hw_debugfs_exit(struct driver_data *dd)
3004{
3005 if (dd->dfs_node)
3006 debugfs_remove_recursive(dd->dfs_node);
3007}
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018static inline void hba_setup(struct driver_data *dd)
3019{
3020 u32 hwdata;
3021 hwdata = readl(dd->mmio + HOST_HSORG);
3022
3023
3024 writel(hwdata |
3025 HSORG_DISABLE_SLOTGRP_INTR |
3026 HSORG_DISABLE_SLOTGRP_PXIS,
3027 dd->mmio + HOST_HSORG);
3028}
3029
3030static int mtip_device_unaligned_constrained(struct driver_data *dd)
3031{
3032 return (dd->pdev->device == P420M_DEVICE_ID ? 1 : 0);
3033}
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045static void mtip_detect_product(struct driver_data *dd)
3046{
3047 u32 hwdata;
3048 unsigned int rev, slotgroups;
3049
3050
3051
3052
3053
3054
3055
3056
3057 hwdata = readl(dd->mmio + HOST_HSORG);
3058
3059 dd->product_type = MTIP_PRODUCT_UNKNOWN;
3060 dd->slot_groups = 1;
3061
3062 if (hwdata & 0x8) {
3063 dd->product_type = MTIP_PRODUCT_ASICFPGA;
3064 rev = (hwdata & HSORG_HWREV) >> 8;
3065 slotgroups = (hwdata & HSORG_SLOTGROUPS) + 1;
3066 dev_info(&dd->pdev->dev,
3067 "ASIC-FPGA design, HS rev 0x%x, "
3068 "%i slot groups [%i slots]\n",
3069 rev,
3070 slotgroups,
3071 slotgroups * 32);
3072
3073 if (slotgroups > MTIP_MAX_SLOT_GROUPS) {
3074 dev_warn(&dd->pdev->dev,
3075 "Warning: driver only supports "
3076 "%i slot groups.\n", MTIP_MAX_SLOT_GROUPS);
3077 slotgroups = MTIP_MAX_SLOT_GROUPS;
3078 }
3079 dd->slot_groups = slotgroups;
3080 return;
3081 }
3082
3083 dev_warn(&dd->pdev->dev, "Unrecognized product id\n");
3084}
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095static int mtip_ftl_rebuild_poll(struct driver_data *dd)
3096{
3097 unsigned long timeout, cnt = 0, start;
3098
3099 dev_warn(&dd->pdev->dev,
3100 "FTL rebuild in progress. Polling for completion.\n");
3101
3102 start = jiffies;
3103 timeout = jiffies + msecs_to_jiffies(MTIP_FTL_REBUILD_TIMEOUT_MS);
3104
3105 do {
3106 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
3107 &dd->dd_flag)))
3108 return -EFAULT;
3109 if (mtip_check_surprise_removal(dd->pdev))
3110 return -EFAULT;
3111
3112 if (mtip_get_identify(dd->port, NULL) < 0)
3113 return -EFAULT;
3114
3115 if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
3116 MTIP_FTL_REBUILD_MAGIC) {
3117 ssleep(1);
3118
3119 if (cnt++ >= 180) {
3120 dev_warn(&dd->pdev->dev,
3121 "FTL rebuild in progress (%d secs).\n",
3122 jiffies_to_msecs(jiffies - start) / 1000);
3123 cnt = 0;
3124 }
3125 } else {
3126 dev_warn(&dd->pdev->dev,
3127 "FTL rebuild complete (%d secs).\n",
3128 jiffies_to_msecs(jiffies - start) / 1000);
3129 mtip_block_initialize(dd);
3130 return 0;
3131 }
3132 ssleep(10);
3133 } while (time_before(jiffies, timeout));
3134
3135
3136 dev_err(&dd->pdev->dev,
3137 "Timed out waiting for FTL rebuild to complete (%d secs).\n",
3138 jiffies_to_msecs(jiffies - start) / 1000);
3139 return -EFAULT;
3140}
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151static int mtip_service_thread(void *data)
3152{
3153 struct driver_data *dd = (struct driver_data *)data;
3154 unsigned long slot, slot_start, slot_wrap;
3155 unsigned int num_cmd_slots = dd->slot_groups * 32;
3156 struct mtip_port *port = dd->port;
3157
3158 while (1) {
3159
3160
3161
3162
3163 wait_event_interruptible(port->svc_wait, (port->flags) &&
3164 !(port->flags & MTIP_PF_PAUSE_IO));
3165
3166 if (kthread_should_stop())
3167 break;
3168
3169 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
3170 &dd->dd_flag)))
3171 break;
3172
3173 set_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
3174 if (test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
3175 slot = 1;
3176
3177 slot_start = num_cmd_slots;
3178 slot_wrap = 0;
3179 while (1) {
3180 slot = find_next_bit(port->cmds_to_issue,
3181 num_cmd_slots, slot);
3182 if (slot_wrap == 1) {
3183 if ((slot_start >= slot) ||
3184 (slot >= num_cmd_slots))
3185 break;
3186 }
3187 if (unlikely(slot_start == num_cmd_slots))
3188 slot_start = slot;
3189
3190 if (unlikely(slot == num_cmd_slots)) {
3191 slot = 1;
3192 slot_wrap = 1;
3193 continue;
3194 }
3195
3196
3197 mtip_issue_ncq_command(port, slot);
3198
3199 clear_bit(slot, port->cmds_to_issue);
3200 }
3201
3202 clear_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
3203 } else if (test_bit(MTIP_PF_REBUILD_BIT, &port->flags)) {
3204 if (!mtip_ftl_rebuild_poll(dd))
3205 set_bit(MTIP_DDF_REBUILD_FAILED_BIT,
3206 &dd->dd_flag);
3207 clear_bit(MTIP_PF_REBUILD_BIT, &port->flags);
3208 }
3209 clear_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
3210
3211 if (test_bit(MTIP_PF_SVC_THD_STOP_BIT, &port->flags))
3212 break;
3213 }
3214 return 0;
3215}
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225static int mtip_hw_init(struct driver_data *dd)
3226{
3227 int i;
3228 int rv;
3229 unsigned int num_command_slots;
3230 unsigned long timeout, timetaken;
3231 unsigned char *buf;
3232 struct smart_attr attr242;
3233
3234 dd->mmio = pcim_iomap_table(dd->pdev)[MTIP_ABAR];
3235
3236 mtip_detect_product(dd);
3237 if (dd->product_type == MTIP_PRODUCT_UNKNOWN) {
3238 rv = -EIO;
3239 goto out1;
3240 }
3241 num_command_slots = dd->slot_groups * 32;
3242
3243 hba_setup(dd);
3244
3245 dd->port = kzalloc_node(sizeof(struct mtip_port), GFP_KERNEL,
3246 dd->numa_node);
3247 if (!dd->port) {
3248 dev_err(&dd->pdev->dev,
3249 "Memory allocation: port structure\n");
3250 return -ENOMEM;
3251 }
3252
3253
3254 for (i = 0; i < MTIP_MAX_SLOT_GROUPS; i++)
3255 dd->work[i].port = dd->port;
3256
3257
3258 if (mtip_device_unaligned_constrained(dd))
3259 dd->unal_qdepth = MTIP_MAX_UNALIGNED_SLOTS;
3260 else
3261 dd->unal_qdepth = 0;
3262
3263
3264 sema_init(&dd->port->cmd_slot, num_command_slots - 1 - dd->unal_qdepth);
3265 sema_init(&dd->port->cmd_slot_unal, dd->unal_qdepth);
3266
3267
3268 for (i = 0; i < MTIP_MAX_SLOT_GROUPS; i++)
3269 spin_lock_init(&dd->port->cmd_issue_lock[i]);
3270
3271
3272 dd->port->mmio = dd->mmio + PORT_OFFSET;
3273 dd->port->dd = dd;
3274
3275
3276 dd->port->command_list =
3277 dmam_alloc_coherent(&dd->pdev->dev,
3278 HW_PORT_PRIV_DMA_SZ + (ATA_SECT_SIZE * 4),
3279 &dd->port->command_list_dma,
3280 GFP_KERNEL);
3281 if (!dd->port->command_list) {
3282 dev_err(&dd->pdev->dev,
3283 "Memory allocation: command list\n");
3284 rv = -ENOMEM;
3285 goto out1;
3286 }
3287
3288
3289 memset(dd->port->command_list,
3290 0,
3291 HW_PORT_PRIV_DMA_SZ + (ATA_SECT_SIZE * 4));
3292
3293
3294 dd->port->rxfis = dd->port->command_list + HW_CMD_SLOT_SZ;
3295 dd->port->rxfis_dma = dd->port->command_list_dma + HW_CMD_SLOT_SZ;
3296
3297
3298 dd->port->command_table = dd->port->rxfis + AHCI_RX_FIS_SZ;
3299 dd->port->command_tbl_dma = dd->port->rxfis_dma + AHCI_RX_FIS_SZ;
3300
3301
3302 dd->port->identify = dd->port->command_table +
3303 HW_CMD_TBL_AR_SZ;
3304 dd->port->identify_dma = dd->port->command_tbl_dma +
3305 HW_CMD_TBL_AR_SZ;
3306
3307
3308 dd->port->sector_buffer = (void *) dd->port->identify + ATA_SECT_SIZE;
3309 dd->port->sector_buffer_dma = dd->port->identify_dma + ATA_SECT_SIZE;
3310
3311
3312 dd->port->log_buf = (void *)dd->port->sector_buffer + ATA_SECT_SIZE;
3313 dd->port->log_buf_dma = dd->port->sector_buffer_dma + ATA_SECT_SIZE;
3314
3315
3316 dd->port->smart_buf = (void *)dd->port->log_buf + ATA_SECT_SIZE;
3317 dd->port->smart_buf_dma = dd->port->log_buf_dma + ATA_SECT_SIZE;
3318
3319
3320
3321 for (i = 0; i < num_command_slots; i++) {
3322 dd->port->commands[i].command_header =
3323 dd->port->command_list +
3324 (sizeof(struct mtip_cmd_hdr) * i);
3325 dd->port->commands[i].command_header_dma =
3326 dd->port->command_list_dma +
3327 (sizeof(struct mtip_cmd_hdr) * i);
3328
3329 dd->port->commands[i].command =
3330 dd->port->command_table + (HW_CMD_TBL_SZ * i);
3331 dd->port->commands[i].command_dma =
3332 dd->port->command_tbl_dma + (HW_CMD_TBL_SZ * i);
3333
3334 if (readl(dd->mmio + HOST_CAP) & HOST_CAP_64)
3335 dd->port->commands[i].command_header->ctbau =
3336 __force_bit2int cpu_to_le32(
3337 (dd->port->commands[i].command_dma >> 16) >> 16);
3338 dd->port->commands[i].command_header->ctba =
3339 __force_bit2int cpu_to_le32(
3340 dd->port->commands[i].command_dma & 0xFFFFFFFF);
3341
3342
3343
3344
3345
3346
3347 sg_init_table(dd->port->commands[i].sg, MTIP_MAX_SG);
3348
3349
3350 atomic_set(&dd->port->commands[i].active, 0);
3351 }
3352
3353
3354 for (i = 0; i < dd->slot_groups; i++) {
3355 dd->port->s_active[i] =
3356 dd->port->mmio + i*0x80 + PORT_SCR_ACT;
3357 dd->port->cmd_issue[i] =
3358 dd->port->mmio + i*0x80 + PORT_COMMAND_ISSUE;
3359 dd->port->completed[i] =
3360 dd->port->mmio + i*0x80 + PORT_SDBV;
3361 }
3362
3363 timetaken = jiffies;
3364 timeout = jiffies + msecs_to_jiffies(30000);
3365 while (((readl(dd->port->mmio + PORT_SCR_STAT) & 0x0F) != 0x03) &&
3366 time_before(jiffies, timeout)) {
3367 mdelay(100);
3368 }
3369 if (unlikely(mtip_check_surprise_removal(dd->pdev))) {
3370 timetaken = jiffies - timetaken;
3371 dev_warn(&dd->pdev->dev,
3372 "Surprise removal detected at %u ms\n",
3373 jiffies_to_msecs(timetaken));
3374 rv = -ENODEV;
3375 goto out2 ;
3376 }
3377 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))) {
3378 timetaken = jiffies - timetaken;
3379 dev_warn(&dd->pdev->dev,
3380 "Removal detected at %u ms\n",
3381 jiffies_to_msecs(timetaken));
3382 rv = -EFAULT;
3383 goto out2;
3384 }
3385
3386
3387 if (!(readl(dd->mmio + HOST_CAP) & HOST_CAP_NZDMA)) {
3388 if (mtip_hba_reset(dd) < 0) {
3389 dev_err(&dd->pdev->dev,
3390 "Card did not reset within timeout\n");
3391 rv = -EIO;
3392 goto out2;
3393 }
3394 } else {
3395
3396 writel(readl(dd->mmio + HOST_IRQ_STAT),
3397 dd->mmio + HOST_IRQ_STAT);
3398 }
3399
3400 mtip_init_port(dd->port);
3401 mtip_start_port(dd->port);
3402
3403
3404 rv = devm_request_irq(&dd->pdev->dev,
3405 dd->pdev->irq,
3406 mtip_irq_handler,
3407 IRQF_SHARED,
3408 dev_driver_string(&dd->pdev->dev),
3409 dd);
3410
3411 if (rv) {
3412 dev_err(&dd->pdev->dev,
3413 "Unable to allocate IRQ %d\n", dd->pdev->irq);
3414 goto out2;
3415 }
3416 irq_set_affinity_hint(dd->pdev->irq, get_cpu_mask(dd->isr_binding));
3417
3418
3419 writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
3420 dd->mmio + HOST_CTL);
3421
3422 init_timer(&dd->port->cmd_timer);
3423 init_waitqueue_head(&dd->port->svc_wait);
3424
3425 dd->port->cmd_timer.data = (unsigned long int) dd->port;
3426 dd->port->cmd_timer.function = mtip_timeout_function;
3427 mod_timer(&dd->port->cmd_timer,
3428 jiffies + msecs_to_jiffies(MTIP_TIMEOUT_CHECK_PERIOD));
3429
3430
3431 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)) {
3432 rv = -EFAULT;
3433 goto out3;
3434 }
3435
3436 if (mtip_get_identify(dd->port, NULL) < 0) {
3437 rv = -EFAULT;
3438 goto out3;
3439 }
3440
3441 if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
3442 MTIP_FTL_REBUILD_MAGIC) {
3443 set_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags);
3444 return MTIP_FTL_REBUILD_MAGIC;
3445 }
3446 mtip_dump_identify(dd->port);
3447
3448
3449 rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
3450 dd->port->log_buf,
3451 dd->port->log_buf_dma, 1);
3452 if (rv) {
3453 dev_warn(&dd->pdev->dev,
3454 "Error in READ LOG EXT (10h) command\n");
3455
3456 } else {
3457 buf = (unsigned char *)dd->port->log_buf;
3458 if (buf[259] & 0x1) {
3459 dev_info(&dd->pdev->dev,
3460 "Write protect bit is set.\n");
3461 set_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag);
3462 }
3463 if (buf[288] == 0xF7) {
3464 dev_info(&dd->pdev->dev,
3465 "Exceeded Tmax, drive in thermal shutdown.\n");
3466 set_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag);
3467 }
3468 if (buf[288] == 0xBF) {
3469 dev_info(&dd->pdev->dev,
3470 "Drive indicates rebuild has failed.\n");
3471
3472 }
3473 }
3474
3475
3476 memset(&attr242, 0, sizeof(struct smart_attr));
3477 if (mtip_get_smart_attr(dd->port, 242, &attr242))
3478 dev_warn(&dd->pdev->dev,
3479 "Unable to check write protect progress\n");
3480 else
3481 dev_info(&dd->pdev->dev,
3482 "Write protect progress: %u%% (%u blocks)\n",
3483 attr242.cur, le32_to_cpu(attr242.data));
3484 return rv;
3485
3486out3:
3487 del_timer_sync(&dd->port->cmd_timer);
3488
3489
3490 writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
3491 dd->mmio + HOST_CTL);
3492
3493
3494 irq_set_affinity_hint(dd->pdev->irq, NULL);
3495 devm_free_irq(&dd->pdev->dev, dd->pdev->irq, dd);
3496
3497out2:
3498 mtip_deinit_port(dd->port);
3499
3500
3501 dmam_free_coherent(&dd->pdev->dev,
3502 HW_PORT_PRIV_DMA_SZ + (ATA_SECT_SIZE * 4),
3503 dd->port->command_list,
3504 dd->port->command_list_dma);
3505out1:
3506
3507 kfree(dd->port);
3508
3509 return rv;
3510}
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520static int mtip_hw_exit(struct driver_data *dd)
3521{
3522
3523
3524
3525
3526 if (!test_bit(MTIP_DDF_CLEANUP_BIT, &dd->dd_flag)) {
3527
3528 if (!test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags))
3529 if (mtip_standby_immediate(dd->port))
3530 dev_warn(&dd->pdev->dev,
3531 "STANDBY IMMEDIATE failed\n");
3532
3533
3534 mtip_deinit_port(dd->port);
3535
3536
3537 writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
3538 dd->mmio + HOST_CTL);
3539 }
3540
3541 del_timer_sync(&dd->port->cmd_timer);
3542
3543
3544 irq_set_affinity_hint(dd->pdev->irq, NULL);
3545 devm_free_irq(&dd->pdev->dev, dd->pdev->irq, dd);
3546
3547
3548 dmam_free_coherent(&dd->pdev->dev,
3549 HW_PORT_PRIV_DMA_SZ + (ATA_SECT_SIZE * 4),
3550 dd->port->command_list,
3551 dd->port->command_list_dma);
3552
3553 kfree(dd->port);
3554
3555 return 0;
3556}
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569static int mtip_hw_shutdown(struct driver_data *dd)
3570{
3571
3572
3573
3574
3575 mtip_standby_immediate(dd->port);
3576
3577 return 0;
3578}
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592static int mtip_hw_suspend(struct driver_data *dd)
3593{
3594
3595
3596
3597
3598 if (mtip_standby_immediate(dd->port) != 0) {
3599 dev_err(&dd->pdev->dev,
3600 "Failed standby-immediate command\n");
3601 return -EFAULT;
3602 }
3603
3604
3605 writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
3606 dd->mmio + HOST_CTL);
3607 mtip_deinit_port(dd->port);
3608
3609 return 0;
3610}
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624static int mtip_hw_resume(struct driver_data *dd)
3625{
3626
3627 hba_setup(dd);
3628
3629
3630 if (mtip_hba_reset(dd) != 0) {
3631 dev_err(&dd->pdev->dev,
3632 "Unable to reset the HBA\n");
3633 return -EFAULT;
3634 }
3635
3636
3637
3638
3639
3640 mtip_init_port(dd->port);
3641 mtip_start_port(dd->port);
3642
3643
3644 writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
3645 dd->mmio + HOST_CTL);
3646
3647 return 0;
3648}
3649
3650
3651
3652
3653
3654static int rssd_disk_name_format(char *prefix,
3655 int index,
3656 char *buf,
3657 int buflen)
3658{
3659 const int base = 'z' - 'a' + 1;
3660 char *begin = buf + strlen(prefix);
3661 char *end = buf + buflen;
3662 char *p;
3663 int unit;
3664
3665 p = end - 1;
3666 *p = '\0';
3667 unit = base;
3668 do {
3669 if (p == begin)
3670 return -EINVAL;
3671 *--p = 'a' + (index % unit);
3672 index = (index / unit) - 1;
3673 } while (index >= 0);
3674
3675 memmove(begin, p, end - p);
3676 memcpy(buf, prefix, strlen(prefix));
3677
3678 return 0;
3679}
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694static int mtip_block_ioctl(struct block_device *dev,
3695 fmode_t mode,
3696 unsigned cmd,
3697 unsigned long arg)
3698{
3699 struct driver_data *dd = dev->bd_disk->private_data;
3700
3701 if (!capable(CAP_SYS_ADMIN))
3702 return -EACCES;
3703
3704 if (!dd)
3705 return -ENOTTY;
3706
3707 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)))
3708 return -ENOTTY;
3709
3710 switch (cmd) {
3711 case BLKFLSBUF:
3712 return -ENOTTY;
3713 default:
3714 return mtip_hw_ioctl(dd, cmd, arg);
3715 }
3716}
3717
3718#ifdef CONFIG_COMPAT
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732static int mtip_block_compat_ioctl(struct block_device *dev,
3733 fmode_t mode,
3734 unsigned cmd,
3735 unsigned long arg)
3736{
3737 struct driver_data *dd = dev->bd_disk->private_data;
3738
3739 if (!capable(CAP_SYS_ADMIN))
3740 return -EACCES;
3741
3742 if (!dd)
3743 return -ENOTTY;
3744
3745 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)))
3746 return -ENOTTY;
3747
3748 switch (cmd) {
3749 case BLKFLSBUF:
3750 return -ENOTTY;
3751 case HDIO_DRIVE_TASKFILE: {
3752 struct mtip_compat_ide_task_request_s __user *compat_req_task;
3753 ide_task_request_t req_task;
3754 int compat_tasksize, outtotal, ret;
3755
3756 compat_tasksize =
3757 sizeof(struct mtip_compat_ide_task_request_s);
3758
3759 compat_req_task =
3760 (struct mtip_compat_ide_task_request_s __user *) arg;
3761
3762 if (copy_from_user(&req_task, (void __user *) arg,
3763 compat_tasksize - (2 * sizeof(compat_long_t))))
3764 return -EFAULT;
3765
3766 if (get_user(req_task.out_size, &compat_req_task->out_size))
3767 return -EFAULT;
3768
3769 if (get_user(req_task.in_size, &compat_req_task->in_size))
3770 return -EFAULT;
3771
3772 outtotal = sizeof(struct mtip_compat_ide_task_request_s);
3773
3774 ret = exec_drive_taskfile(dd, (void __user *) arg,
3775 &req_task, outtotal);
3776
3777 if (copy_to_user((void __user *) arg, &req_task,
3778 compat_tasksize -
3779 (2 * sizeof(compat_long_t))))
3780 return -EFAULT;
3781
3782 if (put_user(req_task.out_size, &compat_req_task->out_size))
3783 return -EFAULT;
3784
3785 if (put_user(req_task.in_size, &compat_req_task->in_size))
3786 return -EFAULT;
3787
3788 return ret;
3789 }
3790 default:
3791 return mtip_hw_ioctl(dd, cmd, arg);
3792 }
3793}
3794#endif
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814static int mtip_block_getgeo(struct block_device *dev,
3815 struct hd_geometry *geo)
3816{
3817 struct driver_data *dd = dev->bd_disk->private_data;
3818 sector_t capacity;
3819
3820 if (!dd)
3821 return -ENOTTY;
3822
3823 if (!(mtip_hw_get_capacity(dd, &capacity))) {
3824 dev_warn(&dd->pdev->dev,
3825 "Could not get drive capacity.\n");
3826 return -ENOTTY;
3827 }
3828
3829 geo->heads = 224;
3830 geo->sectors = 56;
3831 sector_div(capacity, (geo->heads * geo->sectors));
3832 geo->cylinders = capacity;
3833 return 0;
3834}
3835
3836
3837
3838
3839
3840
3841
3842static const struct block_device_operations mtip_block_ops = {
3843 .ioctl = mtip_block_ioctl,
3844#ifdef CONFIG_COMPAT
3845 .compat_ioctl = mtip_block_compat_ioctl,
3846#endif
3847 .getgeo = mtip_block_getgeo,
3848 .owner = THIS_MODULE
3849};
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862static void mtip_make_request(struct request_queue *queue, struct bio *bio)
3863{
3864 struct driver_data *dd = queue->queuedata;
3865 struct scatterlist *sg;
3866 struct bio_vec *bvec;
3867 int i, nents = 0;
3868 int tag = 0, unaligned = 0;
3869
3870 if (unlikely(dd->dd_flag & MTIP_DDF_STOP_IO)) {
3871 if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
3872 &dd->dd_flag))) {
3873 bio_endio(bio, -ENXIO);
3874 return;
3875 }
3876 if (unlikely(test_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag))) {
3877 bio_endio(bio, -ENODATA);
3878 return;
3879 }
3880 if (unlikely(test_bit(MTIP_DDF_WRITE_PROTECT_BIT,
3881 &dd->dd_flag) &&
3882 bio_data_dir(bio))) {
3883 bio_endio(bio, -ENODATA);
3884 return;
3885 }
3886 if (unlikely(test_bit(MTIP_DDF_SEC_LOCK_BIT, &dd->dd_flag))) {
3887 bio_endio(bio, -ENODATA);
3888 return;
3889 }
3890 }
3891
3892 if (unlikely(bio->bi_rw & REQ_DISCARD)) {
3893 bio_endio(bio, mtip_send_trim(dd, bio->bi_sector,
3894 bio_sectors(bio)));
3895 return;
3896 }
3897
3898 if (unlikely(!bio_has_data(bio))) {
3899 blk_queue_flush(queue, 0);
3900 bio_endio(bio, 0);
3901 return;
3902 }
3903
3904 if (bio_data_dir(bio) == WRITE && bio_sectors(bio) <= 64 &&
3905 dd->unal_qdepth) {
3906 if (bio->bi_sector % 8 != 0)
3907 unaligned = 1;
3908 else if (bio_sectors(bio) % 8 != 0)
3909 unaligned = 1;
3910 }
3911
3912 sg = mtip_hw_get_scatterlist(dd, &tag, unaligned);
3913 if (likely(sg != NULL)) {
3914 blk_queue_bounce(queue, &bio);
3915
3916 if (unlikely((bio)->bi_vcnt > MTIP_MAX_SG)) {
3917 dev_warn(&dd->pdev->dev,
3918 "Maximum number of SGL entries exceeded\n");
3919 bio_io_error(bio);
3920 mtip_hw_release_scatterlist(dd, tag, unaligned);
3921 return;
3922 }
3923
3924
3925 bio_for_each_segment(bvec, bio, i) {
3926 sg_set_page(&sg[nents],
3927 bvec->bv_page,
3928 bvec->bv_len,
3929 bvec->bv_offset);
3930 nents++;
3931 }
3932
3933
3934 mtip_hw_submit_io(dd,
3935 bio->bi_sector,
3936 bio_sectors(bio),
3937 nents,
3938 tag,
3939 bio_endio,
3940 bio,
3941 bio_data_dir(bio),
3942 unaligned);
3943 } else
3944 bio_io_error(bio);
3945}
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958static int mtip_block_initialize(struct driver_data *dd)
3959{
3960 int rv = 0, wait_for_rebuild = 0;
3961 sector_t capacity;
3962 unsigned int index = 0;
3963 struct kobject *kobj;
3964 unsigned char thd_name[16];
3965
3966 if (dd->disk)
3967 goto skip_create_disk;
3968
3969
3970 wait_for_rebuild = mtip_hw_init(dd);
3971 if (wait_for_rebuild < 0) {
3972 dev_err(&dd->pdev->dev,
3973 "Protocol layer initialization failed\n");
3974 rv = -EINVAL;
3975 goto protocol_init_error;
3976 }
3977
3978 dd->disk = alloc_disk_node(MTIP_MAX_MINORS, dd->numa_node);
3979 if (dd->disk == NULL) {
3980 dev_err(&dd->pdev->dev,
3981 "Unable to allocate gendisk structure\n");
3982 rv = -EINVAL;
3983 goto alloc_disk_error;
3984 }
3985
3986
3987 do {
3988 if (!ida_pre_get(&rssd_index_ida, GFP_KERNEL))
3989 goto ida_get_error;
3990
3991 spin_lock(&rssd_index_lock);
3992 rv = ida_get_new(&rssd_index_ida, &index);
3993 spin_unlock(&rssd_index_lock);
3994 } while (rv == -EAGAIN);
3995
3996 if (rv)
3997 goto ida_get_error;
3998
3999 rv = rssd_disk_name_format("rssd",
4000 index,
4001 dd->disk->disk_name,
4002 DISK_NAME_LEN);
4003 if (rv)
4004 goto disk_index_error;
4005
4006 dd->disk->driverfs_dev = &dd->pdev->dev;
4007 dd->disk->major = dd->major;
4008 dd->disk->first_minor = dd->instance * MTIP_MAX_MINORS;
4009 dd->disk->fops = &mtip_block_ops;
4010 dd->disk->private_data = dd;
4011 dd->index = index;
4012
4013
4014
4015
4016
4017 if (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)
4018 goto start_service_thread;
4019
4020skip_create_disk:
4021
4022 dd->queue = blk_alloc_queue_node(GFP_KERNEL, dd->numa_node);
4023 if (dd->queue == NULL) {
4024 dev_err(&dd->pdev->dev,
4025 "Unable to allocate request queue\n");
4026 rv = -ENOMEM;
4027 goto block_queue_alloc_init_error;
4028 }
4029
4030
4031 blk_queue_make_request(dd->queue, mtip_make_request);
4032
4033 dd->disk->queue = dd->queue;
4034 dd->queue->queuedata = dd;
4035
4036
4037 set_bit(QUEUE_FLAG_NONROT, &dd->queue->queue_flags);
4038 blk_queue_max_segments(dd->queue, MTIP_MAX_SG);
4039 blk_queue_physical_block_size(dd->queue, 4096);
4040 blk_queue_max_hw_sectors(dd->queue, 0xffff);
4041 blk_queue_max_segment_size(dd->queue, 0x400000);
4042 blk_queue_io_min(dd->queue, 4096);
4043
4044
4045
4046
4047
4048 blk_queue_flush(dd->queue, 0);
4049
4050
4051 if (dd->trim_supp == true) {
4052 set_bit(QUEUE_FLAG_DISCARD, &dd->queue->queue_flags);
4053 dd->queue->limits.discard_granularity = 4096;
4054 blk_queue_max_discard_sectors(dd->queue,
4055 MTIP_MAX_TRIM_ENTRY_LEN * MTIP_MAX_TRIM_ENTRIES);
4056 dd->queue->limits.discard_zeroes_data = 0;
4057 }
4058
4059
4060 if (!(mtip_hw_get_capacity(dd, &capacity))) {
4061 dev_warn(&dd->pdev->dev,
4062 "Could not read drive capacity\n");
4063 rv = -EIO;
4064 goto read_capacity_error;
4065 }
4066 set_capacity(dd->disk, capacity);
4067
4068
4069 add_disk(dd->disk);
4070
4071
4072
4073
4074
4075 kobj = kobject_get(&disk_to_dev(dd->disk)->kobj);
4076 if (kobj) {
4077 mtip_hw_sysfs_init(dd, kobj);
4078 kobject_put(kobj);
4079 }
4080 mtip_hw_debugfs_init(dd);
4081
4082 if (dd->mtip_svc_handler) {
4083 set_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag);
4084 return rv;
4085 }
4086
4087start_service_thread:
4088 sprintf(thd_name, "mtip_svc_thd_%02d", index);
4089 dd->mtip_svc_handler = kthread_create_on_node(mtip_service_thread,
4090 dd, dd->numa_node, "%s",
4091 thd_name);
4092
4093 if (IS_ERR(dd->mtip_svc_handler)) {
4094 dev_err(&dd->pdev->dev, "service thread failed to start\n");
4095 dd->mtip_svc_handler = NULL;
4096 rv = -EFAULT;
4097 goto kthread_run_error;
4098 }
4099 wake_up_process(dd->mtip_svc_handler);
4100 if (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)
4101 rv = wait_for_rebuild;
4102
4103 return rv;
4104
4105kthread_run_error:
4106 mtip_hw_debugfs_exit(dd);
4107
4108
4109 del_gendisk(dd->disk);
4110
4111read_capacity_error:
4112 blk_cleanup_queue(dd->queue);
4113
4114block_queue_alloc_init_error:
4115disk_index_error:
4116 spin_lock(&rssd_index_lock);
4117 ida_remove(&rssd_index_ida, index);
4118 spin_unlock(&rssd_index_lock);
4119
4120ida_get_error:
4121 put_disk(dd->disk);
4122
4123alloc_disk_error:
4124 mtip_hw_exit(dd);
4125
4126protocol_init_error:
4127 return rv;
4128}
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140static int mtip_block_remove(struct driver_data *dd)
4141{
4142 struct kobject *kobj;
4143
4144 if (dd->mtip_svc_handler) {
4145 set_bit(MTIP_PF_SVC_THD_STOP_BIT, &dd->port->flags);
4146 wake_up_interruptible(&dd->port->svc_wait);
4147 kthread_stop(dd->mtip_svc_handler);
4148 }
4149
4150
4151 if (test_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag)) {
4152 kobj = kobject_get(&disk_to_dev(dd->disk)->kobj);
4153 if (kobj) {
4154 mtip_hw_sysfs_exit(dd, kobj);
4155 kobject_put(kobj);
4156 }
4157 }
4158 mtip_hw_debugfs_exit(dd);
4159
4160
4161
4162
4163
4164 if (dd->disk) {
4165 if (dd->disk->queue)
4166 del_gendisk(dd->disk);
4167 else
4168 put_disk(dd->disk);
4169 }
4170
4171 spin_lock(&rssd_index_lock);
4172 ida_remove(&rssd_index_ida, dd->index);
4173 spin_unlock(&rssd_index_lock);
4174
4175 blk_cleanup_queue(dd->queue);
4176 dd->disk = NULL;
4177 dd->queue = NULL;
4178
4179
4180 mtip_hw_exit(dd);
4181
4182 return 0;
4183}
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197static int mtip_block_shutdown(struct driver_data *dd)
4198{
4199
4200 if (dd->disk) {
4201 dev_info(&dd->pdev->dev,
4202 "Shutting down %s ...\n", dd->disk->disk_name);
4203
4204 if (dd->disk->queue) {
4205 del_gendisk(dd->disk);
4206 blk_cleanup_queue(dd->queue);
4207 } else
4208 put_disk(dd->disk);
4209 dd->disk = NULL;
4210 dd->queue = NULL;
4211 }
4212
4213 spin_lock(&rssd_index_lock);
4214 ida_remove(&rssd_index_ida, dd->index);
4215 spin_unlock(&rssd_index_lock);
4216
4217 mtip_hw_shutdown(dd);
4218 return 0;
4219}
4220
4221static int mtip_block_suspend(struct driver_data *dd)
4222{
4223 dev_info(&dd->pdev->dev,
4224 "Suspending %s ...\n", dd->disk->disk_name);
4225 mtip_hw_suspend(dd);
4226 return 0;
4227}
4228
4229static int mtip_block_resume(struct driver_data *dd)
4230{
4231 dev_info(&dd->pdev->dev, "Resuming %s ...\n",
4232 dd->disk->disk_name);
4233 mtip_hw_resume(dd);
4234 return 0;
4235}
4236
4237static void drop_cpu(int cpu)
4238{
4239 cpu_use[cpu]--;
4240}
4241
4242static int get_least_used_cpu_on_node(int node)
4243{
4244 int cpu, least_used_cpu, least_cnt;
4245 const struct cpumask *node_mask;
4246
4247 node_mask = cpumask_of_node(node);
4248 least_used_cpu = cpumask_first(node_mask);
4249 least_cnt = cpu_use[least_used_cpu];
4250 cpu = least_used_cpu;
4251
4252 for_each_cpu(cpu, node_mask) {
4253 if (cpu_use[cpu] < least_cnt) {
4254 least_used_cpu = cpu;
4255 least_cnt = cpu_use[cpu];
4256 }
4257 }
4258 cpu_use[least_used_cpu]++;
4259 return least_used_cpu;
4260}
4261
4262
4263static inline int mtip_get_next_rr_node(void)
4264{
4265 static int next_node = -1;
4266
4267 if (next_node == -1) {
4268 next_node = first_online_node;
4269 return next_node;
4270 }
4271
4272 next_node = next_online_node(next_node);
4273 if (next_node == MAX_NUMNODES)
4274 next_node = first_online_node;
4275 return next_node;
4276}
4277
4278static DEFINE_HANDLER(0);
4279static DEFINE_HANDLER(1);
4280static DEFINE_HANDLER(2);
4281static DEFINE_HANDLER(3);
4282static DEFINE_HANDLER(4);
4283static DEFINE_HANDLER(5);
4284static DEFINE_HANDLER(6);
4285static DEFINE_HANDLER(7);
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296static int mtip_pci_probe(struct pci_dev *pdev,
4297 const struct pci_device_id *ent)
4298{
4299 int rv = 0;
4300 struct driver_data *dd = NULL;
4301 char cpu_list[256];
4302 const struct cpumask *node_mask;
4303 int cpu, i = 0, j = 0;
4304 int my_node = NUMA_NO_NODE;
4305 unsigned long flags;
4306
4307
4308 my_node = pcibus_to_node(pdev->bus);
4309 if (my_node != NUMA_NO_NODE) {
4310 if (!node_online(my_node))
4311 my_node = mtip_get_next_rr_node();
4312 } else {
4313 dev_info(&pdev->dev, "Kernel not reporting proximity, choosing a node\n");
4314 my_node = mtip_get_next_rr_node();
4315 }
4316 dev_info(&pdev->dev, "NUMA node %d (closest: %d,%d, probe on %d:%d)\n",
4317 my_node, pcibus_to_node(pdev->bus), dev_to_node(&pdev->dev),
4318 cpu_to_node(smp_processor_id()), smp_processor_id());
4319
4320 dd = kzalloc_node(sizeof(struct driver_data), GFP_KERNEL, my_node);
4321 if (dd == NULL) {
4322 dev_err(&pdev->dev,
4323 "Unable to allocate memory for driver data\n");
4324 return -ENOMEM;
4325 }
4326
4327
4328 pci_set_drvdata(pdev, dd);
4329
4330 rv = pcim_enable_device(pdev);
4331 if (rv < 0) {
4332 dev_err(&pdev->dev, "Unable to enable device\n");
4333 goto iomap_err;
4334 }
4335
4336
4337 rv = pcim_iomap_regions(pdev, 1 << MTIP_ABAR, MTIP_DRV_NAME);
4338 if (rv < 0) {
4339 dev_err(&pdev->dev, "Unable to map regions\n");
4340 goto iomap_err;
4341 }
4342
4343 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4344 rv = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4345
4346 if (rv) {
4347 rv = pci_set_consistent_dma_mask(pdev,
4348 DMA_BIT_MASK(32));
4349 if (rv) {
4350 dev_warn(&pdev->dev,
4351 "64-bit DMA enable failed\n");
4352 goto setmask_err;
4353 }
4354 }
4355 }
4356
4357
4358 dd->major = mtip_major;
4359 dd->instance = instance;
4360 dd->pdev = pdev;
4361 dd->numa_node = my_node;
4362
4363 INIT_LIST_HEAD(&dd->online_list);
4364 INIT_LIST_HEAD(&dd->remove_list);
4365
4366 memset(dd->workq_name, 0, 32);
4367 snprintf(dd->workq_name, 31, "mtipq%d", dd->instance);
4368
4369 dd->isr_workq = create_workqueue(dd->workq_name);
4370 if (!dd->isr_workq) {
4371 dev_warn(&pdev->dev, "Can't create wq %d\n", dd->instance);
4372 rv = -ENOMEM;
4373 goto block_initialize_err;
4374 }
4375
4376 memset(cpu_list, 0, sizeof(cpu_list));
4377
4378 node_mask = cpumask_of_node(dd->numa_node);
4379 if (!cpumask_empty(node_mask)) {
4380 for_each_cpu(cpu, node_mask)
4381 {
4382 snprintf(&cpu_list[j], 256 - j, "%d ", cpu);
4383 j = strlen(cpu_list);
4384 }
4385
4386 dev_info(&pdev->dev, "Node %d on package %d has %d cpu(s): %s\n",
4387 dd->numa_node,
4388 topology_physical_package_id(cpumask_first(node_mask)),
4389 nr_cpus_node(dd->numa_node),
4390 cpu_list);
4391 } else
4392 dev_dbg(&pdev->dev, "mtip32xx: node_mask empty\n");
4393
4394 dd->isr_binding = get_least_used_cpu_on_node(dd->numa_node);
4395 dev_info(&pdev->dev, "Initial IRQ binding node:cpu %d:%d\n",
4396 cpu_to_node(dd->isr_binding), dd->isr_binding);
4397
4398
4399 dd->work[0].cpu_binding = dd->isr_binding;
4400 dd->work[1].cpu_binding = get_least_used_cpu_on_node(dd->numa_node);
4401 dd->work[2].cpu_binding = get_least_used_cpu_on_node(dd->numa_node);
4402 dd->work[3].cpu_binding = dd->work[0].cpu_binding;
4403 dd->work[4].cpu_binding = dd->work[1].cpu_binding;
4404 dd->work[5].cpu_binding = dd->work[2].cpu_binding;
4405 dd->work[6].cpu_binding = dd->work[2].cpu_binding;
4406 dd->work[7].cpu_binding = dd->work[1].cpu_binding;
4407
4408
4409 for_each_present_cpu(cpu) {
4410 memset(cpu_list, 0, sizeof(cpu_list));
4411 for (i = 0, j = 0; i < MTIP_MAX_SLOT_GROUPS; i++) {
4412 if (dd->work[i].cpu_binding == cpu) {
4413 snprintf(&cpu_list[j], 256 - j, "%d ", i);
4414 j = strlen(cpu_list);
4415 }
4416 }
4417 if (j)
4418 dev_info(&pdev->dev, "CPU %d: WQs %s\n", cpu, cpu_list);
4419 }
4420
4421 INIT_WORK(&dd->work[0].work, mtip_workq_sdbf0);
4422 INIT_WORK(&dd->work[1].work, mtip_workq_sdbf1);
4423 INIT_WORK(&dd->work[2].work, mtip_workq_sdbf2);
4424 INIT_WORK(&dd->work[3].work, mtip_workq_sdbf3);
4425 INIT_WORK(&dd->work[4].work, mtip_workq_sdbf4);
4426 INIT_WORK(&dd->work[5].work, mtip_workq_sdbf5);
4427 INIT_WORK(&dd->work[6].work, mtip_workq_sdbf6);
4428 INIT_WORK(&dd->work[7].work, mtip_workq_sdbf7);
4429
4430 pci_set_master(pdev);
4431 rv = pci_enable_msi(pdev);
4432 if (rv) {
4433 dev_warn(&pdev->dev,
4434 "Unable to enable MSI interrupt.\n");
4435 goto block_initialize_err;
4436 }
4437
4438
4439 rv = mtip_block_initialize(dd);
4440 if (rv < 0) {
4441 dev_err(&pdev->dev,
4442 "Unable to initialize block layer\n");
4443 goto block_initialize_err;
4444 }
4445
4446
4447
4448
4449
4450 instance++;
4451 if (rv != MTIP_FTL_REBUILD_MAGIC)
4452 set_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag);
4453 else
4454 rv = 0;
4455
4456
4457 spin_lock_irqsave(&dev_lock, flags);
4458 list_add(&dd->online_list, &online_list);
4459 spin_unlock_irqrestore(&dev_lock, flags);
4460
4461 goto done;
4462
4463block_initialize_err:
4464 pci_disable_msi(pdev);
4465 if (dd->isr_workq) {
4466 flush_workqueue(dd->isr_workq);
4467 destroy_workqueue(dd->isr_workq);
4468 drop_cpu(dd->work[0].cpu_binding);
4469 drop_cpu(dd->work[1].cpu_binding);
4470 drop_cpu(dd->work[2].cpu_binding);
4471 }
4472setmask_err:
4473 pcim_iounmap_regions(pdev, 1 << MTIP_ABAR);
4474
4475iomap_err:
4476 kfree(dd);
4477 pci_set_drvdata(pdev, NULL);
4478 return rv;
4479done:
4480 return rv;
4481}
4482
4483
4484
4485
4486
4487
4488
4489
4490static void mtip_pci_remove(struct pci_dev *pdev)
4491{
4492 struct driver_data *dd = pci_get_drvdata(pdev);
4493 int counter = 0;
4494 unsigned long flags;
4495
4496 set_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag);
4497
4498 spin_lock_irqsave(&dev_lock, flags);
4499 list_del_init(&dd->online_list);
4500 list_add(&dd->remove_list, &removing_list);
4501 spin_unlock_irqrestore(&dev_lock, flags);
4502
4503 if (mtip_check_surprise_removal(pdev)) {
4504 while (!test_bit(MTIP_DDF_CLEANUP_BIT, &dd->dd_flag)) {
4505 counter++;
4506 msleep(20);
4507 if (counter == 10) {
4508
4509 mtip_command_cleanup(dd);
4510 break;
4511 }
4512 }
4513 }
4514
4515
4516 mtip_block_remove(dd);
4517
4518 if (dd->isr_workq) {
4519 flush_workqueue(dd->isr_workq);
4520 destroy_workqueue(dd->isr_workq);
4521 drop_cpu(dd->work[0].cpu_binding);
4522 drop_cpu(dd->work[1].cpu_binding);
4523 drop_cpu(dd->work[2].cpu_binding);
4524 }
4525
4526 pci_disable_msi(pdev);
4527
4528 spin_lock_irqsave(&dev_lock, flags);
4529 list_del_init(&dd->remove_list);
4530 spin_unlock_irqrestore(&dev_lock, flags);
4531
4532 kfree(dd);
4533 pcim_iounmap_regions(pdev, 1 << MTIP_ABAR);
4534}
4535
4536
4537
4538
4539
4540
4541
4542
4543static int mtip_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
4544{
4545 int rv = 0;
4546 struct driver_data *dd = pci_get_drvdata(pdev);
4547
4548 if (!dd) {
4549 dev_err(&pdev->dev,
4550 "Driver private datastructure is NULL\n");
4551 return -EFAULT;
4552 }
4553
4554 set_bit(MTIP_DDF_RESUME_BIT, &dd->dd_flag);
4555
4556
4557 rv = mtip_block_suspend(dd);
4558 if (rv < 0) {
4559 dev_err(&pdev->dev,
4560 "Failed to suspend controller\n");
4561 return rv;
4562 }
4563
4564
4565
4566
4567
4568 pci_save_state(pdev);
4569 pci_disable_device(pdev);
4570
4571
4572 pci_set_power_state(pdev, PCI_D3hot);
4573
4574 return rv;
4575}
4576
4577
4578
4579
4580
4581
4582
4583
4584static int mtip_pci_resume(struct pci_dev *pdev)
4585{
4586 int rv = 0;
4587 struct driver_data *dd;
4588
4589 dd = pci_get_drvdata(pdev);
4590 if (!dd) {
4591 dev_err(&pdev->dev,
4592 "Driver private datastructure is NULL\n");
4593 return -EFAULT;
4594 }
4595
4596
4597 pci_set_power_state(pdev, PCI_D0);
4598
4599
4600 pci_restore_state(pdev);
4601
4602
4603 rv = pcim_enable_device(pdev);
4604 if (rv < 0) {
4605 dev_err(&pdev->dev,
4606 "Failed to enable card during resume\n");
4607 goto err;
4608 }
4609 pci_set_master(pdev);
4610
4611
4612
4613
4614
4615 rv = mtip_block_resume(dd);
4616 if (rv < 0)
4617 dev_err(&pdev->dev, "Unable to resume\n");
4618
4619err:
4620 clear_bit(MTIP_DDF_RESUME_BIT, &dd->dd_flag);
4621
4622 return rv;
4623}
4624
4625
4626
4627
4628
4629
4630
4631static void mtip_pci_shutdown(struct pci_dev *pdev)
4632{
4633 struct driver_data *dd = pci_get_drvdata(pdev);
4634 if (dd)
4635 mtip_block_shutdown(dd);
4636}
4637
4638
4639static DEFINE_PCI_DEVICE_TABLE(mtip_pci_tbl) = {
4640 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320H_DEVICE_ID) },
4641 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320M_DEVICE_ID) },
4642 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320S_DEVICE_ID) },
4643 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P325M_DEVICE_ID) },
4644 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P420H_DEVICE_ID) },
4645 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P420M_DEVICE_ID) },
4646 { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P425M_DEVICE_ID) },
4647 { 0 }
4648};
4649
4650
4651static struct pci_driver mtip_pci_driver = {
4652 .name = MTIP_DRV_NAME,
4653 .id_table = mtip_pci_tbl,
4654 .probe = mtip_pci_probe,
4655 .remove = mtip_pci_remove,
4656 .suspend = mtip_pci_suspend,
4657 .resume = mtip_pci_resume,
4658 .shutdown = mtip_pci_shutdown,
4659};
4660
4661MODULE_DEVICE_TABLE(pci, mtip_pci_tbl);
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673static int __init mtip_init(void)
4674{
4675 int error;
4676
4677 pr_info(MTIP_DRV_NAME " Version " MTIP_DRV_VERSION "\n");
4678
4679 spin_lock_init(&dev_lock);
4680
4681 INIT_LIST_HEAD(&online_list);
4682 INIT_LIST_HEAD(&removing_list);
4683
4684
4685 error = register_blkdev(0, MTIP_DRV_NAME);
4686 if (error <= 0) {
4687 pr_err("Unable to register block device (%d)\n",
4688 error);
4689 return -EBUSY;
4690 }
4691 mtip_major = error;
4692
4693 dfs_parent = debugfs_create_dir("rssd", NULL);
4694 if (IS_ERR_OR_NULL(dfs_parent)) {
4695 pr_warn("Error creating debugfs parent\n");
4696 dfs_parent = NULL;
4697 }
4698 if (dfs_parent) {
4699 dfs_device_status = debugfs_create_file("device_status",
4700 S_IRUGO, dfs_parent, NULL,
4701 &mtip_device_status_fops);
4702 if (IS_ERR_OR_NULL(dfs_device_status)) {
4703 pr_err("Error creating device_status node\n");
4704 dfs_device_status = NULL;
4705 }
4706 }
4707
4708
4709 error = pci_register_driver(&mtip_pci_driver);
4710 if (error) {
4711 debugfs_remove(dfs_parent);
4712 unregister_blkdev(mtip_major, MTIP_DRV_NAME);
4713 }
4714
4715 return error;
4716}
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728static void __exit mtip_exit(void)
4729{
4730 debugfs_remove_recursive(dfs_parent);
4731
4732
4733 unregister_blkdev(mtip_major, MTIP_DRV_NAME);
4734
4735
4736 pci_unregister_driver(&mtip_pci_driver);
4737}
4738
4739MODULE_AUTHOR("Micron Technology, Inc");
4740MODULE_DESCRIPTION("Micron RealSSD PCIe Block Driver");
4741MODULE_LICENSE("GPL");
4742MODULE_VERSION(MTIP_DRV_VERSION);
4743
4744module_init(mtip_init);
4745module_exit(mtip_exit);
4746