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7#ifndef REGS_H
8#define REGS_H
9
10#include <linux/types.h>
11#include <linux/io.h>
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68#ifdef __BIG_ENDIAN
69#define wr_reg32(reg, data) out_be32(reg, data)
70#define rd_reg32(reg) in_be32(reg)
71#ifdef CONFIG_64BIT
72#define wr_reg64(reg, data) out_be64(reg, data)
73#define rd_reg64(reg) in_be64(reg)
74#endif
75#else
76#ifdef __LITTLE_ENDIAN
77#define wr_reg32(reg, data) __raw_writel(reg, data)
78#define rd_reg32(reg) __raw_readl(reg)
79#ifdef CONFIG_64BIT
80#define wr_reg64(reg, data) __raw_writeq(reg, data)
81#define rd_reg64(reg) __raw_readq(reg)
82#endif
83#endif
84#endif
85
86#ifndef CONFIG_64BIT
87static inline void wr_reg64(u64 __iomem *reg, u64 data)
88{
89 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
90 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
91}
92
93static inline u64 rd_reg64(u64 __iomem *reg)
94{
95 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
96 ((u64)rd_reg32((u32 __iomem *)reg + 1));
97}
98#endif
99
100
101
102
103
104struct jr_outentry {
105 dma_addr_t desc;
106 u32 jrstatus;
107} __packed;
108
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116
117#define CHA_NUM_DECONUM_SHIFT 56
118#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
119
120
121#define CHA_ID_AES_SHIFT 0
122#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
123
124#define CHA_ID_DES_SHIFT 4
125#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
126
127#define CHA_ID_ARC4_SHIFT 8
128#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
129
130#define CHA_ID_MD_SHIFT 12
131#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
132
133#define CHA_ID_RNG_SHIFT 16
134#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
135
136#define CHA_ID_SNW8_SHIFT 20
137#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
138
139#define CHA_ID_KAS_SHIFT 24
140#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
141
142#define CHA_ID_PK_SHIFT 28
143#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
144
145#define CHA_ID_CRC_SHIFT 32
146#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
147
148#define CHA_ID_SNW9_SHIFT 36
149#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
150
151#define CHA_ID_DECO_SHIFT 56
152#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
153
154#define CHA_ID_JR_SHIFT 60
155#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
156
157struct sec_vid {
158 u16 ip_id;
159 u8 maj_rev;
160 u8 min_rev;
161};
162
163struct caam_perfmon {
164
165 u64 req_dequeued;
166 u64 ob_enc_req;
167 u64 ib_dec_req;
168 u64 ob_enc_bytes;
169 u64 ob_prot_bytes;
170 u64 ib_dec_bytes;
171 u64 ib_valid_bytes;
172 u64 rsvd[13];
173
174
175 u64 cha_rev;
176#define CTPR_QI_SHIFT 57
177#define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
178 u64 comp_parms;
179 u64 rsvd1[2];
180
181
182 u64 faultaddr;
183 u32 faultliodn;
184 u32 faultdetail;
185 u32 rsvd2;
186 u32 status;
187 u64 rsvd3;
188
189
190 u32 rtic_id;
191 u32 ccb_id;
192 u64 cha_id;
193 u64 cha_num;
194 u64 caam_id;
195};
196
197
198#define MSTRID_LOCK_LIODN 0x80000000
199#define MSTRID_LOCK_MAKETRUSTED 0x00010000
200
201#define MSTRID_LIODN_MASK 0x0fff
202struct masterid {
203 u32 liodn_ms;
204 u32 liodn_ls;
205};
206
207
208struct partid {
209 u32 rsvd1;
210 u32 pidr;
211};
212
213
214
215struct rngtst {
216 u32 mode;
217 u32 rsvd1[3];
218 u32 reset;
219 u32 rsvd2[3];
220 u32 status;
221 u32 rsvd3;
222 u32 errstat;
223 u32 rsvd4;
224 u32 errctl;
225 u32 rsvd5;
226 u32 entropy;
227 u32 rsvd6[15];
228 u32 verifctl;
229 u32 rsvd7;
230 u32 verifstat;
231 u32 rsvd8;
232 u32 verifdata;
233 u32 rsvd9;
234 u32 xkey;
235 u32 rsvd10;
236 u32 oscctctl;
237 u32 rsvd11;
238 u32 oscct;
239 u32 rsvd12;
240 u32 oscctstat;
241 u32 rsvd13[2];
242 u32 ofifo[4];
243 u32 rsvd14[15];
244};
245
246
247struct rng4tst {
248#define RTMCTL_PRGM 0x00010000
249 u32 rtmctl;
250 u32 rtscmisc;
251 u32 rtpkrrng;
252 union {
253 u32 rtpkrmax;
254 u32 rtpkrsq;
255 };
256#define RTSDCTL_ENT_DLY_SHIFT 16
257#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
258 u32 rtsdctl;
259 union {
260 u32 rtsblim;
261 u32 rttotsam;
262 };
263 u32 rtfrqmin;
264 union {
265 u32 rtfrqmax;
266 u32 rtfrqcnt;
267 };
268 u32 rsvd1[40];
269#define RDSTA_IF0 0x00000001
270 u32 rdsta;
271 u32 rsvd2[15];
272};
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278
279#define KEK_KEY_SIZE 8
280#define TKEK_KEY_SIZE 8
281#define TDSK_KEY_SIZE 8
282
283#define DECO_RESET 1
284#define DECO_RESET_0 (DECO_RESET << 0)
285#define DECO_RESET_1 (DECO_RESET << 1)
286#define DECO_RESET_2 (DECO_RESET << 2)
287#define DECO_RESET_3 (DECO_RESET << 3)
288#define DECO_RESET_4 (DECO_RESET << 4)
289
290struct caam_ctrl {
291
292
293 u32 rsvd1;
294 u32 mcr;
295 u32 rsvd2;
296 u32 scfgr;
297
298
299
300 struct masterid jr_mid[4];
301 u32 rsvd3[12];
302 struct masterid rtic_mid[4];
303 u32 rsvd4[7];
304 u32 deco_rq;
305 struct partid deco_mid[5];
306 u32 rsvd5[22];
307
308
309 u32 deco_avail;
310 u32 deco_reset;
311 u32 rsvd6[182];
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315 u32 kek[KEK_KEY_SIZE];
316 u32 tkek[TKEK_KEY_SIZE];
317 u32 tdsk[TDSK_KEY_SIZE];
318 u32 rsvd7[32];
319 u64 sknonce;
320 u32 rsvd8[70];
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322
323
324 union {
325 struct rngtst rtst[2];
326 struct rng4tst r4tst[2];
327 };
328
329 u32 rsvd9[448];
330
331
332 struct caam_perfmon perfmon;
333};
334
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336
337
338#define MCFGR_SWRESET 0x80000000
339#define MCFGR_WDENABLE 0x40000000
340#define MCFGR_WDFAIL 0x20000000
341#define MCFGR_DMA_RESET 0x10000000
342#define MCFGR_LONG_PTR 0x00010000
343#define SCFGR_RDBENABLE 0x00000400
344
345
346#define MCFGR_ARCACHE_SHIFT 12
347#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
348
349
350#define MCFGR_AWCACHE_SHIFT 8
351#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
352
353
354#define MCFGR_AXIPIPE_SHIFT 4
355#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
356
357#define MCFGR_AXIPRI 0x00000008
358#define MCFGR_BURST_64 0x00000001
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364
365struct caam_job_ring {
366
367 u64 inpring_base;
368 u32 rsvd1;
369 u32 inpring_size;
370 u32 rsvd2;
371 u32 inpring_avail;
372 u32 rsvd3;
373 u32 inpring_jobadd;
374
375
376 u64 outring_base;
377 u32 rsvd4;
378 u32 outring_size;
379 u32 rsvd5;
380 u32 outring_rmvd;
381 u32 rsvd6;
382 u32 outring_used;
383
384
385 u32 rsvd7;
386 u32 jroutstatus;
387 u32 rsvd8;
388 u32 jrintstatus;
389 u32 rconfig_hi;
390 u32 rconfig_lo;
391
392
393 u32 rsvd9;
394 u32 inp_rdidx;
395 u32 rsvd10;
396 u32 out_wtidx;
397
398
399 u32 rsvd11;
400 u32 jrcommand;
401
402 u32 rsvd12[932];
403
404
405 struct caam_perfmon perfmon;
406};
407
408#define JR_RINGSIZE_MASK 0x03ff
409
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414
415#define JRSTA_SSRC_SHIFT 28
416#define JRSTA_SSRC_MASK 0xf0000000
417
418#define JRSTA_SSRC_NONE 0x00000000
419#define JRSTA_SSRC_CCB_ERROR 0x20000000
420#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
421#define JRSTA_SSRC_DECO 0x40000000
422#define JRSTA_SSRC_JRERROR 0x60000000
423#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
424
425#define JRSTA_DECOERR_JUMP 0x08000000
426#define JRSTA_DECOERR_INDEX_SHIFT 8
427#define JRSTA_DECOERR_INDEX_MASK 0xff00
428#define JRSTA_DECOERR_ERROR_MASK 0x00ff
429
430#define JRSTA_DECOERR_NONE 0x00
431#define JRSTA_DECOERR_LINKLEN 0x01
432#define JRSTA_DECOERR_LINKPTR 0x02
433#define JRSTA_DECOERR_JRCTRL 0x03
434#define JRSTA_DECOERR_DESCCMD 0x04
435#define JRSTA_DECOERR_ORDER 0x05
436#define JRSTA_DECOERR_KEYCMD 0x06
437#define JRSTA_DECOERR_LOADCMD 0x07
438#define JRSTA_DECOERR_STORECMD 0x08
439#define JRSTA_DECOERR_OPCMD 0x09
440#define JRSTA_DECOERR_FIFOLDCMD 0x0a
441#define JRSTA_DECOERR_FIFOSTCMD 0x0b
442#define JRSTA_DECOERR_MOVECMD 0x0c
443#define JRSTA_DECOERR_JUMPCMD 0x0d
444#define JRSTA_DECOERR_MATHCMD 0x0e
445#define JRSTA_DECOERR_SHASHCMD 0x0f
446#define JRSTA_DECOERR_SEQCMD 0x10
447#define JRSTA_DECOERR_DECOINTERNAL 0x11
448#define JRSTA_DECOERR_SHDESCHDR 0x12
449#define JRSTA_DECOERR_HDRLEN 0x13
450#define JRSTA_DECOERR_BURSTER 0x14
451#define JRSTA_DECOERR_DESCSIGNATURE 0x15
452#define JRSTA_DECOERR_DMA 0x16
453#define JRSTA_DECOERR_BURSTFIFO 0x17
454#define JRSTA_DECOERR_JRRESET 0x1a
455#define JRSTA_DECOERR_JOBFAIL 0x1b
456#define JRSTA_DECOERR_DNRERR 0x80
457#define JRSTA_DECOERR_UNDEFPCL 0x81
458#define JRSTA_DECOERR_PDBERR 0x82
459#define JRSTA_DECOERR_ANRPLY_LATE 0x83
460#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
461#define JRSTA_DECOERR_SEQOVF 0x85
462#define JRSTA_DECOERR_INVSIGN 0x86
463#define JRSTA_DECOERR_DSASIGN 0x87
464
465#define JRSTA_CCBERR_JUMP 0x08000000
466#define JRSTA_CCBERR_INDEX_MASK 0xff00
467#define JRSTA_CCBERR_INDEX_SHIFT 8
468#define JRSTA_CCBERR_CHAID_MASK 0x00f0
469#define JRSTA_CCBERR_CHAID_SHIFT 4
470#define JRSTA_CCBERR_ERRID_MASK 0x000f
471
472#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
473#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
474#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
475#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
476#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
477#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
478#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
479#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
480#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
481
482#define JRSTA_CCBERR_ERRID_NONE 0x00
483#define JRSTA_CCBERR_ERRID_MODE 0x01
484#define JRSTA_CCBERR_ERRID_DATASIZ 0x02
485#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
486#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
487#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
488#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
489#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
490#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
491#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
492#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
493#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
494#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
495#define JRSTA_CCBERR_ERRID_INVCHA 0x0f
496
497#define JRINT_ERR_INDEX_MASK 0x3fff0000
498#define JRINT_ERR_INDEX_SHIFT 16
499#define JRINT_ERR_TYPE_MASK 0xf00
500#define JRINT_ERR_TYPE_SHIFT 8
501#define JRINT_ERR_HALT_MASK 0xc
502#define JRINT_ERR_HALT_SHIFT 2
503#define JRINT_ERR_HALT_INPROGRESS 0x4
504#define JRINT_ERR_HALT_COMPLETE 0x8
505#define JRINT_JR_ERROR 0x02
506#define JRINT_JR_INT 0x01
507
508#define JRINT_ERR_TYPE_WRITE 1
509#define JRINT_ERR_TYPE_BAD_INPADDR 3
510#define JRINT_ERR_TYPE_BAD_OUTADDR 4
511#define JRINT_ERR_TYPE_INV_INPWRT 5
512#define JRINT_ERR_TYPE_INV_OUTWRT 6
513#define JRINT_ERR_TYPE_RESET 7
514#define JRINT_ERR_TYPE_REMOVE_OFL 8
515#define JRINT_ERR_TYPE_ADD_OFL 9
516
517#define JRCFG_SOE 0x04
518#define JRCFG_ICEN 0x02
519#define JRCFG_IMSK 0x01
520#define JRCFG_ICDCT_SHIFT 8
521#define JRCFG_ICTT_SHIFT 16
522
523#define JRCR_RESET 0x01
524
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527
528
529
530struct rtic_element {
531 u64 address;
532 u32 rsvd;
533 u32 length;
534};
535
536struct rtic_block {
537 struct rtic_element element[2];
538};
539
540struct rtic_memhash {
541 u32 memhash_be[32];
542 u32 memhash_le[32];
543};
544
545struct caam_assurance {
546
547 u32 rsvd1;
548 u32 status;
549 u32 rsvd2;
550 u32 cmd;
551 u32 rsvd3;
552 u32 ctrl;
553 u32 rsvd4;
554 u32 throttle;
555 u32 rsvd5[2];
556 u64 watchdog;
557 u32 rsvd6;
558 u32 rend;
559 u32 rsvd7[50];
560
561
562 struct rtic_block memblk[4];
563 u32 rsvd8[32];
564
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566 struct rtic_memhash hash[4];
567 u32 rsvd_3[640];
568};
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574
575struct caam_queue_if {
576 u32 qi_control_hi;
577 u32 qi_control_lo;
578 u32 rsvd1;
579 u32 qi_status;
580 u32 qi_deq_cfg_hi;
581 u32 qi_deq_cfg_lo;
582 u32 qi_enq_cfg_hi;
583 u32 qi_enq_cfg_lo;
584 u32 rsvd2[1016];
585};
586
587
588#define QICTL_DQEN 0x01
589#define QICTL_STOP 0x02
590#define QICTL_SOE 0x04
591
592
593#define QICTL_MBSI 0x01
594#define QICTL_MHWSI 0x02
595#define QICTL_MWSI 0x04
596#define QICTL_MDWSI 0x08
597#define QICTL_CBSI 0x10
598#define QICTL_CHWSI 0x20
599#define QICTL_CWSI 0x40
600#define QICTL_CDWSI 0x80
601#define QICTL_MBSO 0x0100
602#define QICTL_MHWSO 0x0200
603#define QICTL_MWSO 0x0400
604#define QICTL_MDWSO 0x0800
605#define QICTL_CBSO 0x1000
606#define QICTL_CHWSO 0x2000
607#define QICTL_CWSO 0x4000
608#define QICTL_CDWSO 0x8000
609#define QICTL_DMBS 0x010000
610#define QICTL_EPO 0x020000
611
612
613#define QISTA_PHRDERR 0x01
614#define QISTA_CFRDERR 0x02
615#define QISTA_OFWRERR 0x04
616#define QISTA_BPDERR 0x08
617#define QISTA_BTSERR 0x10
618#define QISTA_CFWRERR 0x20
619#define QISTA_STOPD 0x80000000
620
621
622struct deco_sg_table {
623 u64 addr;
624 u32 elen;
625 u32 bpid_offset;
626};
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636
637struct caam_deco {
638 u32 rsvd1;
639 u32 cls1_mode;
640 u32 rsvd2;
641 u32 cls1_keysize;
642 u32 cls1_datasize_hi;
643 u32 cls1_datasize_lo;
644 u32 rsvd3;
645 u32 cls1_icvsize;
646 u32 rsvd4[5];
647 u32 cha_ctrl;
648 u32 rsvd5;
649 u32 irq_crtl;
650 u32 rsvd6;
651 u32 clr_written;
652 u32 ccb_status_hi;
653 u32 ccb_status_lo;
654 u32 rsvd7[3];
655 u32 aad_size;
656 u32 rsvd8;
657 u32 cls1_iv_size;
658 u32 rsvd9[7];
659 u32 pkha_a_size;
660 u32 rsvd10;
661 u32 pkha_b_size;
662 u32 rsvd11;
663 u32 pkha_n_size;
664 u32 rsvd12;
665 u32 pkha_e_size;
666 u32 rsvd13[24];
667 u32 cls1_ctx[16];
668 u32 rsvd14[48];
669 u32 cls1_key[8];
670 u32 rsvd15[121];
671 u32 cls2_mode;
672 u32 rsvd16;
673 u32 cls2_keysize;
674 u32 cls2_datasize_hi;
675 u32 cls2_datasize_lo;
676 u32 rsvd17;
677 u32 cls2_icvsize;
678 u32 rsvd18[56];
679 u32 cls2_ctx[18];
680 u32 rsvd19[46];
681 u32 cls2_key[32];
682 u32 rsvd20[84];
683 u32 inp_infofifo_hi;
684 u32 inp_infofifo_lo;
685 u32 rsvd21[2];
686 u64 inp_datafifo;
687 u32 rsvd22[2];
688 u64 out_datafifo;
689 u32 rsvd23[2];
690 u32 jr_ctl_hi;
691 u32 jr_ctl_lo;
692 u64 jr_descaddr;
693 u32 op_status_hi;
694 u32 op_status_lo;
695 u32 rsvd24[2];
696 u32 liodn;
697 u32 td_liodn;
698 u32 rsvd26[6];
699 u64 math[4];
700 u32 rsvd27[8];
701 struct deco_sg_table gthr_tbl[4];
702 u32 rsvd28[16];
703 struct deco_sg_table sctr_tbl[4];
704 u32 rsvd29[48];
705 u32 descbuf[64];
706 u32 rsvd30[320];
707};
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730struct caam_full {
731 struct caam_ctrl __iomem ctrl;
732 struct caam_job_ring jr[4];
733 u64 rsvd[512];
734 struct caam_assurance assure;
735 struct caam_queue_if qi;
736};
737
738#endif
739