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13#include <linux/bitops.h>
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/dmapool.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26
27#include "../dmaengine.h"
28#include "internal.h"
29
30
31
32
33
34
35
36
37
38
39
40static inline void dwc_set_masters(struct dw_dma_chan *dwc)
41{
42 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
43 struct dw_dma_slave *dws = dwc->chan.private;
44 unsigned char mmax = dw->nr_masters - 1;
45
46 if (dwc->request_line == ~0) {
47 dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
48 dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
49 }
50}
51
52#define DWC_DEFAULT_CTLLO(_chan) ({ \
53 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
54 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
55 bool _is_slave = is_slave_direction(_dwc->direction); \
56 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
57 DW_DMA_MSIZE_16; \
58 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
59 DW_DMA_MSIZE_16; \
60 \
61 (DWC_CTLL_DST_MSIZE(_dmsize) \
62 | DWC_CTLL_SRC_MSIZE(_smsize) \
63 | DWC_CTLL_LLP_D_EN \
64 | DWC_CTLL_LLP_S_EN \
65 | DWC_CTLL_DMS(_dwc->dst_master) \
66 | DWC_CTLL_SMS(_dwc->src_master)); \
67 })
68
69
70
71
72
73
74#define NR_DESCS_PER_CHANNEL 64
75
76
77
78static struct device *chan2dev(struct dma_chan *chan)
79{
80 return &chan->dev->device;
81}
82static struct device *chan2parent(struct dma_chan *chan)
83{
84 return chan->dev->device.parent;
85}
86
87static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
88{
89 return to_dw_desc(dwc->active_list.next);
90}
91
92static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
93{
94 struct dw_desc *desc, *_desc;
95 struct dw_desc *ret = NULL;
96 unsigned int i = 0;
97 unsigned long flags;
98
99 spin_lock_irqsave(&dwc->lock, flags);
100 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
101 i++;
102 if (async_tx_test_ack(&desc->txd)) {
103 list_del(&desc->desc_node);
104 ret = desc;
105 break;
106 }
107 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
108 }
109 spin_unlock_irqrestore(&dwc->lock, flags);
110
111 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
112
113 return ret;
114}
115
116
117
118
119
120static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
121{
122 unsigned long flags;
123
124 if (desc) {
125 struct dw_desc *child;
126
127 spin_lock_irqsave(&dwc->lock, flags);
128 list_for_each_entry(child, &desc->tx_list, desc_node)
129 dev_vdbg(chan2dev(&dwc->chan),
130 "moving child desc %p to freelist\n",
131 child);
132 list_splice_init(&desc->tx_list, &dwc->free_list);
133 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
134 list_add(&desc->desc_node, &dwc->free_list);
135 spin_unlock_irqrestore(&dwc->lock, flags);
136 }
137}
138
139static void dwc_initialize(struct dw_dma_chan *dwc)
140{
141 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
142 struct dw_dma_slave *dws = dwc->chan.private;
143 u32 cfghi = DWC_CFGH_FIFO_MODE;
144 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
145
146 if (dwc->initialized == true)
147 return;
148
149 if (dws) {
150
151
152
153
154 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
155
156 cfghi = dws->cfg_hi;
157 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
158 } else {
159 if (dwc->direction == DMA_MEM_TO_DEV)
160 cfghi = DWC_CFGH_DST_PER(dwc->request_line);
161 else if (dwc->direction == DMA_DEV_TO_MEM)
162 cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
163 }
164
165 channel_writel(dwc, CFG_LO, cfglo);
166 channel_writel(dwc, CFG_HI, cfghi);
167
168
169 channel_set_bit(dw, MASK.XFER, dwc->mask);
170 channel_set_bit(dw, MASK.ERROR, dwc->mask);
171
172 dwc->initialized = true;
173}
174
175
176
177static inline unsigned int dwc_fast_fls(unsigned long long v)
178{
179
180
181
182
183 if (!(v & 7))
184 return 3;
185 else if (!(v & 3))
186 return 2;
187 else if (!(v & 1))
188 return 1;
189 return 0;
190}
191
192static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
193{
194 dev_err(chan2dev(&dwc->chan),
195 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
196 channel_readl(dwc, SAR),
197 channel_readl(dwc, DAR),
198 channel_readl(dwc, LLP),
199 channel_readl(dwc, CTL_HI),
200 channel_readl(dwc, CTL_LO));
201}
202
203static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
204{
205 channel_clear_bit(dw, CH_EN, dwc->mask);
206 while (dma_readl(dw, CH_EN) & dwc->mask)
207 cpu_relax();
208}
209
210
211
212
213static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
214 struct dw_desc *desc)
215{
216 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
217 u32 ctllo;
218
219
220
221 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
222
223 channel_writel(dwc, SAR, desc->lli.sar);
224 channel_writel(dwc, DAR, desc->lli.dar);
225 channel_writel(dwc, CTL_LO, ctllo);
226 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
227 channel_set_bit(dw, CH_EN, dwc->mask);
228
229
230 dwc->tx_node_active = dwc->tx_node_active->next;
231}
232
233
234static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
235{
236 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
237 unsigned long was_soft_llp;
238
239
240 if (dma_readl(dw, CH_EN) & dwc->mask) {
241 dev_err(chan2dev(&dwc->chan),
242 "BUG: Attempted to start non-idle channel\n");
243 dwc_dump_chan_regs(dwc);
244
245
246 return;
247 }
248
249 if (dwc->nollp) {
250 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
251 &dwc->flags);
252 if (was_soft_llp) {
253 dev_err(chan2dev(&dwc->chan),
254 "BUG: Attempted to start new LLP transfer "
255 "inside ongoing one\n");
256 return;
257 }
258
259 dwc_initialize(dwc);
260
261 dwc->residue = first->total_len;
262 dwc->tx_node_active = &first->tx_list;
263
264
265 dwc_do_single_block(dwc, first);
266
267 return;
268 }
269
270 dwc_initialize(dwc);
271
272 channel_writel(dwc, LLP, first->txd.phys);
273 channel_writel(dwc, CTL_LO,
274 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
275 channel_writel(dwc, CTL_HI, 0);
276 channel_set_bit(dw, CH_EN, dwc->mask);
277}
278
279
280
281static void
282dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
283 bool callback_required)
284{
285 dma_async_tx_callback callback = NULL;
286 void *param = NULL;
287 struct dma_async_tx_descriptor *txd = &desc->txd;
288 struct dw_desc *child;
289 unsigned long flags;
290
291 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
292
293 spin_lock_irqsave(&dwc->lock, flags);
294 dma_cookie_complete(txd);
295 if (callback_required) {
296 callback = txd->callback;
297 param = txd->callback_param;
298 }
299
300
301 list_for_each_entry(child, &desc->tx_list, desc_node)
302 async_tx_ack(&child->txd);
303 async_tx_ack(&desc->txd);
304
305 list_splice_init(&desc->tx_list, &dwc->free_list);
306 list_move(&desc->desc_node, &dwc->free_list);
307
308 if (!is_slave_direction(dwc->direction)) {
309 struct device *parent = chan2parent(&dwc->chan);
310 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
311 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
312 dma_unmap_single(parent, desc->lli.dar,
313 desc->total_len, DMA_FROM_DEVICE);
314 else
315 dma_unmap_page(parent, desc->lli.dar,
316 desc->total_len, DMA_FROM_DEVICE);
317 }
318 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
319 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
320 dma_unmap_single(parent, desc->lli.sar,
321 desc->total_len, DMA_TO_DEVICE);
322 else
323 dma_unmap_page(parent, desc->lli.sar,
324 desc->total_len, DMA_TO_DEVICE);
325 }
326 }
327
328 spin_unlock_irqrestore(&dwc->lock, flags);
329
330 if (callback)
331 callback(param);
332}
333
334static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
335{
336 struct dw_desc *desc, *_desc;
337 LIST_HEAD(list);
338 unsigned long flags;
339
340 spin_lock_irqsave(&dwc->lock, flags);
341 if (dma_readl(dw, CH_EN) & dwc->mask) {
342 dev_err(chan2dev(&dwc->chan),
343 "BUG: XFER bit set, but channel not idle!\n");
344
345
346 dwc_chan_disable(dw, dwc);
347 }
348
349
350
351
352
353 list_splice_init(&dwc->active_list, &list);
354 if (!list_empty(&dwc->queue)) {
355 list_move(dwc->queue.next, &dwc->active_list);
356 dwc_dostart(dwc, dwc_first_active(dwc));
357 }
358
359 spin_unlock_irqrestore(&dwc->lock, flags);
360
361 list_for_each_entry_safe(desc, _desc, &list, desc_node)
362 dwc_descriptor_complete(dwc, desc, true);
363}
364
365
366static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
367{
368 u32 ctlhi = channel_readl(dwc, CTL_HI);
369 u32 ctllo = channel_readl(dwc, CTL_LO);
370
371 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
372}
373
374static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
375{
376 dma_addr_t llp;
377 struct dw_desc *desc, *_desc;
378 struct dw_desc *child;
379 u32 status_xfer;
380 unsigned long flags;
381
382 spin_lock_irqsave(&dwc->lock, flags);
383 llp = channel_readl(dwc, LLP);
384 status_xfer = dma_readl(dw, RAW.XFER);
385
386 if (status_xfer & dwc->mask) {
387
388 dma_writel(dw, CLEAR.XFER, dwc->mask);
389
390 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
391 struct list_head *head, *active = dwc->tx_node_active;
392
393
394
395
396
397 desc = dwc_first_active(dwc);
398
399 head = &desc->tx_list;
400 if (active != head) {
401
402 if (active != head->next)
403 desc = to_dw_desc(active->prev);
404
405 dwc->residue -= desc->len;
406
407 child = to_dw_desc(active);
408
409
410 dwc_do_single_block(dwc, child);
411
412 spin_unlock_irqrestore(&dwc->lock, flags);
413 return;
414 }
415
416
417 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
418 }
419
420 dwc->residue = 0;
421
422 spin_unlock_irqrestore(&dwc->lock, flags);
423
424 dwc_complete_all(dw, dwc);
425 return;
426 }
427
428 if (list_empty(&dwc->active_list)) {
429 dwc->residue = 0;
430 spin_unlock_irqrestore(&dwc->lock, flags);
431 return;
432 }
433
434 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
435 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
436 spin_unlock_irqrestore(&dwc->lock, flags);
437 return;
438 }
439
440 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
441 (unsigned long long)llp);
442
443 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
444
445 dwc->residue = desc->total_len;
446
447
448 if (desc->txd.phys == llp) {
449 spin_unlock_irqrestore(&dwc->lock, flags);
450 return;
451 }
452
453
454 if (desc->lli.llp == llp) {
455
456 dwc->residue -= dwc_get_sent(dwc);
457 spin_unlock_irqrestore(&dwc->lock, flags);
458 return;
459 }
460
461 dwc->residue -= desc->len;
462 list_for_each_entry(child, &desc->tx_list, desc_node) {
463 if (child->lli.llp == llp) {
464
465 dwc->residue -= dwc_get_sent(dwc);
466 spin_unlock_irqrestore(&dwc->lock, flags);
467 return;
468 }
469 dwc->residue -= child->len;
470 }
471
472
473
474
475
476 spin_unlock_irqrestore(&dwc->lock, flags);
477 dwc_descriptor_complete(dwc, desc, true);
478 spin_lock_irqsave(&dwc->lock, flags);
479 }
480
481 dev_err(chan2dev(&dwc->chan),
482 "BUG: All descriptors done, but channel not idle!\n");
483
484
485 dwc_chan_disable(dw, dwc);
486
487 if (!list_empty(&dwc->queue)) {
488 list_move(dwc->queue.next, &dwc->active_list);
489 dwc_dostart(dwc, dwc_first_active(dwc));
490 }
491 spin_unlock_irqrestore(&dwc->lock, flags);
492}
493
494static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
495{
496 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
497 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
498}
499
500static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
501{
502 struct dw_desc *bad_desc;
503 struct dw_desc *child;
504 unsigned long flags;
505
506 dwc_scan_descriptors(dw, dwc);
507
508 spin_lock_irqsave(&dwc->lock, flags);
509
510
511
512
513
514
515 bad_desc = dwc_first_active(dwc);
516 list_del_init(&bad_desc->desc_node);
517 list_move(dwc->queue.next, dwc->active_list.prev);
518
519
520 dma_writel(dw, CLEAR.ERROR, dwc->mask);
521 if (!list_empty(&dwc->active_list))
522 dwc_dostart(dwc, dwc_first_active(dwc));
523
524
525
526
527
528
529
530
531 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
532 " cookie: %d\n", bad_desc->txd.cookie);
533 dwc_dump_lli(dwc, &bad_desc->lli);
534 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
535 dwc_dump_lli(dwc, &child->lli);
536
537 spin_unlock_irqrestore(&dwc->lock, flags);
538
539
540 dwc_descriptor_complete(dwc, bad_desc, true);
541}
542
543
544
545dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
546{
547 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
548 return channel_readl(dwc, SAR);
549}
550EXPORT_SYMBOL(dw_dma_get_src_addr);
551
552dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
553{
554 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
555 return channel_readl(dwc, DAR);
556}
557EXPORT_SYMBOL(dw_dma_get_dst_addr);
558
559
560static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
561 u32 status_err, u32 status_xfer)
562{
563 unsigned long flags;
564
565 if (dwc->mask) {
566 void (*callback)(void *param);
567 void *callback_param;
568
569 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
570 channel_readl(dwc, LLP));
571
572 callback = dwc->cdesc->period_callback;
573 callback_param = dwc->cdesc->period_callback_param;
574
575 if (callback)
576 callback(callback_param);
577 }
578
579
580
581
582
583 if (unlikely(status_err & dwc->mask) ||
584 unlikely(status_xfer & dwc->mask)) {
585 int i;
586
587 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
588 "interrupt, stopping DMA transfer\n",
589 status_xfer ? "xfer" : "error");
590
591 spin_lock_irqsave(&dwc->lock, flags);
592
593 dwc_dump_chan_regs(dwc);
594
595 dwc_chan_disable(dw, dwc);
596
597
598 channel_writel(dwc, LLP, 0);
599 channel_writel(dwc, CTL_LO, 0);
600 channel_writel(dwc, CTL_HI, 0);
601
602 dma_writel(dw, CLEAR.ERROR, dwc->mask);
603 dma_writel(dw, CLEAR.XFER, dwc->mask);
604
605 for (i = 0; i < dwc->cdesc->periods; i++)
606 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
607
608 spin_unlock_irqrestore(&dwc->lock, flags);
609 }
610}
611
612
613
614static void dw_dma_tasklet(unsigned long data)
615{
616 struct dw_dma *dw = (struct dw_dma *)data;
617 struct dw_dma_chan *dwc;
618 u32 status_xfer;
619 u32 status_err;
620 int i;
621
622 status_xfer = dma_readl(dw, RAW.XFER);
623 status_err = dma_readl(dw, RAW.ERROR);
624
625 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
626
627 for (i = 0; i < dw->dma.chancnt; i++) {
628 dwc = &dw->chan[i];
629 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
630 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
631 else if (status_err & (1 << i))
632 dwc_handle_error(dw, dwc);
633 else if (status_xfer & (1 << i))
634 dwc_scan_descriptors(dw, dwc);
635 }
636
637
638
639
640 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
641 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
642}
643
644static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
645{
646 struct dw_dma *dw = dev_id;
647 u32 status;
648
649 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
650 dma_readl(dw, STATUS_INT));
651
652
653
654
655
656 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
657 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
658
659 status = dma_readl(dw, STATUS_INT);
660 if (status) {
661 dev_err(dw->dma.dev,
662 "BUG: Unexpected interrupts pending: 0x%x\n",
663 status);
664
665
666 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
667 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
668 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
669 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
670 }
671
672 tasklet_schedule(&dw->tasklet);
673
674 return IRQ_HANDLED;
675}
676
677
678
679static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
680{
681 struct dw_desc *desc = txd_to_dw_desc(tx);
682 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
683 dma_cookie_t cookie;
684 unsigned long flags;
685
686 spin_lock_irqsave(&dwc->lock, flags);
687 cookie = dma_cookie_assign(tx);
688
689
690
691
692
693
694 if (list_empty(&dwc->active_list)) {
695 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
696 desc->txd.cookie);
697 list_add_tail(&desc->desc_node, &dwc->active_list);
698 dwc_dostart(dwc, dwc_first_active(dwc));
699 } else {
700 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
701 desc->txd.cookie);
702
703 list_add_tail(&desc->desc_node, &dwc->queue);
704 }
705
706 spin_unlock_irqrestore(&dwc->lock, flags);
707
708 return cookie;
709}
710
711static struct dma_async_tx_descriptor *
712dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
713 size_t len, unsigned long flags)
714{
715 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
716 struct dw_dma *dw = to_dw_dma(chan->device);
717 struct dw_desc *desc;
718 struct dw_desc *first;
719 struct dw_desc *prev;
720 size_t xfer_count;
721 size_t offset;
722 unsigned int src_width;
723 unsigned int dst_width;
724 unsigned int data_width;
725 u32 ctllo;
726
727 dev_vdbg(chan2dev(chan),
728 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
729 (unsigned long long)dest, (unsigned long long)src,
730 len, flags);
731
732 if (unlikely(!len)) {
733 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
734 return NULL;
735 }
736
737 dwc->direction = DMA_MEM_TO_MEM;
738
739 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
740 dw->data_width[dwc->dst_master]);
741
742 src_width = dst_width = min_t(unsigned int, data_width,
743 dwc_fast_fls(src | dest | len));
744
745 ctllo = DWC_DEFAULT_CTLLO(chan)
746 | DWC_CTLL_DST_WIDTH(dst_width)
747 | DWC_CTLL_SRC_WIDTH(src_width)
748 | DWC_CTLL_DST_INC
749 | DWC_CTLL_SRC_INC
750 | DWC_CTLL_FC_M2M;
751 prev = first = NULL;
752
753 for (offset = 0; offset < len; offset += xfer_count << src_width) {
754 xfer_count = min_t(size_t, (len - offset) >> src_width,
755 dwc->block_size);
756
757 desc = dwc_desc_get(dwc);
758 if (!desc)
759 goto err_desc_get;
760
761 desc->lli.sar = src + offset;
762 desc->lli.dar = dest + offset;
763 desc->lli.ctllo = ctllo;
764 desc->lli.ctlhi = xfer_count;
765 desc->len = xfer_count << src_width;
766
767 if (!first) {
768 first = desc;
769 } else {
770 prev->lli.llp = desc->txd.phys;
771 list_add_tail(&desc->desc_node,
772 &first->tx_list);
773 }
774 prev = desc;
775 }
776
777 if (flags & DMA_PREP_INTERRUPT)
778
779 prev->lli.ctllo |= DWC_CTLL_INT_EN;
780
781 prev->lli.llp = 0;
782 first->txd.flags = flags;
783 first->total_len = len;
784
785 return &first->txd;
786
787err_desc_get:
788 dwc_desc_put(dwc, first);
789 return NULL;
790}
791
792static struct dma_async_tx_descriptor *
793dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
794 unsigned int sg_len, enum dma_transfer_direction direction,
795 unsigned long flags, void *context)
796{
797 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
798 struct dw_dma *dw = to_dw_dma(chan->device);
799 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
800 struct dw_desc *prev;
801 struct dw_desc *first;
802 u32 ctllo;
803 dma_addr_t reg;
804 unsigned int reg_width;
805 unsigned int mem_width;
806 unsigned int data_width;
807 unsigned int i;
808 struct scatterlist *sg;
809 size_t total_len = 0;
810
811 dev_vdbg(chan2dev(chan), "%s\n", __func__);
812
813 if (unlikely(!is_slave_direction(direction) || !sg_len))
814 return NULL;
815
816 dwc->direction = direction;
817
818 prev = first = NULL;
819
820 switch (direction) {
821 case DMA_MEM_TO_DEV:
822 reg_width = __fls(sconfig->dst_addr_width);
823 reg = sconfig->dst_addr;
824 ctllo = (DWC_DEFAULT_CTLLO(chan)
825 | DWC_CTLL_DST_WIDTH(reg_width)
826 | DWC_CTLL_DST_FIX
827 | DWC_CTLL_SRC_INC);
828
829 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
830 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
831
832 data_width = dw->data_width[dwc->src_master];
833
834 for_each_sg(sgl, sg, sg_len, i) {
835 struct dw_desc *desc;
836 u32 len, dlen, mem;
837
838 mem = sg_dma_address(sg);
839 len = sg_dma_len(sg);
840
841 mem_width = min_t(unsigned int,
842 data_width, dwc_fast_fls(mem | len));
843
844slave_sg_todev_fill_desc:
845 desc = dwc_desc_get(dwc);
846 if (!desc) {
847 dev_err(chan2dev(chan),
848 "not enough descriptors available\n");
849 goto err_desc_get;
850 }
851
852 desc->lli.sar = mem;
853 desc->lli.dar = reg;
854 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
855 if ((len >> mem_width) > dwc->block_size) {
856 dlen = dwc->block_size << mem_width;
857 mem += dlen;
858 len -= dlen;
859 } else {
860 dlen = len;
861 len = 0;
862 }
863
864 desc->lli.ctlhi = dlen >> mem_width;
865 desc->len = dlen;
866
867 if (!first) {
868 first = desc;
869 } else {
870 prev->lli.llp = desc->txd.phys;
871 list_add_tail(&desc->desc_node,
872 &first->tx_list);
873 }
874 prev = desc;
875 total_len += dlen;
876
877 if (len)
878 goto slave_sg_todev_fill_desc;
879 }
880 break;
881 case DMA_DEV_TO_MEM:
882 reg_width = __fls(sconfig->src_addr_width);
883 reg = sconfig->src_addr;
884 ctllo = (DWC_DEFAULT_CTLLO(chan)
885 | DWC_CTLL_SRC_WIDTH(reg_width)
886 | DWC_CTLL_DST_INC
887 | DWC_CTLL_SRC_FIX);
888
889 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
890 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
891
892 data_width = dw->data_width[dwc->dst_master];
893
894 for_each_sg(sgl, sg, sg_len, i) {
895 struct dw_desc *desc;
896 u32 len, dlen, mem;
897
898 mem = sg_dma_address(sg);
899 len = sg_dma_len(sg);
900
901 mem_width = min_t(unsigned int,
902 data_width, dwc_fast_fls(mem | len));
903
904slave_sg_fromdev_fill_desc:
905 desc = dwc_desc_get(dwc);
906 if (!desc) {
907 dev_err(chan2dev(chan),
908 "not enough descriptors available\n");
909 goto err_desc_get;
910 }
911
912 desc->lli.sar = reg;
913 desc->lli.dar = mem;
914 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
915 if ((len >> reg_width) > dwc->block_size) {
916 dlen = dwc->block_size << reg_width;
917 mem += dlen;
918 len -= dlen;
919 } else {
920 dlen = len;
921 len = 0;
922 }
923 desc->lli.ctlhi = dlen >> reg_width;
924 desc->len = dlen;
925
926 if (!first) {
927 first = desc;
928 } else {
929 prev->lli.llp = desc->txd.phys;
930 list_add_tail(&desc->desc_node,
931 &first->tx_list);
932 }
933 prev = desc;
934 total_len += dlen;
935
936 if (len)
937 goto slave_sg_fromdev_fill_desc;
938 }
939 break;
940 default:
941 return NULL;
942 }
943
944 if (flags & DMA_PREP_INTERRUPT)
945
946 prev->lli.ctllo |= DWC_CTLL_INT_EN;
947
948 prev->lli.llp = 0;
949 first->total_len = total_len;
950
951 return &first->txd;
952
953err_desc_get:
954 dwc_desc_put(dwc, first);
955 return NULL;
956}
957
958
959
960
961
962
963
964
965
966static inline void convert_burst(u32 *maxburst)
967{
968 if (*maxburst > 1)
969 *maxburst = fls(*maxburst) - 2;
970 else
971 *maxburst = 0;
972}
973
974static int
975set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
976{
977 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
978
979
980 if (!is_slave_direction(sconfig->direction))
981 return -EINVAL;
982
983 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
984 dwc->direction = sconfig->direction;
985
986
987 if (dwc->request_line == ~0)
988 dwc->request_line = sconfig->slave_id;
989
990 convert_burst(&dwc->dma_sconfig.src_maxburst);
991 convert_burst(&dwc->dma_sconfig.dst_maxburst);
992
993 return 0;
994}
995
996static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
997{
998 u32 cfglo = channel_readl(dwc, CFG_LO);
999 unsigned int count = 20;
1000
1001 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1002 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1003 udelay(2);
1004
1005 dwc->paused = true;
1006}
1007
1008static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1009{
1010 u32 cfglo = channel_readl(dwc, CFG_LO);
1011
1012 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1013
1014 dwc->paused = false;
1015}
1016
1017static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1018 unsigned long arg)
1019{
1020 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1021 struct dw_dma *dw = to_dw_dma(chan->device);
1022 struct dw_desc *desc, *_desc;
1023 unsigned long flags;
1024 LIST_HEAD(list);
1025
1026 if (cmd == DMA_PAUSE) {
1027 spin_lock_irqsave(&dwc->lock, flags);
1028
1029 dwc_chan_pause(dwc);
1030
1031 spin_unlock_irqrestore(&dwc->lock, flags);
1032 } else if (cmd == DMA_RESUME) {
1033 if (!dwc->paused)
1034 return 0;
1035
1036 spin_lock_irqsave(&dwc->lock, flags);
1037
1038 dwc_chan_resume(dwc);
1039
1040 spin_unlock_irqrestore(&dwc->lock, flags);
1041 } else if (cmd == DMA_TERMINATE_ALL) {
1042 spin_lock_irqsave(&dwc->lock, flags);
1043
1044 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1045
1046 dwc_chan_disable(dw, dwc);
1047
1048 dwc_chan_resume(dwc);
1049
1050
1051 list_splice_init(&dwc->queue, &list);
1052 list_splice_init(&dwc->active_list, &list);
1053
1054 spin_unlock_irqrestore(&dwc->lock, flags);
1055
1056
1057 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1058 dwc_descriptor_complete(dwc, desc, false);
1059 } else if (cmd == DMA_SLAVE_CONFIG) {
1060 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1061 } else {
1062 return -ENXIO;
1063 }
1064
1065 return 0;
1066}
1067
1068static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1069{
1070 unsigned long flags;
1071 u32 residue;
1072
1073 spin_lock_irqsave(&dwc->lock, flags);
1074
1075 residue = dwc->residue;
1076 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1077 residue -= dwc_get_sent(dwc);
1078
1079 spin_unlock_irqrestore(&dwc->lock, flags);
1080 return residue;
1081}
1082
1083static enum dma_status
1084dwc_tx_status(struct dma_chan *chan,
1085 dma_cookie_t cookie,
1086 struct dma_tx_state *txstate)
1087{
1088 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1089 enum dma_status ret;
1090
1091 ret = dma_cookie_status(chan, cookie, txstate);
1092 if (ret != DMA_SUCCESS) {
1093 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1094
1095 ret = dma_cookie_status(chan, cookie, txstate);
1096 }
1097
1098 if (ret != DMA_SUCCESS)
1099 dma_set_residue(txstate, dwc_get_residue(dwc));
1100
1101 if (dwc->paused)
1102 return DMA_PAUSED;
1103
1104 return ret;
1105}
1106
1107static void dwc_issue_pending(struct dma_chan *chan)
1108{
1109 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1110
1111 if (!list_empty(&dwc->queue))
1112 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1113}
1114
1115static int dwc_alloc_chan_resources(struct dma_chan *chan)
1116{
1117 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1118 struct dw_dma *dw = to_dw_dma(chan->device);
1119 struct dw_desc *desc;
1120 int i;
1121 unsigned long flags;
1122
1123 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1124
1125
1126 if (dma_readl(dw, CH_EN) & dwc->mask) {
1127 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1128 return -EIO;
1129 }
1130
1131 dma_cookie_init(chan);
1132
1133
1134
1135
1136
1137
1138
1139 dwc_set_masters(dwc);
1140
1141 spin_lock_irqsave(&dwc->lock, flags);
1142 i = dwc->descs_allocated;
1143 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1144 dma_addr_t phys;
1145
1146 spin_unlock_irqrestore(&dwc->lock, flags);
1147
1148 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1149 if (!desc)
1150 goto err_desc_alloc;
1151
1152 memset(desc, 0, sizeof(struct dw_desc));
1153
1154 INIT_LIST_HEAD(&desc->tx_list);
1155 dma_async_tx_descriptor_init(&desc->txd, chan);
1156 desc->txd.tx_submit = dwc_tx_submit;
1157 desc->txd.flags = DMA_CTRL_ACK;
1158 desc->txd.phys = phys;
1159
1160 dwc_desc_put(dwc, desc);
1161
1162 spin_lock_irqsave(&dwc->lock, flags);
1163 i = ++dwc->descs_allocated;
1164 }
1165
1166 spin_unlock_irqrestore(&dwc->lock, flags);
1167
1168 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1169
1170 return i;
1171
1172err_desc_alloc:
1173 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1174
1175 return i;
1176}
1177
1178static void dwc_free_chan_resources(struct dma_chan *chan)
1179{
1180 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1181 struct dw_dma *dw = to_dw_dma(chan->device);
1182 struct dw_desc *desc, *_desc;
1183 unsigned long flags;
1184 LIST_HEAD(list);
1185
1186 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1187 dwc->descs_allocated);
1188
1189
1190 BUG_ON(!list_empty(&dwc->active_list));
1191 BUG_ON(!list_empty(&dwc->queue));
1192 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1193
1194 spin_lock_irqsave(&dwc->lock, flags);
1195 list_splice_init(&dwc->free_list, &list);
1196 dwc->descs_allocated = 0;
1197 dwc->initialized = false;
1198 dwc->request_line = ~0;
1199
1200
1201 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1202 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1203
1204 spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1207 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1208 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1209 }
1210
1211 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1212}
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223int dw_dma_cyclic_start(struct dma_chan *chan)
1224{
1225 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1226 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1227 unsigned long flags;
1228
1229 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1230 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1231 return -ENODEV;
1232 }
1233
1234 spin_lock_irqsave(&dwc->lock, flags);
1235
1236
1237 if (dma_readl(dw, CH_EN) & dwc->mask) {
1238 dev_err(chan2dev(&dwc->chan),
1239 "BUG: Attempted to start non-idle channel\n");
1240 dwc_dump_chan_regs(dwc);
1241 spin_unlock_irqrestore(&dwc->lock, flags);
1242 return -EBUSY;
1243 }
1244
1245 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1246 dma_writel(dw, CLEAR.XFER, dwc->mask);
1247
1248
1249 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1250 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1251 channel_writel(dwc, CTL_HI, 0);
1252
1253 channel_set_bit(dw, CH_EN, dwc->mask);
1254
1255 spin_unlock_irqrestore(&dwc->lock, flags);
1256
1257 return 0;
1258}
1259EXPORT_SYMBOL(dw_dma_cyclic_start);
1260
1261
1262
1263
1264
1265
1266
1267void dw_dma_cyclic_stop(struct dma_chan *chan)
1268{
1269 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1270 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&dwc->lock, flags);
1274
1275 dwc_chan_disable(dw, dwc);
1276
1277 spin_unlock_irqrestore(&dwc->lock, flags);
1278}
1279EXPORT_SYMBOL(dw_dma_cyclic_stop);
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1293 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1294 enum dma_transfer_direction direction)
1295{
1296 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1297 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1298 struct dw_cyclic_desc *cdesc;
1299 struct dw_cyclic_desc *retval = NULL;
1300 struct dw_desc *desc;
1301 struct dw_desc *last = NULL;
1302 unsigned long was_cyclic;
1303 unsigned int reg_width;
1304 unsigned int periods;
1305 unsigned int i;
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&dwc->lock, flags);
1309 if (dwc->nollp) {
1310 spin_unlock_irqrestore(&dwc->lock, flags);
1311 dev_dbg(chan2dev(&dwc->chan),
1312 "channel doesn't support LLP transfers\n");
1313 return ERR_PTR(-EINVAL);
1314 }
1315
1316 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1317 spin_unlock_irqrestore(&dwc->lock, flags);
1318 dev_dbg(chan2dev(&dwc->chan),
1319 "queue and/or active list are not empty\n");
1320 return ERR_PTR(-EBUSY);
1321 }
1322
1323 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1324 spin_unlock_irqrestore(&dwc->lock, flags);
1325 if (was_cyclic) {
1326 dev_dbg(chan2dev(&dwc->chan),
1327 "channel already prepared for cyclic DMA\n");
1328 return ERR_PTR(-EBUSY);
1329 }
1330
1331 retval = ERR_PTR(-EINVAL);
1332
1333 if (unlikely(!is_slave_direction(direction)))
1334 goto out_err;
1335
1336 dwc->direction = direction;
1337
1338 if (direction == DMA_MEM_TO_DEV)
1339 reg_width = __ffs(sconfig->dst_addr_width);
1340 else
1341 reg_width = __ffs(sconfig->src_addr_width);
1342
1343 periods = buf_len / period_len;
1344
1345
1346 if (period_len > (dwc->block_size << reg_width))
1347 goto out_err;
1348 if (unlikely(period_len & ((1 << reg_width) - 1)))
1349 goto out_err;
1350 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1351 goto out_err;
1352
1353 retval = ERR_PTR(-ENOMEM);
1354
1355 if (periods > NR_DESCS_PER_CHANNEL)
1356 goto out_err;
1357
1358 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1359 if (!cdesc)
1360 goto out_err;
1361
1362 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1363 if (!cdesc->desc)
1364 goto out_err_alloc;
1365
1366 for (i = 0; i < periods; i++) {
1367 desc = dwc_desc_get(dwc);
1368 if (!desc)
1369 goto out_err_desc_get;
1370
1371 switch (direction) {
1372 case DMA_MEM_TO_DEV:
1373 desc->lli.dar = sconfig->dst_addr;
1374 desc->lli.sar = buf_addr + (period_len * i);
1375 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1376 | DWC_CTLL_DST_WIDTH(reg_width)
1377 | DWC_CTLL_SRC_WIDTH(reg_width)
1378 | DWC_CTLL_DST_FIX
1379 | DWC_CTLL_SRC_INC
1380 | DWC_CTLL_INT_EN);
1381
1382 desc->lli.ctllo |= sconfig->device_fc ?
1383 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1384 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1385
1386 break;
1387 case DMA_DEV_TO_MEM:
1388 desc->lli.dar = buf_addr + (period_len * i);
1389 desc->lli.sar = sconfig->src_addr;
1390 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1391 | DWC_CTLL_SRC_WIDTH(reg_width)
1392 | DWC_CTLL_DST_WIDTH(reg_width)
1393 | DWC_CTLL_DST_INC
1394 | DWC_CTLL_SRC_FIX
1395 | DWC_CTLL_INT_EN);
1396
1397 desc->lli.ctllo |= sconfig->device_fc ?
1398 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1399 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1400
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 desc->lli.ctlhi = (period_len >> reg_width);
1407 cdesc->desc[i] = desc;
1408
1409 if (last)
1410 last->lli.llp = desc->txd.phys;
1411
1412 last = desc;
1413 }
1414
1415
1416 last->lli.llp = cdesc->desc[0]->txd.phys;
1417
1418 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1419 "period %zu periods %d\n", (unsigned long long)buf_addr,
1420 buf_len, period_len, periods);
1421
1422 cdesc->periods = periods;
1423 dwc->cdesc = cdesc;
1424
1425 return cdesc;
1426
1427out_err_desc_get:
1428 while (i--)
1429 dwc_desc_put(dwc, cdesc->desc[i]);
1430out_err_alloc:
1431 kfree(cdesc);
1432out_err:
1433 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1434 return (struct dw_cyclic_desc *)retval;
1435}
1436EXPORT_SYMBOL(dw_dma_cyclic_prep);
1437
1438
1439
1440
1441
1442void dw_dma_cyclic_free(struct dma_chan *chan)
1443{
1444 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1445 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1446 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1447 int i;
1448 unsigned long flags;
1449
1450 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1451
1452 if (!cdesc)
1453 return;
1454
1455 spin_lock_irqsave(&dwc->lock, flags);
1456
1457 dwc_chan_disable(dw, dwc);
1458
1459 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1460 dma_writel(dw, CLEAR.XFER, dwc->mask);
1461
1462 spin_unlock_irqrestore(&dwc->lock, flags);
1463
1464 for (i = 0; i < cdesc->periods; i++)
1465 dwc_desc_put(dwc, cdesc->desc[i]);
1466
1467 kfree(cdesc->desc);
1468 kfree(cdesc);
1469
1470 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1471}
1472EXPORT_SYMBOL(dw_dma_cyclic_free);
1473
1474
1475
1476static void dw_dma_off(struct dw_dma *dw)
1477{
1478 int i;
1479
1480 dma_writel(dw, CFG, 0);
1481
1482 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1483 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1484 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1485 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1486
1487 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1488 cpu_relax();
1489
1490 for (i = 0; i < dw->dma.chancnt; i++)
1491 dw->chan[i].initialized = false;
1492}
1493
1494int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1495{
1496 struct dw_dma *dw;
1497 size_t size;
1498 bool autocfg;
1499 unsigned int dw_params;
1500 unsigned int nr_channels;
1501 unsigned int max_blk_size = 0;
1502 int err;
1503 int i;
1504
1505 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1506 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1507
1508 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1509
1510 if (!pdata && autocfg) {
1511 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1512 if (!pdata)
1513 return -ENOMEM;
1514
1515
1516 pdata->is_private = true;
1517 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1518 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1519 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1520 return -EINVAL;
1521
1522 if (autocfg)
1523 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1524 else
1525 nr_channels = pdata->nr_channels;
1526
1527 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1528 dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
1529 if (!dw)
1530 return -ENOMEM;
1531
1532 dw->clk = devm_clk_get(chip->dev, "hclk");
1533 if (IS_ERR(dw->clk))
1534 return PTR_ERR(dw->clk);
1535 clk_prepare_enable(dw->clk);
1536
1537 dw->regs = chip->regs;
1538 chip->dw = dw;
1539
1540
1541 if (autocfg) {
1542 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1543
1544 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1545 for (i = 0; i < dw->nr_masters; i++) {
1546 dw->data_width[i] =
1547 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1548 }
1549 } else {
1550 dw->nr_masters = pdata->nr_masters;
1551 memcpy(dw->data_width, pdata->data_width, 4);
1552 }
1553
1554
1555 dw->all_chan_mask = (1 << nr_channels) - 1;
1556
1557
1558 dw_dma_off(dw);
1559
1560
1561 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1562
1563 err = devm_request_irq(chip->dev, chip->irq, dw_dma_interrupt, 0,
1564 "dw_dmac", dw);
1565 if (err)
1566 return err;
1567
1568
1569 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1570 sizeof(struct dw_desc), 4, 0);
1571 if (!dw->desc_pool) {
1572 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1573 return -ENOMEM;
1574 }
1575
1576 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1577
1578 INIT_LIST_HEAD(&dw->dma.channels);
1579 for (i = 0; i < nr_channels; i++) {
1580 struct dw_dma_chan *dwc = &dw->chan[i];
1581 int r = nr_channels - i - 1;
1582
1583 dwc->chan.device = &dw->dma;
1584 dma_cookie_init(&dwc->chan);
1585 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1586 list_add_tail(&dwc->chan.device_node,
1587 &dw->dma.channels);
1588 else
1589 list_add(&dwc->chan.device_node, &dw->dma.channels);
1590
1591
1592 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1593 dwc->priority = r;
1594 else
1595 dwc->priority = i;
1596
1597 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1598 spin_lock_init(&dwc->lock);
1599 dwc->mask = 1 << i;
1600
1601 INIT_LIST_HEAD(&dwc->active_list);
1602 INIT_LIST_HEAD(&dwc->queue);
1603 INIT_LIST_HEAD(&dwc->free_list);
1604
1605 channel_clear_bit(dw, CH_EN, dwc->mask);
1606
1607 dwc->direction = DMA_TRANS_NONE;
1608 dwc->request_line = ~0;
1609
1610
1611 if (autocfg) {
1612 unsigned int dwc_params;
1613 void __iomem *addr = chip->regs + r * sizeof(u32);
1614
1615 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1616
1617 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1618 dwc_params);
1619
1620
1621
1622
1623 dwc->block_size =
1624 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1625 dwc->nollp =
1626 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1627 } else {
1628 dwc->block_size = pdata->block_size;
1629
1630
1631 channel_writel(dwc, LLP, 0xfffffffc);
1632 dwc->nollp =
1633 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1634 channel_writel(dwc, LLP, 0);
1635 }
1636 }
1637
1638
1639 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1640 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1641 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1642 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1643 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1644
1645 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1646 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1647 if (pdata->is_private)
1648 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1649 dw->dma.dev = chip->dev;
1650 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1651 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1652
1653 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1654
1655 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1656 dw->dma.device_control = dwc_control;
1657
1658 dw->dma.device_tx_status = dwc_tx_status;
1659 dw->dma.device_issue_pending = dwc_issue_pending;
1660
1661 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1662
1663 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1664 nr_channels);
1665
1666 dma_async_device_register(&dw->dma);
1667
1668 return 0;
1669}
1670EXPORT_SYMBOL_GPL(dw_dma_probe);
1671
1672int dw_dma_remove(struct dw_dma_chip *chip)
1673{
1674 struct dw_dma *dw = chip->dw;
1675 struct dw_dma_chan *dwc, *_dwc;
1676
1677 dw_dma_off(dw);
1678 dma_async_device_unregister(&dw->dma);
1679
1680 tasklet_kill(&dw->tasklet);
1681
1682 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1683 chan.device_node) {
1684 list_del(&dwc->chan.device_node);
1685 channel_clear_bit(dw, CH_EN, dwc->mask);
1686 }
1687
1688 return 0;
1689}
1690EXPORT_SYMBOL_GPL(dw_dma_remove);
1691
1692void dw_dma_shutdown(struct dw_dma_chip *chip)
1693{
1694 struct dw_dma *dw = chip->dw;
1695
1696 dw_dma_off(dw);
1697 clk_disable_unprepare(dw->clk);
1698}
1699EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1700
1701#ifdef CONFIG_PM_SLEEP
1702
1703int dw_dma_suspend(struct dw_dma_chip *chip)
1704{
1705 struct dw_dma *dw = chip->dw;
1706
1707 dw_dma_off(dw);
1708 clk_disable_unprepare(dw->clk);
1709
1710 return 0;
1711}
1712EXPORT_SYMBOL_GPL(dw_dma_suspend);
1713
1714int dw_dma_resume(struct dw_dma_chip *chip)
1715{
1716 struct dw_dma *dw = chip->dw;
1717
1718 clk_prepare_enable(dw->clk);
1719 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1720
1721 return 0;
1722}
1723EXPORT_SYMBOL_GPL(dw_dma_resume);
1724
1725#endif
1726
1727MODULE_LICENSE("GPL v2");
1728MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1729MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1730MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
1731