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23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/errno.h>
28#include <linux/sched.h>
29#include <linux/i2c.h>
30#include <drm/drm_dp_helper.h>
31#include <drm/drmP.h>
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42
43static int
44i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
45 uint8_t write_byte, uint8_t *read_byte)
46{
47 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
48 int ret;
49
50 ret = (*algo_data->aux_ch)(adapter, mode,
51 write_byte, read_byte);
52 return ret;
53}
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62
63
64static int
65i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
66{
67 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
68 int mode = MODE_I2C_START;
69 int ret;
70
71 if (reading)
72 mode |= MODE_I2C_READ;
73 else
74 mode |= MODE_I2C_WRITE;
75 algo_data->address = address;
76 algo_data->running = true;
77 ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
78 return ret;
79}
80
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83
84
85static void
86i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
87{
88 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
89 int mode = MODE_I2C_STOP;
90
91 if (reading)
92 mode |= MODE_I2C_READ;
93 else
94 mode |= MODE_I2C_WRITE;
95 if (algo_data->running) {
96 (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
97 algo_data->running = false;
98 }
99}
100
101
102
103
104
105static int
106i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
107{
108 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
109 int ret;
110
111 if (!algo_data->running)
112 return -EIO;
113
114 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
115 return ret;
116}
117
118
119
120
121
122static int
123i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
124{
125 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
126 int ret;
127
128 if (!algo_data->running)
129 return -EIO;
130
131 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
132 return ret;
133}
134
135static int
136i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
137 struct i2c_msg *msgs,
138 int num)
139{
140 int ret = 0;
141 bool reading = false;
142 int m;
143 int b;
144
145 for (m = 0; m < num; m++) {
146 u16 len = msgs[m].len;
147 u8 *buf = msgs[m].buf;
148 reading = (msgs[m].flags & I2C_M_RD) != 0;
149 ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
150 if (ret < 0)
151 break;
152 if (reading) {
153 for (b = 0; b < len; b++) {
154 ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
155 if (ret < 0)
156 break;
157 }
158 } else {
159 for (b = 0; b < len; b++) {
160 ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
161 if (ret < 0)
162 break;
163 }
164 }
165 if (ret < 0)
166 break;
167 }
168 if (ret >= 0)
169 ret = num;
170 i2c_algo_dp_aux_stop(adapter, reading);
171 DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
172 return ret;
173}
174
175static u32
176i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
177{
178 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
179 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
180 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
181 I2C_FUNC_10BIT_ADDR;
182}
183
184static const struct i2c_algorithm i2c_dp_aux_algo = {
185 .master_xfer = i2c_algo_dp_aux_xfer,
186 .functionality = i2c_algo_dp_aux_functionality,
187};
188
189static void
190i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
191{
192 (void) i2c_algo_dp_aux_address(adapter, 0, false);
193 (void) i2c_algo_dp_aux_stop(adapter, false);
194}
195
196static int
197i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
198{
199 adapter->algo = &i2c_dp_aux_algo;
200 adapter->retries = 3;
201 i2c_dp_aux_reset_bus(adapter);
202 return 0;
203}
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216
217int
218i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
219{
220 int error;
221
222 error = i2c_dp_aux_prepare_bus(adapter);
223 if (error)
224 return error;
225 error = i2c_add_adapter(adapter);
226 return error;
227}
228EXPORT_SYMBOL(i2c_dp_aux_add_bus);
229
230
231static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
232{
233 return link_status[r - DP_LANE0_1_STATUS];
234}
235
236static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
237 int lane)
238{
239 int i = DP_LANE0_1_STATUS + (lane >> 1);
240 int s = (lane & 1) * 4;
241 u8 l = dp_link_status(link_status, i);
242 return (l >> s) & 0xf;
243}
244
245bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
246 int lane_count)
247{
248 u8 lane_align;
249 u8 lane_status;
250 int lane;
251
252 lane_align = dp_link_status(link_status,
253 DP_LANE_ALIGN_STATUS_UPDATED);
254 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
255 return false;
256 for (lane = 0; lane < lane_count; lane++) {
257 lane_status = dp_get_lane_status(link_status, lane);
258 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
259 return false;
260 }
261 return true;
262}
263EXPORT_SYMBOL(drm_dp_channel_eq_ok);
264
265bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
266 int lane_count)
267{
268 int lane;
269 u8 lane_status;
270
271 for (lane = 0; lane < lane_count; lane++) {
272 lane_status = dp_get_lane_status(link_status, lane);
273 if ((lane_status & DP_LANE_CR_DONE) == 0)
274 return false;
275 }
276 return true;
277}
278EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
279
280u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
281 int lane)
282{
283 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
284 int s = ((lane & 1) ?
285 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
286 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
287 u8 l = dp_link_status(link_status, i);
288
289 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
290}
291EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
292
293u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
294 int lane)
295{
296 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
297 int s = ((lane & 1) ?
298 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
299 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
300 u8 l = dp_link_status(link_status, i);
301
302 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
303}
304EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
305
306void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
307 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
308 udelay(100);
309 else
310 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
311}
312EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
313
314void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
315 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
316 udelay(400);
317 else
318 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
319}
320EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
321
322u8 drm_dp_link_rate_to_bw_code(int link_rate)
323{
324 switch (link_rate) {
325 case 162000:
326 default:
327 return DP_LINK_BW_1_62;
328 case 270000:
329 return DP_LINK_BW_2_7;
330 case 540000:
331 return DP_LINK_BW_5_4;
332 }
333}
334EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
335
336int drm_dp_bw_code_to_link_rate(u8 link_bw)
337{
338 switch (link_bw) {
339 case DP_LINK_BW_1_62:
340 default:
341 return 162000;
342 case DP_LINK_BW_2_7:
343 return 270000;
344 case DP_LINK_BW_5_4:
345 return 540000;
346 }
347}
348EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
349
