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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include "i915_reg.h"
36#include "intel_bios.h"
37#include "intel_ringbuffer.h"
38#include <linux/io-mapping.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include <drm/intel-gtt.h>
42#include <linux/backlight.h>
43#include <linux/intel-iommu.h>
44#include <linux/kref.h>
45#include <linux/pm_qos.h>
46
47
48
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
54#define DRIVER_DATE "20080730"
55
56enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61};
62#define pipe_name(p) ((p) + 'A')
63
64enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
72enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76};
77#define plane_name(p) ((p) + 'A')
78
79#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
80
81enum port {
82 PORT_A = 0,
83 PORT_B,
84 PORT_C,
85 PORT_D,
86 PORT_E,
87 I915_MAX_PORTS
88};
89#define port_name(p) ((p) + 'A')
90
91enum intel_display_power_domain {
92 POWER_DOMAIN_PIPE_A,
93 POWER_DOMAIN_PIPE_B,
94 POWER_DOMAIN_PIPE_C,
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
102};
103
104#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
108
109enum hpd_pin {
110 HPD_NONE = 0,
111 HPD_PORT_A = HPD_NONE,
112 HPD_TV = HPD_NONE,
113 HPD_CRT,
114 HPD_SDVO_B,
115 HPD_SDVO_C,
116 HPD_PORT_B,
117 HPD_PORT_C,
118 HPD_PORT_D,
119 HPD_NUM_PINS
120};
121
122#define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
128
129#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
130
131#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
134
135struct drm_i915_private;
136
137enum intel_dpll_id {
138 DPLL_ID_PRIVATE = -1,
139
140 DPLL_ID_PCH_PLL_A,
141 DPLL_ID_PCH_PLL_B,
142};
143#define I915_NUM_PLLS 2
144
145struct intel_dpll_hw_state {
146 uint32_t dpll;
147 uint32_t fp0;
148 uint32_t fp1;
149};
150
151struct intel_shared_dpll {
152 int refcount;
153 int active;
154 bool on;
155 const char *name;
156
157 enum intel_dpll_id id;
158 struct intel_dpll_hw_state hw_state;
159 void (*enable)(struct drm_i915_private *dev_priv,
160 struct intel_shared_dpll *pll);
161 void (*disable)(struct drm_i915_private *dev_priv,
162 struct intel_shared_dpll *pll);
163 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
164 struct intel_shared_dpll *pll,
165 struct intel_dpll_hw_state *hw_state);
166};
167
168
169struct intel_link_m_n {
170 uint32_t tu;
171 uint32_t gmch_m;
172 uint32_t gmch_n;
173 uint32_t link_m;
174 uint32_t link_n;
175};
176
177void intel_link_compute_m_n(int bpp, int nlanes,
178 int pixel_clock, int link_clock,
179 struct intel_link_m_n *m_n);
180
181struct intel_ddi_plls {
182 int spll_refcount;
183 int wrpll1_refcount;
184 int wrpll2_refcount;
185};
186
187
188
189
190
191
192
193
194
195
196
197#define DRIVER_MAJOR 1
198#define DRIVER_MINOR 6
199#define DRIVER_PATCHLEVEL 0
200
201#define WATCH_COHERENCY 0
202#define WATCH_LISTS 0
203#define WATCH_GTT 0
204
205#define I915_GEM_PHYS_CURSOR_0 1
206#define I915_GEM_PHYS_CURSOR_1 2
207#define I915_GEM_PHYS_OVERLAY_REGS 3
208#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
209
210struct drm_i915_gem_phys_object {
211 int id;
212 struct page **page_list;
213 drm_dma_handle_t *handle;
214 struct drm_i915_gem_object *cur_obj;
215};
216
217struct opregion_header;
218struct opregion_acpi;
219struct opregion_swsci;
220struct opregion_asle;
221
222struct intel_opregion {
223 struct opregion_header __iomem *header;
224 struct opregion_acpi __iomem *acpi;
225 struct opregion_swsci __iomem *swsci;
226 struct opregion_asle __iomem *asle;
227 void __iomem *vbt;
228 u32 __iomem *lid_state;
229};
230#define OPREGION_SIZE (8*1024)
231
232struct intel_overlay;
233struct intel_overlay_error_state;
234
235struct drm_i915_master_private {
236 drm_local_map_t *sarea;
237 struct _drm_i915_sarea *sarea_priv;
238};
239#define I915_FENCE_REG_NONE -1
240#define I915_MAX_NUM_FENCES 32
241
242#define I915_MAX_NUM_FENCE_BITS 6
243
244struct drm_i915_fence_reg {
245 struct list_head lru_list;
246 struct drm_i915_gem_object *obj;
247 int pin_count;
248};
249
250struct sdvo_device_mapping {
251 u8 initialized;
252 u8 dvo_port;
253 u8 slave_addr;
254 u8 dvo_wiring;
255 u8 i2c_pin;
256 u8 ddc_pin;
257};
258
259struct intel_display_error_state;
260
261struct drm_i915_error_state {
262 struct kref ref;
263 u32 eir;
264 u32 pgtbl_er;
265 u32 ier;
266 u32 ccid;
267 u32 derrmr;
268 u32 forcewake;
269 bool waiting[I915_NUM_RINGS];
270 u32 pipestat[I915_MAX_PIPES];
271 u32 tail[I915_NUM_RINGS];
272 u32 head[I915_NUM_RINGS];
273 u32 ctl[I915_NUM_RINGS];
274 u32 ipeir[I915_NUM_RINGS];
275 u32 ipehr[I915_NUM_RINGS];
276 u32 instdone[I915_NUM_RINGS];
277 u32 acthd[I915_NUM_RINGS];
278 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
279 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
280 u32 rc_psmi[I915_NUM_RINGS];
281
282 u32 cpu_ring_head[I915_NUM_RINGS];
283 u32 cpu_ring_tail[I915_NUM_RINGS];
284 u32 error;
285 u32 err_int;
286 u32 instpm[I915_NUM_RINGS];
287 u32 instps[I915_NUM_RINGS];
288 u32 extra_instdone[I915_NUM_INSTDONE_REG];
289 u32 seqno[I915_NUM_RINGS];
290 u64 bbaddr;
291 u32 fault_reg[I915_NUM_RINGS];
292 u32 done_reg;
293 u32 faddr[I915_NUM_RINGS];
294 u64 fence[I915_MAX_NUM_FENCES];
295 struct timeval time;
296 struct drm_i915_error_ring {
297 struct drm_i915_error_object {
298 int page_count;
299 u32 gtt_offset;
300 u32 *pages[0];
301 } *ringbuffer, *batchbuffer, *ctx;
302 struct drm_i915_error_request {
303 long jiffies;
304 u32 seqno;
305 u32 tail;
306 } *requests;
307 int num_requests;
308 } ring[I915_NUM_RINGS];
309 struct drm_i915_error_buffer {
310 u32 size;
311 u32 name;
312 u32 rseqno, wseqno;
313 u32 gtt_offset;
314 u32 read_domains;
315 u32 write_domain;
316 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
317 s32 pinned:2;
318 u32 tiling:2;
319 u32 dirty:1;
320 u32 purgeable:1;
321 s32 ring:4;
322 u32 cache_level:2;
323 } *active_bo, *pinned_bo;
324 u32 active_bo_count, pinned_bo_count;
325 struct intel_overlay_error_state *overlay;
326 struct intel_display_error_state *display;
327};
328
329struct intel_crtc_config;
330struct intel_crtc;
331struct intel_limit;
332struct dpll;
333
334struct drm_i915_display_funcs {
335 bool (*fbc_enabled)(struct drm_device *dev);
336 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
337 void (*disable_fbc)(struct drm_device *dev);
338 int (*get_display_clock_speed)(struct drm_device *dev);
339 int (*get_fifo_size)(struct drm_device *dev, int plane);
340
341
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343
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345
346
347
348
349
350
351
352
353 bool (*find_dpll)(const struct intel_limit *limit,
354 struct drm_crtc *crtc,
355 int target, int refclk,
356 struct dpll *match_clock,
357 struct dpll *best_clock);
358 void (*update_wm)(struct drm_device *dev);
359 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
360 uint32_t sprite_width, int pixel_size,
361 bool enable);
362 void (*modeset_global_resources)(struct drm_device *dev);
363
364
365 bool (*get_pipe_config)(struct intel_crtc *,
366 struct intel_crtc_config *);
367 int (*crtc_mode_set)(struct drm_crtc *crtc,
368 int x, int y,
369 struct drm_framebuffer *old_fb);
370 void (*crtc_enable)(struct drm_crtc *crtc);
371 void (*crtc_disable)(struct drm_crtc *crtc);
372 void (*off)(struct drm_crtc *crtc);
373 void (*write_eld)(struct drm_connector *connector,
374 struct drm_crtc *crtc);
375 void (*fdi_link_train)(struct drm_crtc *crtc);
376 void (*init_clock_gating)(struct drm_device *dev);
377 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
378 struct drm_framebuffer *fb,
379 struct drm_i915_gem_object *obj);
380 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
381 int x, int y);
382 void (*hpd_irq_setup)(struct drm_device *dev);
383
384
385
386
387
388};
389
390struct drm_i915_gt_funcs {
391 void (*force_wake_get)(struct drm_i915_private *dev_priv);
392 void (*force_wake_put)(struct drm_i915_private *dev_priv);
393};
394
395#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
396 func(is_mobile) sep \
397 func(is_i85x) sep \
398 func(is_i915g) sep \
399 func(is_i945gm) sep \
400 func(is_g33) sep \
401 func(need_gfx_hws) sep \
402 func(is_g4x) sep \
403 func(is_pineview) sep \
404 func(is_broadwater) sep \
405 func(is_crestline) sep \
406 func(is_ivybridge) sep \
407 func(is_valleyview) sep \
408 func(is_haswell) sep \
409 func(has_force_wake) sep \
410 func(has_fbc) sep \
411 func(has_pipe_cxsr) sep \
412 func(has_hotplug) sep \
413 func(cursor_needs_physical) sep \
414 func(has_overlay) sep \
415 func(overlay_needs_physical) sep \
416 func(supports_tv) sep \
417 func(has_bsd_ring) sep \
418 func(has_blt_ring) sep \
419 func(has_vebox_ring) sep \
420 func(has_llc) sep \
421 func(has_ddi) sep \
422 func(has_fpga_dbg)
423
424#define DEFINE_FLAG(name) u8 name:1
425#define SEP_SEMICOLON ;
426
427struct intel_device_info {
428 u32 display_mmio_offset;
429 u8 num_pipes:3;
430 u8 gen;
431 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
432};
433
434#undef DEFINE_FLAG
435#undef SEP_SEMICOLON
436
437enum i915_cache_level {
438 I915_CACHE_NONE = 0,
439 I915_CACHE_LLC,
440 I915_CACHE_LLC_MLC,
441};
442
443typedef uint32_t gen6_gtt_pte_t;
444
445
446
447
448
449
450
451
452struct i915_gtt {
453 unsigned long start;
454 size_t total;
455 size_t stolen_size;
456
457 unsigned long mappable_end;
458 struct io_mapping *mappable;
459 phys_addr_t mappable_base;
460
461
462 void __iomem *gsm;
463
464 bool do_idle_maps;
465 dma_addr_t scratch_page_dma;
466 struct page *scratch_page;
467
468
469 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
470 size_t *stolen, phys_addr_t *mappable_base,
471 unsigned long *mappable_end);
472 void (*gtt_remove)(struct drm_device *dev);
473 void (*gtt_clear_range)(struct drm_device *dev,
474 unsigned int first_entry,
475 unsigned int num_entries);
476 void (*gtt_insert_entries)(struct drm_device *dev,
477 struct sg_table *st,
478 unsigned int pg_start,
479 enum i915_cache_level cache_level);
480 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
481 dma_addr_t addr,
482 enum i915_cache_level level);
483};
484#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
485
486#define I915_PPGTT_PD_ENTRIES 512
487#define I915_PPGTT_PT_ENTRIES 1024
488struct i915_hw_ppgtt {
489 struct drm_device *dev;
490 unsigned num_pd_entries;
491 struct page **pt_pages;
492 uint32_t pd_offset;
493 dma_addr_t *pt_dma_addr;
494 dma_addr_t scratch_page_dma_addr;
495
496
497 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
498 unsigned int first_entry,
499 unsigned int num_entries);
500 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
501 struct sg_table *st,
502 unsigned int pg_start,
503 enum i915_cache_level cache_level);
504 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
505 dma_addr_t addr,
506 enum i915_cache_level level);
507 int (*enable)(struct drm_device *dev);
508 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
509};
510
511struct i915_ctx_hang_stats {
512
513 unsigned batch_pending;
514
515
516 unsigned batch_active;
517};
518
519
520#define DEFAULT_CONTEXT_ID 0
521struct i915_hw_context {
522 struct kref ref;
523 int id;
524 bool is_initialized;
525 struct drm_i915_file_private *file_priv;
526 struct intel_ring_buffer *ring;
527 struct drm_i915_gem_object *obj;
528 struct i915_ctx_hang_stats hang_stats;
529};
530
531enum no_fbc_reason {
532 FBC_NO_OUTPUT,
533 FBC_STOLEN_TOO_SMALL,
534 FBC_UNSUPPORTED_MODE,
535 FBC_MODE_TOO_LARGE,
536 FBC_BAD_PLANE,
537 FBC_NOT_TILED,
538 FBC_MULTIPLE_PIPES,
539 FBC_MODULE_PARAM,
540};
541
542enum intel_pch {
543 PCH_NONE = 0,
544 PCH_IBX,
545 PCH_CPT,
546 PCH_LPT,
547 PCH_NOP,
548};
549
550enum intel_sbi_destination {
551 SBI_ICLK,
552 SBI_MPHY,
553};
554
555#define QUIRK_PIPEA_FORCE (1<<0)
556#define QUIRK_LVDS_SSC_DISABLE (1<<1)
557#define QUIRK_INVERT_BRIGHTNESS (1<<2)
558#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
559
560struct intel_fbdev;
561struct intel_fbc_work;
562
563struct intel_gmbus {
564 struct i2c_adapter adapter;
565 u32 force_bit;
566 u32 reg0;
567 u32 gpio_reg;
568 struct i2c_algo_bit_data bit_algo;
569 struct drm_i915_private *dev_priv;
570};
571
572struct i915_suspend_saved_registers {
573 u8 saveLBB;
574 u32 saveDSPACNTR;
575 u32 saveDSPBCNTR;
576 u32 saveDSPARB;
577 u32 savePIPEACONF;
578 u32 savePIPEBCONF;
579 u32 savePIPEASRC;
580 u32 savePIPEBSRC;
581 u32 saveFPA0;
582 u32 saveFPA1;
583 u32 saveDPLL_A;
584 u32 saveDPLL_A_MD;
585 u32 saveHTOTAL_A;
586 u32 saveHBLANK_A;
587 u32 saveHSYNC_A;
588 u32 saveVTOTAL_A;
589 u32 saveVBLANK_A;
590 u32 saveVSYNC_A;
591 u32 saveBCLRPAT_A;
592 u32 saveTRANSACONF;
593 u32 saveTRANS_HTOTAL_A;
594 u32 saveTRANS_HBLANK_A;
595 u32 saveTRANS_HSYNC_A;
596 u32 saveTRANS_VTOTAL_A;
597 u32 saveTRANS_VBLANK_A;
598 u32 saveTRANS_VSYNC_A;
599 u32 savePIPEASTAT;
600 u32 saveDSPASTRIDE;
601 u32 saveDSPASIZE;
602 u32 saveDSPAPOS;
603 u32 saveDSPAADDR;
604 u32 saveDSPASURF;
605 u32 saveDSPATILEOFF;
606 u32 savePFIT_PGM_RATIOS;
607 u32 saveBLC_HIST_CTL;
608 u32 saveBLC_PWM_CTL;
609 u32 saveBLC_PWM_CTL2;
610 u32 saveBLC_CPU_PWM_CTL;
611 u32 saveBLC_CPU_PWM_CTL2;
612 u32 saveFPB0;
613 u32 saveFPB1;
614 u32 saveDPLL_B;
615 u32 saveDPLL_B_MD;
616 u32 saveHTOTAL_B;
617 u32 saveHBLANK_B;
618 u32 saveHSYNC_B;
619 u32 saveVTOTAL_B;
620 u32 saveVBLANK_B;
621 u32 saveVSYNC_B;
622 u32 saveBCLRPAT_B;
623 u32 saveTRANSBCONF;
624 u32 saveTRANS_HTOTAL_B;
625 u32 saveTRANS_HBLANK_B;
626 u32 saveTRANS_HSYNC_B;
627 u32 saveTRANS_VTOTAL_B;
628 u32 saveTRANS_VBLANK_B;
629 u32 saveTRANS_VSYNC_B;
630 u32 savePIPEBSTAT;
631 u32 saveDSPBSTRIDE;
632 u32 saveDSPBSIZE;
633 u32 saveDSPBPOS;
634 u32 saveDSPBADDR;
635 u32 saveDSPBSURF;
636 u32 saveDSPBTILEOFF;
637 u32 saveVGA0;
638 u32 saveVGA1;
639 u32 saveVGA_PD;
640 u32 saveVGACNTRL;
641 u32 saveADPA;
642 u32 saveLVDS;
643 u32 savePP_ON_DELAYS;
644 u32 savePP_OFF_DELAYS;
645 u32 saveDVOA;
646 u32 saveDVOB;
647 u32 saveDVOC;
648 u32 savePP_ON;
649 u32 savePP_OFF;
650 u32 savePP_CONTROL;
651 u32 savePP_DIVISOR;
652 u32 savePFIT_CONTROL;
653 u32 save_palette_a[256];
654 u32 save_palette_b[256];
655 u32 saveDPFC_CB_BASE;
656 u32 saveFBC_CFB_BASE;
657 u32 saveFBC_LL_BASE;
658 u32 saveFBC_CONTROL;
659 u32 saveFBC_CONTROL2;
660 u32 saveIER;
661 u32 saveIIR;
662 u32 saveIMR;
663 u32 saveDEIER;
664 u32 saveDEIMR;
665 u32 saveGTIER;
666 u32 saveGTIMR;
667 u32 saveFDI_RXA_IMR;
668 u32 saveFDI_RXB_IMR;
669 u32 saveCACHE_MODE_0;
670 u32 saveMI_ARB_STATE;
671 u32 saveSWF0[16];
672 u32 saveSWF1[16];
673 u32 saveSWF2[3];
674 u8 saveMSR;
675 u8 saveSR[8];
676 u8 saveGR[25];
677 u8 saveAR_INDEX;
678 u8 saveAR[21];
679 u8 saveDACMASK;
680 u8 saveCR[37];
681 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
682 u32 saveCURACNTR;
683 u32 saveCURAPOS;
684 u32 saveCURABASE;
685 u32 saveCURBCNTR;
686 u32 saveCURBPOS;
687 u32 saveCURBBASE;
688 u32 saveCURSIZE;
689 u32 saveDP_B;
690 u32 saveDP_C;
691 u32 saveDP_D;
692 u32 savePIPEA_GMCH_DATA_M;
693 u32 savePIPEB_GMCH_DATA_M;
694 u32 savePIPEA_GMCH_DATA_N;
695 u32 savePIPEB_GMCH_DATA_N;
696 u32 savePIPEA_DP_LINK_M;
697 u32 savePIPEB_DP_LINK_M;
698 u32 savePIPEA_DP_LINK_N;
699 u32 savePIPEB_DP_LINK_N;
700 u32 saveFDI_RXA_CTL;
701 u32 saveFDI_TXA_CTL;
702 u32 saveFDI_RXB_CTL;
703 u32 saveFDI_TXB_CTL;
704 u32 savePFA_CTL_1;
705 u32 savePFB_CTL_1;
706 u32 savePFA_WIN_SZ;
707 u32 savePFB_WIN_SZ;
708 u32 savePFA_WIN_POS;
709 u32 savePFB_WIN_POS;
710 u32 savePCH_DREF_CONTROL;
711 u32 saveDISP_ARB_CTL;
712 u32 savePIPEA_DATA_M1;
713 u32 savePIPEA_DATA_N1;
714 u32 savePIPEA_LINK_M1;
715 u32 savePIPEA_LINK_N1;
716 u32 savePIPEB_DATA_M1;
717 u32 savePIPEB_DATA_N1;
718 u32 savePIPEB_LINK_M1;
719 u32 savePIPEB_LINK_N1;
720 u32 saveMCHBAR_RENDER_STANDBY;
721 u32 savePCH_PORT_HOTPLUG;
722};
723
724struct intel_gen6_power_mgmt {
725 struct work_struct work;
726 struct delayed_work vlv_work;
727 u32 pm_iir;
728
729
730 spinlock_t lock;
731
732
733
734 u8 cur_delay;
735 u8 min_delay;
736 u8 max_delay;
737 u8 rpe_delay;
738 u8 hw_max;
739
740 struct delayed_work delayed_resume_work;
741
742
743
744
745
746 struct mutex hw_lock;
747};
748
749
750extern spinlock_t mchdev_lock;
751
752struct intel_ilk_power_mgmt {
753 u8 cur_delay;
754 u8 min_delay;
755 u8 max_delay;
756 u8 fmax;
757 u8 fstart;
758
759 u64 last_count1;
760 unsigned long last_time1;
761 unsigned long chipset_power;
762 u64 last_count2;
763 struct timespec last_time2;
764 unsigned long gfx_power;
765 u8 corr;
766
767 int c_m;
768 int r_t;
769
770 struct drm_i915_gem_object *pwrctx;
771 struct drm_i915_gem_object *renderctx;
772};
773
774
775struct i915_power_well {
776 struct drm_device *device;
777 spinlock_t lock;
778
779 int count;
780 int i915_request;
781};
782
783struct i915_dri1_state {
784 unsigned allow_batchbuffer : 1;
785 u32 __iomem *gfx_hws_cpu_addr;
786
787 unsigned int cpp;
788 int back_offset;
789 int front_offset;
790 int current_page;
791 int page_flipping;
792
793 uint32_t counter;
794};
795
796struct intel_l3_parity {
797 u32 *remap_info;
798 struct work_struct error_work;
799};
800
801struct i915_gem_mm {
802
803 struct drm_mm stolen;
804
805 struct drm_mm gtt_space;
806
807
808 struct list_head bound_list;
809
810
811
812
813
814 struct list_head unbound_list;
815
816
817 unsigned long stolen_base;
818
819 int gtt_mtrr;
820
821
822 struct i915_hw_ppgtt *aliasing_ppgtt;
823
824 struct shrinker inactive_shrinker;
825 bool shrinker_no_lock_stealing;
826
827
828
829
830
831
832
833
834
835
836 struct list_head active_list;
837
838
839
840
841
842
843
844
845
846
847
848 struct list_head inactive_list;
849
850
851 struct list_head fence_list;
852
853
854
855
856
857
858
859
860 struct delayed_work retire_work;
861
862
863
864
865
866 bool interruptible;
867
868
869
870
871
872
873
874
875
876 int suspended;
877
878
879 uint32_t bit_6_swizzle_x;
880
881 uint32_t bit_6_swizzle_y;
882
883
884 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
885
886
887 size_t object_memory;
888 u32 object_count;
889};
890
891struct drm_i915_error_state_buf {
892 unsigned bytes;
893 unsigned size;
894 int err;
895 u8 *buf;
896 loff_t start;
897 loff_t pos;
898};
899
900struct i915_gpu_error {
901
902#define DRM_I915_HANGCHECK_PERIOD 1500
903#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
904 struct timer_list hangcheck_timer;
905
906
907 spinlock_t lock;
908
909 struct drm_i915_error_state *first_error;
910 struct work_struct work;
911
912 unsigned long last_reset;
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932 atomic_t reset_counter;
933
934
935
936
937
938
939
940
941#define I915_RESET_IN_PROGRESS_FLAG 1
942#define I915_WEDGED 0xffffffff
943
944
945
946
947
948 wait_queue_head_t reset_queue;
949
950
951 unsigned int stop_rings;
952};
953
954enum modeset_restore {
955 MODESET_ON_LID_OPEN,
956 MODESET_DONE,
957 MODESET_SUSPENDED,
958};
959
960struct intel_vbt_data {
961 struct drm_display_mode *lfp_lvds_vbt_mode;
962 struct drm_display_mode *sdvo_lvds_vbt_mode;
963
964
965 unsigned int int_tv_support:1;
966 unsigned int lvds_dither:1;
967 unsigned int lvds_vbt:1;
968 unsigned int int_crt_support:1;
969 unsigned int lvds_use_ssc:1;
970 unsigned int display_clock_mode:1;
971 unsigned int fdi_rx_polarity_inverted:1;
972 int lvds_ssc_freq;
973 unsigned int bios_lvds_val;
974
975
976 int edp_rate;
977 int edp_lanes;
978 int edp_preemphasis;
979 int edp_vswing;
980 bool edp_initialized;
981 bool edp_support;
982 int edp_bpp;
983 struct edp_power_seq edp_pps;
984
985 int crt_ddc_pin;
986
987 int child_dev_num;
988 struct child_device_config *child_dev;
989};
990
991typedef struct drm_i915_private {
992 struct drm_device *dev;
993 struct kmem_cache *slab;
994
995 const struct intel_device_info *info;
996
997 int relative_constants_mode;
998
999 void __iomem *regs;
1000
1001 struct drm_i915_gt_funcs gt;
1002
1003
1004 unsigned gt_fifo_count;
1005
1006 unsigned forcewake_count;
1007
1008 spinlock_t gt_lock;
1009
1010 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1011
1012
1013
1014
1015 struct mutex gmbus_mutex;
1016
1017
1018
1019
1020 uint32_t gpio_mmio_base;
1021
1022 wait_queue_head_t gmbus_wait_queue;
1023
1024 struct pci_dev *bridge_dev;
1025 struct intel_ring_buffer ring[I915_NUM_RINGS];
1026 uint32_t last_seqno, next_seqno;
1027
1028 drm_dma_handle_t *status_page_dmah;
1029 struct resource mch_res;
1030
1031 atomic_t irq_received;
1032
1033
1034 spinlock_t irq_lock;
1035
1036
1037 struct pm_qos_request pm_qos;
1038
1039
1040 struct mutex dpio_lock;
1041
1042
1043 u32 irq_mask;
1044 u32 gt_irq_mask;
1045
1046 struct work_struct hotplug_work;
1047 bool enable_hotplug_processing;
1048 struct {
1049 unsigned long hpd_last_jiffies;
1050 int hpd_cnt;
1051 enum {
1052 HPD_ENABLED = 0,
1053 HPD_DISABLED = 1,
1054 HPD_MARK_DISABLED = 2
1055 } hpd_mark;
1056 } hpd_stats[HPD_NUM_PINS];
1057 u32 hpd_event_bits;
1058 struct timer_list hotplug_reenable_timer;
1059
1060 int num_plane;
1061
1062 unsigned long cfb_size;
1063 unsigned int cfb_fb;
1064 enum plane cfb_plane;
1065 int cfb_y;
1066 struct intel_fbc_work *fbc_work;
1067
1068 struct intel_opregion opregion;
1069 struct intel_vbt_data vbt;
1070
1071
1072 struct intel_overlay *overlay;
1073 unsigned int sprite_scaling_enabled;
1074
1075
1076 struct {
1077 int level;
1078 bool enabled;
1079 spinlock_t lock;
1080 struct backlight_device *device;
1081 } backlight;
1082
1083
1084 struct drm_display_mode *lfp_lvds_vbt_mode;
1085 struct drm_display_mode *sdvo_lvds_vbt_mode;
1086 bool no_aux_handshake;
1087
1088 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
1089 int fence_reg_start;
1090 int num_fence_regs;
1091
1092 unsigned int fsb_freq, mem_freq, is_ddr3;
1093
1094 struct workqueue_struct *wq;
1095
1096
1097 struct drm_i915_display_funcs display;
1098
1099
1100 enum intel_pch pch_type;
1101 unsigned short pch_id;
1102
1103 unsigned long quirks;
1104
1105 enum modeset_restore modeset_restore;
1106 struct mutex modeset_restore_lock;
1107
1108 struct i915_gtt gtt;
1109
1110 struct i915_gem_mm mm;
1111
1112
1113
1114 struct sdvo_device_mapping sdvo_mappings[2];
1115
1116 struct drm_crtc *plane_to_crtc_mapping[3];
1117 struct drm_crtc *pipe_to_crtc_mapping[3];
1118 wait_queue_head_t pending_flip_queue;
1119
1120 int num_shared_dpll;
1121 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1122 struct intel_ddi_plls ddi_plls;
1123
1124
1125 bool render_reclock_avail;
1126 bool lvds_downclock_avail;
1127
1128 int lvds_downclock;
1129 u16 orig_clock;
1130
1131 bool mchbar_need_disable;
1132
1133 struct intel_l3_parity l3_parity;
1134
1135
1136 struct intel_gen6_power_mgmt rps;
1137
1138
1139
1140 struct intel_ilk_power_mgmt ips;
1141
1142
1143 struct i915_power_well power_well;
1144
1145 enum no_fbc_reason no_fbc_reason;
1146
1147 struct drm_mm_node *compressed_fb;
1148 struct drm_mm_node *compressed_llb;
1149
1150 struct i915_gpu_error gpu_error;
1151
1152 struct drm_i915_gem_object *vlv_pctx;
1153
1154
1155 struct intel_fbdev *fbdev;
1156
1157
1158
1159
1160
1161 struct work_struct console_resume_work;
1162
1163 struct drm_property *broadcast_rgb_property;
1164 struct drm_property *force_audio_property;
1165
1166 bool hw_contexts_disabled;
1167 uint32_t hw_context_size;
1168
1169 u32 fdi_rx_config;
1170
1171 struct i915_suspend_saved_registers regfile;
1172
1173
1174
1175 struct i915_dri1_state dri1;
1176} drm_i915_private_t;
1177
1178
1179#define for_each_ring(ring__, dev_priv__, i__) \
1180 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1181 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1182
1183enum hdmi_force_audio {
1184 HDMI_AUDIO_OFF_DVI = -2,
1185 HDMI_AUDIO_OFF,
1186 HDMI_AUDIO_AUTO,
1187 HDMI_AUDIO_ON,
1188};
1189
1190#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1191
1192struct drm_i915_gem_object_ops {
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206 int (*get_pages)(struct drm_i915_gem_object *);
1207 void (*put_pages)(struct drm_i915_gem_object *);
1208};
1209
1210struct drm_i915_gem_object {
1211 struct drm_gem_object base;
1212
1213 const struct drm_i915_gem_object_ops *ops;
1214
1215
1216 struct drm_mm_node *gtt_space;
1217
1218 struct drm_mm_node *stolen;
1219 struct list_head global_list;
1220
1221
1222 struct list_head ring_list;
1223 struct list_head mm_list;
1224
1225 struct list_head exec_list;
1226
1227
1228
1229
1230
1231
1232 unsigned int active:1;
1233
1234
1235
1236
1237
1238 unsigned int dirty:1;
1239
1240
1241
1242
1243
1244
1245 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1246
1247
1248
1249
1250 unsigned int madv:2;
1251
1252
1253
1254
1255 unsigned int tiling_mode:2;
1256
1257
1258
1259
1260
1261
1262
1263 unsigned int fence_dirty:1;
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274 unsigned int pin_count:4;
1275#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1276
1277
1278
1279
1280
1281 unsigned int map_and_fenceable:1;
1282
1283
1284
1285
1286
1287
1288 unsigned int fault_mappable:1;
1289 unsigned int pin_mappable:1;
1290
1291
1292
1293
1294 unsigned int pending_fenced_gpu_access:1;
1295 unsigned int fenced_gpu_access:1;
1296
1297 unsigned int cache_level:2;
1298
1299 unsigned int has_aliasing_ppgtt_mapping:1;
1300 unsigned int has_global_gtt_mapping:1;
1301 unsigned int has_dma_mapping:1;
1302
1303 struct sg_table *pages;
1304 int pages_pin_count;
1305
1306
1307 void *dma_buf_vmapping;
1308 int vmapping_count;
1309
1310
1311
1312
1313 struct hlist_node exec_node;
1314 unsigned long exec_handle;
1315 struct drm_i915_gem_exec_object2 *exec_entry;
1316
1317
1318
1319
1320
1321
1322 uint32_t gtt_offset;
1323
1324 struct intel_ring_buffer *ring;
1325
1326
1327 uint32_t last_read_seqno;
1328 uint32_t last_write_seqno;
1329
1330 uint32_t last_fenced_seqno;
1331
1332
1333 uint32_t stride;
1334
1335
1336 unsigned long *bit_17;
1337
1338
1339 uint32_t user_pin_count;
1340 struct drm_file *pin_filp;
1341
1342
1343 struct drm_i915_gem_phys_object *phys_obj;
1344};
1345#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1346
1347#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359struct drm_i915_gem_request {
1360
1361 struct intel_ring_buffer *ring;
1362
1363
1364 uint32_t seqno;
1365
1366
1367 u32 head;
1368
1369
1370 u32 tail;
1371
1372
1373 struct i915_hw_context *ctx;
1374
1375
1376 struct drm_i915_gem_object *batch_obj;
1377
1378
1379 unsigned long emitted_jiffies;
1380
1381
1382 struct list_head list;
1383
1384 struct drm_i915_file_private *file_priv;
1385
1386 struct list_head client_list;
1387};
1388
1389struct drm_i915_file_private {
1390 struct {
1391 spinlock_t lock;
1392 struct list_head request_list;
1393 } mm;
1394 struct idr context_idr;
1395
1396 struct i915_ctx_hang_stats hang_stats;
1397};
1398
1399#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1400
1401#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1402#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1403#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1404#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1405#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1406#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1407#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1408#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1409#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1410#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1411#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1412#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1413#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1414#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1415#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1416#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1417#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1418#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1419#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1420#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1421 (dev)->pci_device == 0x0152 || \
1422 (dev)->pci_device == 0x015a)
1423#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1424 (dev)->pci_device == 0x0106 || \
1425 (dev)->pci_device == 0x010A)
1426#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1427#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1428#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1429#define IS_ULT(dev) (IS_HASWELL(dev) && \
1430 ((dev)->pci_device & 0xFF00) == 0x0A00)
1431
1432
1433
1434
1435
1436
1437
1438#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1439#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1440#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1441#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1442#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1443#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1444
1445#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1446#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1447#define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1448#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1449#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1450
1451#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1452#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1453
1454#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1455#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1456
1457
1458#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1459
1460
1461
1462
1463#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1464 IS_I915GM(dev)))
1465#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1466#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1467#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1468#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1469#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1470#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1471
1472#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1473
1474#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1475#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1476#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1477
1478#define HAS_IPS(dev) (IS_ULT(dev))
1479
1480#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1481
1482#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1483#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1484#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1485
1486#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1487#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1488#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1489#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1490#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1491#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1492
1493#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1494#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1495#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1496#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1497#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1498#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1499
1500#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1501
1502#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1503
1504#define GT_FREQUENCY_MULTIPLIER 50
1505
1506#include "i915_trace.h"
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525#define INTEL_RC6_ENABLE (1<<0)
1526#define INTEL_RC6p_ENABLE (1<<1)
1527#define INTEL_RC6pp_ENABLE (1<<2)
1528
1529extern struct drm_ioctl_desc i915_ioctls[];
1530extern int i915_max_ioctl;
1531extern unsigned int i915_fbpercrtc __always_unused;
1532extern int i915_panel_ignore_lid __read_mostly;
1533extern unsigned int i915_powersave __read_mostly;
1534extern int i915_semaphores __read_mostly;
1535extern unsigned int i915_lvds_downclock __read_mostly;
1536extern int i915_lvds_channel_mode __read_mostly;
1537extern int i915_panel_use_ssc __read_mostly;
1538extern int i915_vbt_sdvo_panel_type __read_mostly;
1539extern int i915_enable_rc6 __read_mostly;
1540extern int i915_enable_fbc __read_mostly;
1541extern bool i915_enable_hangcheck __read_mostly;
1542extern int i915_enable_ppgtt __read_mostly;
1543extern unsigned int i915_preliminary_hw_support __read_mostly;
1544extern int i915_disable_power_well __read_mostly;
1545extern int i915_enable_ips __read_mostly;
1546
1547extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1548extern int i915_resume(struct drm_device *dev);
1549extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1550extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1551
1552
1553void i915_update_dri1_breadcrumb(struct drm_device *dev);
1554extern void i915_kernel_lost_context(struct drm_device * dev);
1555extern int i915_driver_load(struct drm_device *, unsigned long flags);
1556extern int i915_driver_unload(struct drm_device *);
1557extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1558extern void i915_driver_lastclose(struct drm_device * dev);
1559extern void i915_driver_preclose(struct drm_device *dev,
1560 struct drm_file *file_priv);
1561extern void i915_driver_postclose(struct drm_device *dev,
1562 struct drm_file *file_priv);
1563extern int i915_driver_device_is_agp(struct drm_device * dev);
1564#ifdef CONFIG_COMPAT
1565extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1566 unsigned long arg);
1567#endif
1568extern int i915_emit_box(struct drm_device *dev,
1569 struct drm_clip_rect *box,
1570 int DR1, int DR4);
1571extern int intel_gpu_reset(struct drm_device *dev);
1572extern int i915_reset(struct drm_device *dev);
1573extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1574extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1575extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1576extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1577
1578extern void intel_console_resume(struct work_struct *work);
1579
1580
1581void i915_hangcheck_elapsed(unsigned long data);
1582void i915_handle_error(struct drm_device *dev, bool wedged);
1583
1584extern void intel_irq_init(struct drm_device *dev);
1585extern void intel_pm_init(struct drm_device *dev);
1586extern void intel_hpd_init(struct drm_device *dev);
1587extern void intel_gt_init(struct drm_device *dev);
1588extern void intel_gt_sanitize(struct drm_device *dev);
1589
1590void i915_error_state_free(struct kref *error_ref);
1591
1592void
1593i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1594
1595void
1596i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1597
1598#ifdef CONFIG_DEBUG_FS
1599extern void i915_destroy_error_state(struct drm_device *dev);
1600#else
1601#define i915_destroy_error_state(x)
1602#endif
1603
1604
1605
1606int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1607 struct drm_file *file_priv);
1608int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1609 struct drm_file *file_priv);
1610int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1611 struct drm_file *file_priv);
1612int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1613 struct drm_file *file_priv);
1614int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1615 struct drm_file *file_priv);
1616int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1617 struct drm_file *file_priv);
1618int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1619 struct drm_file *file_priv);
1620int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file_priv);
1622int i915_gem_execbuffer(struct drm_device *dev, void *data,
1623 struct drm_file *file_priv);
1624int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1625 struct drm_file *file_priv);
1626int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1627 struct drm_file *file_priv);
1628int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1629 struct drm_file *file_priv);
1630int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1631 struct drm_file *file_priv);
1632int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1633 struct drm_file *file);
1634int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1635 struct drm_file *file);
1636int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1637 struct drm_file *file_priv);
1638int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1639 struct drm_file *file_priv);
1640int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1641 struct drm_file *file_priv);
1642int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1643 struct drm_file *file_priv);
1644int i915_gem_set_tiling(struct drm_device *dev, void *data,
1645 struct drm_file *file_priv);
1646int i915_gem_get_tiling(struct drm_device *dev, void *data,
1647 struct drm_file *file_priv);
1648int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1649 struct drm_file *file_priv);
1650int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1651 struct drm_file *file_priv);
1652void i915_gem_load(struct drm_device *dev);
1653void *i915_gem_object_alloc(struct drm_device *dev);
1654void i915_gem_object_free(struct drm_i915_gem_object *obj);
1655int i915_gem_init_object(struct drm_gem_object *obj);
1656void i915_gem_object_init(struct drm_i915_gem_object *obj,
1657 const struct drm_i915_gem_object_ops *ops);
1658struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1659 size_t size);
1660void i915_gem_free_object(struct drm_gem_object *obj);
1661
1662int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1663 uint32_t alignment,
1664 bool map_and_fenceable,
1665 bool nonblocking);
1666void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1667int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1668int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1669void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1670void i915_gem_lastclose(struct drm_device *dev);
1671
1672int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1673static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1674{
1675 struct sg_page_iter sg_iter;
1676
1677 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1678 return sg_page_iter_page(&sg_iter);
1679
1680 return NULL;
1681}
1682static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1683{
1684 BUG_ON(obj->pages == NULL);
1685 obj->pages_pin_count++;
1686}
1687static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1688{
1689 BUG_ON(obj->pages_pin_count == 0);
1690 obj->pages_pin_count--;
1691}
1692
1693int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1694int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1695 struct intel_ring_buffer *to);
1696void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1697 struct intel_ring_buffer *ring);
1698
1699int i915_gem_dumb_create(struct drm_file *file_priv,
1700 struct drm_device *dev,
1701 struct drm_mode_create_dumb *args);
1702int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1703 uint32_t handle, uint64_t *offset);
1704int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1705 uint32_t handle);
1706
1707
1708
1709static inline bool
1710i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1711{
1712 return (int32_t)(seq1 - seq2) >= 0;
1713}
1714
1715int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1716int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1717int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1718int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1719
1720static inline bool
1721i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1722{
1723 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1724 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1725 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1726 return true;
1727 } else
1728 return false;
1729}
1730
1731static inline void
1732i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1733{
1734 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1735 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1736 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1737 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1738 }
1739}
1740
1741void i915_gem_retire_requests(struct drm_device *dev);
1742void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1743int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1744 bool interruptible);
1745static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1746{
1747 return unlikely(atomic_read(&error->reset_counter)
1748 & I915_RESET_IN_PROGRESS_FLAG);
1749}
1750
1751static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1752{
1753 return atomic_read(&error->reset_counter) == I915_WEDGED;
1754}
1755
1756void i915_gem_reset(struct drm_device *dev);
1757void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1758int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1759 uint32_t read_domains,
1760 uint32_t write_domain);
1761int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1762int __must_check i915_gem_init(struct drm_device *dev);
1763int __must_check i915_gem_init_hw(struct drm_device *dev);
1764void i915_gem_l3_remap(struct drm_device *dev);
1765void i915_gem_init_swizzling(struct drm_device *dev);
1766void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1767int __must_check i915_gpu_idle(struct drm_device *dev);
1768int __must_check i915_gem_idle(struct drm_device *dev);
1769int __i915_add_request(struct intel_ring_buffer *ring,
1770 struct drm_file *file,
1771 struct drm_i915_gem_object *batch_obj,
1772 u32 *seqno);
1773#define i915_add_request(ring, seqno) \
1774 __i915_add_request(ring, NULL, NULL, seqno)
1775int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1776 uint32_t seqno);
1777int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1778int __must_check
1779i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1780 bool write);
1781int __must_check
1782i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1783int __must_check
1784i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1785 u32 alignment,
1786 struct intel_ring_buffer *pipelined);
1787int i915_gem_attach_phys_object(struct drm_device *dev,
1788 struct drm_i915_gem_object *obj,
1789 int id,
1790 int align);
1791void i915_gem_detach_phys_object(struct drm_device *dev,
1792 struct drm_i915_gem_object *obj);
1793void i915_gem_free_all_phys_object(struct drm_device *dev);
1794void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1795
1796uint32_t
1797i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1798uint32_t
1799i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1800 int tiling_mode, bool fenced);
1801
1802int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1803 enum i915_cache_level cache_level);
1804
1805struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1806 struct dma_buf *dma_buf);
1807
1808struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1809 struct drm_gem_object *gem_obj, int flags);
1810
1811void i915_gem_restore_fences(struct drm_device *dev);
1812
1813
1814void i915_gem_context_init(struct drm_device *dev);
1815void i915_gem_context_fini(struct drm_device *dev);
1816void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1817int i915_switch_context(struct intel_ring_buffer *ring,
1818 struct drm_file *file, int to_id);
1819void i915_gem_context_free(struct kref *ctx_ref);
1820static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1821{
1822 kref_get(&ctx->ref);
1823}
1824
1825static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1826{
1827 kref_put(&ctx->ref, i915_gem_context_free);
1828}
1829
1830struct i915_ctx_hang_stats * __must_check
1831i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
1832 struct drm_file *file,
1833 u32 id);
1834int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1835 struct drm_file *file);
1836int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *file);
1838
1839
1840void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1841void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1842 struct drm_i915_gem_object *obj,
1843 enum i915_cache_level cache_level);
1844void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1845 struct drm_i915_gem_object *obj);
1846
1847void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1848int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1849void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1850 enum i915_cache_level cache_level);
1851void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1852void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1853void i915_gem_init_global_gtt(struct drm_device *dev);
1854void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1855 unsigned long mappable_end, unsigned long end);
1856int i915_gem_gtt_init(struct drm_device *dev);
1857static inline void i915_gem_chipset_flush(struct drm_device *dev)
1858{
1859 if (INTEL_INFO(dev)->gen < 6)
1860 intel_gtt_chipset_flush();
1861}
1862
1863
1864
1865int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1866 unsigned alignment,
1867 unsigned cache_level,
1868 bool mappable,
1869 bool nonblock);
1870int i915_gem_evict_everything(struct drm_device *dev);
1871
1872
1873int i915_gem_init_stolen(struct drm_device *dev);
1874int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1875void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1876void i915_gem_cleanup_stolen(struct drm_device *dev);
1877struct drm_i915_gem_object *
1878i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1879struct drm_i915_gem_object *
1880i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1881 u32 stolen_offset,
1882 u32 gtt_offset,
1883 u32 size);
1884void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1885
1886
1887inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1888{
1889 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1890
1891 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1892 obj->tiling_mode != I915_TILING_NONE;
1893}
1894
1895void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1896void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1897void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1898
1899
1900void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1901 const char *where, uint32_t mark);
1902#if WATCH_LISTS
1903int i915_verify_lists(struct drm_device *dev);
1904#else
1905#define i915_verify_lists(dev) 0
1906#endif
1907void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1908 int handle);
1909void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1910 const char *where, uint32_t mark);
1911
1912
1913int i915_debugfs_init(struct drm_minor *minor);
1914void i915_debugfs_cleanup(struct drm_minor *minor);
1915__printf(2, 3)
1916void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1917
1918
1919extern int i915_save_state(struct drm_device *dev);
1920extern int i915_restore_state(struct drm_device *dev);
1921
1922
1923void i915_save_display_reg(struct drm_device *dev);
1924void i915_restore_display_reg(struct drm_device *dev);
1925
1926
1927void i915_setup_sysfs(struct drm_device *dev_priv);
1928void i915_teardown_sysfs(struct drm_device *dev_priv);
1929
1930
1931extern int intel_setup_gmbus(struct drm_device *dev);
1932extern void intel_teardown_gmbus(struct drm_device *dev);
1933static inline bool intel_gmbus_is_port_valid(unsigned port)
1934{
1935 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1936}
1937
1938extern struct i2c_adapter *intel_gmbus_get_adapter(
1939 struct drm_i915_private *dev_priv, unsigned port);
1940extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1941extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1942static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1943{
1944 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1945}
1946extern void intel_i2c_reset(struct drm_device *dev);
1947
1948
1949extern int intel_opregion_setup(struct drm_device *dev);
1950#ifdef CONFIG_ACPI
1951extern void intel_opregion_init(struct drm_device *dev);
1952extern void intel_opregion_fini(struct drm_device *dev);
1953extern void intel_opregion_asle_intr(struct drm_device *dev);
1954#else
1955static inline void intel_opregion_init(struct drm_device *dev) { return; }
1956static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1957static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1958#endif
1959
1960
1961#ifdef CONFIG_ACPI
1962extern void intel_register_dsm_handler(void);
1963extern void intel_unregister_dsm_handler(void);
1964#else
1965static inline void intel_register_dsm_handler(void) { return; }
1966static inline void intel_unregister_dsm_handler(void) { return; }
1967#endif
1968
1969
1970extern void intel_modeset_init_hw(struct drm_device *dev);
1971extern void intel_modeset_suspend_hw(struct drm_device *dev);
1972extern void intel_modeset_init(struct drm_device *dev);
1973extern void intel_modeset_gem_init(struct drm_device *dev);
1974extern void intel_modeset_cleanup(struct drm_device *dev);
1975extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1976extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1977 bool force_restore);
1978extern void i915_redisable_vga(struct drm_device *dev);
1979extern bool intel_fbc_enabled(struct drm_device *dev);
1980extern void intel_disable_fbc(struct drm_device *dev);
1981extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1982extern void intel_init_pch_refclk(struct drm_device *dev);
1983extern void gen6_set_rps(struct drm_device *dev, u8 val);
1984extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1985extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1986extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1987extern void intel_detect_pch(struct drm_device *dev);
1988extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1989extern int intel_enable_rc6(const struct drm_device *dev);
1990
1991extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1992int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1993 struct drm_file *file);
1994
1995
1996#ifdef CONFIG_DEBUG_FS
1997extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1998extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
1999 struct intel_overlay_error_state *error);
2000
2001extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2002extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2003 struct drm_device *dev,
2004 struct intel_display_error_state *error);
2005#endif
2006
2007
2008
2009
2010
2011void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2012void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2013int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
2014
2015int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2016int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2017
2018
2019u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2020void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2021u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2022u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2023void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
2024u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2025 enum intel_sbi_destination destination);
2026void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2027 enum intel_sbi_destination destination);
2028
2029int vlv_gpu_freq(int ddr_freq, int val);
2030int vlv_freq_opcode(int ddr_freq, int val);
2031
2032#define __i915_read(x, y) \
2033 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2034
2035__i915_read(8, b)
2036__i915_read(16, w)
2037__i915_read(32, l)
2038__i915_read(64, q)
2039#undef __i915_read
2040
2041#define __i915_write(x, y) \
2042 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2043
2044__i915_write(8, b)
2045__i915_write(16, w)
2046__i915_write(32, l)
2047__i915_write(64, q)
2048#undef __i915_write
2049
2050#define I915_READ8(reg) i915_read8(dev_priv, (reg))
2051#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2052
2053#define I915_READ16(reg) i915_read16(dev_priv, (reg))
2054#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2055#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2056#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2057
2058#define I915_READ(reg) i915_read32(dev_priv, (reg))
2059#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2060#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2061#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2062
2063#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2064#define I915_READ64(reg) i915_read64(dev_priv, (reg))
2065
2066#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2067#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2068
2069
2070#define INTEL_BROADCAST_RGB_AUTO 0
2071#define INTEL_BROADCAST_RGB_FULL 1
2072#define INTEL_BROADCAST_RGB_LIMITED 2
2073
2074static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2075{
2076 if (HAS_PCH_SPLIT(dev))
2077 return CPU_VGACNTRL;
2078 else if (IS_VALLEYVIEW(dev))
2079 return VLV_VGACNTRL;
2080 else
2081 return VGACNTRL;
2082}
2083
2084static inline void __user *to_user_ptr(u64 address)
2085{
2086 return (void __user *)(uintptr_t)address;
2087}
2088
2089static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2090{
2091 unsigned long j = msecs_to_jiffies(m);
2092
2093 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2094}
2095
2096static inline unsigned long
2097timespec_to_jiffies_timeout(const struct timespec *value)
2098{
2099 unsigned long j = timespec_to_jiffies(value);
2100
2101 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2102}
2103
2104#endif
2105