1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/export.h>
32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include "intel_drv.h"
36#include <drm/i915_drm.h>
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
53
54
55static const char *tv_format_names[] = {
56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
67struct intel_sdvo {
68 struct intel_encoder base;
69
70 struct i2c_adapter *i2c;
71 u8 slave_addr;
72
73 struct i2c_adapter ddc;
74
75
76 uint32_t sdvo_reg;
77
78
79 uint16_t controlled_output;
80
81
82
83
84
85 struct intel_sdvo_caps caps;
86
87
88 int pixel_clock_min, pixel_clock_max;
89
90
91
92
93
94 uint16_t attached_output;
95
96
97
98
99 uint16_t hotplug_active;
100
101
102
103
104
105 uint32_t color_range;
106 bool color_range_auto;
107
108
109
110
111
112
113
114
115 bool is_tv;
116
117
118 bool is_sdvob;
119
120
121 int tv_format_index;
122
123
124
125
126 bool is_hdmi;
127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
129 bool rgb_quant_range_selectable;
130
131
132
133
134
135 bool is_lvds;
136
137
138
139
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
142
143 uint8_t ddc_bus;
144
145
146
147
148 uint8_t dtd_sdvo_flags;
149};
150
151struct intel_sdvo_connector {
152 struct intel_connector base;
153
154
155 uint16_t output_flag;
156
157 enum hdmi_force_audio force_audio;
158
159
160 u8 tv_format_supported[TV_FORMAT_NUM];
161 int format_supported_num;
162 struct drm_property *tv_format;
163
164
165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
180 struct drm_property *dot_crawl;
181
182
183 struct drm_property *brightness;
184
185
186 u32 left_margin, right_margin, top_margin, bottom_margin;
187
188
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
202 u32 cur_dot_crawl, max_dot_crawl;
203};
204
205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
206{
207 return container_of(encoder, struct intel_sdvo, base.base);
208}
209
210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
221static bool
222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
230
231
232
233
234
235
236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
237{
238 struct drm_device *dev = intel_sdvo->base.base.dev;
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 u32 bval = val, cval = val;
241 int i;
242
243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
246 return;
247 }
248
249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
254
255
256
257
258
259 for (i = 0; i < 2; i++)
260 {
261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
265 }
266}
267
268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
269{
270 struct i2c_msg msgs[] = {
271 {
272 .addr = intel_sdvo->slave_addr,
273 .flags = 0,
274 .len = 1,
275 .buf = &addr,
276 },
277 {
278 .addr = intel_sdvo->slave_addr,
279 .flags = I2C_M_RD,
280 .len = 1,
281 .buf = ch,
282 }
283 };
284 int ret;
285
286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
287 return true;
288
289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
290 return false;
291}
292
293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294
295static const struct _sdvo_cmd_name {
296 u8 cmd;
297 const char *name;
298} sdvo_cmd_names[] = {
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
410};
411
412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
413
414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
415 const void *args, int args_len)
416{
417 int i;
418
419 DRM_DEBUG_KMS("%s: W: %02X ",
420 SDVO_NAME(intel_sdvo), cmd);
421 for (i = 0; i < args_len; i++)
422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
423 for (; i < 8; i++)
424 DRM_LOG_KMS(" ");
425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
426 if (cmd == sdvo_cmd_names[i].cmd) {
427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
428 break;
429 }
430 }
431 if (i == ARRAY_SIZE(sdvo_cmd_names))
432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
434}
435
436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
448{
449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
453
454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
459 if (!msgs) {
460 kfree(buf);
461 return false;
462 }
463
464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
465
466 for (i = 0; i < args_len; i++) {
467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
496 ret = false;
497 goto out;
498 }
499 if (ret != i+3) {
500
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
502 ret = false;
503 }
504
505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
509}
510
511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
513{
514 u8 retry = 15;
515 u8 status;
516 int i;
517
518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552 }
553
554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
556 else
557 DRM_LOG_KMS("(??? %d)", status);
558
559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
561
562
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
569 }
570 DRM_LOG_KMS("\n");
571 return true;
572
573log_fail:
574 DRM_LOG_KMS("... failed\n");
575 return false;
576}
577
578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
590{
591
592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
595}
596
597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
598{
599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
603}
604
605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
610
611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
613
614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
620}
621
622
623
624
625
626
627
628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
629{
630 struct intel_sdvo_get_trained_inputs_response response;
631
632 BUILD_BUG_ON(sizeof(response) != 1);
633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
643 u16 outputs)
644{
645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
648}
649
650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
659 int mode)
660{
661 u8 state = SDVO_ENCODER_STATE_ON;
662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
680}
681
682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
687
688 BUILD_BUG_ON(sizeof(clocks) != 4);
689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
692 return false;
693
694
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
697 return true;
698}
699
700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
701 u16 outputs)
702{
703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
706}
707
708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
709 struct intel_sdvo_dtd *dtd)
710{
711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
713}
714
715static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717{
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720}
721
722static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
723 struct intel_sdvo_dtd *dtd)
724{
725 return intel_sdvo_set_timing(intel_sdvo,
726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727}
728
729static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
730 struct intel_sdvo_dtd *dtd)
731{
732 return intel_sdvo_set_timing(intel_sdvo,
733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734}
735
736static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738{
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741}
742
743static bool
744intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748{
749 struct intel_sdvo_preferred_input_timing_args args;
750
751 memset(&args, 0, sizeof(args));
752 args.clock = clock;
753 args.width = width;
754 args.height = height;
755 args.interlace = 0;
756
757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
760 args.scaled = 1;
761
762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
765}
766
767static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
768 struct intel_sdvo_dtd *dtd)
769{
770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
776}
777
778static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
779{
780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
781}
782
783static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
784 const struct drm_display_mode *mode)
785{
786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
789 int mode_clock;
790
791 width = mode->hdisplay;
792 height = mode->vdisplay;
793
794
795 h_blank_len = mode->htotal - mode->hdisplay;
796 h_sync_len = mode->hsync_end - mode->hsync_start;
797
798 v_blank_len = mode->vtotal - mode->vdisplay;
799 v_sync_len = mode->vsync_end - mode->vsync_start;
800
801 h_sync_offset = mode->hsync_start - mode->hdisplay;
802 v_sync_offset = mode->vsync_start - mode->vdisplay;
803
804 mode_clock = mode->clock;
805 mode_clock /= 10;
806 dtd->part1.clock = mode_clock;
807
808 dtd->part1.h_active = width & 0xff;
809 dtd->part1.h_blank = h_blank_len & 0xff;
810 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
811 ((h_blank_len >> 8) & 0xf);
812 dtd->part1.v_active = height & 0xff;
813 dtd->part1.v_blank = v_blank_len & 0xff;
814 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
815 ((v_blank_len >> 8) & 0xf);
816
817 dtd->part2.h_sync_off = h_sync_offset & 0xff;
818 dtd->part2.h_sync_width = h_sync_len & 0xff;
819 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
820 (v_sync_len & 0xf);
821 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
822 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
823 ((v_sync_len & 0x30) >> 4);
824
825 dtd->part2.dtd_flags = 0x18;
826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
827 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
828 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
829 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
830 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
831 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
832
833 dtd->part2.sdvo_flags = 0;
834 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835 dtd->part2.reserved = 0;
836}
837
838static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
839 const struct intel_sdvo_dtd *dtd)
840{
841 mode->hdisplay = dtd->part1.h_active;
842 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
844 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
845 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
846 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
848 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
849
850 mode->vdisplay = dtd->part1.v_active;
851 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852 mode->vsync_start = mode->vdisplay;
853 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
854 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
855 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856 mode->vsync_end = mode->vsync_start +
857 (dtd->part2.v_sync_off_width & 0xf);
858 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
860 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
861
862 mode->clock = dtd->part1.clock * 10;
863
864 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
865 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866 mode->flags |= DRM_MODE_FLAG_INTERLACE;
867 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
868 mode->flags |= DRM_MODE_FLAG_PHSYNC;
869 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
870 mode->flags |= DRM_MODE_FLAG_PVSYNC;
871}
872
873static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
874{
875 struct intel_sdvo_encode encode;
876
877 BUILD_BUG_ON(sizeof(encode) != 2);
878 return intel_sdvo_get_value(intel_sdvo,
879 SDVO_CMD_GET_SUPP_ENCODE,
880 &encode, sizeof(encode));
881}
882
883static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
884 uint8_t mode)
885{
886 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
887}
888
889static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
890 uint8_t mode)
891{
892 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
893}
894
895#if 0
896static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
897{
898 int i, j;
899 uint8_t set_buf_index[2];
900 uint8_t av_split;
901 uint8_t buf_size;
902 uint8_t buf[48];
903 uint8_t *pos;
904
905 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
906
907 for (i = 0; i <= av_split; i++) {
908 set_buf_index[0] = i; set_buf_index[1] = 0;
909 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
910 set_buf_index, 2);
911 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
912 intel_sdvo_read_response(encoder, &buf_size, 1);
913
914 pos = buf;
915 for (j = 0; j <= buf_size; j += 8) {
916 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
917 NULL, 0);
918 intel_sdvo_read_response(encoder, pos, 8);
919 pos += 8;
920 }
921 }
922}
923#endif
924
925static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
926 unsigned if_index, uint8_t tx_rate,
927 uint8_t *data, unsigned length)
928{
929 uint8_t set_buf_index[2] = { if_index, 0 };
930 uint8_t hbuf_size, tmp[8];
931 int i;
932
933 if (!intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_HBUF_INDEX,
935 set_buf_index, 2))
936 return false;
937
938 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
939 &hbuf_size, 1))
940 return false;
941
942
943 hbuf_size++;
944
945 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
946 if_index, length, hbuf_size);
947
948 for (i = 0; i < hbuf_size; i += 8) {
949 memset(tmp, 0, 8);
950 if (i < length)
951 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
952
953 if (!intel_sdvo_set_value(intel_sdvo,
954 SDVO_CMD_SET_HBUF_DATA,
955 tmp, 8))
956 return false;
957 }
958
959 return intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_TXRATE,
961 &tx_rate, 1);
962}
963
964static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
965 const struct drm_display_mode *adjusted_mode)
966{
967 struct dip_infoframe avi_if = {
968 .type = DIP_TYPE_AVI,
969 .ver = DIP_VERSION_AVI,
970 .len = DIP_LEN_AVI,
971 };
972 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
973 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
974
975 if (intel_sdvo->rgb_quant_range_selectable) {
976 if (intel_crtc->config.limited_color_range)
977 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
978 else
979 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
980 }
981
982 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
983
984 intel_dip_infoframe_csum(&avi_if);
985
986
987
988 memcpy(sdvo_data, &avi_if, 3);
989 sdvo_data[3] = avi_if.checksum;
990 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
991
992 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
993 SDVO_HBUF_TX_VSYNC,
994 sdvo_data, sizeof(sdvo_data));
995}
996
997static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
998{
999 struct intel_sdvo_tv_format format;
1000 uint32_t format_map;
1001
1002 format_map = 1 << intel_sdvo->tv_format_index;
1003 memset(&format, 0, sizeof(format));
1004 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1005
1006 BUILD_BUG_ON(sizeof(format) != 6);
1007 return intel_sdvo_set_value(intel_sdvo,
1008 SDVO_CMD_SET_TV_FORMAT,
1009 &format, sizeof(format));
1010}
1011
1012static bool
1013intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1014 const struct drm_display_mode *mode)
1015{
1016 struct intel_sdvo_dtd output_dtd;
1017
1018 if (!intel_sdvo_set_target_output(intel_sdvo,
1019 intel_sdvo->attached_output))
1020 return false;
1021
1022 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1023 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1024 return false;
1025
1026 return true;
1027}
1028
1029
1030
1031static bool
1032intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1033 const struct drm_display_mode *mode,
1034 struct drm_display_mode *adjusted_mode)
1035{
1036 struct intel_sdvo_dtd input_dtd;
1037
1038
1039 if (!intel_sdvo_set_target_input(intel_sdvo))
1040 return false;
1041
1042 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1043 mode->clock / 10,
1044 mode->hdisplay,
1045 mode->vdisplay))
1046 return false;
1047
1048 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1049 &input_dtd))
1050 return false;
1051
1052 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1053 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1054
1055 return true;
1056}
1057
1058static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1059{
1060 unsigned dotclock = pipe_config->adjusted_mode.clock;
1061 struct dpll *clock = &pipe_config->dpll;
1062
1063
1064
1065 if (dotclock >= 100000 && dotclock < 140500) {
1066 clock->p1 = 2;
1067 clock->p2 = 10;
1068 clock->n = 3;
1069 clock->m1 = 16;
1070 clock->m2 = 8;
1071 } else if (dotclock >= 140500 && dotclock <= 200000) {
1072 clock->p1 = 1;
1073 clock->p2 = 10;
1074 clock->n = 6;
1075 clock->m1 = 12;
1076 clock->m2 = 8;
1077 } else {
1078 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1079 }
1080
1081 pipe_config->clock_set = true;
1082}
1083
1084static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1085 struct intel_crtc_config *pipe_config)
1086{
1087 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1089 struct drm_display_mode *mode = &pipe_config->requested_mode;
1090
1091 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1092 pipe_config->pipe_bpp = 8*3;
1093
1094 if (HAS_PCH_SPLIT(encoder->base.dev))
1095 pipe_config->has_pch_encoder = true;
1096
1097
1098
1099
1100
1101
1102 if (intel_sdvo->is_tv) {
1103 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1104 return false;
1105
1106 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1107 mode,
1108 adjusted_mode);
1109 pipe_config->sdvo_tv_clock = true;
1110 } else if (intel_sdvo->is_lvds) {
1111 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1112 intel_sdvo->sdvo_lvds_fixed_mode))
1113 return false;
1114
1115 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1116 mode,
1117 adjusted_mode);
1118 }
1119
1120
1121
1122
1123 pipe_config->pixel_multiplier =
1124 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1125 adjusted_mode->clock *= pipe_config->pixel_multiplier;
1126
1127 if (intel_sdvo->color_range_auto) {
1128
1129
1130
1131 if (intel_sdvo->has_hdmi_monitor &&
1132 drm_match_cea_mode(adjusted_mode) > 1)
1133 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
1134 else
1135 intel_sdvo->color_range = 0;
1136 }
1137
1138 if (intel_sdvo->color_range)
1139 pipe_config->limited_color_range = true;
1140
1141
1142 if (intel_sdvo->is_tv)
1143 i9xx_adjust_sdvo_tv_clock(pipe_config);
1144
1145 return true;
1146}
1147
1148static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
1149{
1150 struct drm_device *dev = intel_encoder->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 struct drm_crtc *crtc = intel_encoder->base.crtc;
1153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1154 struct drm_display_mode *adjusted_mode =
1155 &intel_crtc->config.adjusted_mode;
1156 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1157 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
1158 u32 sdvox;
1159 struct intel_sdvo_in_out_map in_out;
1160 struct intel_sdvo_dtd input_dtd, output_dtd;
1161 int rate;
1162
1163 if (!mode)
1164 return;
1165
1166
1167
1168
1169
1170
1171
1172 in_out.in0 = intel_sdvo->attached_output;
1173 in_out.in1 = 0;
1174
1175 intel_sdvo_set_value(intel_sdvo,
1176 SDVO_CMD_SET_IN_OUT_MAP,
1177 &in_out, sizeof(in_out));
1178
1179
1180 if (!intel_sdvo_set_target_output(intel_sdvo,
1181 intel_sdvo->attached_output))
1182 return;
1183
1184
1185 if (intel_sdvo->is_lvds)
1186 intel_sdvo_get_dtd_from_mode(&output_dtd,
1187 intel_sdvo->sdvo_lvds_fixed_mode);
1188 else
1189 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1190 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1191 DRM_INFO("Setting output timings on %s failed\n",
1192 SDVO_NAME(intel_sdvo));
1193
1194
1195 if (!intel_sdvo_set_target_input(intel_sdvo))
1196 return;
1197
1198 if (intel_sdvo->has_hdmi_monitor) {
1199 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1200 intel_sdvo_set_colorimetry(intel_sdvo,
1201 SDVO_COLORIMETRY_RGB256);
1202 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
1203 } else
1204 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1205
1206 if (intel_sdvo->is_tv &&
1207 !intel_sdvo_set_tv_format(intel_sdvo))
1208 return;
1209
1210
1211
1212
1213 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1214 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1215 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1216 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1217 DRM_INFO("Setting input timings on %s failed\n",
1218 SDVO_NAME(intel_sdvo));
1219
1220 switch (intel_crtc->config.pixel_multiplier) {
1221 default:
1222 WARN(1, "unknown pixel mutlipler specified\n");
1223 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1224 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1225 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1226 }
1227 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1228 return;
1229
1230
1231 if (INTEL_INFO(dev)->gen >= 4) {
1232
1233
1234 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1235 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
1236 sdvox |= intel_sdvo->color_range;
1237 if (INTEL_INFO(dev)->gen < 5)
1238 sdvox |= SDVO_BORDER_ENABLE;
1239 } else {
1240 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1241 switch (intel_sdvo->sdvo_reg) {
1242 case GEN3_SDVOB:
1243 sdvox &= SDVOB_PRESERVE_MASK;
1244 break;
1245 case GEN3_SDVOC:
1246 sdvox &= SDVOC_PRESERVE_MASK;
1247 break;
1248 }
1249 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1250 }
1251
1252 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1253 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
1254 else
1255 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
1256
1257 if (intel_sdvo->has_hdmi_audio)
1258 sdvox |= SDVO_AUDIO_ENABLE;
1259
1260 if (INTEL_INFO(dev)->gen >= 4) {
1261
1262 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1263
1264 } else {
1265 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1266 << SDVO_PORT_MULTIPLY_SHIFT;
1267 }
1268
1269 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1270 INTEL_INFO(dev)->gen < 5)
1271 sdvox |= SDVO_STALL_SELECT;
1272 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1273}
1274
1275static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1276{
1277 struct intel_sdvo_connector *intel_sdvo_connector =
1278 to_intel_sdvo_connector(&connector->base);
1279 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1280 u16 active_outputs = 0;
1281
1282 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1283
1284 if (active_outputs & intel_sdvo_connector->output_flag)
1285 return true;
1286 else
1287 return false;
1288}
1289
1290static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1291 enum pipe *pipe)
1292{
1293 struct drm_device *dev = encoder->base.dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1296 u16 active_outputs = 0;
1297 u32 tmp;
1298
1299 tmp = I915_READ(intel_sdvo->sdvo_reg);
1300 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1301
1302 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1303 return false;
1304
1305 if (HAS_PCH_CPT(dev))
1306 *pipe = PORT_TO_PIPE_CPT(tmp);
1307 else
1308 *pipe = PORT_TO_PIPE(tmp);
1309
1310 return true;
1311}
1312
1313static void intel_sdvo_get_config(struct intel_encoder *encoder,
1314 struct intel_crtc_config *pipe_config)
1315{
1316 struct drm_device *dev = encoder->base.dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1319 struct intel_sdvo_dtd dtd;
1320 int encoder_pixel_multiplier = 0;
1321 u32 flags = 0, sdvox;
1322 u8 val;
1323 bool ret;
1324
1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1326 if (!ret) {
1327
1328
1329 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1330 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1331 } else {
1332 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1334 else
1335 flags |= DRM_MODE_FLAG_NHSYNC;
1336
1337 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1339 else
1340 flags |= DRM_MODE_FLAG_NVSYNC;
1341 }
1342
1343 pipe_config->adjusted_mode.flags |= flags;
1344
1345
1346
1347
1348
1349
1350
1351
1352 if (IS_I915G(dev) || IS_I915GM(dev)) {
1353 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1354 pipe_config->pixel_multiplier =
1355 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1356 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1357 }
1358
1359
1360 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
1361 switch (val) {
1362 case SDVO_CLOCK_RATE_MULT_1X:
1363 encoder_pixel_multiplier = 1;
1364 break;
1365 case SDVO_CLOCK_RATE_MULT_2X:
1366 encoder_pixel_multiplier = 2;
1367 break;
1368 case SDVO_CLOCK_RATE_MULT_4X:
1369 encoder_pixel_multiplier = 4;
1370 break;
1371 }
1372
1373 if(HAS_PCH_SPLIT(dev))
1374 return;
1375
1376 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1377 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1378 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1379}
1380
1381static void intel_disable_sdvo(struct intel_encoder *encoder)
1382{
1383 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1384 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1385 u32 temp;
1386
1387 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1388 if (0)
1389 intel_sdvo_set_encoder_power_state(intel_sdvo,
1390 DRM_MODE_DPMS_OFF);
1391
1392 temp = I915_READ(intel_sdvo->sdvo_reg);
1393 if ((temp & SDVO_ENABLE) != 0) {
1394
1395
1396 if (HAS_PCH_IBX(encoder->base.dev)) {
1397 struct drm_crtc *crtc = encoder->base.crtc;
1398 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1399
1400 if (temp & SDVO_PIPE_B_SELECT) {
1401 temp &= ~SDVO_PIPE_B_SELECT;
1402 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1403 POSTING_READ(intel_sdvo->sdvo_reg);
1404
1405
1406 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1407 POSTING_READ(intel_sdvo->sdvo_reg);
1408
1409
1410
1411 if (crtc)
1412 intel_wait_for_vblank(encoder->base.dev, pipe);
1413 else
1414 msleep(50);
1415 }
1416 }
1417
1418 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1419 }
1420}
1421
1422static void intel_enable_sdvo(struct intel_encoder *encoder)
1423{
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1427 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1428 u32 temp;
1429 bool input1, input2;
1430 int i;
1431 u8 status;
1432
1433 temp = I915_READ(intel_sdvo->sdvo_reg);
1434 if ((temp & SDVO_ENABLE) == 0) {
1435
1436
1437 if (HAS_PCH_IBX(dev))
1438 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
1439
1440 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1441 }
1442 for (i = 0; i < 2; i++)
1443 intel_wait_for_vblank(dev, intel_crtc->pipe);
1444
1445 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1446
1447
1448
1449
1450 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1451 DRM_DEBUG_KMS("First %s output reported failure to "
1452 "sync\n", SDVO_NAME(intel_sdvo));
1453 }
1454
1455 if (0)
1456 intel_sdvo_set_encoder_power_state(intel_sdvo,
1457 DRM_MODE_DPMS_ON);
1458 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1459}
1460
1461
1462static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
1463{
1464 struct drm_crtc *crtc;
1465 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1466
1467
1468 if (mode != DRM_MODE_DPMS_ON)
1469 mode = DRM_MODE_DPMS_OFF;
1470
1471 if (mode == connector->dpms)
1472 return;
1473
1474 connector->dpms = mode;
1475
1476
1477 crtc = intel_sdvo->base.base.crtc;
1478 if (!crtc) {
1479 intel_sdvo->base.connectors_active = false;
1480 return;
1481 }
1482
1483
1484
1485 if (mode != DRM_MODE_DPMS_ON) {
1486 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1487 if (0)
1488 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1489
1490 intel_sdvo->base.connectors_active = false;
1491
1492 intel_crtc_update_dpms(crtc);
1493 } else {
1494 intel_sdvo->base.connectors_active = true;
1495
1496 intel_crtc_update_dpms(crtc);
1497
1498 if (0)
1499 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1500 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1501 }
1502
1503 intel_modeset_check_state(connector->dev);
1504}
1505
1506static int intel_sdvo_mode_valid(struct drm_connector *connector,
1507 struct drm_display_mode *mode)
1508{
1509 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1510
1511 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1512 return MODE_NO_DBLESCAN;
1513
1514 if (intel_sdvo->pixel_clock_min > mode->clock)
1515 return MODE_CLOCK_LOW;
1516
1517 if (intel_sdvo->pixel_clock_max < mode->clock)
1518 return MODE_CLOCK_HIGH;
1519
1520 if (intel_sdvo->is_lvds) {
1521 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1522 return MODE_PANEL;
1523
1524 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1525 return MODE_PANEL;
1526 }
1527
1528 return MODE_OK;
1529}
1530
1531static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1532{
1533 BUILD_BUG_ON(sizeof(*caps) != 8);
1534 if (!intel_sdvo_get_value(intel_sdvo,
1535 SDVO_CMD_GET_DEVICE_CAPS,
1536 caps, sizeof(*caps)))
1537 return false;
1538
1539 DRM_DEBUG_KMS("SDVO capabilities:\n"
1540 " vendor_id: %d\n"
1541 " device_id: %d\n"
1542 " device_rev_id: %d\n"
1543 " sdvo_version_major: %d\n"
1544 " sdvo_version_minor: %d\n"
1545 " sdvo_inputs_mask: %d\n"
1546 " smooth_scaling: %d\n"
1547 " sharp_scaling: %d\n"
1548 " up_scaling: %d\n"
1549 " down_scaling: %d\n"
1550 " stall_support: %d\n"
1551 " output_flags: %d\n",
1552 caps->vendor_id,
1553 caps->device_id,
1554 caps->device_rev_id,
1555 caps->sdvo_version_major,
1556 caps->sdvo_version_minor,
1557 caps->sdvo_inputs_mask,
1558 caps->smooth_scaling,
1559 caps->sharp_scaling,
1560 caps->up_scaling,
1561 caps->down_scaling,
1562 caps->stall_support,
1563 caps->output_flags);
1564
1565 return true;
1566}
1567
1568static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1569{
1570 struct drm_device *dev = intel_sdvo->base.base.dev;
1571 uint16_t hotplug;
1572
1573
1574
1575 if (IS_I945G(dev) || IS_I945GM(dev))
1576 return 0;
1577
1578 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1579 &hotplug, sizeof(hotplug)))
1580 return 0;
1581
1582 return hotplug;
1583}
1584
1585static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1586{
1587 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1588
1589 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1590 &intel_sdvo->hotplug_active, 2);
1591}
1592
1593static bool
1594intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1595{
1596
1597 return hweight16(intel_sdvo->caps.output_flags) > 1;
1598}
1599
1600static struct edid *
1601intel_sdvo_get_edid(struct drm_connector *connector)
1602{
1603 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1604 return drm_get_edid(connector, &sdvo->ddc);
1605}
1606
1607
1608static struct edid *
1609intel_sdvo_get_analog_edid(struct drm_connector *connector)
1610{
1611 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1612
1613 return drm_get_edid(connector,
1614 intel_gmbus_get_adapter(dev_priv,
1615 dev_priv->vbt.crt_ddc_pin));
1616}
1617
1618static enum drm_connector_status
1619intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1620{
1621 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1622 enum drm_connector_status status;
1623 struct edid *edid;
1624
1625 edid = intel_sdvo_get_edid(connector);
1626
1627 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1628 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1629
1630
1631
1632
1633
1634 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1635 intel_sdvo->ddc_bus = ddc;
1636 edid = intel_sdvo_get_edid(connector);
1637 if (edid)
1638 break;
1639 }
1640
1641
1642
1643
1644 if (edid == NULL)
1645 intel_sdvo->ddc_bus = saved_ddc;
1646 }
1647
1648
1649
1650
1651
1652 if (edid == NULL)
1653 edid = intel_sdvo_get_analog_edid(connector);
1654
1655 status = connector_status_unknown;
1656 if (edid != NULL) {
1657
1658 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1659 status = connector_status_connected;
1660 if (intel_sdvo->is_hdmi) {
1661 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1662 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1663 intel_sdvo->rgb_quant_range_selectable =
1664 drm_rgb_quant_range_selectable(edid);
1665 }
1666 } else
1667 status = connector_status_disconnected;
1668 kfree(edid);
1669 }
1670
1671 if (status == connector_status_connected) {
1672 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1673 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1674 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
1675 }
1676
1677 return status;
1678}
1679
1680static bool
1681intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1682 struct edid *edid)
1683{
1684 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1685 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1686
1687 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1688 connector_is_digital, monitor_is_digital);
1689 return connector_is_digital == monitor_is_digital;
1690}
1691
1692static enum drm_connector_status
1693intel_sdvo_detect(struct drm_connector *connector, bool force)
1694{
1695 uint16_t response;
1696 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1697 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1698 enum drm_connector_status ret;
1699
1700 if (!intel_sdvo_get_value(intel_sdvo,
1701 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1702 &response, 2))
1703 return connector_status_unknown;
1704
1705 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1706 response & 0xff, response >> 8,
1707 intel_sdvo_connector->output_flag);
1708
1709 if (response == 0)
1710 return connector_status_disconnected;
1711
1712 intel_sdvo->attached_output = response;
1713
1714 intel_sdvo->has_hdmi_monitor = false;
1715 intel_sdvo->has_hdmi_audio = false;
1716 intel_sdvo->rgb_quant_range_selectable = false;
1717
1718 if ((intel_sdvo_connector->output_flag & response) == 0)
1719 ret = connector_status_disconnected;
1720 else if (IS_TMDS(intel_sdvo_connector))
1721 ret = intel_sdvo_tmds_sink_detect(connector);
1722 else {
1723 struct edid *edid;
1724
1725
1726 edid = intel_sdvo_get_edid(connector);
1727 if (edid == NULL)
1728 edid = intel_sdvo_get_analog_edid(connector);
1729 if (edid != NULL) {
1730 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1731 edid))
1732 ret = connector_status_connected;
1733 else
1734 ret = connector_status_disconnected;
1735
1736 kfree(edid);
1737 } else
1738 ret = connector_status_connected;
1739 }
1740
1741
1742 if (ret == connector_status_connected) {
1743 intel_sdvo->is_tv = false;
1744 intel_sdvo->is_lvds = false;
1745
1746 if (response & SDVO_TV_MASK)
1747 intel_sdvo->is_tv = true;
1748 if (response & SDVO_LVDS_MASK)
1749 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1750 }
1751
1752 return ret;
1753}
1754
1755static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1756{
1757 struct edid *edid;
1758
1759
1760 edid = intel_sdvo_get_edid(connector);
1761
1762
1763
1764
1765
1766
1767
1768 if (edid == NULL)
1769 edid = intel_sdvo_get_analog_edid(connector);
1770
1771 if (edid != NULL) {
1772 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1773 edid)) {
1774 drm_mode_connector_update_edid_property(connector, edid);
1775 drm_add_edid_modes(connector, edid);
1776 }
1777
1778 kfree(edid);
1779 }
1780}
1781
1782
1783
1784
1785
1786
1787static const struct drm_display_mode sdvo_tv_modes[] = {
1788 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1789 416, 0, 200, 201, 232, 233, 0,
1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1791 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1792 416, 0, 240, 241, 272, 273, 0,
1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1794 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1795 496, 0, 300, 301, 332, 333, 0,
1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1797 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1798 736, 0, 350, 351, 382, 383, 0,
1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1800 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1801 736, 0, 400, 401, 432, 433, 0,
1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1803 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1804 736, 0, 480, 481, 512, 513, 0,
1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1806 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1807 800, 0, 480, 481, 512, 513, 0,
1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1809 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1810 800, 0, 576, 577, 608, 609, 0,
1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1812 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1813 816, 0, 350, 351, 382, 383, 0,
1814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1815 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1816 816, 0, 400, 401, 432, 433, 0,
1817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1818 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1819 816, 0, 480, 481, 512, 513, 0,
1820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1821 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1822 816, 0, 540, 541, 572, 573, 0,
1823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1824 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1825 816, 0, 576, 577, 608, 609, 0,
1826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1827 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1828 864, 0, 576, 577, 608, 609, 0,
1829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1830 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1831 896, 0, 600, 601, 632, 633, 0,
1832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1833 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1834 928, 0, 624, 625, 656, 657, 0,
1835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1836 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1837 1016, 0, 766, 767, 798, 799, 0,
1838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1839 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1840 1120, 0, 768, 769, 800, 801, 0,
1841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1842 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1843 1376, 0, 1024, 1025, 1056, 1057, 0,
1844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1845};
1846
1847static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1848{
1849 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1850 struct intel_sdvo_sdtv_resolution_request tv_res;
1851 uint32_t reply = 0, format_map = 0;
1852 int i;
1853
1854
1855
1856
1857 format_map = 1 << intel_sdvo->tv_format_index;
1858 memcpy(&tv_res, &format_map,
1859 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1860
1861 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1862 return;
1863
1864 BUILD_BUG_ON(sizeof(tv_res) != 3);
1865 if (!intel_sdvo_write_cmd(intel_sdvo,
1866 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1867 &tv_res, sizeof(tv_res)))
1868 return;
1869 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1870 return;
1871
1872 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1873 if (reply & (1 << i)) {
1874 struct drm_display_mode *nmode;
1875 nmode = drm_mode_duplicate(connector->dev,
1876 &sdvo_tv_modes[i]);
1877 if (nmode)
1878 drm_mode_probed_add(connector, nmode);
1879 }
1880}
1881
1882static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1883{
1884 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1885 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1886 struct drm_display_mode *newmode;
1887
1888
1889
1890
1891
1892 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
1893 newmode = drm_mode_duplicate(connector->dev,
1894 dev_priv->vbt.sdvo_lvds_vbt_mode);
1895 if (newmode != NULL) {
1896
1897 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1898 DRM_MODE_TYPE_DRIVER);
1899 drm_mode_probed_add(connector, newmode);
1900 }
1901 }
1902
1903
1904
1905
1906
1907
1908 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1909
1910 list_for_each_entry(newmode, &connector->probed_modes, head) {
1911 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1912 intel_sdvo->sdvo_lvds_fixed_mode =
1913 drm_mode_duplicate(connector->dev, newmode);
1914
1915 intel_sdvo->is_lvds = true;
1916 break;
1917 }
1918 }
1919
1920}
1921
1922static int intel_sdvo_get_modes(struct drm_connector *connector)
1923{
1924 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1925
1926 if (IS_TV(intel_sdvo_connector))
1927 intel_sdvo_get_tv_modes(connector);
1928 else if (IS_LVDS(intel_sdvo_connector))
1929 intel_sdvo_get_lvds_modes(connector);
1930 else
1931 intel_sdvo_get_ddc_modes(connector);
1932
1933 return !list_empty(&connector->probed_modes);
1934}
1935
1936static void
1937intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1938{
1939 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1940 struct drm_device *dev = connector->dev;
1941
1942 if (intel_sdvo_connector->left)
1943 drm_property_destroy(dev, intel_sdvo_connector->left);
1944 if (intel_sdvo_connector->right)
1945 drm_property_destroy(dev, intel_sdvo_connector->right);
1946 if (intel_sdvo_connector->top)
1947 drm_property_destroy(dev, intel_sdvo_connector->top);
1948 if (intel_sdvo_connector->bottom)
1949 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1950 if (intel_sdvo_connector->hpos)
1951 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1952 if (intel_sdvo_connector->vpos)
1953 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1954 if (intel_sdvo_connector->saturation)
1955 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1956 if (intel_sdvo_connector->contrast)
1957 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1958 if (intel_sdvo_connector->hue)
1959 drm_property_destroy(dev, intel_sdvo_connector->hue);
1960 if (intel_sdvo_connector->sharpness)
1961 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1962 if (intel_sdvo_connector->flicker_filter)
1963 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1964 if (intel_sdvo_connector->flicker_filter_2d)
1965 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1966 if (intel_sdvo_connector->flicker_filter_adaptive)
1967 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1968 if (intel_sdvo_connector->tv_luma_filter)
1969 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1970 if (intel_sdvo_connector->tv_chroma_filter)
1971 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1972 if (intel_sdvo_connector->dot_crawl)
1973 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1974 if (intel_sdvo_connector->brightness)
1975 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1976}
1977
1978static void intel_sdvo_destroy(struct drm_connector *connector)
1979{
1980 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1981
1982 if (intel_sdvo_connector->tv_format)
1983 drm_property_destroy(connector->dev,
1984 intel_sdvo_connector->tv_format);
1985
1986 intel_sdvo_destroy_enhance_property(connector);
1987 drm_sysfs_connector_remove(connector);
1988 drm_connector_cleanup(connector);
1989 kfree(intel_sdvo_connector);
1990}
1991
1992static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1993{
1994 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1995 struct edid *edid;
1996 bool has_audio = false;
1997
1998 if (!intel_sdvo->is_hdmi)
1999 return false;
2000
2001 edid = intel_sdvo_get_edid(connector);
2002 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2003 has_audio = drm_detect_monitor_audio(edid);
2004 kfree(edid);
2005
2006 return has_audio;
2007}
2008
2009static int
2010intel_sdvo_set_property(struct drm_connector *connector,
2011 struct drm_property *property,
2012 uint64_t val)
2013{
2014 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2015 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2016 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2017 uint16_t temp_value;
2018 uint8_t cmd;
2019 int ret;
2020
2021 ret = drm_object_property_set_value(&connector->base, property, val);
2022 if (ret)
2023 return ret;
2024
2025 if (property == dev_priv->force_audio_property) {
2026 int i = val;
2027 bool has_audio;
2028
2029 if (i == intel_sdvo_connector->force_audio)
2030 return 0;
2031
2032 intel_sdvo_connector->force_audio = i;
2033
2034 if (i == HDMI_AUDIO_AUTO)
2035 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2036 else
2037 has_audio = (i == HDMI_AUDIO_ON);
2038
2039 if (has_audio == intel_sdvo->has_hdmi_audio)
2040 return 0;
2041
2042 intel_sdvo->has_hdmi_audio = has_audio;
2043 goto done;
2044 }
2045
2046 if (property == dev_priv->broadcast_rgb_property) {
2047 bool old_auto = intel_sdvo->color_range_auto;
2048 uint32_t old_range = intel_sdvo->color_range;
2049
2050 switch (val) {
2051 case INTEL_BROADCAST_RGB_AUTO:
2052 intel_sdvo->color_range_auto = true;
2053 break;
2054 case INTEL_BROADCAST_RGB_FULL:
2055 intel_sdvo->color_range_auto = false;
2056 intel_sdvo->color_range = 0;
2057 break;
2058 case INTEL_BROADCAST_RGB_LIMITED:
2059 intel_sdvo->color_range_auto = false;
2060
2061
2062 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
2063 break;
2064 default:
2065 return -EINVAL;
2066 }
2067
2068 if (old_auto == intel_sdvo->color_range_auto &&
2069 old_range == intel_sdvo->color_range)
2070 return 0;
2071
2072 goto done;
2073 }
2074
2075#define CHECK_PROPERTY(name, NAME) \
2076 if (intel_sdvo_connector->name == property) { \
2077 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2078 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2079 cmd = SDVO_CMD_SET_##NAME; \
2080 intel_sdvo_connector->cur_##name = temp_value; \
2081 goto set_value; \
2082 }
2083
2084 if (property == intel_sdvo_connector->tv_format) {
2085 if (val >= TV_FORMAT_NUM)
2086 return -EINVAL;
2087
2088 if (intel_sdvo->tv_format_index ==
2089 intel_sdvo_connector->tv_format_supported[val])
2090 return 0;
2091
2092 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
2093 goto done;
2094 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
2095 temp_value = val;
2096 if (intel_sdvo_connector->left == property) {
2097 drm_object_property_set_value(&connector->base,
2098 intel_sdvo_connector->right, val);
2099 if (intel_sdvo_connector->left_margin == temp_value)
2100 return 0;
2101
2102 intel_sdvo_connector->left_margin = temp_value;
2103 intel_sdvo_connector->right_margin = temp_value;
2104 temp_value = intel_sdvo_connector->max_hscan -
2105 intel_sdvo_connector->left_margin;
2106 cmd = SDVO_CMD_SET_OVERSCAN_H;
2107 goto set_value;
2108 } else if (intel_sdvo_connector->right == property) {
2109 drm_object_property_set_value(&connector->base,
2110 intel_sdvo_connector->left, val);
2111 if (intel_sdvo_connector->right_margin == temp_value)
2112 return 0;
2113
2114 intel_sdvo_connector->left_margin = temp_value;
2115 intel_sdvo_connector->right_margin = temp_value;
2116 temp_value = intel_sdvo_connector->max_hscan -
2117 intel_sdvo_connector->left_margin;
2118 cmd = SDVO_CMD_SET_OVERSCAN_H;
2119 goto set_value;
2120 } else if (intel_sdvo_connector->top == property) {
2121 drm_object_property_set_value(&connector->base,
2122 intel_sdvo_connector->bottom, val);
2123 if (intel_sdvo_connector->top_margin == temp_value)
2124 return 0;
2125
2126 intel_sdvo_connector->top_margin = temp_value;
2127 intel_sdvo_connector->bottom_margin = temp_value;
2128 temp_value = intel_sdvo_connector->max_vscan -
2129 intel_sdvo_connector->top_margin;
2130 cmd = SDVO_CMD_SET_OVERSCAN_V;
2131 goto set_value;
2132 } else if (intel_sdvo_connector->bottom == property) {
2133 drm_object_property_set_value(&connector->base,
2134 intel_sdvo_connector->top, val);
2135 if (intel_sdvo_connector->bottom_margin == temp_value)
2136 return 0;
2137
2138 intel_sdvo_connector->top_margin = temp_value;
2139 intel_sdvo_connector->bottom_margin = temp_value;
2140 temp_value = intel_sdvo_connector->max_vscan -
2141 intel_sdvo_connector->top_margin;
2142 cmd = SDVO_CMD_SET_OVERSCAN_V;
2143 goto set_value;
2144 }
2145 CHECK_PROPERTY(hpos, HPOS)
2146 CHECK_PROPERTY(vpos, VPOS)
2147 CHECK_PROPERTY(saturation, SATURATION)
2148 CHECK_PROPERTY(contrast, CONTRAST)
2149 CHECK_PROPERTY(hue, HUE)
2150 CHECK_PROPERTY(brightness, BRIGHTNESS)
2151 CHECK_PROPERTY(sharpness, SHARPNESS)
2152 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2153 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2154 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2155 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2156 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
2157 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
2158 }
2159
2160 return -EINVAL;
2161
2162set_value:
2163 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2164 return -EIO;
2165
2166
2167done:
2168 if (intel_sdvo->base.base.crtc)
2169 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2170
2171 return 0;
2172#undef CHECK_PROPERTY
2173}
2174
2175static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2176 .dpms = intel_sdvo_dpms,
2177 .detect = intel_sdvo_detect,
2178 .fill_modes = drm_helper_probe_single_connector_modes,
2179 .set_property = intel_sdvo_set_property,
2180 .destroy = intel_sdvo_destroy,
2181};
2182
2183static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2184 .get_modes = intel_sdvo_get_modes,
2185 .mode_valid = intel_sdvo_mode_valid,
2186 .best_encoder = intel_best_encoder,
2187};
2188
2189static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2190{
2191 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
2192
2193 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2194 drm_mode_destroy(encoder->dev,
2195 intel_sdvo->sdvo_lvds_fixed_mode);
2196
2197 i2c_del_adapter(&intel_sdvo->ddc);
2198 intel_encoder_destroy(encoder);
2199}
2200
2201static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2202 .destroy = intel_sdvo_enc_destroy,
2203};
2204
2205static void
2206intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2207{
2208 uint16_t mask = 0;
2209 unsigned int num_bits;
2210
2211
2212
2213
2214 switch (sdvo->controlled_output) {
2215 case SDVO_OUTPUT_LVDS1:
2216 mask |= SDVO_OUTPUT_LVDS1;
2217 case SDVO_OUTPUT_LVDS0:
2218 mask |= SDVO_OUTPUT_LVDS0;
2219 case SDVO_OUTPUT_TMDS1:
2220 mask |= SDVO_OUTPUT_TMDS1;
2221 case SDVO_OUTPUT_TMDS0:
2222 mask |= SDVO_OUTPUT_TMDS0;
2223 case SDVO_OUTPUT_RGB1:
2224 mask |= SDVO_OUTPUT_RGB1;
2225 case SDVO_OUTPUT_RGB0:
2226 mask |= SDVO_OUTPUT_RGB0;
2227 break;
2228 }
2229
2230
2231 mask &= sdvo->caps.output_flags;
2232 num_bits = hweight16(mask);
2233
2234 if (num_bits > 3)
2235 num_bits = 3;
2236
2237
2238 sdvo->ddc_bus = 1 << num_bits;
2239}
2240
2241
2242
2243
2244
2245
2246
2247
2248static void
2249intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2250 struct intel_sdvo *sdvo, u32 reg)
2251{
2252 struct sdvo_device_mapping *mapping;
2253
2254 if (sdvo->is_sdvob)
2255 mapping = &(dev_priv->sdvo_mappings[0]);
2256 else
2257 mapping = &(dev_priv->sdvo_mappings[1]);
2258
2259 if (mapping->initialized)
2260 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2261 else
2262 intel_sdvo_guess_ddc_bus(sdvo);
2263}
2264
2265static void
2266intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2267 struct intel_sdvo *sdvo, u32 reg)
2268{
2269 struct sdvo_device_mapping *mapping;
2270 u8 pin;
2271
2272 if (sdvo->is_sdvob)
2273 mapping = &dev_priv->sdvo_mappings[0];
2274 else
2275 mapping = &dev_priv->sdvo_mappings[1];
2276
2277 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
2278 pin = mapping->i2c_pin;
2279 else
2280 pin = GMBUS_PORT_DPB;
2281
2282 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2283
2284
2285
2286
2287 intel_gmbus_force_bit(sdvo->i2c, true);
2288}
2289
2290
2291static void
2292intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2293{
2294 intel_gmbus_force_bit(sdvo->i2c, false);
2295}
2296
2297static bool
2298intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2299{
2300 return intel_sdvo_check_supp_encode(intel_sdvo);
2301}
2302
2303static u8
2304intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 struct sdvo_device_mapping *my_mapping, *other_mapping;
2308
2309 if (sdvo->is_sdvob) {
2310 my_mapping = &dev_priv->sdvo_mappings[0];
2311 other_mapping = &dev_priv->sdvo_mappings[1];
2312 } else {
2313 my_mapping = &dev_priv->sdvo_mappings[1];
2314 other_mapping = &dev_priv->sdvo_mappings[0];
2315 }
2316
2317
2318 if (my_mapping->slave_addr)
2319 return my_mapping->slave_addr;
2320
2321
2322
2323
2324 if (other_mapping->slave_addr) {
2325 if (other_mapping->slave_addr == 0x70)
2326 return 0x72;
2327 else
2328 return 0x70;
2329 }
2330
2331
2332
2333
2334 if (sdvo->is_sdvob)
2335 return 0x70;
2336 else
2337 return 0x72;
2338}
2339
2340static void
2341intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2342 struct intel_sdvo *encoder)
2343{
2344 drm_connector_init(encoder->base.base.dev,
2345 &connector->base.base,
2346 &intel_sdvo_connector_funcs,
2347 connector->base.base.connector_type);
2348
2349 drm_connector_helper_add(&connector->base.base,
2350 &intel_sdvo_connector_helper_funcs);
2351
2352 connector->base.base.interlace_allowed = 1;
2353 connector->base.base.doublescan_allowed = 0;
2354 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2355 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2356
2357 intel_connector_attach_encoder(&connector->base, &encoder->base);
2358 drm_sysfs_connector_add(&connector->base.base);
2359}
2360
2361static void
2362intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2363 struct intel_sdvo_connector *connector)
2364{
2365 struct drm_device *dev = connector->base.base.dev;
2366
2367 intel_attach_force_audio_property(&connector->base.base);
2368 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2369 intel_attach_broadcast_rgb_property(&connector->base.base);
2370 intel_sdvo->color_range_auto = true;
2371 }
2372}
2373
2374static bool
2375intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2376{
2377 struct drm_encoder *encoder = &intel_sdvo->base.base;
2378 struct drm_connector *connector;
2379 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2380 struct intel_connector *intel_connector;
2381 struct intel_sdvo_connector *intel_sdvo_connector;
2382
2383 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2384 if (!intel_sdvo_connector)
2385 return false;
2386
2387 if (device == 0) {
2388 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2389 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2390 } else if (device == 1) {
2391 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2392 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2393 }
2394
2395 intel_connector = &intel_sdvo_connector->base;
2396 connector = &intel_connector->base;
2397 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2398 intel_sdvo_connector->output_flag) {
2399 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2400
2401
2402
2403 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2404 intel_sdvo_enable_hotplug(intel_encoder);
2405 } else {
2406 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2407 }
2408 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2409 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2410
2411 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2412 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2413 intel_sdvo->is_hdmi = true;
2414 }
2415
2416 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2417 if (intel_sdvo->is_hdmi)
2418 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2419
2420 return true;
2421}
2422
2423static bool
2424intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2425{
2426 struct drm_encoder *encoder = &intel_sdvo->base.base;
2427 struct drm_connector *connector;
2428 struct intel_connector *intel_connector;
2429 struct intel_sdvo_connector *intel_sdvo_connector;
2430
2431 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2432 if (!intel_sdvo_connector)
2433 return false;
2434
2435 intel_connector = &intel_sdvo_connector->base;
2436 connector = &intel_connector->base;
2437 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2438 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2439
2440 intel_sdvo->controlled_output |= type;
2441 intel_sdvo_connector->output_flag = type;
2442
2443 intel_sdvo->is_tv = true;
2444
2445 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2446
2447 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2448 goto err;
2449
2450 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2451 goto err;
2452
2453 return true;
2454
2455err:
2456 intel_sdvo_destroy(connector);
2457 return false;
2458}
2459
2460static bool
2461intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2462{
2463 struct drm_encoder *encoder = &intel_sdvo->base.base;
2464 struct drm_connector *connector;
2465 struct intel_connector *intel_connector;
2466 struct intel_sdvo_connector *intel_sdvo_connector;
2467
2468 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2469 if (!intel_sdvo_connector)
2470 return false;
2471
2472 intel_connector = &intel_sdvo_connector->base;
2473 connector = &intel_connector->base;
2474 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2475 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2476 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2477
2478 if (device == 0) {
2479 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2480 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2481 } else if (device == 1) {
2482 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2483 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2484 }
2485
2486 intel_sdvo_connector_init(intel_sdvo_connector,
2487 intel_sdvo);
2488 return true;
2489}
2490
2491static bool
2492intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2493{
2494 struct drm_encoder *encoder = &intel_sdvo->base.base;
2495 struct drm_connector *connector;
2496 struct intel_connector *intel_connector;
2497 struct intel_sdvo_connector *intel_sdvo_connector;
2498
2499 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2500 if (!intel_sdvo_connector)
2501 return false;
2502
2503 intel_connector = &intel_sdvo_connector->base;
2504 connector = &intel_connector->base;
2505 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2506 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2507
2508 if (device == 0) {
2509 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2510 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2511 } else if (device == 1) {
2512 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2513 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2514 }
2515
2516 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2517 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2518 goto err;
2519
2520 return true;
2521
2522err:
2523 intel_sdvo_destroy(connector);
2524 return false;
2525}
2526
2527static bool
2528intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2529{
2530 intel_sdvo->is_tv = false;
2531 intel_sdvo->is_lvds = false;
2532
2533
2534
2535 if (flags & SDVO_OUTPUT_TMDS0)
2536 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2537 return false;
2538
2539 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2540 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2541 return false;
2542
2543
2544 if (flags & SDVO_OUTPUT_SVID0)
2545 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2546 return false;
2547
2548 if (flags & SDVO_OUTPUT_CVBS0)
2549 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2550 return false;
2551
2552 if (flags & SDVO_OUTPUT_YPRPB0)
2553 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2554 return false;
2555
2556 if (flags & SDVO_OUTPUT_RGB0)
2557 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2558 return false;
2559
2560 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2561 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2562 return false;
2563
2564 if (flags & SDVO_OUTPUT_LVDS0)
2565 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2566 return false;
2567
2568 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2569 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2570 return false;
2571
2572 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2573 unsigned char bytes[2];
2574
2575 intel_sdvo->controlled_output = 0;
2576 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2577 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2578 SDVO_NAME(intel_sdvo),
2579 bytes[0], bytes[1]);
2580 return false;
2581 }
2582 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2583
2584 return true;
2585}
2586
2587static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2588{
2589 struct drm_device *dev = intel_sdvo->base.base.dev;
2590 struct drm_connector *connector, *tmp;
2591
2592 list_for_each_entry_safe(connector, tmp,
2593 &dev->mode_config.connector_list, head) {
2594 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2595 intel_sdvo_destroy(connector);
2596 }
2597}
2598
2599static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2600 struct intel_sdvo_connector *intel_sdvo_connector,
2601 int type)
2602{
2603 struct drm_device *dev = intel_sdvo->base.base.dev;
2604 struct intel_sdvo_tv_format format;
2605 uint32_t format_map, i;
2606
2607 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2608 return false;
2609
2610 BUILD_BUG_ON(sizeof(format) != 6);
2611 if (!intel_sdvo_get_value(intel_sdvo,
2612 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2613 &format, sizeof(format)))
2614 return false;
2615
2616 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2617
2618 if (format_map == 0)
2619 return false;
2620
2621 intel_sdvo_connector->format_supported_num = 0;
2622 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2623 if (format_map & (1 << i))
2624 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2625
2626
2627 intel_sdvo_connector->tv_format =
2628 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2629 "mode", intel_sdvo_connector->format_supported_num);
2630 if (!intel_sdvo_connector->tv_format)
2631 return false;
2632
2633 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2634 drm_property_add_enum(
2635 intel_sdvo_connector->tv_format, i,
2636 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2637
2638 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2639 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2640 intel_sdvo_connector->tv_format, 0);
2641 return true;
2642
2643}
2644
2645#define ENHANCEMENT(name, NAME) do { \
2646 if (enhancements.name) { \
2647 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2648 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2649 return false; \
2650 intel_sdvo_connector->max_##name = data_value[0]; \
2651 intel_sdvo_connector->cur_##name = response; \
2652 intel_sdvo_connector->name = \
2653 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2654 if (!intel_sdvo_connector->name) return false; \
2655 drm_object_attach_property(&connector->base, \
2656 intel_sdvo_connector->name, \
2657 intel_sdvo_connector->cur_##name); \
2658 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2659 data_value[0], data_value[1], response); \
2660 } \
2661} while (0)
2662
2663static bool
2664intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2665 struct intel_sdvo_connector *intel_sdvo_connector,
2666 struct intel_sdvo_enhancements_reply enhancements)
2667{
2668 struct drm_device *dev = intel_sdvo->base.base.dev;
2669 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2670 uint16_t response, data_value[2];
2671
2672
2673 if (enhancements.overscan_h) {
2674 if (!intel_sdvo_get_value(intel_sdvo,
2675 SDVO_CMD_GET_MAX_OVERSCAN_H,
2676 &data_value, 4))
2677 return false;
2678
2679 if (!intel_sdvo_get_value(intel_sdvo,
2680 SDVO_CMD_GET_OVERSCAN_H,
2681 &response, 2))
2682 return false;
2683
2684 intel_sdvo_connector->max_hscan = data_value[0];
2685 intel_sdvo_connector->left_margin = data_value[0] - response;
2686 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2687 intel_sdvo_connector->left =
2688 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2689 if (!intel_sdvo_connector->left)
2690 return false;
2691
2692 drm_object_attach_property(&connector->base,
2693 intel_sdvo_connector->left,
2694 intel_sdvo_connector->left_margin);
2695
2696 intel_sdvo_connector->right =
2697 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2698 if (!intel_sdvo_connector->right)
2699 return false;
2700
2701 drm_object_attach_property(&connector->base,
2702 intel_sdvo_connector->right,
2703 intel_sdvo_connector->right_margin);
2704 DRM_DEBUG_KMS("h_overscan: max %d, "
2705 "default %d, current %d\n",
2706 data_value[0], data_value[1], response);
2707 }
2708
2709 if (enhancements.overscan_v) {
2710 if (!intel_sdvo_get_value(intel_sdvo,
2711 SDVO_CMD_GET_MAX_OVERSCAN_V,
2712 &data_value, 4))
2713 return false;
2714
2715 if (!intel_sdvo_get_value(intel_sdvo,
2716 SDVO_CMD_GET_OVERSCAN_V,
2717 &response, 2))
2718 return false;
2719
2720 intel_sdvo_connector->max_vscan = data_value[0];
2721 intel_sdvo_connector->top_margin = data_value[0] - response;
2722 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2723 intel_sdvo_connector->top =
2724 drm_property_create_range(dev, 0,
2725 "top_margin", 0, data_value[0]);
2726 if (!intel_sdvo_connector->top)
2727 return false;
2728
2729 drm_object_attach_property(&connector->base,
2730 intel_sdvo_connector->top,
2731 intel_sdvo_connector->top_margin);
2732
2733 intel_sdvo_connector->bottom =
2734 drm_property_create_range(dev, 0,
2735 "bottom_margin", 0, data_value[0]);
2736 if (!intel_sdvo_connector->bottom)
2737 return false;
2738
2739 drm_object_attach_property(&connector->base,
2740 intel_sdvo_connector->bottom,
2741 intel_sdvo_connector->bottom_margin);
2742 DRM_DEBUG_KMS("v_overscan: max %d, "
2743 "default %d, current %d\n",
2744 data_value[0], data_value[1], response);
2745 }
2746
2747 ENHANCEMENT(hpos, HPOS);
2748 ENHANCEMENT(vpos, VPOS);
2749 ENHANCEMENT(saturation, SATURATION);
2750 ENHANCEMENT(contrast, CONTRAST);
2751 ENHANCEMENT(hue, HUE);
2752 ENHANCEMENT(sharpness, SHARPNESS);
2753 ENHANCEMENT(brightness, BRIGHTNESS);
2754 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2755 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2756 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2757 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2758 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2759
2760 if (enhancements.dot_crawl) {
2761 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2762 return false;
2763
2764 intel_sdvo_connector->max_dot_crawl = 1;
2765 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2766 intel_sdvo_connector->dot_crawl =
2767 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2768 if (!intel_sdvo_connector->dot_crawl)
2769 return false;
2770
2771 drm_object_attach_property(&connector->base,
2772 intel_sdvo_connector->dot_crawl,
2773 intel_sdvo_connector->cur_dot_crawl);
2774 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2775 }
2776
2777 return true;
2778}
2779
2780static bool
2781intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2782 struct intel_sdvo_connector *intel_sdvo_connector,
2783 struct intel_sdvo_enhancements_reply enhancements)
2784{
2785 struct drm_device *dev = intel_sdvo->base.base.dev;
2786 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2787 uint16_t response, data_value[2];
2788
2789 ENHANCEMENT(brightness, BRIGHTNESS);
2790
2791 return true;
2792}
2793#undef ENHANCEMENT
2794
2795static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2796 struct intel_sdvo_connector *intel_sdvo_connector)
2797{
2798 union {
2799 struct intel_sdvo_enhancements_reply reply;
2800 uint16_t response;
2801 } enhancements;
2802
2803 BUILD_BUG_ON(sizeof(enhancements) != 2);
2804
2805 enhancements.response = 0;
2806 intel_sdvo_get_value(intel_sdvo,
2807 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2808 &enhancements, sizeof(enhancements));
2809 if (enhancements.response == 0) {
2810 DRM_DEBUG_KMS("No enhancement is supported\n");
2811 return true;
2812 }
2813
2814 if (IS_TV(intel_sdvo_connector))
2815 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2816 else if (IS_LVDS(intel_sdvo_connector))
2817 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2818 else
2819 return true;
2820}
2821
2822static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2823 struct i2c_msg *msgs,
2824 int num)
2825{
2826 struct intel_sdvo *sdvo = adapter->algo_data;
2827
2828 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2829 return -EIO;
2830
2831 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2832}
2833
2834static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2835{
2836 struct intel_sdvo *sdvo = adapter->algo_data;
2837 return sdvo->i2c->algo->functionality(sdvo->i2c);
2838}
2839
2840static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2841 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2842 .functionality = intel_sdvo_ddc_proxy_func
2843};
2844
2845static bool
2846intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2847 struct drm_device *dev)
2848{
2849 sdvo->ddc.owner = THIS_MODULE;
2850 sdvo->ddc.class = I2C_CLASS_DDC;
2851 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2852 sdvo->ddc.dev.parent = &dev->pdev->dev;
2853 sdvo->ddc.algo_data = sdvo;
2854 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2855
2856 return i2c_add_adapter(&sdvo->ddc) == 0;
2857}
2858
2859bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2860{
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 struct intel_encoder *intel_encoder;
2863 struct intel_sdvo *intel_sdvo;
2864 int i;
2865 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2866 if (!intel_sdvo)
2867 return false;
2868
2869 intel_sdvo->sdvo_reg = sdvo_reg;
2870 intel_sdvo->is_sdvob = is_sdvob;
2871 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
2872 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2873 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2874 goto err_i2c_bus;
2875
2876
2877 intel_encoder = &intel_sdvo->base;
2878 intel_encoder->type = INTEL_OUTPUT_SDVO;
2879 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2880
2881
2882 for (i = 0; i < 0x40; i++) {
2883 u8 byte;
2884
2885 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
2886 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2887 SDVO_NAME(intel_sdvo));
2888 goto err;
2889 }
2890 }
2891
2892 intel_encoder->compute_config = intel_sdvo_compute_config;
2893 intel_encoder->disable = intel_disable_sdvo;
2894 intel_encoder->mode_set = intel_sdvo_mode_set;
2895 intel_encoder->enable = intel_enable_sdvo;
2896 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2897 intel_encoder->get_config = intel_sdvo_get_config;
2898
2899
2900 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2901 goto err;
2902
2903 if (intel_sdvo_output_setup(intel_sdvo,
2904 intel_sdvo->caps.output_flags) != true) {
2905 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2906 SDVO_NAME(intel_sdvo));
2907
2908 goto err_output;
2909 }
2910
2911
2912
2913
2914 if (intel_sdvo->hotplug_active) {
2915 intel_encoder->hpd_pin =
2916 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2917 }
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927 intel_sdvo->base.cloneable = false;
2928
2929 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2930
2931
2932 if (!intel_sdvo_set_target_input(intel_sdvo))
2933 goto err_output;
2934
2935 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2936 &intel_sdvo->pixel_clock_min,
2937 &intel_sdvo->pixel_clock_max))
2938 goto err_output;
2939
2940 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2941 "clock range %dMHz - %dMHz, "
2942 "input 1: %c, input 2: %c, "
2943 "output 1: %c, output 2: %c\n",
2944 SDVO_NAME(intel_sdvo),
2945 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2946 intel_sdvo->caps.device_rev_id,
2947 intel_sdvo->pixel_clock_min / 1000,
2948 intel_sdvo->pixel_clock_max / 1000,
2949 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2950 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2951
2952 intel_sdvo->caps.output_flags &
2953 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2954 intel_sdvo->caps.output_flags &
2955 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2956 return true;
2957
2958err_output:
2959 intel_sdvo_output_cleanup(intel_sdvo);
2960
2961err:
2962 drm_encoder_cleanup(&intel_encoder->base);
2963 i2c_del_adapter(&intel_sdvo->ddc);
2964err_i2c_bus:
2965 intel_sdvo_unselect_i2c_bus(intel_sdvo);
2966 kfree(intel_sdvo);
2967
2968 return false;
2969}
2970