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31#ifndef __MGA_DRV_H__
32#define __MGA_DRV_H__
33
34
35
36
37#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
38
39#define DRIVER_NAME "mga"
40#define DRIVER_DESC "Matrox G200/G400"
41#define DRIVER_DATE "20051102"
42
43#define DRIVER_MAJOR 3
44#define DRIVER_MINOR 2
45#define DRIVER_PATCHLEVEL 1
46
47typedef struct drm_mga_primary_buffer {
48 u8 *start;
49 u8 *end;
50 int size;
51
52 u32 tail;
53 int space;
54 volatile long wrapped;
55
56 volatile u32 *status;
57
58 u32 last_flush;
59 u32 last_wrap;
60
61 u32 high_mark;
62} drm_mga_primary_buffer_t;
63
64typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev;
67 drm_mga_age_t age;
68 struct drm_buf *buf;
69} drm_mga_freelist_t;
70
71typedef struct {
72 drm_mga_freelist_t *list_entry;
73 int discard;
74 int dispatched;
75} drm_mga_buf_priv_t;
76
77typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv;
80
81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail;
83
84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
86
87 int chipset;
88 int usec_timeout;
89
90
91
92
93
94
95 int used_new_dma_init;
96
97
98
99
100
101 u32 dma_access;
102
103
104
105
106
107
108 u32 wagp_enable;
109
110
111
112
113
114
115
116 resource_size_t mmio_base;
117 resource_size_t mmio_size;
118
119
120 u32 clear_cmd;
121 u32 maccess;
122
123 atomic_t vbl_received;
124 wait_queue_head_t fence_queue;
125 atomic_t last_fence_retired;
126 u32 next_fence_to_post;
127
128 unsigned int fb_cpp;
129 unsigned int front_offset;
130 unsigned int front_pitch;
131 unsigned int back_offset;
132 unsigned int back_pitch;
133
134 unsigned int depth_cpp;
135 unsigned int depth_offset;
136 unsigned int depth_pitch;
137
138 unsigned int texture_offset;
139 unsigned int texture_size;
140
141 drm_local_map_t *sarea;
142 drm_local_map_t *mmio;
143 drm_local_map_t *status;
144 drm_local_map_t *warp;
145 drm_local_map_t *primary;
146 drm_local_map_t *agp_textures;
147
148 unsigned long agp_handle;
149 unsigned int agp_size;
150} drm_mga_private_t;
151
152extern struct drm_ioctl_desc mga_ioctls[];
153extern int mga_max_ioctl;
154
155
156extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
157 struct drm_file *file_priv);
158extern int mga_dma_init(struct drm_device *dev, void *data,
159 struct drm_file *file_priv);
160extern int mga_dma_flush(struct drm_device *dev, void *data,
161 struct drm_file *file_priv);
162extern int mga_dma_reset(struct drm_device *dev, void *data,
163 struct drm_file *file_priv);
164extern int mga_dma_buffers(struct drm_device *dev, void *data,
165 struct drm_file *file_priv);
166extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
167extern int mga_driver_unload(struct drm_device *dev);
168extern void mga_driver_lastclose(struct drm_device *dev);
169extern int mga_driver_dma_quiescent(struct drm_device *dev);
170
171extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
172
173extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
174extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
175extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
176
177extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
178
179
180extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
181extern int mga_warp_init(drm_mga_private_t *dev_priv);
182
183
184extern int mga_enable_vblank(struct drm_device *dev, int crtc);
185extern void mga_disable_vblank(struct drm_device *dev, int crtc);
186extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
187extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
188extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
189extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
190extern void mga_driver_irq_preinstall(struct drm_device *dev);
191extern int mga_driver_irq_postinstall(struct drm_device *dev);
192extern void mga_driver_irq_uninstall(struct drm_device *dev);
193extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
194 unsigned long arg);
195
196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
197
198#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
199#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
200#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
201#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
202
203#define DWGREG0 0x1c00
204#define DWGREG0_END 0x1dff
205#define DWGREG1 0x2c00
206#define DWGREG1_END 0x2dff
207
208#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
209#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
210#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
211#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
212
213
214
215
216
217#define MGA_EMIT_STATE(dev_priv, dirty) \
218do { \
219 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
220 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
221 mga_g400_emit_state(dev_priv); \
222 else \
223 mga_g200_emit_state(dev_priv); \
224 } \
225} while (0)
226
227#define WRAP_TEST_WITH_RETURN(dev_priv) \
228do { \
229 if (test_bit(0, &dev_priv->prim.wrapped)) { \
230 if (mga_is_idle(dev_priv)) { \
231 mga_do_dma_wrap_end(dev_priv); \
232 } else if (dev_priv->prim.space < \
233 dev_priv->prim.high_mark) { \
234 if (MGA_DMA_DEBUG) \
235 DRM_INFO("wrap...\n"); \
236 return -EBUSY; \
237 } \
238 } \
239} while (0)
240
241#define WRAP_WAIT_WITH_RETURN(dev_priv) \
242do { \
243 if (test_bit(0, &dev_priv->prim.wrapped)) { \
244 if (mga_do_wait_for_idle(dev_priv) < 0) { \
245 if (MGA_DMA_DEBUG) \
246 DRM_INFO("wrap...\n"); \
247 return -EBUSY; \
248 } \
249 mga_do_dma_wrap_end(dev_priv); \
250 } \
251} while (0)
252
253
254
255
256
257#define MGA_VERBOSE 0
258
259#define DMA_LOCALS unsigned int write; volatile u8 *prim;
260
261#define DMA_BLOCK_SIZE (5 * sizeof(u32))
262
263#define BEGIN_DMA(n) \
264do { \
265 if (MGA_VERBOSE) { \
266 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
267 DRM_INFO(" space=0x%x req=0x%Zx\n", \
268 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
269 } \
270 prim = dev_priv->prim.start; \
271 write = dev_priv->prim.tail; \
272} while (0)
273
274#define BEGIN_DMA_WRAP() \
275do { \
276 if (MGA_VERBOSE) { \
277 DRM_INFO("BEGIN_DMA()\n"); \
278 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
279 } \
280 prim = dev_priv->prim.start; \
281 write = dev_priv->prim.tail; \
282} while (0)
283
284#define ADVANCE_DMA() \
285do { \
286 dev_priv->prim.tail = write; \
287 if (MGA_VERBOSE) \
288 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
289 write, dev_priv->prim.space); \
290} while (0)
291
292#define FLUSH_DMA() \
293do { \
294 if (0) { \
295 DRM_INFO("\n"); \
296 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
297 dev_priv->prim.tail, \
298 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
299 dev_priv->primary->offset)); \
300 } \
301 if (!test_bit(0, &dev_priv->prim.wrapped)) { \
302 if (dev_priv->prim.space < dev_priv->prim.high_mark) \
303 mga_do_dma_wrap_start(dev_priv); \
304 else \
305 mga_do_dma_flush(dev_priv); \
306 } \
307} while (0)
308
309
310
311#define DMA_WRITE(offset, val) \
312do { \
313 if (MGA_VERBOSE) \
314 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
315 (u32)(val), write + (offset) * sizeof(u32)); \
316 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
317} while (0)
318
319#define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
320do { \
321 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
322 (DMAREG(reg1) << 8) | \
323 (DMAREG(reg2) << 16) | \
324 (DMAREG(reg3) << 24))); \
325 DMA_WRITE(1, val0); \
326 DMA_WRITE(2, val1); \
327 DMA_WRITE(3, val2); \
328 DMA_WRITE(4, val3); \
329 write += DMA_BLOCK_SIZE; \
330} while (0)
331
332
333
334
335#define SET_AGE(age, h, w) \
336do { \
337 (age)->head = h; \
338 (age)->wrap = w; \
339} while (0)
340
341#define TEST_AGE(age, h, w) ((age)->wrap < w || \
342 ((age)->wrap == w && \
343 (age)->head < h))
344
345#define AGE_BUFFER(buf_priv) \
346do { \
347 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
348 if ((buf_priv)->dispatched) { \
349 entry->age.head = (dev_priv->prim.tail + \
350 dev_priv->primary->offset); \
351 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
352 } else { \
353 entry->age.head = 0; \
354 entry->age.wrap = 0; \
355 } \
356} while (0)
357
358#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
359 MGA_DWGENGSTS | \
360 MGA_ENDPRDMASTS)
361#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
362 MGA_ENDPRDMASTS)
363
364#define MGA_DMA_DEBUG 0
365
366
367
368#define MGA_CRTC_INDEX 0x1fd4
369#define MGA_CRTC_DATA 0x1fd5
370
371
372#define MGA_VINTCLR (1 << 4)
373#define MGA_VINTEN (1 << 5)
374
375#define MGA_ALPHACTRL 0x2c7c
376#define MGA_AR0 0x1c60
377#define MGA_AR1 0x1c64
378#define MGA_AR2 0x1c68
379#define MGA_AR3 0x1c6c
380#define MGA_AR4 0x1c70
381#define MGA_AR5 0x1c74
382#define MGA_AR6 0x1c78
383
384#define MGA_CXBNDRY 0x1c80
385#define MGA_CXLEFT 0x1ca0
386#define MGA_CXRIGHT 0x1ca4
387
388#define MGA_DMAPAD 0x1c54
389#define MGA_DSTORG 0x2cb8
390#define MGA_DWGCTL 0x1c00
391# define MGA_OPCOD_MASK (15 << 0)
392# define MGA_OPCOD_TRAP (4 << 0)
393# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
394# define MGA_OPCOD_BITBLT (8 << 0)
395# define MGA_OPCOD_ILOAD (9 << 0)
396# define MGA_ATYPE_MASK (7 << 4)
397# define MGA_ATYPE_RPL (0 << 4)
398# define MGA_ATYPE_RSTR (1 << 4)
399# define MGA_ATYPE_ZI (3 << 4)
400# define MGA_ATYPE_BLK (4 << 4)
401# define MGA_ATYPE_I (7 << 4)
402# define MGA_LINEAR (1 << 7)
403# define MGA_ZMODE_MASK (7 << 8)
404# define MGA_ZMODE_NOZCMP (0 << 8)
405# define MGA_ZMODE_ZE (2 << 8)
406# define MGA_ZMODE_ZNE (3 << 8)
407# define MGA_ZMODE_ZLT (4 << 8)
408# define MGA_ZMODE_ZLTE (5 << 8)
409# define MGA_ZMODE_ZGT (6 << 8)
410# define MGA_ZMODE_ZGTE (7 << 8)
411# define MGA_SOLID (1 << 11)
412# define MGA_ARZERO (1 << 12)
413# define MGA_SGNZERO (1 << 13)
414# define MGA_SHIFTZERO (1 << 14)
415# define MGA_BOP_MASK (15 << 16)
416# define MGA_BOP_ZERO (0 << 16)
417# define MGA_BOP_DST (10 << 16)
418# define MGA_BOP_SRC (12 << 16)
419# define MGA_BOP_ONE (15 << 16)
420# define MGA_TRANS_SHIFT 20
421# define MGA_TRANS_MASK (15 << 20)
422# define MGA_BLTMOD_MASK (15 << 25)
423# define MGA_BLTMOD_BMONOLEF (0 << 25)
424# define MGA_BLTMOD_BMONOWF (4 << 25)
425# define MGA_BLTMOD_PLAN (1 << 25)
426# define MGA_BLTMOD_BFCOL (2 << 25)
427# define MGA_BLTMOD_BU32BGR (3 << 25)
428# define MGA_BLTMOD_BU32RGB (7 << 25)
429# define MGA_BLTMOD_BU24BGR (11 << 25)
430# define MGA_BLTMOD_BU24RGB (15 << 25)
431# define MGA_PATTERN (1 << 29)
432# define MGA_TRANSC (1 << 30)
433# define MGA_CLIPDIS (1 << 31)
434#define MGA_DWGSYNC 0x2c4c
435
436#define MGA_FCOL 0x1c24
437#define MGA_FIFOSTATUS 0x1e10
438#define MGA_FOGCOL 0x1cf4
439#define MGA_FXBNDRY 0x1c84
440#define MGA_FXLEFT 0x1ca8
441#define MGA_FXRIGHT 0x1cac
442
443#define MGA_ICLEAR 0x1e18
444# define MGA_SOFTRAPICLR (1 << 0)
445# define MGA_VLINEICLR (1 << 5)
446#define MGA_IEN 0x1e1c
447# define MGA_SOFTRAPIEN (1 << 0)
448# define MGA_VLINEIEN (1 << 5)
449
450#define MGA_LEN 0x1c5c
451
452#define MGA_MACCESS 0x1c04
453
454#define MGA_PITCH 0x1c8c
455#define MGA_PLNWT 0x1c1c
456#define MGA_PRIMADDRESS 0x1e58
457# define MGA_DMA_GENERAL (0 << 0)
458# define MGA_DMA_BLIT (1 << 0)
459# define MGA_DMA_VECTOR (2 << 0)
460# define MGA_DMA_VERTEX (3 << 0)
461#define MGA_PRIMEND 0x1e5c
462# define MGA_PRIMNOSTART (1 << 0)
463# define MGA_PAGPXFER (1 << 1)
464#define MGA_PRIMPTR 0x1e50
465# define MGA_PRIMPTREN0 (1 << 0)
466# define MGA_PRIMPTREN1 (1 << 1)
467
468#define MGA_RST 0x1e40
469# define MGA_SOFTRESET (1 << 0)
470# define MGA_SOFTEXTRST (1 << 1)
471
472#define MGA_SECADDRESS 0x2c40
473#define MGA_SECEND 0x2c44
474#define MGA_SETUPADDRESS 0x2cd0
475#define MGA_SETUPEND 0x2cd4
476#define MGA_SGN 0x1c58
477#define MGA_SOFTRAP 0x2c48
478#define MGA_SRCORG 0x2cb4
479# define MGA_SRMMAP_MASK (1 << 0)
480# define MGA_SRCMAP_FB (0 << 0)
481# define MGA_SRCMAP_SYSMEM (1 << 0)
482# define MGA_SRCACC_MASK (1 << 1)
483# define MGA_SRCACC_PCI (0 << 1)
484# define MGA_SRCACC_AGP (1 << 1)
485#define MGA_STATUS 0x1e14
486# define MGA_SOFTRAPEN (1 << 0)
487# define MGA_VSYNCPEN (1 << 4)
488# define MGA_VLINEPEN (1 << 5)
489# define MGA_DWGENGSTS (1 << 16)
490# define MGA_ENDPRDMASTS (1 << 17)
491#define MGA_STENCIL 0x2cc8
492#define MGA_STENCILCTL 0x2ccc
493
494#define MGA_TDUALSTAGE0 0x2cf8
495#define MGA_TDUALSTAGE1 0x2cfc
496#define MGA_TEXBORDERCOL 0x2c5c
497#define MGA_TEXCTL 0x2c30
498#define MGA_TEXCTL2 0x2c3c
499# define MGA_DUALTEX (1 << 7)
500# define MGA_G400_TC2_MAGIC (1 << 15)
501# define MGA_MAP1_ENABLE (1 << 31)
502#define MGA_TEXFILTER 0x2c58
503#define MGA_TEXHEIGHT 0x2c2c
504#define MGA_TEXORG 0x2c24
505# define MGA_TEXORGMAP_MASK (1 << 0)
506# define MGA_TEXORGMAP_FB (0 << 0)
507# define MGA_TEXORGMAP_SYSMEM (1 << 0)
508# define MGA_TEXORGACC_MASK (1 << 1)
509# define MGA_TEXORGACC_PCI (0 << 1)
510# define MGA_TEXORGACC_AGP (1 << 1)
511#define MGA_TEXORG1 0x2ca4
512#define MGA_TEXORG2 0x2ca8
513#define MGA_TEXORG3 0x2cac
514#define MGA_TEXORG4 0x2cb0
515#define MGA_TEXTRANS 0x2c34
516#define MGA_TEXTRANSHIGH 0x2c38
517#define MGA_TEXWIDTH 0x2c28
518
519#define MGA_WACCEPTSEQ 0x1dd4
520#define MGA_WCODEADDR 0x1e6c
521#define MGA_WFLAG 0x1dc4
522#define MGA_WFLAG1 0x1de0
523#define MGA_WFLAGNB 0x1e64
524#define MGA_WFLAGNB1 0x1e08
525#define MGA_WGETMSB 0x1dc8
526#define MGA_WIADDR 0x1dc0
527#define MGA_WIADDR2 0x1dd8
528# define MGA_WMODE_SUSPEND (0 << 0)
529# define MGA_WMODE_RESUME (1 << 0)
530# define MGA_WMODE_JUMP (2 << 0)
531# define MGA_WMODE_START (3 << 0)
532# define MGA_WAGP_ENABLE (1 << 2)
533#define MGA_WMISC 0x1e70
534# define MGA_WUCODECACHE_ENABLE (1 << 0)
535# define MGA_WMASTER_ENABLE (1 << 1)
536# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
537#define MGA_WVRTXSZ 0x1dcc
538
539#define MGA_YBOT 0x1c9c
540#define MGA_YDST 0x1c90
541#define MGA_YDSTLEN 0x1c88
542#define MGA_YDSTORG 0x1c94
543#define MGA_YTOP 0x1c98
544
545#define MGA_ZORG 0x1c0c
546
547
548
549#define MGA_EXEC 0x0100
550
551
552
553#define MGA_AGP_PLL 0x1e4c
554# define MGA_AGP2XPLL_DISABLE (0 << 0)
555# define MGA_AGP2XPLL_ENABLE (1 << 0)
556
557
558
559#define MGA_WR0 0x2d00
560#define MGA_WR1 0x2d04
561#define MGA_WR2 0x2d08
562#define MGA_WR3 0x2d0c
563#define MGA_WR4 0x2d10
564#define MGA_WR5 0x2d14
565#define MGA_WR6 0x2d18
566#define MGA_WR7 0x2d1c
567#define MGA_WR8 0x2d20
568#define MGA_WR9 0x2d24
569#define MGA_WR10 0x2d28
570#define MGA_WR11 0x2d2c
571#define MGA_WR12 0x2d30
572#define MGA_WR13 0x2d34
573#define MGA_WR14 0x2d38
574#define MGA_WR15 0x2d3c
575#define MGA_WR16 0x2d40
576#define MGA_WR17 0x2d44
577#define MGA_WR18 0x2d48
578#define MGA_WR19 0x2d4c
579#define MGA_WR20 0x2d50
580#define MGA_WR21 0x2d54
581#define MGA_WR22 0x2d58
582#define MGA_WR23 0x2d5c
583#define MGA_WR24 0x2d60
584#define MGA_WR25 0x2d64
585#define MGA_WR26 0x2d68
586#define MGA_WR27 0x2d6c
587#define MGA_WR28 0x2d70
588#define MGA_WR29 0x2d74
589#define MGA_WR30 0x2d78
590#define MGA_WR31 0x2d7c
591#define MGA_WR32 0x2d80
592#define MGA_WR33 0x2d84
593#define MGA_WR34 0x2d88
594#define MGA_WR35 0x2d8c
595#define MGA_WR36 0x2d90
596#define MGA_WR37 0x2d94
597#define MGA_WR38 0x2d98
598#define MGA_WR39 0x2d9c
599#define MGA_WR40 0x2da0
600#define MGA_WR41 0x2da4
601#define MGA_WR42 0x2da8
602#define MGA_WR43 0x2dac
603#define MGA_WR44 0x2db0
604#define MGA_WR45 0x2db4
605#define MGA_WR46 0x2db8
606#define MGA_WR47 0x2dbc
607#define MGA_WR48 0x2dc0
608#define MGA_WR49 0x2dc4
609#define MGA_WR50 0x2dc8
610#define MGA_WR51 0x2dcc
611#define MGA_WR52 0x2dd0
612#define MGA_WR53 0x2dd4
613#define MGA_WR54 0x2dd8
614#define MGA_WR55 0x2ddc
615#define MGA_WR56 0x2de0
616#define MGA_WR57 0x2de4
617#define MGA_WR58 0x2de8
618#define MGA_WR59 0x2dec
619#define MGA_WR60 0x2df0
620#define MGA_WR61 0x2df4
621#define MGA_WR62 0x2df8
622#define MGA_WR63 0x2dfc
623# define MGA_G400_WR_MAGIC (1 << 6)
624# define MGA_G400_WR56_MAGIC 0x46480000
625
626#define MGA_ILOAD_ALIGN 64
627#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
628
629#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
630 MGA_ATYPE_I | \
631 MGA_ZMODE_NOZCMP | \
632 MGA_ARZERO | \
633 MGA_SGNZERO | \
634 MGA_BOP_SRC | \
635 (15 << MGA_TRANS_SHIFT))
636
637#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
638 MGA_ZMODE_NOZCMP | \
639 MGA_SOLID | \
640 MGA_ARZERO | \
641 MGA_SGNZERO | \
642 MGA_SHIFTZERO | \
643 MGA_BOP_SRC | \
644 (0 << MGA_TRANS_SHIFT) | \
645 MGA_BLTMOD_BMONOLEF | \
646 MGA_TRANSC | \
647 MGA_CLIPDIS)
648
649#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
650 MGA_ATYPE_RPL | \
651 MGA_SGNZERO | \
652 MGA_SHIFTZERO | \
653 MGA_BOP_SRC | \
654 (0 << MGA_TRANS_SHIFT) | \
655 MGA_BLTMOD_BFCOL | \
656 MGA_CLIPDIS)
657
658
659
660static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
661{
662 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
663 return (status == MGA_ENDPRDMASTS);
664}
665
666#endif
667
