LXR linux/drivers/gpu/drm/nouveau/core/engine/xtensa.c

   1/*
   2 * Copyright 2013 Ilia Mirkin
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23#include <engine/xtensa.h>
  24
  25u32
  26_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr)
  27{
  28        struct nouveau_xtensa *xtensa = (void *)object;
  29        return nv_rd32(xtensa, xtensa->addr + addr);
  30}
  31
  32void
  33_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data)
  34{
  35        struct nouveau_xtensa *xtensa = (void *)object;
  36        nv_wr32(xtensa, xtensa->addr + addr, data);
  37}
  38
  39int
  40_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent,
  41                            struct nouveau_object *engine,
  42                            struct nouveau_oclass *oclass, void *data, u32 size,
  43                            struct nouveau_object **pobject)
  44{
  45        struct nouveau_engctx *engctx;
  46        int ret;
  47
  48        ret = nouveau_engctx_create(parent, engine, oclass, NULL,
  49                                    0x10000, 0x1000,
  50                                    NVOBJ_FLAG_ZERO_ALLOC, &engctx);
  51        *pobject = nv_object(engctx);
  52        return ret;
  53}
  54
  55void
  56_nouveau_xtensa_intr(struct nouveau_subdev *subdev)
  57{
  58        struct nouveau_xtensa *xtensa = (void *)subdev;
  59        u32 unk104 = nv_ro32(xtensa, 0xd04);
  60        u32 intr = nv_ro32(xtensa, 0xc20);
  61        u32 chan = nv_ro32(xtensa, 0xc28);
  62        u32 unk10c = nv_ro32(xtensa, 0xd0c);
  63
  64        if (intr & 0x10)
  65                nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");
  66        nv_wo32(xtensa, 0xc20, intr);
  67        intr = nv_ro32(xtensa, 0xc20);
  68        if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
  69                nv_debug(xtensa, "Enabling FIFO_CTRL\n");
  70                nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
  71        }
  72}
  73
  74int
  75nouveau_xtensa_create_(struct nouveau_object *parent,
  76                       struct nouveau_object *engine,
  77                       struct nouveau_oclass *oclass, u32 addr, bool enable,
  78                       const char *iname, const char *fname,
  79                       int length, void **pobject)
  80{
  81        struct nouveau_xtensa *xtensa;
  82        int ret;
  83
  84        ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
  85                                     fname, length, pobject);
  86        xtensa = *pobject;
  87        if (ret)
  88                return ret;
  89
  90        nv_subdev(xtensa)->intr = _nouveau_xtensa_intr;
  91
  92        xtensa->addr = addr;
  93
  94        return 0;
  95}
  96
  97int
  98_nouveau_xtensa_init(struct nouveau_object *object)
  99{
 100        struct nouveau_device *device = nv_device(object);
 101        struct nouveau_xtensa *xtensa = (void *)object;
 102        const struct firmware *fw;
 103        char name[32];
 104        int i, ret;
 105        u32 tmp;
 106
 107        ret = nouveau_engine_init(&xtensa->base);
 108        if (ret)
 109                return ret;
 110
 111        if (!xtensa->gpu_fw) {
 112                snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
 113                         xtensa->addr >> 12);
 114
 115                ret = request_firmware(&fw, name, &device->pdev->dev);
 116                if (ret) {
 117                        nv_warn(xtensa, "unable to load firmware %s\n", name);
 118                        return ret;
 119                }
 120
 121                if (fw->size > 0x40000) {
 122                        nv_warn(xtensa, "firmware %s too large\n", name);
 123                        release_firmware(fw);
 124                        return -EINVAL;
 125                }
 126
 127                ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
 128                                         &xtensa->gpu_fw);
 129                if (ret) {
 130                        release_firmware(fw);
 131                        return ret;
 132                }
 133
 134                nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",
 135                         xtensa->gpu_fw->addr);
 136
 137                for (i = 0; i < fw->size / 4; i++)
 138                        nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));
 139                release_firmware(fw);
 140        }
 141
 142        nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */
 143        nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */
 144
 145        nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
 146        nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
 147        nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
 148
 149        nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
 150        nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
 151        nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
 152
 153        tmp = nv_rd32(xtensa, 0x0);
 154        nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */
 155
 156        nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */
 157
 158        nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
 159        nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
 160
 161        return 0;
 162}
 163
 164int
 165_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend)
 166{
 167        struct nouveau_xtensa *xtensa = (void *)object;
 168
 169        nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
 170        nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
 171
 172        if (!suspend)
 173                nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw);
 174
 175        return nouveau_engine_fini(&xtensa->base, suspend);
 176}
 177