LXR linux/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <subdev/bios.h>
  26#include <subdev/bios/pll.h>
  27#include <subdev/clock.h>
  28#include <subdev/devinit/priv.h>
  29
  30#include "pll.h"
  31
  32struct nv04_clock_priv {
  33        struct nouveau_clock base;
  34};
  35
  36int
  37nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
  38                    int clk, struct nouveau_pll_vals *pv)
  39{
  40        int N1, M1, N2, M2, P;
  41        int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
  42        if (ret) {
  43                pv->refclk = info->refclk;
  44                pv->N1 = N1;
  45                pv->M1 = M1;
  46                pv->N2 = N2;
  47                pv->M2 = M2;
  48                pv->log2P = P;
  49        }
  50        return ret;
  51}
  52
  53int
  54nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
  55                    struct nouveau_pll_vals *pv)
  56{
  57        struct nouveau_devinit *devinit = nouveau_devinit(clk);
  58        int cv = nouveau_bios(clk)->version.chip;
  59
  60        if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
  61            cv >= 0x40) {
  62                if (reg1 > 0x405c)
  63                        setPLL_double_highregs(devinit, reg1, pv);
  64                else
  65                        setPLL_double_lowregs(devinit, reg1, pv);
  66        } else
  67                setPLL_single(devinit, reg1, pv);
  68
  69        return 0;
  70}
  71
  72static int
  73nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  74                struct nouveau_oclass *oclass, void *data, u32 size,
  75                struct nouveau_object **pobject)
  76{
  77        struct nv04_clock_priv *priv;
  78        int ret;
  79
  80        ret = nouveau_clock_create(parent, engine, oclass, &priv);
  81        *pobject = nv_object(priv);
  82        if (ret)
  83                return ret;
  84
  85        priv->base.pll_calc = nv04_clock_pll_calc;
  86        priv->base.pll_prog = nv04_clock_pll_prog;
  87        return 0;
  88}
  89
  90struct nouveau_oclass
  91nv04_clock_oclass = {
  92        .handle = NV_SUBDEV(CLOCK, 0x04),
  93        .ofuncs = &(struct nouveau_ofuncs) {
  94                .ctor = nv04_clock_ctor,
  95                .dtor = _nouveau_clock_dtor,
  96                .init = _nouveau_clock_init,
  97                .fini = _nouveau_clock_fini,
  98        },
  99};
 100