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25#include <core/gpuobj.h>
26#include <core/option.h>
27
28#include <subdev/timer.h>
29#include <subdev/vm.h>
30
31#include "nv04.h"
32
33#define NV44_GART_SIZE (512 * 1024 * 1024)
34#define NV44_GART_PAGE ( 4 * 1024)
35
36
37
38
39
40static void
41nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
42 dma_addr_t *list, u32 pte, u32 cnt)
43{
44 u32 base = (pte << 2) & ~0x0000000f;
45 u32 tmp[4];
46
47 tmp[0] = nv_ro32(pgt, base + 0x0);
48 tmp[1] = nv_ro32(pgt, base + 0x4);
49 tmp[2] = nv_ro32(pgt, base + 0x8);
50 tmp[3] = nv_ro32(pgt, base + 0xc);
51
52 while (cnt--) {
53 u32 addr = list ? (*list++ >> 12) : (null >> 12);
54 switch (pte++ & 0x3) {
55 case 0:
56 tmp[0] &= ~0x07ffffff;
57 tmp[0] |= addr;
58 break;
59 case 1:
60 tmp[0] &= ~0xf8000000;
61 tmp[0] |= addr << 27;
62 tmp[1] &= ~0x003fffff;
63 tmp[1] |= addr >> 5;
64 break;
65 case 2:
66 tmp[1] &= ~0xffc00000;
67 tmp[1] |= addr << 22;
68 tmp[2] &= ~0x0001ffff;
69 tmp[2] |= addr >> 10;
70 break;
71 case 3:
72 tmp[2] &= ~0xfffe0000;
73 tmp[2] |= addr << 17;
74 tmp[3] &= ~0x00000fff;
75 tmp[3] |= addr >> 15;
76 break;
77 }
78 }
79
80 nv_wo32(pgt, base + 0x0, tmp[0]);
81 nv_wo32(pgt, base + 0x4, tmp[1]);
82 nv_wo32(pgt, base + 0x8, tmp[2]);
83 nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
84}
85
86static void
87nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
88 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
89{
90 struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
91 u32 tmp[4];
92 int i;
93
94 if (pte & 3) {
95 u32 max = 4 - (pte & 3);
96 u32 part = (cnt > max) ? max : cnt;
97 nv44_vm_fill(pgt, priv->null, list, pte, part);
98 pte += part;
99 list += part;
100 cnt -= part;
101 }
102
103 while (cnt >= 4) {
104 for (i = 0; i < 4; i++)
105 tmp[i] = *list++ >> 12;
106 nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27);
107 nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22);
108 nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
109 nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
110 cnt -= 4;
111 }
112
113 if (cnt)
114 nv44_vm_fill(pgt, priv->null, list, pte, cnt);
115}
116
117static void
118nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
119{
120 struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
121
122 if (pte & 3) {
123 u32 max = 4 - (pte & 3);
124 u32 part = (cnt > max) ? max : cnt;
125 nv44_vm_fill(pgt, priv->null, NULL, pte, part);
126 pte += part;
127 cnt -= part;
128 }
129
130 while (cnt >= 4) {
131 nv_wo32(pgt, pte++ * 4, 0x00000000);
132 nv_wo32(pgt, pte++ * 4, 0x00000000);
133 nv_wo32(pgt, pte++ * 4, 0x00000000);
134 nv_wo32(pgt, pte++ * 4, 0x00000000);
135 cnt -= 4;
136 }
137
138 if (cnt)
139 nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);
140}
141
142static void
143nv44_vm_flush(struct nouveau_vm *vm)
144{
145 struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
146 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
147 nv_wr32(priv, 0x100808, 0x00000020);
148 if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
149 nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
150 nv_wr32(priv, 0x100808, 0x00000000);
151}
152
153
154
155
156
157static int
158nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
159 struct nouveau_oclass *oclass, void *data, u32 size,
160 struct nouveau_object **pobject)
161{
162 struct nouveau_device *device = nv_device(parent);
163 struct nv04_vmmgr_priv *priv;
164 int ret;
165
166 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
167 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
168 return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
169 data, size, pobject);
170 }
171
172 ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
173 "pciegart", &priv);
174 *pobject = nv_object(priv);
175 if (ret)
176 return ret;
177
178 priv->base.create = nv04_vm_create;
179 priv->base.limit = NV44_GART_SIZE;
180 priv->base.dma_bits = 39;
181 priv->base.pgt_bits = 32 - 12;
182 priv->base.spg_shift = 12;
183 priv->base.lpg_shift = 12;
184 priv->base.map_sg = nv44_vm_map_sg;
185 priv->base.unmap = nv44_vm_unmap;
186 priv->base.flush = nv44_vm_flush;
187
188 priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null);
189 if (!priv->nullp) {
190 nv_error(priv, "unable to allocate dummy pages\n");
191 return -ENOMEM;
192 }
193
194 ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
195 &priv->vm);
196 if (ret)
197 return ret;
198
199 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
200 (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
201 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
202 &priv->vm->pgt[0].obj[0]);
203 priv->vm->pgt[0].refcount[0] = 1;
204 if (ret)
205 return ret;
206
207 return 0;
208}
209
210static int
211nv44_vmmgr_init(struct nouveau_object *object)
212{
213 struct nv04_vmmgr_priv *priv = (void *)object;
214 struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
215 u32 addr;
216 int ret;
217
218 ret = nouveau_vmmgr_init(&priv->base);
219 if (ret)
220 return ret;
221
222
223
224
225
226 addr = nv_rd32(priv, 0x10020c);
227 addr -= ((gart->addr >> 19) + 1) << 19;
228
229 nv_wr32(priv, 0x100850, 0x80000000);
230 nv_wr32(priv, 0x100818, priv->null);
231 nv_wr32(priv, 0x100804, NV44_GART_SIZE);
232 nv_wr32(priv, 0x100850, 0x00008000);
233 nv_mask(priv, 0x10008c, 0x00000200, 0x00000200);
234 nv_wr32(priv, 0x100820, 0x00000000);
235 nv_wr32(priv, 0x10082c, 0x00000001);
236 nv_wr32(priv, 0x100800, addr | 0x00000010);
237 return 0;
238}
239
240struct nouveau_oclass
241nv44_vmmgr_oclass = {
242 .handle = NV_SUBDEV(VM, 0x44),
243 .ofuncs = &(struct nouveau_ofuncs) {
244 .ctor = nv44_vmmgr_ctor,
245 .dtor = nv04_vmmgr_dtor,
246 .init = nv44_vmmgr_init,
247 .fini = _nouveau_vmmgr_fini,
248 },
249};
250
