LXR linux/drivers/gpu/drm/radeon/atombios

   1/*
   2 * Copyright 2007-11 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26#include <drm/drmP.h>
  27#include <drm/drm_crtc_helper.h>
  28#include <drm/radeon_drm.h>
  29#include "radeon.h"
  30#include "atom.h"
  31#include <linux/backlight.h>
  32
  33extern int atom_debug;
  34
  35static u8
  36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37{
  38        u8 backlight_level;
  39        u32 bios_2_scratch;
  40
  41        if (rdev->family >= CHIP_R600)
  42                bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43        else
  44                bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46        backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                           ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49        return backlight_level;
  50}
  51
  52static void
  53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                       u8 backlight_level)
  55{
  56        u32 bios_2_scratch;
  57
  58        if (rdev->family >= CHIP_R600)
  59                bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60        else
  61                bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63        bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64        bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                           ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67        if (rdev->family >= CHIP_R600)
  68                WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69        else
  70                WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71}
  72
  73u8
  74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75{
  76        struct drm_device *dev = radeon_encoder->base.dev;
  77        struct radeon_device *rdev = dev->dev_private;
  78
  79        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                return 0;
  81
  82        return radeon_atom_get_backlight_level_from_reg(rdev);
  83}
  84
  85void
  86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87{
  88        struct drm_encoder *encoder = &radeon_encoder->base;
  89        struct drm_device *dev = radeon_encoder->base.dev;
  90        struct radeon_device *rdev = dev->dev_private;
  91        struct radeon_encoder_atom_dig *dig;
  92        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93        int index;
  94
  95        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                return;
  97
  98        if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99            radeon_encoder->enc_priv) {
 100                dig = radeon_encoder->enc_priv;
 101                dig->backlight_level = level;
 102                radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                switch (radeon_encoder->encoder_id) {
 105                case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                        index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                        if (dig->backlight_level == 0) {
 109                                args.ucAction = ATOM_LCD_BLOFF;
 110                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                        } else {
 112                                args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                args.ucAction = ATOM_LCD_BLON;
 115                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                        }
 117                        break;
 118                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                        if (dig->backlight_level == 0)
 123                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                        else {
 125                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                        }
 128                        break;
 129                default:
 130                        break;
 131                }
 132        }
 133}
 134
 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138{
 139        u8 level;
 140
 141        /* Convert brightness to hardware level */
 142        if (bd->props.brightness < 0)
 143                level = 0;
 144        else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                level = RADEON_MAX_BL_LEVEL;
 146        else
 147                level = bd->props.brightness;
 148
 149        return level;
 150}
 151
 152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153{
 154        struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155        struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157        atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159        return 0;
 160}
 161
 162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163{
 164        struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165        struct radeon_encoder *radeon_encoder = pdata->encoder;
 166        struct drm_device *dev = radeon_encoder->base.dev;
 167        struct radeon_device *rdev = dev->dev_private;
 168
 169        return radeon_atom_get_backlight_level_from_reg(rdev);
 170}
 171
 172static const struct backlight_ops radeon_atom_backlight_ops = {
 173        .get_brightness = radeon_atom_backlight_get_brightness,
 174        .update_status  = radeon_atom_backlight_update_status,
 175};
 176
 177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                struct drm_connector *drm_connector)
 179{
 180        struct drm_device *dev = radeon_encoder->base.dev;
 181        struct radeon_device *rdev = dev->dev_private;
 182        struct backlight_device *bd;
 183        struct backlight_properties props;
 184        struct radeon_backlight_privdata *pdata;
 185        struct radeon_encoder_atom_dig *dig;
 186        u8 backlight_level;
 187        char bl_name[16];
 188
 189        /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190         * so don't register a backlight device
 191         */
 192        if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193            (rdev->pdev->device == 0x6741))
 194                return;
 195
 196        if (!radeon_encoder->enc_priv)
 197                return;
 198
 199        if (!rdev->is_atom_bios)
 200                return;
 201
 202        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                return;
 204
 205        pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206        if (!pdata) {
 207                DRM_ERROR("Memory allocation failed\n");
 208                goto error;
 209        }
 210
 211        memset(&props, 0, sizeof(props));
 212        props.max_brightness = RADEON_MAX_BL_LEVEL;
 213        props.type = BACKLIGHT_RAW;
 214        snprintf(bl_name, sizeof(bl_name),
 215                 "radeon_bl%d", dev->primary->index);
 216        bd = backlight_device_register(bl_name, &drm_connector->kdev,
 217                                       pdata, &radeon_atom_backlight_ops, &props);
 218        if (IS_ERR(bd)) {
 219                DRM_ERROR("Backlight registration failed\n");
 220                goto error;
 221        }
 222
 223        pdata->encoder = radeon_encoder;
 224
 225        backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 226
 227        dig = radeon_encoder->enc_priv;
 228        dig->bl_dev = bd;
 229
 230        bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 231        bd->props.power = FB_BLANK_UNBLANK;
 232        backlight_update_status(bd);
 233
 234        DRM_INFO("radeon atom DIG backlight initialized\n");
 235
 236        return;
 237
 238error:
 239        kfree(pdata);
 240        return;
 241}
 242
 243static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 244{
 245        struct drm_device *dev = radeon_encoder->base.dev;
 246        struct radeon_device *rdev = dev->dev_private;
 247        struct backlight_device *bd = NULL;
 248        struct radeon_encoder_atom_dig *dig;
 249
 250        if (!radeon_encoder->enc_priv)
 251                return;
 252
 253        if (!rdev->is_atom_bios)
 254                return;
 255
 256        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 257                return;
 258
 259        dig = radeon_encoder->enc_priv;
 260        bd = dig->bl_dev;
 261        dig->bl_dev = NULL;
 262
 263        if (bd) {
 264                struct radeon_legacy_backlight_privdata *pdata;
 265
 266                pdata = bl_get_data(bd);
 267                backlight_device_unregister(bd);
 268                kfree(pdata);
 269
 270                DRM_INFO("radeon atom LVDS backlight unloaded\n");
 271        }
 272}
 273
 274#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 275
 276void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 277{
 278}
 279
 280static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 281{
 282}
 283
 284#endif
 285
 286/* evil but including atombios.h is much worse */
 287bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 288                                struct drm_display_mode *mode);
 289
 290
 291static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 292{
 293        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 294        switch (radeon_encoder->encoder_id) {
 295        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 296        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 297        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 298        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 299        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 300        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 301        case ENCODER_OBJECT_ID_INTERNAL_DDI:
 302        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 303        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 304        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 305        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 306        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 307                return true;
 308        default:
 309                return false;
 310        }
 311}
 312
 313static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 314                                   const struct drm_display_mode *mode,
 315                                   struct drm_display_mode *adjusted_mode)
 316{
 317        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 318        struct drm_device *dev = encoder->dev;
 319        struct radeon_device *rdev = dev->dev_private;
 320
 321        /* set the active encoder to connector routing */
 322        radeon_encoder_set_active_device(encoder);
 323        drm_mode_set_crtcinfo(adjusted_mode, 0);
 324
 325        /* hw bug */
 326        if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 327            && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 328                adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 329
 330        /* get the native mode for LVDS */
 331        if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 332                radeon_panel_mode_fixup(encoder, adjusted_mode);
 333
 334        /* get the native mode for TV */
 335        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 336                struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 337                if (tv_dac) {
 338                        if (tv_dac->tv_std == TV_STD_NTSC ||
 339                            tv_dac->tv_std == TV_STD_NTSC_J ||
 340                            tv_dac->tv_std == TV_STD_PAL_M)
 341                                radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 342                        else
 343                                radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 344                }
 345        }
 346
 347        if (ASIC_IS_DCE3(rdev) &&
 348            ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 349             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 350                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 351                radeon_dp_set_link_config(connector, adjusted_mode);
 352        }
 353
 354        return true;
 355}
 356
 357static void
 358atombios_dac_setup(struct drm_encoder *encoder, int action)
 359{
 360        struct drm_device *dev = encoder->dev;
 361        struct radeon_device *rdev = dev->dev_private;
 362        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 363        DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 364        int index = 0;
 365        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 366
 367        memset(&args, 0, sizeof(args));
 368
 369        switch (radeon_encoder->encoder_id) {
 370        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 371        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 372                index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 373                break;
 374        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 375        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 376                index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 377                break;
 378        }
 379
 380        args.ucAction = action;
 381
 382        if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 383                args.ucDacStandard = ATOM_DAC1_PS2;
 384        else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 385                args.ucDacStandard = ATOM_DAC1_CV;
 386        else {
 387                switch (dac_info->tv_std) {
 388                case TV_STD_PAL:
 389                case TV_STD_PAL_M:
 390                case TV_STD_SCART_PAL:
 391                case TV_STD_SECAM:
 392                case TV_STD_PAL_CN:
 393                        args.ucDacStandard = ATOM_DAC1_PAL;
 394                        break;
 395                case TV_STD_NTSC:
 396                case TV_STD_NTSC_J:
 397                case TV_STD_PAL_60:
 398                default:
 399                        args.ucDacStandard = ATOM_DAC1_NTSC;
 400                        break;
 401                }
 402        }
 403        args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 404
 405        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 406
 407}
 408
 409static void
 410atombios_tv_setup(struct drm_encoder *encoder, int action)
 411{
 412        struct drm_device *dev = encoder->dev;
 413        struct radeon_device *rdev = dev->dev_private;
 414        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 415        TV_ENCODER_CONTROL_PS_ALLOCATION args;
 416        int index = 0;
 417        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 418
 419        memset(&args, 0, sizeof(args));
 420
 421        index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 422
 423        args.sTVEncoder.ucAction = action;
 424
 425        if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 426                args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 427        else {
 428                switch (dac_info->tv_std) {
 429                case TV_STD_NTSC:
 430                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 431                        break;
 432                case TV_STD_PAL:
 433                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 434                        break;
 435                case TV_STD_PAL_M:
 436                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 437                        break;
 438                case TV_STD_PAL_60:
 439                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 440                        break;
 441                case TV_STD_NTSC_J:
 442                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 443                        break;
 444                case TV_STD_SCART_PAL:
 445                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 446                        break;
 447                case TV_STD_SECAM:
 448                        args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 449                        break;
 450                case TV_STD_PAL_CN:
 451                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 452                        break;
 453                default:
 454                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 455                        break;
 456                }
 457        }
 458
 459        args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 460
 461        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 462
 463}
 464
 465static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 466{
 467        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 468        int bpc = 8;
 469
 470        if (connector)
 471                bpc = radeon_get_monitor_bpc(connector);
 472
 473        switch (bpc) {
 474        case 0:
 475                return PANEL_BPC_UNDEFINE;
 476        case 6:
 477                return PANEL_6BIT_PER_COLOR;
 478        case 8:
 479        default:
 480                return PANEL_8BIT_PER_COLOR;
 481        case 10:
 482                return PANEL_10BIT_PER_COLOR;
 483        case 12:
 484                return PANEL_12BIT_PER_COLOR;
 485        case 16:
 486                return PANEL_16BIT_PER_COLOR;
 487        }
 488}
 489
 490union dvo_encoder_control {
 491        ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 492        DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 493        DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 494        DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 495};
 496
 497void
 498atombios_dvo_setup(struct drm_encoder *encoder, int action)
 499{
 500        struct drm_device *dev = encoder->dev;
 501        struct radeon_device *rdev = dev->dev_private;
 502        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 503        union dvo_encoder_control args;
 504        int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 505        uint8_t frev, crev;
 506
 507        memset(&args, 0, sizeof(args));
 508
 509        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 510                return;
 511
 512        /* some R4xx chips have the wrong frev */
 513        if (rdev->family <= CHIP_RV410)
 514                frev = 1;
 515
 516        switch (frev) {
 517        case 1:
 518                switch (crev) {
 519                case 1:
 520                        /* R4xx, R5xx */
 521                        args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 522
 523                        if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 524                                args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 525
 526                        args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 527                        break;
 528                case 2:
 529                        /* RS600/690/740 */
 530                        args.dvo.sDVOEncoder.ucAction = action;
 531                        args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 532                        /* DFP1, CRT1, TV1 depending on the type of port */
 533                        args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 534
 535                        if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 536                                args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 537                        break;
 538                case 3:
 539                        /* R6xx */
 540                        args.dvo_v3.ucAction = action;
 541                        args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 542                        args.dvo_v3.ucDVOConfig = 0; /* XXX */
 543                        break;
 544                case 4:
 545                        /* DCE8 */
 546                        args.dvo_v4.ucAction = action;
 547                        args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 548                        args.dvo_v4.ucDVOConfig = 0; /* XXX */
 549                        args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 550                        break;
 551                default:
 552                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 553                        break;
 554                }
 555                break;
 556        default:
 557                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 558                break;
 559        }
 560
 561        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 562}
 563
 564union lvds_encoder_control {
 565        LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 566        LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 567};
 568
 569void
 570atombios_digital_setup(struct drm_encoder *encoder, int action)
 571{
 572        struct drm_device *dev = encoder->dev;
 573        struct radeon_device *rdev = dev->dev_private;
 574        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 575        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 576        union lvds_encoder_control args;
 577        int index = 0;
 578        int hdmi_detected = 0;
 579        uint8_t frev, crev;
 580
 581        if (!dig)
 582                return;
 583
 584        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 585                hdmi_detected = 1;
 586
 587        memset(&args, 0, sizeof(args));
 588
 589        switch (radeon_encoder->encoder_id) {
 590        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 591                index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 592                break;
 593        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 594        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 595                index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 596                break;
 597        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 598                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 599                        index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 600                else
 601                        index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 602                break;
 603        }
 604
 605        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 606                return;
 607
 608        switch (frev) {
 609        case 1:
 610        case 2:
 611                switch (crev) {
 612                case 1:
 613                        args.v1.ucMisc = 0;
 614                        args.v1.ucAction = action;
 615                        if (hdmi_detected)
 616                                args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 617                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 618                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 619                                if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 620                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 621                                if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 622                                        args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 623                        } else {
 624                                if (dig->linkb)
 625                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 626                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 627                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 628                                /*if (pScrn->rgbBits == 8) */
 629                                args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 630                        }
 631                        break;
 632                case 2:
 633                case 3:
 634                        args.v2.ucMisc = 0;
 635                        args.v2.ucAction = action;
 636                        if (crev == 3) {
 637                                if (dig->coherent_mode)
 638                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 639                        }
 640                        if (hdmi_detected)
 641                                args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 642                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 643                        args.v2.ucTruncate = 0;
 644                        args.v2.ucSpatial = 0;
 645                        args.v2.ucTemporal = 0;
 646                        args.v2.ucFRC = 0;
 647                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 648                                if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 649                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 650                                if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 651                                        args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 652                                        if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 653                                                args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 654                                }
 655                                if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 656                                        args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 657                                        if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 658                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 659                                        if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 660                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 661                                }
 662                        } else {
 663                                if (dig->linkb)
 664                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 665                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 666                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 667                        }
 668                        break;
 669                default:
 670                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 671                        break;
 672                }
 673                break;
 674        default:
 675                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 676                break;
 677        }
 678
 679        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 680}
 681
 682int
 683atombios_get_encoder_mode(struct drm_encoder *encoder)
 684{
 685        struct drm_device *dev = encoder->dev;
 686        struct radeon_device *rdev = dev->dev_private;
 687        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 688        struct drm_connector *connector;
 689        struct radeon_connector *radeon_connector;
 690        struct radeon_connector_atom_dig *dig_connector;
 691
 692        /* dp bridges are always DP */
 693        if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 694                return ATOM_ENCODER_MODE_DP;
 695
 696        /* DVO is always DVO */
 697        if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 698            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 699                return ATOM_ENCODER_MODE_DVO;
 700
 701        connector = radeon_get_connector_for_encoder(encoder);
 702        /* if we don't have an active device yet, just use one of
 703         * the connectors tied to the encoder.
 704         */
 705        if (!connector)
 706                connector = radeon_get_connector_for_encoder_init(encoder);
 707        radeon_connector = to_radeon_connector(connector);
 708
 709        switch (connector->connector_type) {
 710        case DRM_MODE_CONNECTOR_DVII:
 711        case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 712                if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 713                    radeon_audio &&
 714                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 715                        return ATOM_ENCODER_MODE_HDMI;
 716                else if (radeon_connector->use_digital)
 717                        return ATOM_ENCODER_MODE_DVI;
 718                else
 719                        return ATOM_ENCODER_MODE_CRT;
 720                break;
 721        case DRM_MODE_CONNECTOR_DVID:
 722        case DRM_MODE_CONNECTOR_HDMIA:
 723        default:
 724                if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 725                    radeon_audio &&
 726                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 727                        return ATOM_ENCODER_MODE_HDMI;
 728                else
 729                        return ATOM_ENCODER_MODE_DVI;
 730                break;
 731        case DRM_MODE_CONNECTOR_LVDS:
 732                return ATOM_ENCODER_MODE_LVDS;
 733                break;
 734        case DRM_MODE_CONNECTOR_DisplayPort:
 735                dig_connector = radeon_connector->con_priv;
 736                if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 737                    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 738                        return ATOM_ENCODER_MODE_DP;
 739                else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 740                         radeon_audio &&
 741                         !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 742                        return ATOM_ENCODER_MODE_HDMI;
 743                else
 744                        return ATOM_ENCODER_MODE_DVI;
 745                break;
 746        case DRM_MODE_CONNECTOR_eDP:
 747                return ATOM_ENCODER_MODE_DP;
 748        case DRM_MODE_CONNECTOR_DVIA:
 749        case DRM_MODE_CONNECTOR_VGA:
 750                return ATOM_ENCODER_MODE_CRT;
 751                break;
 752        case DRM_MODE_CONNECTOR_Composite:
 753        case DRM_MODE_CONNECTOR_SVIDEO:
 754        case DRM_MODE_CONNECTOR_9PinDIN:
 755                /* fix me */
 756                return ATOM_ENCODER_MODE_TV;
 757                /*return ATOM_ENCODER_MODE_CV;*/
 758                break;
 759        }
 760}
 761
 762/*
 763 * DIG Encoder/Transmitter Setup
 764 *
 765 * DCE 3.0/3.1
 766 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 767 * Supports up to 3 digital outputs
 768 * - 2 DIG encoder blocks.
 769 * DIG1 can drive UNIPHY link A or link B
 770 * DIG2 can drive UNIPHY link B or LVTMA
 771 *
 772 * DCE 3.2
 773 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 774 * Supports up to 5 digital outputs
 775 * - 2 DIG encoder blocks.
 776 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 777 *
 778 * DCE 4.0/5.0/6.0
 779 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 780 * Supports up to 6 digital outputs
 781 * - 6 DIG encoder blocks.
 782 * - DIG to PHY mapping is hardcoded
 783 * DIG1 drives UNIPHY0 link A, A+B
 784 * DIG2 drives UNIPHY0 link B
 785 * DIG3 drives UNIPHY1 link A, A+B
 786 * DIG4 drives UNIPHY1 link B
 787 * DIG5 drives UNIPHY2 link A, A+B
 788 * DIG6 drives UNIPHY2 link B
 789 *
 790 * DCE 4.1
 791 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 792 * Supports up to 6 digital outputs
 793 * - 2 DIG encoder blocks.
 794 * llano
 795 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 796 * ontario
 797 * DIG1 drives UNIPHY0/1/2 link A
 798 * DIG2 drives UNIPHY0/1/2 link B
 799 *
 800 * Routing
 801 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 802 * Examples:
 803 * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 804 * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 805 * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 806 * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 807 */
 808
 809union dig_encoder_control {
 810        DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 811        DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 812        DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 813        DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 814};
 815
 816void
 817atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 818{
 819        struct drm_device *dev = encoder->dev;
 820        struct radeon_device *rdev = dev->dev_private;
 821        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 822        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 823        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 824        union dig_encoder_control args;
 825        int index = 0;
 826        uint8_t frev, crev;
 827        int dp_clock = 0;
 828        int dp_lane_count = 0;
 829        int hpd_id = RADEON_HPD_NONE;
 830
 831        if (connector) {
 832                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 833                struct radeon_connector_atom_dig *dig_connector =
 834                        radeon_connector->con_priv;
 835
 836                dp_clock = dig_connector->dp_clock;
 837                dp_lane_count = dig_connector->dp_lane_count;
 838                hpd_id = radeon_connector->hpd.hpd;
 839        }
 840
 841        /* no dig encoder assigned */
 842        if (dig->dig_encoder == -1)
 843                return;
 844
 845        memset(&args, 0, sizeof(args));
 846
 847        if (ASIC_IS_DCE4(rdev))
 848                index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 849        else {
 850                if (dig->dig_encoder)
 851                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 852                else
 853                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 854        }
 855
 856        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 857                return;
 858
 859        switch (frev) {
 860        case 1:
 861                switch (crev) {
 862                case 1:
 863                        args.v1.ucAction = action;
 864                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 865                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 866                                args.v3.ucPanelMode = panel_mode;
 867                        else
 868                                args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 869
 870                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 871                                args.v1.ucLaneNum = dp_lane_count;
 872                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 873                                args.v1.ucLaneNum = 8;
 874                        else
 875                                args.v1.ucLaneNum = 4;
 876
 877                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 878                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 879                        switch (radeon_encoder->encoder_id) {
 880                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 881                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 882                                break;
 883                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 884                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 885                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 886                                break;
 887                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 888                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 889                                break;
 890                        }
 891                        if (dig->linkb)
 892                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 893                        else
 894                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 895                        break;
 896                case 2:
 897                case 3:
 898                        args.v3.ucAction = action;
 899                        args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 900                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 901                                args.v3.ucPanelMode = panel_mode;
 902                        else
 903                                args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 904
 905                        if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 906                                args.v3.ucLaneNum = dp_lane_count;
 907                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 908                                args.v3.ucLaneNum = 8;
 909                        else
 910                                args.v3.ucLaneNum = 4;
 911
 912                        if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 913                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 914                        args.v3.acConfig.ucDigSel = dig->dig_encoder;
 915                        args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 916                        break;
 917                case 4:
 918                        args.v4.ucAction = action;
 919                        args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 920                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 921                                args.v4.ucPanelMode = panel_mode;
 922                        else
 923                                args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 924
 925                        if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 926                                args.v4.ucLaneNum = dp_lane_count;
 927                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 928                                args.v4.ucLaneNum = 8;
 929                        else
 930                                args.v4.ucLaneNum = 4;
 931
 932                        if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 933                                if (dp_clock == 540000)
 934                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 935                                else if (dp_clock == 324000)
 936                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 937                                else if (dp_clock == 270000)
 938                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 939                                else
 940                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 941                        }
 942                        args.v4.acConfig.ucDigSel = dig->dig_encoder;
 943                        args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 944                        if (hpd_id == RADEON_HPD_NONE)
 945                                args.v4.ucHPD_ID = 0;
 946                        else
 947                                args.v4.ucHPD_ID = hpd_id + 1;
 948                        break;
 949                default:
 950                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 951                        break;
 952                }
 953                break;
 954        default:
 955                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 956                break;
 957        }
 958
 959        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 960
 961}
 962
 963union dig_transmitter_control {
 964        DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 965        DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 966        DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 967        DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 968        DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 969};
 970
 971void
 972atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 973{
 974        struct drm_device *dev = encoder->dev;
 975        struct radeon_device *rdev = dev->dev_private;
 976        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 977        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 978        struct drm_connector *connector;
 979        union dig_transmitter_control args;
 980        int index = 0;
 981        uint8_t frev, crev;
 982        bool is_dp = false;
 983        int pll_id = 0;
 984        int dp_clock = 0;
 985        int dp_lane_count = 0;
 986        int connector_object_id = 0;
 987        int igp_lane_info = 0;
 988        int dig_encoder = dig->dig_encoder;
 989        int hpd_id = RADEON_HPD_NONE;
 990
 991        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 992                connector = radeon_get_connector_for_encoder_init(encoder);
 993                /* just needed to avoid bailing in the encoder check.  the encoder
 994                 * isn't used for init
 995                 */
 996                dig_encoder = 0;
 997        } else
 998                connector = radeon_get_connector_for_encoder(encoder);
 999
1000        if (connector) {

1001                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1002                struct radeon_connector_atom_dig *dig_connector =
1003                        radeon_connector->con_priv;
1004
1005                hpd_id = radeon_connector->hpd.hpd;
1006                dp_clock = dig_connector->dp_clock;
1007                dp_lane_count = dig_connector->dp_lane_count;
1008                connector_object_id =
1009                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1010                igp_lane_info = dig_connector->igp_lane_info;
1011        }
1012
1013        if (encoder->crtc) {
1014                struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1015                pll_id = radeon_crtc->pll_id;
1016        }
1017
1018        /* no dig encoder assigned */
1019        if (dig_encoder == -1)
1020                return;
1021
1022        if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1023                is_dp = true;
1024
1025        memset(&args, 0, sizeof(args));
1026
1027        switch (radeon_encoder->encoder_id) {
1028        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1029                index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1030                break;
1031        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1032        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1033        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1034        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1035                index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1036                break;
1037        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1038                index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1039                break;
1040        }
1041
1042        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1043                return;
1044
1045        switch (frev) {
1046        case 1:
1047                switch (crev) {
1048                case 1:
1049                        args.v1.ucAction = action;
1050                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1051                                args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1052                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1053                                args.v1.asMode.ucLaneSel = lane_num;
1054                                args.v1.asMode.ucLaneSet = lane_set;
1055                        } else {
1056                                if (is_dp)
1057                                        args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1058                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1059                                        args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1060                                else
1061                                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1062                        }
1063
1064                        args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1065
1066                        if (dig_encoder)
1067                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1068                        else
1069                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1070
1071                        if ((rdev->flags & RADEON_IS_IGP) &&
1072                            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1073                                if (is_dp ||
1074                                    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1075                                        if (igp_lane_info & 0x1)
1076                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1077                                        else if (igp_lane_info & 0x2)
1078                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1079                                        else if (igp_lane_info & 0x4)
1080                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1081                                        else if (igp_lane_info & 0x8)
1082                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1083                                } else {
1084                                        if (igp_lane_info & 0x3)
1085                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1086                                        else if (igp_lane_info & 0xc)
1087                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1088                                }
1089                        }
1090
1091                        if (dig->linkb)
1092                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1093                        else
1094                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1095
1096                        if (is_dp)
1097                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1098                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1099                                if (dig->coherent_mode)
1100                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1101                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1102                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1103                        }
1104                        break;
1105                case 2:
1106                        args.v2.ucAction = action;
1107                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1108                                args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1109                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1110                                args.v2.asMode.ucLaneSel = lane_num;
1111                                args.v2.asMode.ucLaneSet = lane_set;
1112                        } else {
1113                                if (is_dp)
1114                                        args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1115                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1116                                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1117                                else
1118                                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1119                        }
1120
1121                        args.v2.acConfig.ucEncoderSel = dig_encoder;
1122                        if (dig->linkb)
1123                                args.v2.acConfig.ucLinkSel = 1;
1124
1125                        switch (radeon_encoder->encoder_id) {
1126                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1127                                args.v2.acConfig.ucTransmitterSel = 0;
1128                                break;
1129                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1130                                args.v2.acConfig.ucTransmitterSel = 1;
1131                                break;
1132                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1133                                args.v2.acConfig.ucTransmitterSel = 2;
1134                                break;
1135                        }
1136
1137                        if (is_dp) {
1138                                args.v2.acConfig.fCoherentMode = 1;
1139                                args.v2.acConfig.fDPConnector = 1;
1140                        } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1141                                if (dig->coherent_mode)
1142                                        args.v2.acConfig.fCoherentMode = 1;
1143                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1144                                        args.v2.acConfig.fDualLinkConnector = 1;
1145                        }
1146                        break;
1147                case 3:
1148                        args.v3.ucAction = action;
1149                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1150                                args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1151                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1152                                args.v3.asMode.ucLaneSel = lane_num;
1153                                args.v3.asMode.ucLaneSet = lane_set;
1154                        } else {
1155                                if (is_dp)
1156                                        args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1157                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1158                                        args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1159                                else
1160                                        args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1161                        }
1162
1163                        if (is_dp)
1164                                args.v3.ucLaneNum = dp_lane_count;
1165                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1166                                args.v3.ucLaneNum = 8;
1167                        else
1168                                args.v3.ucLaneNum = 4;
1169
1170                        if (dig->linkb)
1171                                args.v3.acConfig.ucLinkSel = 1;
1172                        if (dig_encoder & 1)
1173                                args.v3.acConfig.ucEncoderSel = 1;
1174
1175                        /* Select the PLL for the PHY
1176                         * DP PHY should be clocked from external src if there is
1177                         * one.
1178                         */
1179                        /* On DCE4, if there is an external clock, it generates the DP ref clock */
1180                        if (is_dp && rdev->clock.dp_extclk)
1181                                args.v3.acConfig.ucRefClkSource = 2; /* external src */
1182                        else
1183                                args.v3.acConfig.ucRefClkSource = pll_id;
1184
1185                        switch (radeon_encoder->encoder_id) {
1186                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1187                                args.v3.acConfig.ucTransmitterSel = 0;
1188                                break;
1189                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1190                                args.v3.acConfig.ucTransmitterSel = 1;
1191                                break;
1192                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1193                                args.v3.acConfig.ucTransmitterSel = 2;
1194                                break;
1195                        }
1196
1197                        if (is_dp)
1198                                args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1199                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1200                                if (dig->coherent_mode)
1201                                        args.v3.acConfig.fCoherentMode = 1;
1202                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1203                                        args.v3.acConfig.fDualLinkConnector = 1;
1204                        }
1205                        break;
1206                case 4:
1207                        args.v4.ucAction = action;
1208                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1209                                args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1210                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1211                                args.v4.asMode.ucLaneSel = lane_num;
1212                                args.v4.asMode.ucLaneSet = lane_set;
1213                        } else {
1214                                if (is_dp)
1215                                        args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1216                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1217                                        args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1218                                else
1219                                        args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1220                        }
1221
1222                        if (is_dp)
1223                                args.v4.ucLaneNum = dp_lane_count;
1224                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1225                                args.v4.ucLaneNum = 8;
1226                        else
1227                                args.v4.ucLaneNum = 4;
1228
1229                        if (dig->linkb)
1230                                args.v4.acConfig.ucLinkSel = 1;
1231                        if (dig_encoder & 1)
1232                                args.v4.acConfig.ucEncoderSel = 1;
1233
1234                        /* Select the PLL for the PHY
1235                         * DP PHY should be clocked from external src if there is
1236                         * one.
1237                         */
1238                        /* On DCE5 DCPLL usually generates the DP ref clock */
1239                        if (is_dp) {
1240                                if (rdev->clock.dp_extclk)
1241                                        args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1242                                else
1243                                        args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1244                        } else
1245                                args.v4.acConfig.ucRefClkSource = pll_id;
1246
1247                        switch (radeon_encoder->encoder_id) {
1248                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1249                                args.v4.acConfig.ucTransmitterSel = 0;
1250                                break;
1251                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1252                                args.v4.acConfig.ucTransmitterSel = 1;
1253                                break;
1254                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1255                                args.v4.acConfig.ucTransmitterSel = 2;
1256                                break;
1257                        }
1258
1259                        if (is_dp)
1260                                args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1261                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1262                                if (dig->coherent_mode)
1263                                        args.v4.acConfig.fCoherentMode = 1;
1264                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1265                                        args.v4.acConfig.fDualLinkConnector = 1;
1266                        }
1267                        break;
1268                case 5:
1269                        args.v5.ucAction = action;
1270                        if (is_dp)
1271                                args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1272                        else
1273                                args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1274
1275                        switch (radeon_encoder->encoder_id) {
1276                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1277                                if (dig->linkb)
1278                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1279                                else
1280                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1281                                break;
1282                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1283                                if (dig->linkb)
1284                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1285                                else
1286                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1287                                break;
1288                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1289                                if (dig->linkb)
1290                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1291                                else
1292                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1293                                break;
1294                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1295                                args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1296                                break;
1297                        }
1298                        if (is_dp)
1299                                args.v5.ucLaneNum = dp_lane_count;
1300                        else if (radeon_encoder->pixel_clock > 165000)
1301                                args.v5.ucLaneNum = 8;
1302                        else
1303                                args.v5.ucLaneNum = 4;
1304                        args.v5.ucConnObjId = connector_object_id;
1305                        args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1306
1307                        if (is_dp && rdev->clock.dp_extclk)
1308                                args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1309                        else
1310                                args.v5.asConfig.ucPhyClkSrcId = pll_id;
1311
1312                        if (is_dp)
1313                                args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1314                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1315                                if (dig->coherent_mode)
1316                                        args.v5.asConfig.ucCoherentMode = 1;
1317                        }
1318                        if (hpd_id == RADEON_HPD_NONE)
1319                                args.v5.asConfig.ucHPDSel = 0;
1320                        else
1321                                args.v5.asConfig.ucHPDSel = hpd_id + 1;
1322                        args.v5.ucDigEncoderSel = 1 << dig_encoder;
1323                        args.v5.ucDPLaneSet = lane_set;
1324                        break;
1325                default:
1326                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1327                        break;
1328                }
1329                break;
1330        default:
1331                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1332                break;
1333        }
1334
1335        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1336}
1337
1338bool
1339atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1340{
1341        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1342        struct drm_device *dev = radeon_connector->base.dev;
1343        struct radeon_device *rdev = dev->dev_private;
1344        union dig_transmitter_control args;
1345        int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1346        uint8_t frev, crev;
1347
1348        if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1349                goto done;
1350
1351        if (!ASIC_IS_DCE4(rdev))
1352                goto done;
1353
1354        if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1355            (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1356                goto done;
1357
1358        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1359                goto done;
1360
1361        memset(&args, 0, sizeof(args));
1362
1363        args.v1.ucAction = action;
1364
1365        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1366
1367        /* wait for the panel to power up */
1368        if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1369                int i;
1370
1371                for (i = 0; i < 300; i++) {
1372                        if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1373                                return true;
1374                        mdelay(1);
1375                }
1376                return false;
1377        }
1378done:
1379        return true;
1380}
1381
1382union external_encoder_control {
1383        EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1384        EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1385};
1386
1387static void
1388atombios_external_encoder_setup(struct drm_encoder *encoder,
1389                                struct drm_encoder *ext_encoder,
1390                                int action)
1391{
1392        struct drm_device *dev = encoder->dev;
1393        struct radeon_device *rdev = dev->dev_private;
1394        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1395        struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1396        union external_encoder_control args;
1397        struct drm_connector *connector;
1398        int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1399        u8 frev, crev;
1400        int dp_clock = 0;
1401        int dp_lane_count = 0;
1402        int connector_object_id = 0;
1403        u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1404
1405        if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1406                connector = radeon_get_connector_for_encoder_init(encoder);
1407        else
1408                connector = radeon_get_connector_for_encoder(encoder);
1409
1410        if (connector) {
1411                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1412                struct radeon_connector_atom_dig *dig_connector =
1413                        radeon_connector->con_priv;
1414
1415                dp_clock = dig_connector->dp_clock;
1416                dp_lane_count = dig_connector->dp_lane_count;
1417                connector_object_id =
1418                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1419        }
1420
1421        memset(&args, 0, sizeof(args));
1422
1423        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1424                return;
1425
1426        switch (frev) {
1427        case 1:
1428                /* no params on frev 1 */
1429                break;
1430        case 2:
1431                switch (crev) {
1432                case 1:
1433                case 2:
1434                        args.v1.sDigEncoder.ucAction = action;
1435                        args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1436                        args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1437
1438                        if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1439                                if (dp_clock == 270000)
1440                                        args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1441                                args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1442                        } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1443                                args.v1.sDigEncoder.ucLaneNum = 8;
1444                        else
1445                                args.v1.sDigEncoder.ucLaneNum = 4;
1446                        break;
1447                case 3:
1448                        args.v3.sExtEncoder.ucAction = action;
1449                        if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1450                                args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1451                        else
1452                                args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1453                        args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1454
1455                        if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1456                                if (dp_clock == 270000)
1457                                        args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1458                                else if (dp_clock == 540000)
1459                                        args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1460                                args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1461                        } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1462                                args.v3.sExtEncoder.ucLaneNum = 8;
1463                        else
1464                                args.v3.sExtEncoder.ucLaneNum = 4;
1465                        switch (ext_enum) {
1466                        case GRAPH_OBJECT_ENUM_ID1:
1467                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1468                                break;
1469                        case GRAPH_OBJECT_ENUM_ID2:
1470                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1471                                break;
1472                        case GRAPH_OBJECT_ENUM_ID3:
1473                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1474                                break;
1475                        }
1476                        args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1477                        break;
1478                default:
1479                        DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1480                        return;
1481                }
1482                break;
1483        default:
1484                DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1485                return;
1486        }
1487        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1488}
1489
1490static void
1491atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1492{
1493        struct drm_device *dev = encoder->dev;
1494        struct radeon_device *rdev = dev->dev_private;
1495        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1496        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1497        ENABLE_YUV_PS_ALLOCATION args;
1498        int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1499        uint32_t temp, reg;
1500
1501        memset(&args, 0, sizeof(args));
1502
1503        if (rdev->family >= CHIP_R600)
1504                reg = R600_BIOS_3_SCRATCH;
1505        else
1506                reg = RADEON_BIOS_3_SCRATCH;
1507
1508        /* XXX: fix up scratch reg handling */
1509        temp = RREG32(reg);
1510        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1511                WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1512                             (radeon_crtc->crtc_id << 18)));
1513        else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1514                WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1515        else
1516                WREG32(reg, 0);
1517
1518        if (enable)
1519                args.ucEnable = ATOM_ENABLE;
1520        args.ucCRTC = radeon_crtc->crtc_id;
1521
1522        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1523
1524        WREG32(reg, temp);
1525}
1526
1527static void
1528radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1529{
1530        struct drm_device *dev = encoder->dev;
1531        struct radeon_device *rdev = dev->dev_private;
1532        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1533        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1534        int index = 0;
1535
1536        memset(&args, 0, sizeof(args));
1537
1538        switch (radeon_encoder->encoder_id) {
1539        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1540        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1541                index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1542                break;
1543        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1544        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1545        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1546                index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1547                break;
1548        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1549                index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1550                break;
1551        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1552                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1553                        index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1554                else
1555                        index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1556                break;
1557        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1558        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1559                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1560                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1561                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1562                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1563                else
1564                        index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1565                break;
1566        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1567        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1568                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1569                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1570                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1571                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1572                else
1573                        index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1574                break;
1575        default:
1576                return;
1577        }
1578
1579        switch (mode) {
1580        case DRM_MODE_DPMS_ON:
1581                args.ucAction = ATOM_ENABLE;
1582                /* workaround for DVOOutputControl on some RS690 systems */
1583                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1584                        u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1585                        WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1586                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1587                        WREG32(RADEON_BIOS_3_SCRATCH, reg);
1588                } else
1589                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1590                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1591                        args.ucAction = ATOM_LCD_BLON;
1592                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1593                }
1594                break;
1595        case DRM_MODE_DPMS_STANDBY:
1596        case DRM_MODE_DPMS_SUSPEND:
1597        case DRM_MODE_DPMS_OFF:
1598                args.ucAction = ATOM_DISABLE;
1599                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1600                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1601                        args.ucAction = ATOM_LCD_BLOFF;
1602                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1603                }
1604                break;
1605        }
1606}
1607
1608static void
1609radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1610{
1611        struct drm_device *dev = encoder->dev;
1612        struct radeon_device *rdev = dev->dev_private;
1613        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1614        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1615        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1616        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1617        struct radeon_connector *radeon_connector = NULL;
1618        struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1619
1620        if (connector) {
1621                radeon_connector = to_radeon_connector(connector);
1622                radeon_dig_connector = radeon_connector->con_priv;
1623        }
1624
1625        switch (mode) {
1626        case DRM_MODE_DPMS_ON:
1627                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1628                        if (!connector)
1629                                dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1630                        else
1631                                dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1632
1633                        /* setup and enable the encoder */
1634                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1635                        atombios_dig_encoder_setup(encoder,
1636                                                   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1637                                                   dig->panel_mode);
1638                        if (ext_encoder) {
1639                                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1640                                        atombios_external_encoder_setup(encoder, ext_encoder,
1641                                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1642                        }
1643                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1644                } else if (ASIC_IS_DCE4(rdev)) {
1645                        /* setup and enable the encoder */
1646                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1647                        /* enable the transmitter */
1648                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1649                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1650                } else {
1651                        /* setup and enable the encoder and transmitter */
1652                        atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1653                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1654                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1655                        /* some early dce3.2 boards have a bug in their transmitter control table */
1656                        if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1657                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1658                }
1659                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1660                        if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1661                                atombios_set_edp_panel_power(connector,
1662                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
1663                                radeon_dig_connector->edp_on = true;
1664                        }
1665                        radeon_dp_link_train(encoder, connector);
1666                        if (ASIC_IS_DCE4(rdev))
1667                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1668                }
1669                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1670                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1671                break;
1672        case DRM_MODE_DPMS_STANDBY:
1673        case DRM_MODE_DPMS_SUSPEND:
1674        case DRM_MODE_DPMS_OFF:
1675                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1676                        /* disable the transmitter */
1677                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1678                } else if (ASIC_IS_DCE4(rdev)) {
1679                        /* disable the transmitter */
1680                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1681                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1682                } else {
1683                        /* disable the encoder and transmitter */
1684                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1685                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1686                        atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1687                }
1688                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1689                        if (ASIC_IS_DCE4(rdev))
1690                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1691                        if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1692                                atombios_set_edp_panel_power(connector,
1693                                                             ATOM_TRANSMITTER_ACTION_POWER_OFF);
1694                                radeon_dig_connector->edp_on = false;
1695                        }
1696                }
1697                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1698                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1699                break;
1700        }
1701}
1702
1703static void
1704radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1705                             struct drm_encoder *ext_encoder,
1706                             int mode)
1707{
1708        struct drm_device *dev = encoder->dev;
1709        struct radeon_device *rdev = dev->dev_private;
1710
1711        switch (mode) {
1712        case DRM_MODE_DPMS_ON:
1713        default:
1714                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1715                        atombios_external_encoder_setup(encoder, ext_encoder,
1716                                                        EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1717                        atombios_external_encoder_setup(encoder, ext_encoder,
1718                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1719                } else
1720                        atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1721                break;
1722        case DRM_MODE_DPMS_STANDBY:
1723        case DRM_MODE_DPMS_SUSPEND:
1724        case DRM_MODE_DPMS_OFF:
1725                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1726                        atombios_external_encoder_setup(encoder, ext_encoder,
1727                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1728                        atombios_external_encoder_setup(encoder, ext_encoder,
1729                                                        EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1730                } else
1731                        atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1732                break;
1733        }
1734}
1735
1736static void
1737radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1738{
1739        struct drm_device *dev = encoder->dev;
1740        struct radeon_device *rdev = dev->dev_private;
1741        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1742        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1743
1744        DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1745                  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1746                  radeon_encoder->active_device);
1747        switch (radeon_encoder->encoder_id) {
1748        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1749        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1750        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1751        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1752        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1753        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1754        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1755        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1756                radeon_atom_encoder_dpms_avivo(encoder, mode);
1757                break;
1758        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1759        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1760        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1761        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1762        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1763                radeon_atom_encoder_dpms_dig(encoder, mode);
1764                break;
1765        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1766                if (ASIC_IS_DCE5(rdev)) {
1767                        switch (mode) {
1768                        case DRM_MODE_DPMS_ON:
1769                                atombios_dvo_setup(encoder, ATOM_ENABLE);
1770                                break;
1771                        case DRM_MODE_DPMS_STANDBY:
1772                        case DRM_MODE_DPMS_SUSPEND:
1773                        case DRM_MODE_DPMS_OFF:
1774                                atombios_dvo_setup(encoder, ATOM_DISABLE);
1775                                break;
1776                        }
1777                } else if (ASIC_IS_DCE3(rdev))
1778                        radeon_atom_encoder_dpms_dig(encoder, mode);
1779                else
1780                        radeon_atom_encoder_dpms_avivo(encoder, mode);
1781                break;
1782        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1783        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1784                if (ASIC_IS_DCE5(rdev)) {
1785                        switch (mode) {
1786                        case DRM_MODE_DPMS_ON:
1787                                atombios_dac_setup(encoder, ATOM_ENABLE);
1788                                break;
1789                        case DRM_MODE_DPMS_STANDBY:
1790                        case DRM_MODE_DPMS_SUSPEND:
1791                        case DRM_MODE_DPMS_OFF:
1792                                atombios_dac_setup(encoder, ATOM_DISABLE);
1793                                break;
1794                        }
1795                } else
1796                        radeon_atom_encoder_dpms_avivo(encoder, mode);
1797                break;
1798        default:
1799                return;
1800        }
1801
1802        if (ext_encoder)
1803                radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1804
1805        radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1806
1807}
1808
1809union crtc_source_param {
1810        SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1811        SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1812};
1813
1814static void
1815atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1816{
1817        struct drm_device *dev = encoder->dev;
1818        struct radeon_device *rdev = dev->dev_private;
1819        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1820        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1821        union crtc_source_param args;
1822        int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1823        uint8_t frev, crev;
1824        struct radeon_encoder_atom_dig *dig;
1825
1826        memset(&args, 0, sizeof(args));
1827
1828        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1829                return;
1830
1831        switch (frev) {
1832        case 1:
1833                switch (crev) {
1834                case 1:
1835                default:
1836                        if (ASIC_IS_AVIVO(rdev))
1837                                args.v1.ucCRTC = radeon_crtc->crtc_id;
1838                        else {
1839                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1840                                        args.v1.ucCRTC = radeon_crtc->crtc_id;
1841                                } else {
1842                                        args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1843                                }
1844                        }
1845                        switch (radeon_encoder->encoder_id) {
1846                        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1847                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1848                                args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1849                                break;
1850                        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1851                        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1852                                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1853                                        args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1854                                else
1855                                        args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1856                                break;
1857                        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1858                        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1859                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1860                                args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1861                                break;
1862                        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1863                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1864                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1865                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1866                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1867                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1868                                else
1869                                        args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1870                                break;
1871                        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1872                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1873                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1874                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1875                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1876                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1877                                else
1878                                        args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1879                                break;
1880                        }
1881                        break;
1882                case 2:
1883                        args.v2.ucCRTC = radeon_crtc->crtc_id;
1884                        if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1885                                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1886
1887                                if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1888                                        args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1889                                else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1890                                        args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1891                                else
1892                                        args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1893                        } else
1894                                args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1895                        switch (radeon_encoder->encoder_id) {
1896                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1897                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1898                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1899                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1900                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1901                                dig = radeon_encoder->enc_priv;
1902                                switch (dig->dig_encoder) {
1903                                case 0:
1904                                        args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1905                                        break;
1906                                case 1:
1907                                        args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1908                                        break;
1909                                case 2:
1910                                        args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1911                                        break;
1912                                case 3:
1913                                        args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1914                                        break;
1915                                case 4:
1916                                        args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1917                                        break;
1918                                case 5:
1919                                        args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1920                                        break;
1921                                case 6:
1922                                        args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1923                                        break;
1924                                }
1925                                break;
1926                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1927                                args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1928                                break;
1929                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1930                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1931                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1932                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1933                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1934                                else
1935                                        args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1936                                break;
1937                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1938                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1939                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1940                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1941                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1942                                else
1943                                        args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1944                                break;
1945                        }
1946                        break;
1947                }
1948                break;
1949        default:
1950                DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1951                return;
1952        }
1953
1954        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1955
1956        /* update scratch regs with new routing */
1957        radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1958}
1959
1960static void
1961atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1962                              struct drm_display_mode *mode)
1963{
1964        struct drm_device *dev = encoder->dev;
1965        struct radeon_device *rdev = dev->dev_private;
1966        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1967        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1968
1969        /* Funky macbooks */
1970        if ((dev->pdev->device == 0x71C5) &&
1971            (dev->pdev->subsystem_vendor == 0x106b) &&
1972            (dev->pdev->subsystem_device == 0x0080)) {
1973                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1974                        uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1975
1976                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1977                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1978
1979                        WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1980                }
1981        }
1982
1983        /* set scaler clears this on some chips */
1984        if (ASIC_IS_AVIVO(rdev) &&
1985            (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1986                if (ASIC_IS_DCE8(rdev)) {
1987                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1988                                WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1989                                       CIK_INTERLEAVE_EN);
1990                        else
1991                                WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1992                } else if (ASIC_IS_DCE4(rdev)) {
1993                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1994                                WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1995                                       EVERGREEN_INTERLEAVE_EN);
1996                        else
1997                                WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1998                } else {
1999                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2000                                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,

2001                                       AVIVO_D1MODE_INTERLEAVE_EN);
2002                        else
2003                                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2004                }
2005        }
2006}
2007
2008static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2009{
2010        struct drm_device *dev = encoder->dev;
2011        struct radeon_device *rdev = dev->dev_private;
2012        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2013        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2014        struct drm_encoder *test_encoder;
2015        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2016        uint32_t dig_enc_in_use = 0;
2017
2018        if (ASIC_IS_DCE6(rdev)) {
2019                /* DCE6 */
2020                switch (radeon_encoder->encoder_id) {
2021                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2022                        if (dig->linkb)
2023                                return 1;
2024                        else
2025                                return 0;
2026                        break;
2027                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2028                        if (dig->linkb)
2029                                return 3;
2030                        else
2031                                return 2;
2032                        break;
2033                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2034                        if (dig->linkb)
2035                                return 5;
2036                        else
2037                                return 4;
2038                        break;
2039                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2040                        return 6;
2041                        break;
2042                }
2043        } else if (ASIC_IS_DCE4(rdev)) {
2044                /* DCE4/5 */
2045                if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2046                        /* ontario follows DCE4 */
2047                        if (rdev->family == CHIP_PALM) {
2048                                if (dig->linkb)
2049                                        return 1;
2050                                else
2051                                        return 0;
2052                        } else
2053                                /* llano follows DCE3.2 */
2054                                return radeon_crtc->crtc_id;
2055                } else {
2056                        switch (radeon_encoder->encoder_id) {
2057                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2058                                if (dig->linkb)
2059                                        return 1;
2060                                else
2061                                        return 0;
2062                                break;
2063                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2064                                if (dig->linkb)
2065                                        return 3;
2066                                else
2067                                        return 2;
2068                                break;
2069                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2070                                if (dig->linkb)
2071                                        return 5;
2072                                else
2073                                        return 4;
2074                                break;
2075                        }
2076                }
2077        }
2078
2079        /* on DCE32 and encoder can driver any block so just crtc id */
2080        if (ASIC_IS_DCE32(rdev)) {
2081                return radeon_crtc->crtc_id;
2082        }
2083
2084        /* on DCE3 - LVTMA can only be driven by DIGB */
2085        list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2086                struct radeon_encoder *radeon_test_encoder;
2087
2088                if (encoder == test_encoder)
2089                        continue;
2090
2091                if (!radeon_encoder_is_digital(test_encoder))
2092                        continue;
2093
2094                radeon_test_encoder = to_radeon_encoder(test_encoder);
2095                dig = radeon_test_encoder->enc_priv;
2096
2097                if (dig->dig_encoder >= 0)
2098                        dig_enc_in_use |= (1 << dig->dig_encoder);
2099        }
2100
2101        if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2102                if (dig_enc_in_use & 0x2)
2103                        DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2104                return 1;
2105        }
2106        if (!(dig_enc_in_use & 1))
2107                return 0;
2108        return 1;
2109}
2110
2111/* This only needs to be called once at startup */
2112void
2113radeon_atom_encoder_init(struct radeon_device *rdev)
2114{
2115        struct drm_device *dev = rdev->ddev;
2116        struct drm_encoder *encoder;
2117
2118        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2119                struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2120                struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2121
2122                switch (radeon_encoder->encoder_id) {
2123                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2124                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2125                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2126                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2127                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2128                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2129                        break;
2130                default:
2131                        break;
2132                }
2133
2134                if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2135                        atombios_external_encoder_setup(encoder, ext_encoder,
2136                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2137        }
2138}
2139
2140static void
2141radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2142                             struct drm_display_mode *mode,
2143                             struct drm_display_mode *adjusted_mode)
2144{
2145        struct drm_device *dev = encoder->dev;
2146        struct radeon_device *rdev = dev->dev_private;
2147        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2148
2149        radeon_encoder->pixel_clock = adjusted_mode->clock;
2150
2151        /* need to call this here rather than in prepare() since we need some crtc info */
2152        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2153
2154        if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2155                if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2156                        atombios_yuv_setup(encoder, true);
2157                else
2158                        atombios_yuv_setup(encoder, false);
2159        }
2160
2161        switch (radeon_encoder->encoder_id) {
2162        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2163        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2164        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2165        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2166                atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2167                break;
2168        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2169        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2170        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2171        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2172        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2173                /* handled in dpms */
2174                break;
2175        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2176        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2177        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2178                atombios_dvo_setup(encoder, ATOM_ENABLE);
2179                break;
2180        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2181        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2182        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2183        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2184                atombios_dac_setup(encoder, ATOM_ENABLE);
2185                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2186                        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2187                                atombios_tv_setup(encoder, ATOM_ENABLE);
2188                        else
2189                                atombios_tv_setup(encoder, ATOM_DISABLE);
2190                }
2191                break;
2192        }
2193
2194        atombios_apply_encoder_quirks(encoder, adjusted_mode);
2195
2196        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2197                if (rdev->asic->display.hdmi_enable)
2198                        radeon_hdmi_enable(rdev, encoder, true);
2199                if (rdev->asic->display.hdmi_setmode)
2200                        radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2201        }
2202}
2203
2204static bool
2205atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2206{
2207        struct drm_device *dev = encoder->dev;
2208        struct radeon_device *rdev = dev->dev_private;
2209        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2210        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2211
2212        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2213                                       ATOM_DEVICE_CV_SUPPORT |
2214                                       ATOM_DEVICE_CRT_SUPPORT)) {
2215                DAC_LOAD_DETECTION_PS_ALLOCATION args;
2216                int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2217                uint8_t frev, crev;
2218
2219                memset(&args, 0, sizeof(args));
2220
2221                if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2222                        return false;
2223
2224                args.sDacload.ucMisc = 0;
2225
2226                if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2227                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2228                        args.sDacload.ucDacType = ATOM_DAC_A;
2229                else
2230                        args.sDacload.ucDacType = ATOM_DAC_B;
2231
2232                if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2233                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2234                else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2235                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2236                else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2237                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2238                        if (crev >= 3)
2239                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2240                } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2241                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2242                        if (crev >= 3)
2243                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2244                }
2245
2246                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2247
2248                return true;
2249        } else
2250                return false;
2251}
2252
2253static enum drm_connector_status
2254radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2255{
2256        struct drm_device *dev = encoder->dev;
2257        struct radeon_device *rdev = dev->dev_private;
2258        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2259        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2260        uint32_t bios_0_scratch;
2261
2262        if (!atombios_dac_load_detect(encoder, connector)) {
2263                DRM_DEBUG_KMS("detect returned false \n");
2264                return connector_status_unknown;
2265        }
2266
2267        if (rdev->family >= CHIP_R600)
2268                bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2269        else
2270                bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2271
2272        DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2273        if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2274                if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2275                        return connector_status_connected;
2276        }
2277        if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2278                if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2279                        return connector_status_connected;
2280        }
2281        if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2282                if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2283                        return connector_status_connected;
2284        }
2285        if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2286                if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2287                        return connector_status_connected; /* CTV */
2288                else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2289                        return connector_status_connected; /* STV */
2290        }
2291        return connector_status_disconnected;
2292}
2293
2294static enum drm_connector_status
2295radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2296{
2297        struct drm_device *dev = encoder->dev;
2298        struct radeon_device *rdev = dev->dev_private;
2299        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2300        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2301        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2302        u32 bios_0_scratch;
2303
2304        if (!ASIC_IS_DCE4(rdev))
2305                return connector_status_unknown;
2306
2307        if (!ext_encoder)
2308                return connector_status_unknown;
2309
2310        if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2311                return connector_status_unknown;
2312
2313        /* load detect on the dp bridge */
2314        atombios_external_encoder_setup(encoder, ext_encoder,
2315                                        EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2316
2317        bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2318
2319        DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2320        if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2321                if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2322                        return connector_status_connected;
2323        }
2324        if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2325                if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2326                        return connector_status_connected;
2327        }
2328        if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2329                if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2330                        return connector_status_connected;
2331        }
2332        if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2333                if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2334                        return connector_status_connected; /* CTV */
2335                else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2336                        return connector_status_connected; /* STV */
2337        }
2338        return connector_status_disconnected;
2339}
2340
2341void
2342radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2343{
2344        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2345
2346        if (ext_encoder)
2347                /* ddc_setup on the dp bridge */
2348                atombios_external_encoder_setup(encoder, ext_encoder,
2349                                                EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2350
2351}
2352
2353static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2354{
2355        struct radeon_device *rdev = encoder->dev->dev_private;
2356        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2357        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2358
2359        if ((radeon_encoder->active_device &
2360             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2361            (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2362             ENCODER_OBJECT_ID_NONE)) {
2363                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2364                if (dig) {
2365                        dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2366                        if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2367                                if (rdev->family >= CHIP_R600)
2368                                        dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2369                                else
2370                                        /* RS600/690/740 have only 1 afmt block */
2371                                        dig->afmt = rdev->mode_info.afmt[0];
2372                        }
2373                }
2374        }
2375
2376        radeon_atom_output_lock(encoder, true);
2377
2378        if (connector) {
2379                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2380
2381                /* select the clock/data port if it uses a router */
2382                if (radeon_connector->router.cd_valid)
2383                        radeon_router_select_cd_port(radeon_connector);
2384
2385                /* turn eDP panel on for mode set */
2386                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2387                        atombios_set_edp_panel_power(connector,
2388                                                     ATOM_TRANSMITTER_ACTION_POWER_ON);
2389        }
2390
2391        /* this is needed for the pll/ss setup to work correctly in some cases */
2392        atombios_set_encoder_crtc_source(encoder);
2393}
2394
2395static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2396{
2397        /* need to call this here as we need the crtc set up */
2398        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2399        radeon_atom_output_lock(encoder, false);
2400}
2401
2402static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2403{
2404        struct drm_device *dev = encoder->dev;
2405        struct radeon_device *rdev = dev->dev_private;
2406        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2407        struct radeon_encoder_atom_dig *dig;
2408
2409        /* check for pre-DCE3 cards with shared encoders;
2410         * can't really use the links individually, so don't disable
2411         * the encoder if it's in use by another connector
2412         */
2413        if (!ASIC_IS_DCE3(rdev)) {
2414                struct drm_encoder *other_encoder;
2415                struct radeon_encoder *other_radeon_encoder;
2416
2417                list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2418                        other_radeon_encoder = to_radeon_encoder(other_encoder);
2419                        if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2420                            drm_helper_encoder_in_use(other_encoder))
2421                                goto disable_done;
2422                }
2423        }
2424
2425        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2426
2427        switch (radeon_encoder->encoder_id) {
2428        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2429        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2430        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2431        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2432                atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2433                break;
2434        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2435        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2436        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2437        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2438        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2439                /* handled in dpms */
2440                break;
2441        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2442        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2443        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2444                atombios_dvo_setup(encoder, ATOM_DISABLE);
2445                break;
2446        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2447        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2448        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2449        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2450                atombios_dac_setup(encoder, ATOM_DISABLE);
2451                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2452                        atombios_tv_setup(encoder, ATOM_DISABLE);
2453                break;
2454        }
2455
2456disable_done:
2457        if (radeon_encoder_is_digital(encoder)) {
2458                if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2459                        if (rdev->asic->display.hdmi_enable)
2460                                radeon_hdmi_enable(rdev, encoder, false);
2461                }
2462                dig = radeon_encoder->enc_priv;
2463                dig->dig_encoder = -1;
2464        }
2465        radeon_encoder->active_device = 0;
2466}
2467
2468/* these are handled by the primary encoders */
2469static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2470{
2471
2472}
2473
2474static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2475{
2476
2477}
2478
2479static void
2480radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2481                         struct drm_display_mode *mode,
2482                         struct drm_display_mode *adjusted_mode)
2483{
2484
2485}
2486
2487static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2488{
2489
2490}
2491
2492static void
2493radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2494{
2495
2496}
2497
2498static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2499                                       const struct drm_display_mode *mode,
2500                                       struct drm_display_mode *adjusted_mode)
2501{
2502        return true;
2503}
2504
2505static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2506        .dpms = radeon_atom_ext_dpms,
2507        .mode_fixup = radeon_atom_ext_mode_fixup,
2508        .prepare = radeon_atom_ext_prepare,
2509        .mode_set = radeon_atom_ext_mode_set,
2510        .commit = radeon_atom_ext_commit,
2511        .disable = radeon_atom_ext_disable,
2512        /* no detect for TMDS/LVDS yet */
2513};
2514
2515static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2516        .dpms = radeon_atom_encoder_dpms,
2517        .mode_fixup = radeon_atom_mode_fixup,
2518        .prepare = radeon_atom_encoder_prepare,
2519        .mode_set = radeon_atom_encoder_mode_set,
2520        .commit = radeon_atom_encoder_commit,
2521        .disable = radeon_atom_encoder_disable,
2522        .detect = radeon_atom_dig_detect,
2523};
2524
2525static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2526        .dpms = radeon_atom_encoder_dpms,
2527        .mode_fixup = radeon_atom_mode_fixup,
2528        .prepare = radeon_atom_encoder_prepare,
2529        .mode_set = radeon_atom_encoder_mode_set,
2530        .commit = radeon_atom_encoder_commit,
2531        .detect = radeon_atom_dac_detect,
2532};
2533
2534void radeon_enc_destroy(struct drm_encoder *encoder)
2535{
2536        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2537        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2538                radeon_atom_backlight_exit(radeon_encoder);
2539        kfree(radeon_encoder->enc_priv);
2540        drm_encoder_cleanup(encoder);
2541        kfree(radeon_encoder);
2542}
2543
2544static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2545        .destroy = radeon_enc_destroy,
2546};
2547
2548static struct radeon_encoder_atom_dac *
2549radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2550{
2551        struct drm_device *dev = radeon_encoder->base.dev;
2552        struct radeon_device *rdev = dev->dev_private;
2553        struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2554
2555        if (!dac)
2556                return NULL;
2557
2558        dac->tv_std = radeon_atombios_get_tv_info(rdev);
2559        return dac;
2560}
2561
2562static struct radeon_encoder_atom_dig *
2563radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2564{
2565        int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2566        struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2567
2568        if (!dig)
2569                return NULL;
2570
2571        /* coherent mode by default */
2572        dig->coherent_mode = true;
2573        dig->dig_encoder = -1;
2574
2575        if (encoder_enum == 2)
2576                dig->linkb = true;
2577        else
2578                dig->linkb = false;
2579
2580        return dig;
2581}
2582
2583void
2584radeon_add_atom_encoder(struct drm_device *dev,
2585                        uint32_t encoder_enum,
2586                        uint32_t supported_device,
2587                        u16 caps)
2588{
2589        struct radeon_device *rdev = dev->dev_private;
2590        struct drm_encoder *encoder;
2591        struct radeon_encoder *radeon_encoder;
2592
2593        /* see if we already added it */
2594        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2595                radeon_encoder = to_radeon_encoder(encoder);
2596                if (radeon_encoder->encoder_enum == encoder_enum) {
2597                        radeon_encoder->devices |= supported_device;
2598                        return;
2599                }
2600
2601        }
2602
2603        /* add a new one */
2604        radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2605        if (!radeon_encoder)
2606                return;
2607
2608        encoder = &radeon_encoder->base;
2609        switch (rdev->num_crtc) {
2610        case 1:
2611                encoder->possible_crtcs = 0x1;
2612                break;
2613        case 2:
2614        default:
2615                encoder->possible_crtcs = 0x3;
2616                break;
2617        case 4:
2618                encoder->possible_crtcs = 0xf;
2619                break;
2620        case 6:
2621                encoder->possible_crtcs = 0x3f;
2622                break;
2623        }
2624
2625        radeon_encoder->enc_priv = NULL;
2626
2627        radeon_encoder->encoder_enum = encoder_enum;
2628        radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2629        radeon_encoder->devices = supported_device;
2630        radeon_encoder->rmx_type = RMX_OFF;
2631        radeon_encoder->underscan_type = UNDERSCAN_OFF;
2632        radeon_encoder->is_ext_encoder = false;
2633        radeon_encoder->caps = caps;
2634
2635        switch (radeon_encoder->encoder_id) {
2636        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2637        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2638        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2639        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2640                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2641                        radeon_encoder->rmx_type = RMX_FULL;
2642                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2643                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2644                } else {
2645                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2646                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2647                }
2648                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2649                break;
2650        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2651                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2652                radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2653                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2654                break;
2655        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2656        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2657        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2658                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2659                radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2660                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2661                break;
2662        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2663        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2664        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2665        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2666        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2667        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2668        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2669        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2670                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2671                        radeon_encoder->rmx_type = RMX_FULL;
2672                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2673                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2674                } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2675                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2676                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2677                } else {
2678                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2679                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2680                }
2681                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2682                break;
2683        case ENCODER_OBJECT_ID_SI170B:
2684        case ENCODER_OBJECT_ID_CH7303:
2685        case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2686        case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2687        case ENCODER_OBJECT_ID_TITFP513:
2688        case ENCODER_OBJECT_ID_VT1623:
2689        case ENCODER_OBJECT_ID_HDMI_SI1930:
2690        case ENCODER_OBJECT_ID_TRAVIS:
2691        case ENCODER_OBJECT_ID_NUTMEG:
2692                /* these are handled by the primary encoders */
2693                radeon_encoder->is_ext_encoder = true;
2694                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2695                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2696                else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2697                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2698                else
2699                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2700                drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2701                break;
2702        }
2703}
2704