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30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40
41struct radeon_bo;
42struct radeon_device;
43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
65 TV_STD_PAL_N,
66};
67
68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
84#define RADEON_MAX_I2C_BUS 16
85
86
87
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89
90
91
92
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94
95
96
97
98
99
100struct radeon_i2c_bus_rec {
101 bool valid;
102
103 uint8_t i2c_id;
104
105 enum radeon_hpd_id hpd;
106
107 bool hw_capable;
108
109 bool mm_i2c;
110
111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
136
137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
149#define RADEON_PLL_USE_POST_DIV (1 << 12)
150#define RADEON_PLL_IS_LCD (1 << 13)
151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152
153struct radeon_pll {
154
155 uint32_t reference_freq;
156
157
158 uint32_t reference_div;
159 uint32_t post_div;
160
161
162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
168 uint32_t best_vco;
169
170
171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
179
180
181 uint32_t flags;
182
183
184 uint32_t id;
185};
186
187struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
190 union {
191 struct i2c_algo_bit_data bit;
192 struct i2c_algo_dp_aux_data dp;
193 } algo;
194 struct radeon_i2c_bus_rec rec;
195};
196
197
198enum radeon_connector_table {
199 CT_NONE = 0,
200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
209 CT_RN50_POWER,
210 CT_MAC_X800,
211 CT_MAC_G5_9600,
212 CT_SAM440EP,
213 CT_MAC_G4_SILVER
214};
215
216enum radeon_dvo_chip {
217 DVO_SIL164,
218 DVO_SIL1178,
219};
220
221struct radeon_fbdev;
222
223struct radeon_afmt {
224 bool enabled;
225 int offset;
226 bool last_buffer_filled_status;
227 int id;
228};
229
230struct radeon_mode_info {
231 struct atom_context *atom_context;
232 struct card_info *atom_card_info;
233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
235 struct radeon_crtc *crtcs[6];
236 struct radeon_afmt *afmt[6];
237
238 struct drm_property *coherent_mode_property;
239
240 struct drm_property *load_detect_property;
241
242 struct drm_property *tv_std_property;
243
244 struct drm_property *tmds_pll_property;
245
246 struct drm_property *underscan_property;
247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
249
250 struct edid *bios_hardcoded_edid;
251 int bios_hardcoded_edid_size;
252
253
254 struct radeon_fbdev *rfbdev;
255
256 u16 firmware_flags;
257
258 struct radeon_encoder *bl_encoder;
259};
260
261#define RADEON_MAX_BL_LEVEL 0xFF
262
263#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
264
265struct radeon_backlight_privdata {
266 struct radeon_encoder *encoder;
267 uint8_t negative;
268};
269
270#endif
271
272#define MAX_H_CODE_TIMING_LEN 32
273#define MAX_V_CODE_TIMING_LEN 32
274
275
276
277struct radeon_tv_regs {
278 uint32_t tv_uv_adr;
279 uint32_t timing_cntl;
280 uint32_t hrestart;
281 uint32_t vrestart;
282 uint32_t frestart;
283 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
284 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
285};
286
287struct radeon_atom_ss {
288 uint16_t percentage;
289 uint8_t type;
290 uint16_t step;
291 uint8_t delay;
292 uint8_t range;
293 uint8_t refdiv;
294
295 uint16_t rate;
296 uint16_t amount;
297};
298
299struct radeon_crtc {
300 struct drm_crtc base;
301 int crtc_id;
302 u16 lut_r[256], lut_g[256], lut_b[256];
303 bool enabled;
304 bool can_tile;
305 uint32_t crtc_offset;
306 struct drm_gem_object *cursor_bo;
307 uint64_t cursor_addr;
308 int cursor_width;
309 int cursor_height;
310 int max_cursor_width;
311 int max_cursor_height;
312 uint32_t legacy_display_base_addr;
313 uint32_t legacy_cursor_offset;
314 enum radeon_rmx_type rmx_type;
315 u8 h_border;
316 u8 v_border;
317 fixed20_12 vsc;
318 fixed20_12 hsc;
319 struct drm_display_mode native_mode;
320 int pll_id;
321
322 struct radeon_unpin_work *unpin_work;
323 int deferred_flip_completion;
324
325 struct radeon_atom_ss ss;
326 bool ss_enabled;
327 u32 adjusted_clock;
328 int bpc;
329 u32 pll_reference_div;
330 u32 pll_post_div;
331 u32 pll_flags;
332 struct drm_encoder *encoder;
333 struct drm_connector *connector;
334
335 u32 line_time;
336 u32 wm_low;
337 u32 wm_high;
338 struct drm_display_mode hw_mode;
339};
340
341struct radeon_encoder_primary_dac {
342
343 uint32_t ps2_pdac_adj;
344};
345
346struct radeon_encoder_lvds {
347
348 uint16_t panel_vcc_delay;
349 uint8_t panel_pwr_delay;
350 uint8_t panel_digon_delay;
351 uint8_t panel_blon_delay;
352 uint16_t panel_ref_divider;
353 uint8_t panel_post_divider;
354 uint16_t panel_fb_divider;
355 bool use_bios_dividers;
356 uint32_t lvds_gen_cntl;
357
358 struct drm_display_mode native_mode;
359 struct backlight_device *bl_dev;
360 int dpms_mode;
361 uint8_t backlight_level;
362};
363
364struct radeon_encoder_tv_dac {
365
366 uint32_t ps2_tvdac_adj;
367 uint32_t ntsc_tvdac_adj;
368 uint32_t pal_tvdac_adj;
369
370 int h_pos;
371 int v_pos;
372 int h_size;
373 int supported_tv_stds;
374 bool tv_on;
375 enum radeon_tv_std tv_std;
376 struct radeon_tv_regs tv;
377};
378
379struct radeon_encoder_int_tmds {
380
381 struct radeon_tmds_pll tmds_pll[4];
382};
383
384struct radeon_encoder_ext_tmds {
385
386 struct radeon_i2c_chan *i2c_bus;
387 uint8_t slave_addr;
388 enum radeon_dvo_chip dvo_chip;
389};
390
391
392struct radeon_encoder_atom_dig {
393 bool linkb;
394
395 bool coherent_mode;
396 int dig_encoder;
397
398 uint32_t lcd_misc;
399 uint16_t panel_pwr_delay;
400 uint32_t lcd_ss_id;
401
402 struct drm_display_mode native_mode;
403 struct backlight_device *bl_dev;
404 int dpms_mode;
405 uint8_t backlight_level;
406 int panel_mode;
407 struct radeon_afmt *afmt;
408};
409
410struct radeon_encoder_atom_dac {
411 enum radeon_tv_std tv_std;
412};
413
414struct radeon_encoder {
415 struct drm_encoder base;
416 uint32_t encoder_enum;
417 uint32_t encoder_id;
418 uint32_t devices;
419 uint32_t active_device;
420 uint32_t flags;
421 uint32_t pixel_clock;
422 enum radeon_rmx_type rmx_type;
423 enum radeon_underscan_type underscan_type;
424 uint32_t underscan_hborder;
425 uint32_t underscan_vborder;
426 struct drm_display_mode native_mode;
427 void *enc_priv;
428 int audio_polling_active;
429 bool is_ext_encoder;
430 u16 caps;
431};
432
433struct radeon_connector_atom_dig {
434 uint32_t igp_lane_info;
435
436 struct radeon_i2c_chan *dp_i2c_bus;
437 u8 dpcd[DP_RECEIVER_CAP_SIZE];
438 u8 dp_sink_type;
439 int dp_clock;
440 int dp_lane_count;
441 bool edp_on;
442};
443
444struct radeon_gpio_rec {
445 bool valid;
446 u8 id;
447 u32 reg;
448 u32 mask;
449};
450
451struct radeon_hpd {
452 enum radeon_hpd_id hpd;
453 u8 plugged_state;
454 struct radeon_gpio_rec gpio;
455};
456
457struct radeon_router {
458 u32 router_id;
459 struct radeon_i2c_bus_rec i2c_info;
460 u8 i2c_addr;
461
462 bool ddc_valid;
463 u8 ddc_mux_type;
464 u8 ddc_mux_control_pin;
465 u8 ddc_mux_state;
466
467 bool cd_valid;
468 u8 cd_mux_type;
469 u8 cd_mux_control_pin;
470 u8 cd_mux_state;
471};
472
473struct radeon_connector {
474 struct drm_connector base;
475 uint32_t connector_id;
476 uint32_t devices;
477 struct radeon_i2c_chan *ddc_bus;
478
479 bool shared_ddc;
480 bool use_digital;
481
482
483 struct edid *edid;
484 void *con_priv;
485 bool dac_load_detect;
486 bool detected_by_load;
487 uint16_t connector_object_id;
488 struct radeon_hpd hpd;
489 struct radeon_router router;
490 struct radeon_i2c_chan *router_bus;
491};
492
493struct radeon_framebuffer {
494 struct drm_framebuffer base;
495 struct drm_gem_object *obj;
496};
497
498#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
499 ((em) == ATOM_ENCODER_MODE_DP_MST))
500
501struct atom_clock_dividers {
502 u32 post_div;
503 union {
504 struct {
505#ifdef __BIG_ENDIAN
506 u32 reserved : 6;
507 u32 whole_fb_div : 12;
508 u32 frac_fb_div : 14;
509#else
510 u32 frac_fb_div : 14;
511 u32 whole_fb_div : 12;
512 u32 reserved : 6;
513#endif
514 };
515 u32 fb_div;
516 };
517 u32 ref_div;
518 bool enable_post_div;
519 bool enable_dithen;
520 u32 vco_mode;
521 u32 real_clock;
522
523 u32 post_divider;
524 u32 flags;
525};
526
527struct atom_mpll_param {
528 union {
529 struct {
530#ifdef __BIG_ENDIAN
531 u32 reserved : 8;
532 u32 clkfrac : 12;
533 u32 clkf : 12;
534#else
535 u32 clkf : 12;
536 u32 clkfrac : 12;
537 u32 reserved : 8;
538#endif
539 };
540 u32 fb_div;
541 };
542 u32 post_div;
543 u32 bwcntl;
544 u32 dll_speed;
545 u32 vco_mode;
546 u32 yclk_sel;
547 u32 qdr;
548 u32 half_rate;
549};
550
551#define MEM_TYPE_GDDR5 0x50
552#define MEM_TYPE_GDDR4 0x40
553#define MEM_TYPE_GDDR3 0x30
554#define MEM_TYPE_DDR2 0x20
555#define MEM_TYPE_GDDR1 0x10
556#define MEM_TYPE_DDR3 0xb0
557#define MEM_TYPE_MASK 0xf0
558
559struct atom_memory_info {
560 u8 mem_vendor;
561 u8 mem_type;
562};
563
564#define MAX_AC_TIMING_ENTRIES 16
565
566struct atom_memory_clock_range_table
567{
568 u8 num_entries;
569 u8 rsv[3];
570 u32 mclk[MAX_AC_TIMING_ENTRIES];
571};
572
573#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
574#define VBIOS_MAX_AC_TIMING_ENTRIES 20
575
576struct atom_mc_reg_entry {
577 u32 mclk_max;
578 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
579};
580
581struct atom_mc_register_address {
582 u16 s1;
583 u8 pre_reg_data;
584};
585
586struct atom_mc_reg_table {
587 u8 last;
588 u8 num_entries;
589 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
590 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
591};
592
593#define MAX_VOLTAGE_ENTRIES 32
594
595struct atom_voltage_table_entry
596{
597 u16 value;
598 u32 smio_low;
599};
600
601struct atom_voltage_table
602{
603 u32 count;
604 u32 mask_low;
605 u32 phase_delay;
606 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
607};
608
609extern enum radeon_tv_std
610radeon_combios_get_tv_info(struct radeon_device *rdev);
611extern enum radeon_tv_std
612radeon_atombios_get_tv_info(struct radeon_device *rdev);
613extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
614 u16 *vddc, u16 *vddci, u16 *mvdd);
615
616extern struct drm_connector *
617radeon_get_connector_for_encoder(struct drm_encoder *encoder);
618extern struct drm_connector *
619radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
620extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
621 u32 pixel_clock);
622
623extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
624extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
625extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
626extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
627extern int radeon_get_monitor_bpc(struct drm_connector *connector);
628
629extern void radeon_connector_hotplug(struct drm_connector *connector);
630extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
631 struct drm_display_mode *mode);
632extern void radeon_dp_set_link_config(struct drm_connector *connector,
633 const struct drm_display_mode *mode);
634extern void radeon_dp_link_train(struct drm_encoder *encoder,
635 struct drm_connector *connector);
636extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
637extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
638extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
639extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
640 struct drm_connector *connector);
641extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
642extern void radeon_atom_encoder_init(struct radeon_device *rdev);
643extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
644extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
645 int action, uint8_t lane_num,
646 uint8_t lane_set);
647extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
648extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
649extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
650 u8 write_byte, u8 *read_byte);
651
652extern void radeon_i2c_init(struct radeon_device *rdev);
653extern void radeon_i2c_fini(struct radeon_device *rdev);
654extern void radeon_combios_i2c_init(struct radeon_device *rdev);
655extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
656extern void radeon_i2c_add(struct radeon_device *rdev,
657 struct radeon_i2c_bus_rec *rec,
658 const char *name);
659extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
660 struct radeon_i2c_bus_rec *i2c_bus);
661extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
662 struct radeon_i2c_bus_rec *rec,
663 const char *name);
664extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
665 struct radeon_i2c_bus_rec *rec,
666 const char *name);
667extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
668extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
669 u8 slave_addr,
670 u8 addr,
671 u8 *val);
672extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
673 u8 slave_addr,
674 u8 addr,
675 u8 val);
676extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
677extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
678extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
679extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
680
681extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
682
683extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
684 struct radeon_atom_ss *ss,
685 int id);
686extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
687 struct radeon_atom_ss *ss,
688 int id, u32 clock);
689
690extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
691 uint64_t freq,
692 uint32_t *dot_clock_p,
693 uint32_t *fb_div_p,
694 uint32_t *frac_fb_div_p,
695 uint32_t *ref_div_p,
696 uint32_t *post_div_p);
697
698extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
699 u32 freq,
700 u32 *dot_clock_p,
701 u32 *fb_div_p,
702 u32 *frac_fb_div_p,
703 u32 *ref_div_p,
704 u32 *post_div_p);
705
706extern void radeon_setup_encoder_clones(struct drm_device *dev);
707
708struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
709struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
710struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
711struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
712struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
713extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
714extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
715extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
716extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
717extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
718
719extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
720extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
721 struct drm_framebuffer *old_fb);
722extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
723 struct drm_framebuffer *fb,
724 int x, int y,
725 enum mode_set_atomic state);
726extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
727 struct drm_display_mode *mode,
728 struct drm_display_mode *adjusted_mode,
729 int x, int y,
730 struct drm_framebuffer *old_fb);
731extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
732
733extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
734 struct drm_framebuffer *old_fb);
735extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
736 struct drm_framebuffer *fb,
737 int x, int y,
738 enum mode_set_atomic state);
739extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
740 struct drm_framebuffer *fb,
741 int x, int y, int atomic);
742extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
743 struct drm_file *file_priv,
744 uint32_t handle,
745 uint32_t width,
746 uint32_t height);
747extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
748 int x, int y);
749
750extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
751 int *vpos, int *hpos);
752
753extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
754extern struct edid *
755radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
756extern bool radeon_atom_get_clock_info(struct drm_device *dev);
757extern bool radeon_combios_get_clock_info(struct drm_device *dev);
758extern struct radeon_encoder_atom_dig *
759radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
760extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
761 struct radeon_encoder_int_tmds *tmds);
762extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
763 struct radeon_encoder_int_tmds *tmds);
764extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
765 struct radeon_encoder_int_tmds *tmds);
766extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
767 struct radeon_encoder_ext_tmds *tmds);
768extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
769 struct radeon_encoder_ext_tmds *tmds);
770extern struct radeon_encoder_primary_dac *
771radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
772extern struct radeon_encoder_tv_dac *
773radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
774extern struct radeon_encoder_lvds *
775radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
776extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
777extern struct radeon_encoder_tv_dac *
778radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
779extern struct radeon_encoder_primary_dac *
780radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
781extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
782extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
783extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
784extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
785extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
786extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
787extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
788extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
789extern void
790radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
791extern void
792radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
793extern void
794radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
795extern void
796radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
797extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
798 u16 blue, int regno);
799extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
800 u16 *blue, int regno);
801int radeon_framebuffer_init(struct drm_device *dev,
802 struct radeon_framebuffer *rfb,
803 struct drm_mode_fb_cmd2 *mode_cmd,
804 struct drm_gem_object *obj);
805
806int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
807bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
808bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
809void radeon_atombios_init_crtc(struct drm_device *dev,
810 struct radeon_crtc *radeon_crtc);
811void radeon_legacy_init_crtc(struct drm_device *dev,
812 struct radeon_crtc *radeon_crtc);
813
814void radeon_get_clock_info(struct drm_device *dev);
815
816extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
817extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
818
819void radeon_enc_destroy(struct drm_encoder *encoder);
820void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
821void radeon_combios_asic_init(struct drm_device *dev);
822bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
823 const struct drm_display_mode *mode,
824 struct drm_display_mode *adjusted_mode);
825void radeon_panel_mode_fixup(struct drm_encoder *encoder,
826 struct drm_display_mode *adjusted_mode);
827void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
828
829
830void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
831 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
832 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
833void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
834 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
835 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
836void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
837 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
838 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
839void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
840 struct drm_display_mode *mode,
841 struct drm_display_mode *adjusted_mode);
842
843
844int radeon_fbdev_init(struct radeon_device *rdev);
845void radeon_fbdev_fini(struct radeon_device *rdev);
846void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
847int radeon_fbdev_total_size(struct radeon_device *rdev);
848bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
849
850void radeon_fb_output_poll_changed(struct radeon_device *rdev);
851
852void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
853
854int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
855#endif
856
