LXR linux/drivers/gpu/drm/tilcdc/tilcdc

   1/*
   2 * Copyright (C) 2012 Texas Instruments
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __TILCDC_REGS_H__
  19#define __TILCDC_REGS_H__
  20
  21/* LCDC register definitions, based on da8xx-fb */
  22
  23#include <linux/bitops.h>
  24
  25#include "tilcdc_drv.h"
  26
  27/* LCDC Status Register */
  28#define LCDC_END_OF_FRAME1                       BIT(9)
  29#define LCDC_END_OF_FRAME0                       BIT(8)
  30#define LCDC_PL_LOAD_DONE                        BIT(6)
  31#define LCDC_FIFO_UNDERFLOW                      BIT(5)
  32#define LCDC_SYNC_LOST                           BIT(2)
  33#define LCDC_FRAME_DONE                          BIT(0)
  34
  35/* LCDC DMA Control Register */
  36#define LCDC_DMA_BURST_SIZE(x)                   ((x) << 4)
  37#define LCDC_DMA_BURST_1                         0x0
  38#define LCDC_DMA_BURST_2                         0x1
  39#define LCDC_DMA_BURST_4                         0x2
  40#define LCDC_DMA_BURST_8                         0x3
  41#define LCDC_DMA_BURST_16                        0x4
  42#define LCDC_V1_END_OF_FRAME_INT_ENA             BIT(2)
  43#define LCDC_V2_END_OF_FRAME0_INT_ENA            BIT(8)
  44#define LCDC_V2_END_OF_FRAME1_INT_ENA            BIT(9)
  45#define LCDC_DUAL_FRAME_BUFFER_ENABLE            BIT(0)
  46
  47/* LCDC Control Register */
  48#define LCDC_CLK_DIVISOR(x)                      ((x) << 8)
  49#define LCDC_RASTER_MODE                         0x01
  50
  51/* LCDC Raster Control Register */
  52#define LCDC_PALETTE_LOAD_MODE(x)                ((x) << 20)
  53#define PALETTE_AND_DATA                         0x00
  54#define PALETTE_ONLY                             0x01
  55#define DATA_ONLY                                0x02
  56
  57#define LCDC_MONO_8BIT_MODE                      BIT(9)
  58#define LCDC_RASTER_ORDER                        BIT(8)
  59#define LCDC_TFT_MODE                            BIT(7)
  60#define LCDC_V1_UNDERFLOW_INT_ENA                BIT(6)
  61#define LCDC_V2_UNDERFLOW_INT_ENA                BIT(5)
  62#define LCDC_V1_PL_INT_ENA                       BIT(4)
  63#define LCDC_V2_PL_INT_ENA                       BIT(6)
  64#define LCDC_MONOCHROME_MODE                     BIT(1)
  65#define LCDC_RASTER_ENABLE                       BIT(0)
  66#define LCDC_TFT_ALT_ENABLE                      BIT(23)
  67#define LCDC_STN_565_ENABLE                      BIT(24)
  68#define LCDC_V2_DMA_CLK_EN                       BIT(2)
  69#define LCDC_V2_LIDD_CLK_EN                      BIT(1)
  70#define LCDC_V2_CORE_CLK_EN                      BIT(0)
  71#define LCDC_V2_LPP_B10                          26
  72#define LCDC_V2_TFT_24BPP_MODE                   BIT(25)
  73#define LCDC_V2_TFT_24BPP_UNPACK                 BIT(26)
  74
  75/* LCDC Raster Timing 2 Register */
  76#define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  77#define LCDC_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  78#define LCDC_SYNC_CTRL                           BIT(25)
  79#define LCDC_SYNC_EDGE                           BIT(24)
  80#define LCDC_INVERT_PIXEL_CLOCK                  BIT(22)
  81#define LCDC_INVERT_HSYNC                        BIT(21)
  82#define LCDC_INVERT_VSYNC                        BIT(20)
  83#define LCDC_LPP_B10                             BIT(26)
  84
  85/* LCDC Block */
  86#define LCDC_PID_REG                             0x0
  87#define LCDC_CTRL_REG                            0x4
  88#define LCDC_STAT_REG                            0x8
  89#define LCDC_RASTER_CTRL_REG                     0x28
  90#define LCDC_RASTER_TIMING_0_REG                 0x2c
  91#define LCDC_RASTER_TIMING_1_REG                 0x30
  92#define LCDC_RASTER_TIMING_2_REG                 0x34
  93#define LCDC_DMA_CTRL_REG                        0x40
  94#define LCDC_DMA_FB_BASE_ADDR_0_REG              0x44
  95#define LCDC_DMA_FB_CEILING_ADDR_0_REG           0x48
  96#define LCDC_DMA_FB_BASE_ADDR_1_REG              0x4c
  97#define LCDC_DMA_FB_CEILING_ADDR_1_REG           0x50
  98
  99/* Interrupt Registers available only in Version 2 */
 100#define LCDC_RAW_STAT_REG                        0x58
 101#define LCDC_MASKED_STAT_REG                     0x5c
 102#define LCDC_INT_ENABLE_SET_REG                  0x60
 103#define LCDC_INT_ENABLE_CLR_REG                  0x64
 104#define LCDC_END_OF_INT_IND_REG                  0x68
 105
 106/* Clock registers available only on Version 2 */
 107#define LCDC_CLK_ENABLE_REG                      0x6c
 108#define LCDC_CLK_RESET_REG                       0x70
 109#define LCDC_CLK_MAIN_RESET                      BIT(3)
 110
 111
 112/*
 113 * Helpers:
 114 */
 115
 116static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
 117{
 118        struct tilcdc_drm_private *priv = dev->dev_private;
 119        iowrite32(data, priv->mmio + reg);
 120}
 121
 122static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
 123{
 124        struct tilcdc_drm_private *priv = dev->dev_private;
 125        return ioread32(priv->mmio + reg);
 126}
 127
 128static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
 129{
 130        tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
 131}
 132
 133static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
 134{
 135        tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
 136}
 137
 138/* the register to read/clear irqstatus differs between v1 and v2 of the IP */
 139static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
 140{
 141        struct tilcdc_drm_private *priv = dev->dev_private;
 142        return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
 143}
 144
 145static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
 146{
 147        return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
 148}
 149
 150static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
 151{
 152        tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
 153}
 154
 155#endif /* __TILCDC_REGS_H__ */
 156