1/* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10#ifndef TEGRA_DC_H 11#define TEGRA_DC_H 1 12 13#define DC_CMD_GENERAL_INCR_SYNCPT 0x000 14#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 15#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 16#define DC_CMD_WIN_A_INCR_SYNCPT 0x008 17#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 18#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 19#define DC_CMD_WIN_B_INCR_SYNCPT 0x010 20#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 21#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 22#define DC_CMD_WIN_C_INCR_SYNCPT 0x018 23#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 24#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 25#define DC_CMD_CONT_SYNCPT_VSYNC 0x028 26#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 27#define DC_CMD_DISPLAY_COMMAND 0x032 28#define DISP_CTRL_MODE_STOP (0 << 5) 29#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 30#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 31#define DC_CMD_SIGNAL_RAISE 0x033 32#define DC_CMD_DISPLAY_POWER_CONTROL 0x036 33#define PW0_ENABLE (1 << 0) 34#define PW1_ENABLE (1 << 2) 35#define PW2_ENABLE (1 << 4) 36#define PW3_ENABLE (1 << 6) 37#define PW4_ENABLE (1 << 8) 38#define PM0_ENABLE (1 << 16) 39#define PM1_ENABLE (1 << 18) 40 41#define DC_CMD_INT_STATUS 0x037 42#define DC_CMD_INT_MASK 0x038 43#define DC_CMD_INT_ENABLE 0x039 44#define DC_CMD_INT_TYPE 0x03a 45#define DC_CMD_INT_POLARITY 0x03b 46#define CTXSW_INT (1 << 0) 47#define FRAME_END_INT (1 << 1) 48#define VBLANK_INT (1 << 2) 49#define WIN_A_UF_INT (1 << 8) 50#define WIN_B_UF_INT (1 << 9) 51#define WIN_C_UF_INT (1 << 10) 52#define WIN_A_OF_INT (1 << 14) 53#define WIN_B_OF_INT (1 << 15) 54#define WIN_C_OF_INT (1 << 16) 55 56#define DC_CMD_SIGNAL_RAISE1 0x03c 57#define DC_CMD_SIGNAL_RAISE2 0x03d 58#define DC_CMD_SIGNAL_RAISE3 0x03e 59 60#define DC_CMD_STATE_ACCESS 0x040 61#define READ_MUX (1 << 0) 62#define WRITE_MUX (1 << 2) 63 64#define DC_CMD_STATE_CONTROL 0x041 65#define GENERAL_ACT_REQ (1 << 0) 66#define WIN_A_ACT_REQ (1 << 1) 67#define WIN_B_ACT_REQ (1 << 2) 68#define WIN_C_ACT_REQ (1 << 3) 69#define GENERAL_UPDATE (1 << 8) 70#define WIN_A_UPDATE (1 << 9) 71#define WIN_B_UPDATE (1 << 10) 72#define WIN_C_UPDATE (1 << 11) 73#define NC_HOST_TRIG (1 << 24) 74 75#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 76#define WINDOW_A_SELECT (1 << 4) 77#define WINDOW_B_SELECT (1 << 5) 78#define WINDOW_C_SELECT (1 << 6) 79 80#define DC_CMD_REG_ACT_CONTROL 0x043 81 82#define DC_COM_CRC_CONTROL 0x300 83#define DC_COM_CRC_CHECKSUM 0x301 84#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 85#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 86#define LVS_OUTPUT_POLARITY_LOW (1 << 28) 87#define LHS_OUTPUT_POLARITY_LOW (1 << 30) 88#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 89#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 90#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 91#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 92 93#define DC_COM_PIN_MISC_CONTROL 0x31b 94#define DC_COM_PIN_PM0_CONTROL 0x31c 95#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 96#define DC_COM_PIN_PM1_CONTROL 0x31e 97#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 98 99#define DC_COM_SPI_CONTROL 0x320 100#define DC_COM_SPI_START_BYTE 0x321 101#define DC_COM_HSPI_WRITE_DATA_AB 0x322 102#define DC_COM_HSPI_WRITE_DATA_CD 0x323 103#define DC_COM_HSPI_CS_DC 0x324 104#define DC_COM_SCRATCH_REGISTER_A 0x325 105#define DC_COM_SCRATCH_REGISTER_B 0x326 106#define DC_COM_GPIO_CTRL 0x327 107#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 108#define DC_COM_CRC_CHECKSUM_LATCHED 0x329 109 110#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 111#define H_PULSE_0_ENABLE (1 << 8) 112#define H_PULSE_1_ENABLE (1 << 10) 113#define H_PULSE_2_ENABLE (1 << 12) 114 115#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 116 117#define DC_DISP_DISP_WIN_OPTIONS 0x402 118#define HDMI_ENABLE (1 << 30) 119 120#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 121#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 122#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 123#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 124#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 125 126#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 127#define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 128#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 129#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 130#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 131 132#define DC_DISP_DISP_TIMING_OPTIONS 0x405 133#define VSYNC_H_POSITION(x) ((x) & 0xfff) 134 135#define DC_DISP_REF_TO_SYNC 0x406 136#define DC_DISP_SYNC_WIDTH 0x407 137#define DC_DISP_BACK_PORCH 0x408 138#define DC_DISP_ACTIVE 0x409 139#define DC_DISP_FRONT_PORCH 0x40a 140#define DC_DISP_H_PULSE0_CONTROL 0x40b 141#define DC_DISP_H_PULSE0_POSITION_A 0x40c 142#define DC_DISP_H_PULSE0_POSITION_B 0x40d 143#define DC_DISP_H_PULSE0_POSITION_C 0x40e 144#define DC_DISP_H_PULSE0_POSITION_D 0x40f 145#define DC_DISP_H_PULSE1_CONTROL 0x410 146#define DC_DISP_H_PULSE1_POSITION_A 0x411 147#define DC_DISP_H_PULSE1_POSITION_B 0x412 148#define DC_DISP_H_PULSE1_POSITION_C 0x413 149#define DC_DISP_H_PULSE1_POSITION_D 0x414 150#define DC_DISP_H_PULSE2_CONTROL 0x415 151#define DC_DISP_H_PULSE2_POSITION_A 0x416 152#define DC_DISP_H_PULSE2_POSITION_B 0x417 153#define DC_DISP_H_PULSE2_POSITION_C 0x418 154#define DC_DISP_H_PULSE2_POSITION_D 0x419 155#define DC_DISP_V_PULSE0_CONTROL 0x41a 156#define DC_DISP_V_PULSE0_POSITION_A 0x41b 157#define DC_DISP_V_PULSE0_POSITION_B 0x41c 158#define DC_DISP_V_PULSE0_POSITION_C 0x41d 159#define DC_DISP_V_PULSE1_CONTROL 0x41e 160#define DC_DISP_V_PULSE1_POSITION_A 0x41f 161#define DC_DISP_V_PULSE1_POSITION_B 0x420 162#define DC_DISP_V_PULSE1_POSITION_C 0x421 163#define DC_DISP_V_PULSE2_CONTROL 0x422 164#define DC_DISP_V_PULSE2_POSITION_A 0x423 165#define DC_DISP_V_PULSE3_CONTROL 0x424 166#define DC_DISP_V_PULSE3_POSITION_A 0x425 167#define DC_DISP_M0_CONTROL 0x426 168#define DC_DISP_M1_CONTROL 0x427 169#define DC_DISP_DI_CONTROL 0x428 170#define DC_DISP_PP_CONTROL 0x429 171#define DC_DISP_PP_SELECT_A 0x42a 172#define DC_DISP_PP_SELECT_B 0x42b 173#define DC_DISP_PP_SELECT_C 0x42c 174#define DC_DISP_PP_SELECT_D 0x42d 175 176#define PULSE_MODE_NORMAL (0 << 3) 177#define PULSE_MODE_ONE_CLOCK (1 << 3) 178#define PULSE_POLARITY_HIGH (0 << 4) 179#define PULSE_POLARITY_LOW (1 << 4) 180#define PULSE_QUAL_ALWAYS (0 << 6) 181#define PULSE_QUAL_VACTIVE (2 << 6) 182#define PULSE_QUAL_VACTIVE1 (3 << 6) 183#define PULSE_LAST_START_A (0 << 8) 184#define PULSE_LAST_END_A (1 << 8) 185#define PULSE_LAST_START_B (2 << 8) 186#define PULSE_LAST_END_B (3 << 8) 187#define PULSE_LAST_START_C (4 << 8) 188#define PULSE_LAST_END_C (5 << 8) 189#define PULSE_LAST_START_D (6 << 8) 190#define PULSE_LAST_END_D (7 << 8) 191 192#define PULSE_START(x) (((x) & 0xfff) << 0) 193#define PULSE_END(x) (((x) & 0xfff) << 16) 194 195#define DC_DISP_DISP_CLOCK_CONTROL 0x42e 196#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 197#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 198#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 199#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 200#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 201#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 202#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 203#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 204#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 205#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 206#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 207#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 208#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 209#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 210 211#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 212#define DISP_DATA_FORMAT_DF1P1C (0 << 0) 213#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 214#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 215#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 216#define DISP_DATA_FORMAT_DF2S (4 << 0) 217#define DISP_DATA_FORMAT_DF3S (5 << 0) 218#define DISP_DATA_FORMAT_DFSPI (6 << 0) 219#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 220#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 221#define DISP_ALIGNMENT_MSB (0 << 8) 222#define DISP_ALIGNMENT_LSB (1 << 8) 223#define DISP_ORDER_RED_BLUE (0 << 9) 224#define DISP_ORDER_BLUE_RED (1 << 9) 225 226#define DC_DISP_DISP_COLOR_CONTROL 0x430 227#define BASE_COLOR_SIZE666 (0 << 0) 228#define BASE_COLOR_SIZE111 (1 << 0) 229#define BASE_COLOR_SIZE222 (2 << 0) 230#define BASE_COLOR_SIZE333 (3 << 0) 231#define BASE_COLOR_SIZE444 (4 << 0) 232#define BASE_COLOR_SIZE555 (5 << 0) 233#define BASE_COLOR_SIZE565 (6 << 0) 234#define BASE_COLOR_SIZE332 (7 << 0) 235#define BASE_COLOR_SIZE888 (8 << 0) 236#define DITHER_CONTROL_DISABLE (0 << 8) 237#define DITHER_CONTROL_ORDERED (2 << 8) 238#define DITHER_CONTROL_ERRDIFF (3 << 8) 239 240#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 241 242#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 243#define DE_SELECT_ACTIVE_BLANK (0 << 0) 244#define DE_SELECT_ACTIVE (1 << 0) 245#define DE_SELECT_ACTIVE_IS (2 << 0) 246#define DE_CONTROL_ONECLK (0 << 2) 247#define DE_CONTROL_NORMAL (1 << 2) 248#define DE_CONTROL_EARLY_EXT (2 << 2) 249#define DE_CONTROL_EARLY (3 << 2) 250#define DE_CONTROL_ACTIVE_BLANK (4 << 2) 251 252#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 253#define DC_DISP_LCD_SPI_OPTIONS 0x434 254#define DC_DISP_BORDER_COLOR 0x435 255#define DC_DISP_COLOR_KEY0_LOWER 0x436 256#define DC_DISP_COLOR_KEY0_UPPER 0x437 257#define DC_DISP_COLOR_KEY1_LOWER 0x438 258#define DC_DISP_COLOR_KEY1_UPPER 0x439 259 260#define DC_DISP_CURSOR_FOREGROUND 0x43c 261#define DC_DISP_CURSOR_BACKGROUND 0x43d 262 263#define DC_DISP_CURSOR_START_ADDR 0x43e 264#define DC_DISP_CURSOR_START_ADDR_NS 0x43f 265 266#define DC_DISP_CURSOR_POSITION 0x440 267#define DC_DISP_CURSOR_POSITION_NS 0x441 268 269#define DC_DISP_INIT_SEQ_CONTROL 0x442 270#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 271#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 272#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 273#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 274 275#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 276#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 277#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 278#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 279#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 280 281#define DC_DISP_DAC_CRT_CTRL 0x4c0 282#define DC_DISP_DISP_MISC_CONTROL 0x4c1 283#define DC_DISP_SD_CONTROL 0x4c2 284#define DC_DISP_SD_CSC_COEFF 0x4c3 285#define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 286#define DC_DISP_SD_FLICKER_CONTROL 0x4cd 287#define DC_DISP_DC_PIXEL_COUNT 0x4ce 288#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 289#define DC_DISP_SD_BL_PARAMETERS 0x4d7 290#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 291#define DC_DISP_SD_BL_CONTROL 0x4dc 292#define DC_DISP_SD_HW_K_VALUES 0x4dd 293#define DC_DISP_SD_MAN_K_VALUES 0x4de 294 295#define DC_WIN_CSC_YOF 0x611 296#define DC_WIN_CSC_KYRGB 0x612 297#define DC_WIN_CSC_KUR 0x613 298#define DC_WIN_CSC_KVR 0x614 299#define DC_WIN_CSC_KUG 0x615 300#define DC_WIN_CSC_KVG 0x616 301#define DC_WIN_CSC_KUB 0x617 302#define DC_WIN_CSC_KVB 0x618 303 304#define DC_WIN_WIN_OPTIONS 0x700 305#define COLOR_EXPAND (1 << 6) 306#define CSC_ENABLE (1 << 18) 307#define WIN_ENABLE (1 << 30) 308 309#define DC_WIN_BYTE_SWAP 0x701 310#define BYTE_SWAP_NOSWAP (0 << 0) 311#define BYTE_SWAP_SWAP2 (1 << 0) 312#define BYTE_SWAP_SWAP4 (2 << 0) 313#define BYTE_SWAP_SWAP4HW (3 << 0) 314 315#define DC_WIN_BUFFER_CONTROL 0x702 316#define BUFFER_CONTROL_HOST (0 << 0) 317#define BUFFER_CONTROL_VI (1 << 0) 318#define BUFFER_CONTROL_EPP (2 << 0) 319#define BUFFER_CONTROL_MPEGE (3 << 0) 320#define BUFFER_CONTROL_SB2D (4 << 0) 321 322#define DC_WIN_COLOR_DEPTH 0x703 323#define WIN_COLOR_DEPTH_P1 0 324#define WIN_COLOR_DEPTH_P2 1 325#define WIN_COLOR_DEPTH_P4 2 326#define WIN_COLOR_DEPTH_P8 3 327#define WIN_COLOR_DEPTH_B4G4R4A4 4 328#define WIN_COLOR_DEPTH_B5G5R5A 5 329#define WIN_COLOR_DEPTH_B5G6R5 6 330#define WIN_COLOR_DEPTH_AB5G5R5 7 331#define WIN_COLOR_DEPTH_B8G8R8A8 12 332#define WIN_COLOR_DEPTH_R8G8B8A8 13 333#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 334#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 335#define WIN_COLOR_DEPTH_YCbCr422 16 336#define WIN_COLOR_DEPTH_YUV422 17 337#define WIN_COLOR_DEPTH_YCbCr420P 18 338#define WIN_COLOR_DEPTH_YUV420P 19 339#define WIN_COLOR_DEPTH_YCbCr422P 20 340#define WIN_COLOR_DEPTH_YUV422P 21 341#define WIN_COLOR_DEPTH_YCbCr422R 22 342#define WIN_COLOR_DEPTH_YUV422R 23 343#define WIN_COLOR_DEPTH_YCbCr422RA 24 344#define WIN_COLOR_DEPTH_YUV422RA 25 345 346#define DC_WIN_POSITION 0x704 347#define H_POSITION(x) (((x) & 0x1fff) << 0) 348#define V_POSITION(x) (((x) & 0x1fff) << 16) 349 350#define DC_WIN_SIZE 0x705 351#define H_SIZE(x) (((x) & 0x1fff) << 0) 352#define V_SIZE(x) (((x) & 0x1fff) << 16) 353 354#define DC_WIN_PRESCALED_SIZE 0x706 355#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 356#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) 357 358#define DC_WIN_H_INITIAL_DDA 0x707 359#define DC_WIN_V_INITIAL_DDA 0x708 360#define DC_WIN_DDA_INC 0x709 361#define H_DDA_INC(x) (((x) & 0xffff) << 0) 362#define V_DDA_INC(x) (((x) & 0xffff) << 16) 363 364#define DC_WIN_LINE_STRIDE 0x70a 365#define DC_WIN_BUF_STRIDE 0x70b 366#define DC_WIN_UV_BUF_STRIDE 0x70c 367#define DC_WIN_BUFFER_ADDR_MODE 0x70d 368#define DC_WIN_DV_CONTROL 0x70e 369 370#define DC_WIN_BLEND_NOKEY 0x70f 371#define DC_WIN_BLEND_1WIN 0x710 372#define DC_WIN_BLEND_2WIN_X 0x711 373#define DC_WIN_BLEND_2WIN_Y 0x712 374#define DC_WIN_BLEND_3WIN_XY 0x713 375 376#define DC_WIN_HP_FETCH_CONTROL 0x714 377 378#define DC_WINBUF_START_ADDR 0x800 379#define DC_WINBUF_START_ADDR_NS 0x801 380#define DC_WINBUF_START_ADDR_U 0x802 381#define DC_WINBUF_START_ADDR_U_NS 0x803 382#define DC_WINBUF_START_ADDR_V 0x804 383#define DC_WINBUF_START_ADDR_V_NS 0x805 384 385#define DC_WINBUF_ADDR_H_OFFSET 0x806 386#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 387#define DC_WINBUF_ADDR_V_OFFSET 0x808 388#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 389 390#define DC_WINBUF_UFLOW_STATUS 0x80a 391 392#define DC_WINBUF_AD_UFLOW_STATUS 0xbca 393#define DC_WINBUF_BD_UFLOW_STATUS 0xdca 394#define DC_WINBUF_CD_UFLOW_STATUS 0xfca 395 396/* synchronization points */ 397#define SYNCPT_VBLANK0 26 398#define SYNCPT_VBLANK1 27 399 400#endif /* TEGRA_DC_H */ 401