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23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/delay.h>
31#include <linux/firmware.h>
32#include <linux/i2c.h>
33#include <linux/hardirq.h>
34#include <asm/div64.h>
35
36#include "dvb_frontend.h"
37#include "drxk.h"
38#include "drxk_hard.h"
39#include "dvb_math.h"
40
41static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
42static int power_down_qam(struct drxk_state *state);
43static int set_dvbt_standard(struct drxk_state *state,
44 enum operation_mode o_mode);
45static int set_qam_standard(struct drxk_state *state,
46 enum operation_mode o_mode);
47static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
48 s32 tuner_freq_offset);
49static int set_dvbt_standard(struct drxk_state *state,
50 enum operation_mode o_mode);
51static int dvbt_start(struct drxk_state *state);
52static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
53 s32 tuner_freq_offset);
54static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
55static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
56static int switch_antenna_to_qam(struct drxk_state *state);
57static int switch_antenna_to_dvbt(struct drxk_state *state);
58
59static bool is_dvbt(struct drxk_state *state)
60{
61 return state->m_operation_mode == OM_DVBT;
62}
63
64static bool is_qam(struct drxk_state *state)
65{
66 return state->m_operation_mode == OM_QAM_ITU_A ||
67 state->m_operation_mode == OM_QAM_ITU_B ||
68 state->m_operation_mode == OM_QAM_ITU_C;
69}
70
71#define NOA1ROM 0
72
73#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
74#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
75
76#define DEFAULT_MER_83 165
77#define DEFAULT_MER_93 250
78
79#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
80#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
81#endif
82
83#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
84#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
85#endif
86
87#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
88#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
89
90#ifndef DRXK_KI_RAGC_ATV
91#define DRXK_KI_RAGC_ATV 4
92#endif
93#ifndef DRXK_KI_IAGC_ATV
94#define DRXK_KI_IAGC_ATV 6
95#endif
96#ifndef DRXK_KI_DAGC_ATV
97#define DRXK_KI_DAGC_ATV 7
98#endif
99
100#ifndef DRXK_KI_RAGC_QAM
101#define DRXK_KI_RAGC_QAM 3
102#endif
103#ifndef DRXK_KI_IAGC_QAM
104#define DRXK_KI_IAGC_QAM 4
105#endif
106#ifndef DRXK_KI_DAGC_QAM
107#define DRXK_KI_DAGC_QAM 7
108#endif
109#ifndef DRXK_KI_RAGC_DVBT
110#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
111#endif
112#ifndef DRXK_KI_IAGC_DVBT
113#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
114#endif
115#ifndef DRXK_KI_DAGC_DVBT
116#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
117#endif
118
119#ifndef DRXK_AGC_DAC_OFFSET
120#define DRXK_AGC_DAC_OFFSET (0x800)
121#endif
122
123#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
124#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
125#endif
126
127#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
128#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
129#endif
130
131#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
132#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
133#endif
134
135#ifndef DRXK_QAM_SYMBOLRATE_MAX
136#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
137#endif
138
139#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
140#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
141#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
142#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
143#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
144#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
145#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
146#define DRXK_BL_ROM_OFFSET_UCODE 0
147
148#define DRXK_BLC_TIMEOUT 100
149
150#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
151#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
152
153#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
154
155#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
156#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
157#endif
158
159#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
160#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
161#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
162#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
163#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
164
165static unsigned int debug;
166module_param(debug, int, 0644);
167MODULE_PARM_DESC(debug, "enable debug messages");
168
169#define dprintk(level, fmt, arg...) do { \
170if (debug >= level) \
171 pr_debug(fmt, ##arg); \
172} while (0)
173
174
175static inline u32 MulDiv32(u32 a, u32 b, u32 c)
176{
177 u64 tmp64;
178
179 tmp64 = (u64) a * (u64) b;
180 do_div(tmp64, c);
181
182 return (u32) tmp64;
183}
184
185static inline u32 Frac28a(u32 a, u32 c)
186{
187 int i = 0;
188 u32 Q1 = 0;
189 u32 R0 = 0;
190
191 R0 = (a % c) << 4;
192 Q1 = a / c;
193
194
195
196
197
198 for (i = 0; i < 7; i++) {
199 Q1 = (Q1 << 4) | (R0 / c);
200 R0 = (R0 % c) << 4;
201 }
202
203 if ((R0 >> 3) >= c)
204 Q1++;
205
206 return Q1;
207}
208
209static inline u32 log10times100(u32 value)
210{
211 return (100L * intlog10(value)) >> 24;
212}
213
214
215
216
217
218static int drxk_i2c_lock(struct drxk_state *state)
219{
220 i2c_lock_adapter(state->i2c);
221 state->drxk_i2c_exclusive_lock = true;
222
223 return 0;
224}
225
226static void drxk_i2c_unlock(struct drxk_state *state)
227{
228 if (!state->drxk_i2c_exclusive_lock)
229 return;
230
231 i2c_unlock_adapter(state->i2c);
232 state->drxk_i2c_exclusive_lock = false;
233}
234
235static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
236 unsigned len)
237{
238 if (state->drxk_i2c_exclusive_lock)
239 return __i2c_transfer(state->i2c, msgs, len);
240 else
241 return i2c_transfer(state->i2c, msgs, len);
242}
243
244static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
245{
246 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
247 .buf = val, .len = 1}
248 };
249
250 return drxk_i2c_transfer(state, msgs, 1);
251}
252
253static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
254{
255 int status;
256 struct i2c_msg msg = {
257 .addr = adr, .flags = 0, .buf = data, .len = len };
258
259 dprintk(3, ":");
260 if (debug > 2) {
261 int i;
262 for (i = 0; i < len; i++)
263 pr_cont(" %02x", data[i]);
264 pr_cont("\n");
265 }
266 status = drxk_i2c_transfer(state, &msg, 1);
267 if (status >= 0 && status != 1)
268 status = -EIO;
269
270 if (status < 0)
271 pr_err("i2c write error at addr 0x%02x\n", adr);
272
273 return status;
274}
275
276static int i2c_read(struct drxk_state *state,
277 u8 adr, u8 *msg, int len, u8 *answ, int alen)
278{
279 int status;
280 struct i2c_msg msgs[2] = {
281 {.addr = adr, .flags = 0,
282 .buf = msg, .len = len},
283 {.addr = adr, .flags = I2C_M_RD,
284 .buf = answ, .len = alen}
285 };
286
287 status = drxk_i2c_transfer(state, msgs, 2);
288 if (status != 2) {
289 if (debug > 2)
290 pr_cont(": ERROR!\n");
291 if (status >= 0)
292 status = -EIO;
293
294 pr_err("i2c read error at addr 0x%02x\n", adr);
295 return status;
296 }
297 if (debug > 2) {
298 int i;
299 dprintk(2, ": read from");
300 for (i = 0; i < len; i++)
301 pr_cont(" %02x", msg[i]);
302 pr_cont(", value = ");
303 for (i = 0; i < alen; i++)
304 pr_cont(" %02x", answ[i]);
305 pr_cont("\n");
306 }
307 return 0;
308}
309
310static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
311{
312 int status;
313 u8 adr = state->demod_address, mm1[4], mm2[2], len;
314
315 if (state->single_master)
316 flags |= 0xC0;
317
318 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
319 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
320 mm1[1] = ((reg >> 16) & 0xFF);
321 mm1[2] = ((reg >> 24) & 0xFF) | flags;
322 mm1[3] = ((reg >> 7) & 0xFF);
323 len = 4;
324 } else {
325 mm1[0] = ((reg << 1) & 0xFF);
326 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
327 len = 2;
328 }
329 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
330 status = i2c_read(state, adr, mm1, len, mm2, 2);
331 if (status < 0)
332 return status;
333 if (data)
334 *data = mm2[0] | (mm2[1] << 8);
335
336 return 0;
337}
338
339static int read16(struct drxk_state *state, u32 reg, u16 *data)
340{
341 return read16_flags(state, reg, data, 0);
342}
343
344static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
345{
346 int status;
347 u8 adr = state->demod_address, mm1[4], mm2[4], len;
348
349 if (state->single_master)
350 flags |= 0xC0;
351
352 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
353 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
354 mm1[1] = ((reg >> 16) & 0xFF);
355 mm1[2] = ((reg >> 24) & 0xFF) | flags;
356 mm1[3] = ((reg >> 7) & 0xFF);
357 len = 4;
358 } else {
359 mm1[0] = ((reg << 1) & 0xFF);
360 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
361 len = 2;
362 }
363 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
364 status = i2c_read(state, adr, mm1, len, mm2, 4);
365 if (status < 0)
366 return status;
367 if (data)
368 *data = mm2[0] | (mm2[1] << 8) |
369 (mm2[2] << 16) | (mm2[3] << 24);
370
371 return 0;
372}
373
374static int read32(struct drxk_state *state, u32 reg, u32 *data)
375{
376 return read32_flags(state, reg, data, 0);
377}
378
379static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
380{
381 u8 adr = state->demod_address, mm[6], len;
382
383 if (state->single_master)
384 flags |= 0xC0;
385 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
386 mm[0] = (((reg << 1) & 0xFF) | 0x01);
387 mm[1] = ((reg >> 16) & 0xFF);
388 mm[2] = ((reg >> 24) & 0xFF) | flags;
389 mm[3] = ((reg >> 7) & 0xFF);
390 len = 4;
391 } else {
392 mm[0] = ((reg << 1) & 0xFF);
393 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
394 len = 2;
395 }
396 mm[len] = data & 0xff;
397 mm[len + 1] = (data >> 8) & 0xff;
398
399 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
400 return i2c_write(state, adr, mm, len + 2);
401}
402
403static int write16(struct drxk_state *state, u32 reg, u16 data)
404{
405 return write16_flags(state, reg, data, 0);
406}
407
408static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
409{
410 u8 adr = state->demod_address, mm[8], len;
411
412 if (state->single_master)
413 flags |= 0xC0;
414 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
415 mm[0] = (((reg << 1) & 0xFF) | 0x01);
416 mm[1] = ((reg >> 16) & 0xFF);
417 mm[2] = ((reg >> 24) & 0xFF) | flags;
418 mm[3] = ((reg >> 7) & 0xFF);
419 len = 4;
420 } else {
421 mm[0] = ((reg << 1) & 0xFF);
422 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
423 len = 2;
424 }
425 mm[len] = data & 0xff;
426 mm[len + 1] = (data >> 8) & 0xff;
427 mm[len + 2] = (data >> 16) & 0xff;
428 mm[len + 3] = (data >> 24) & 0xff;
429 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
430
431 return i2c_write(state, adr, mm, len + 4);
432}
433
434static int write32(struct drxk_state *state, u32 reg, u32 data)
435{
436 return write32_flags(state, reg, data, 0);
437}
438
439static int write_block(struct drxk_state *state, u32 address,
440 const int block_size, const u8 p_block[])
441{
442 int status = 0, blk_size = block_size;
443 u8 flags = 0;
444
445 if (state->single_master)
446 flags |= 0xC0;
447
448 while (blk_size > 0) {
449 int chunk = blk_size > state->m_chunk_size ?
450 state->m_chunk_size : blk_size;
451 u8 *adr_buf = &state->chunk[0];
452 u32 adr_length = 0;
453
454 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
455 adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
456 adr_buf[1] = ((address >> 16) & 0xFF);
457 adr_buf[2] = ((address >> 24) & 0xFF);
458 adr_buf[3] = ((address >> 7) & 0xFF);
459 adr_buf[2] |= flags;
460 adr_length = 4;
461 if (chunk == state->m_chunk_size)
462 chunk -= 2;
463 } else {
464 adr_buf[0] = ((address << 1) & 0xFF);
465 adr_buf[1] = (((address >> 16) & 0x0F) |
466 ((address >> 18) & 0xF0));
467 adr_length = 2;
468 }
469 memcpy(&state->chunk[adr_length], p_block, chunk);
470 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
471 if (debug > 1) {
472 int i;
473 if (p_block)
474 for (i = 0; i < chunk; i++)
475 pr_cont(" %02x", p_block[i]);
476 pr_cont("\n");
477 }
478 status = i2c_write(state, state->demod_address,
479 &state->chunk[0], chunk + adr_length);
480 if (status < 0) {
481 pr_err("%s: i2c write error at addr 0x%02x\n",
482 __func__, address);
483 break;
484 }
485 p_block += chunk;
486 address += (chunk >> 1);
487 blk_size -= chunk;
488 }
489 return status;
490}
491
492#ifndef DRXK_MAX_RETRIES_POWERUP
493#define DRXK_MAX_RETRIES_POWERUP 20
494#endif
495
496static int power_up_device(struct drxk_state *state)
497{
498 int status;
499 u8 data = 0;
500 u16 retry_count = 0;
501
502 dprintk(1, "\n");
503
504 status = i2c_read1(state, state->demod_address, &data);
505 if (status < 0) {
506 do {
507 data = 0;
508 status = i2c_write(state, state->demod_address,
509 &data, 1);
510 usleep_range(10000, 11000);
511 retry_count++;
512 if (status < 0)
513 continue;
514 status = i2c_read1(state, state->demod_address,
515 &data);
516 } while (status < 0 &&
517 (retry_count < DRXK_MAX_RETRIES_POWERUP));
518 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
519 goto error;
520 }
521
522
523 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
524 if (status < 0)
525 goto error;
526 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
527 if (status < 0)
528 goto error;
529
530 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
531 if (status < 0)
532 goto error;
533
534 state->m_current_power_mode = DRX_POWER_UP;
535
536error:
537 if (status < 0)
538 pr_err("Error %d on %s\n", status, __func__);
539
540 return status;
541}
542
543
544static int init_state(struct drxk_state *state)
545{
546
547
548
549
550 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
551 u32 ul_vsb_if_agc_output_level = 0;
552 u32 ul_vsb_if_agc_min_level = 0;
553 u32 ul_vsb_if_agc_max_level = 0x7FFF;
554 u32 ul_vsb_if_agc_speed = 3;
555
556 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
557 u32 ul_vsb_rf_agc_output_level = 0;
558 u32 ul_vsb_rf_agc_min_level = 0;
559 u32 ul_vsb_rf_agc_max_level = 0x7FFF;
560 u32 ul_vsb_rf_agc_speed = 3;
561 u32 ul_vsb_rf_agc_top = 9500;
562 u32 ul_vsb_rf_agc_cut_off_current = 4000;
563
564 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
565 u32 ul_atv_if_agc_output_level = 0;
566 u32 ul_atv_if_agc_min_level = 0;
567 u32 ul_atv_if_agc_max_level = 0;
568 u32 ul_atv_if_agc_speed = 3;
569
570 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
571 u32 ul_atv_rf_agc_output_level = 0;
572 u32 ul_atv_rf_agc_min_level = 0;
573 u32 ul_atv_rf_agc_max_level = 0;
574 u32 ul_atv_rf_agc_top = 9500;
575 u32 ul_atv_rf_agc_cut_off_current = 4000;
576 u32 ul_atv_rf_agc_speed = 3;
577
578 u32 ulQual83 = DEFAULT_MER_83;
579 u32 ulQual93 = DEFAULT_MER_93;
580
581 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
582 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
583
584
585
586
587 u32 ul_gpio_cfg = 0x0113;
588 u32 ul_invert_ts_clock = 0;
589 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
590 u32 ul_dvbt_bitrate = 50000000;
591 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
592
593 u32 ul_insert_rs_byte = 0;
594
595 u32 ul_rf_mirror = 1;
596 u32 ul_power_down = 0;
597
598 dprintk(1, "\n");
599
600 state->m_has_lna = false;
601 state->m_has_dvbt = false;
602 state->m_has_dvbc = false;
603 state->m_has_atv = false;
604 state->m_has_oob = false;
605 state->m_has_audio = false;
606
607 if (!state->m_chunk_size)
608 state->m_chunk_size = 124;
609
610 state->m_osc_clock_freq = 0;
611 state->m_smart_ant_inverted = false;
612 state->m_b_p_down_open_bridge = false;
613
614
615 state->m_sys_clock_freq = 151875;
616
617
618 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
619 HI_I2C_DELAY) / 1000;
620
621 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
622 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
623 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
624
625 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
626
627 state->m_b_power_down = (ul_power_down != 0);
628
629 state->m_drxk_a3_patch_code = false;
630
631
632
633 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
634 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
635 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
636 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
637 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
638 state->m_vsb_pga_cfg = 140;
639
640
641 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
642 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
643 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
644 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
645 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
646 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
647 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
648 state->m_vsb_pre_saw_cfg.reference = 0x07;
649 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
650
651 state->m_Quality83percent = DEFAULT_MER_83;
652 state->m_Quality93percent = DEFAULT_MER_93;
653 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
654 state->m_Quality83percent = ulQual83;
655 state->m_Quality93percent = ulQual93;
656 }
657
658
659 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
660 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
661 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
662 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
663 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
664
665
666 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
667 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
668 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
669 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
670 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
671 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
672 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
673 state->m_atv_pre_saw_cfg.reference = 0x04;
674 state->m_atv_pre_saw_cfg.use_pre_saw = true;
675
676
677
678 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
679 state->m_dvbt_rf_agc_cfg.output_level = 0;
680 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
681 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
682 state->m_dvbt_rf_agc_cfg.top = 0x2100;
683 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
684 state->m_dvbt_rf_agc_cfg.speed = 1;
685
686
687
688 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
689 state->m_dvbt_if_agc_cfg.output_level = 0;
690 state->m_dvbt_if_agc_cfg.min_output_level = 0;
691 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
692 state->m_dvbt_if_agc_cfg.top = 13424;
693 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
694 state->m_dvbt_if_agc_cfg.speed = 3;
695 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
696 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
697
698
699 state->m_dvbt_pre_saw_cfg.reference = 4;
700 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
701
702
703 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
704 state->m_qam_rf_agc_cfg.output_level = 0;
705 state->m_qam_rf_agc_cfg.min_output_level = 6023;
706 state->m_qam_rf_agc_cfg.max_output_level = 27000;
707 state->m_qam_rf_agc_cfg.top = 0x2380;
708 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
709 state->m_qam_rf_agc_cfg.speed = 3;
710
711
712 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
713 state->m_qam_if_agc_cfg.output_level = 0;
714 state->m_qam_if_agc_cfg.min_output_level = 0;
715 state->m_qam_if_agc_cfg.max_output_level = 9000;
716 state->m_qam_if_agc_cfg.top = 0x0511;
717 state->m_qam_if_agc_cfg.cut_off_current = 0;
718 state->m_qam_if_agc_cfg.speed = 3;
719 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
720 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
721
722 state->m_qam_pga_cfg = 140;
723 state->m_qam_pre_saw_cfg.reference = 4;
724 state->m_qam_pre_saw_cfg.use_pre_saw = false;
725
726 state->m_operation_mode = OM_NONE;
727 state->m_drxk_state = DRXK_UNINITIALIZED;
728
729
730 state->m_enable_mpeg_output = true;
731 state->m_insert_rs_byte = false;
732 state->m_invert_data = false;
733 state->m_invert_err = false;
734 state->m_invert_str = false;
735 state->m_invert_val = false;
736 state->m_invert_clk = (ul_invert_ts_clock != 0);
737
738
739
740
741 state->m_dvbt_bitrate = ul_dvbt_bitrate;
742 state->m_dvbc_bitrate = ul_dvbc_bitrate;
743
744 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
745
746
747 state->m_mpeg_ts_static_bitrate = 19392658;
748 state->m_disable_te_ihandling = false;
749
750 if (ul_insert_rs_byte)
751 state->m_insert_rs_byte = true;
752
753 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
754 if (ul_mpeg_lock_time_out < 10000)
755 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
756 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
757 if (ul_demod_lock_time_out < 10000)
758 state->m_demod_lock_time_out = ul_demod_lock_time_out;
759
760
761 state->m_constellation = DRX_CONSTELLATION_AUTO;
762 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
763 state->m_fec_rs_plen = 204 * 8;
764 state->m_fec_rs_prescale = 1;
765
766 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
767 state->m_agcfast_clip_ctrl_delay = 0;
768
769 state->m_gpio_cfg = ul_gpio_cfg;
770
771 state->m_b_power_down = false;
772 state->m_current_power_mode = DRX_POWER_DOWN;
773
774 state->m_rfmirror = (ul_rf_mirror == 0);
775 state->m_if_agc_pol = false;
776 return 0;
777}
778
779static int drxx_open(struct drxk_state *state)
780{
781 int status = 0;
782 u32 jtag = 0;
783 u16 bid = 0;
784 u16 key = 0;
785
786 dprintk(1, "\n");
787
788 status = write16(state, SCU_RAM_GPIO__A,
789 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
790 if (status < 0)
791 goto error;
792
793 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
794 if (status < 0)
795 goto error;
796 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
797 if (status < 0)
798 goto error;
799 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
800 if (status < 0)
801 goto error;
802 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
803 if (status < 0)
804 goto error;
805 status = write16(state, SIO_TOP_COMM_KEY__A, key);
806error:
807 if (status < 0)
808 pr_err("Error %d on %s\n", status, __func__);
809 return status;
810}
811
812static int get_device_capabilities(struct drxk_state *state)
813{
814 u16 sio_pdr_ohw_cfg = 0;
815 u32 sio_top_jtagid_lo = 0;
816 int status;
817 const char *spin = "";
818
819 dprintk(1, "\n");
820
821
822
823 status = write16(state, SCU_RAM_GPIO__A,
824 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
825 if (status < 0)
826 goto error;
827 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
828 if (status < 0)
829 goto error;
830 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
831 if (status < 0)
832 goto error;
833 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
834 if (status < 0)
835 goto error;
836
837 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
838 case 0:
839
840 break;
841 case 1:
842
843 state->m_osc_clock_freq = 27000;
844 break;
845 case 2:
846
847 state->m_osc_clock_freq = 20250;
848 break;
849 case 3:
850
851 state->m_osc_clock_freq = 20250;
852 break;
853 default:
854 pr_err("Clock Frequency is unknown\n");
855 return -EINVAL;
856 }
857
858
859
860
861 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
862 if (status < 0)
863 goto error;
864
865 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
866
867
868 switch ((sio_top_jtagid_lo >> 29) & 0xF) {
869 case 0:
870 state->m_device_spin = DRXK_SPIN_A1;
871 spin = "A1";
872 break;
873 case 2:
874 state->m_device_spin = DRXK_SPIN_A2;
875 spin = "A2";
876 break;
877 case 3:
878 state->m_device_spin = DRXK_SPIN_A3;
879 spin = "A3";
880 break;
881 default:
882 state->m_device_spin = DRXK_SPIN_UNKNOWN;
883 status = -EINVAL;
884 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
885 goto error2;
886 }
887 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
888 case 0x13:
889
890 state->m_has_lna = false;
891 state->m_has_oob = false;
892 state->m_has_atv = false;
893 state->m_has_audio = false;
894 state->m_has_dvbt = true;
895 state->m_has_dvbc = true;
896 state->m_has_sawsw = true;
897 state->m_has_gpio2 = false;
898 state->m_has_gpio1 = false;
899 state->m_has_irqn = false;
900 break;
901 case 0x15:
902
903 state->m_has_lna = false;
904 state->m_has_oob = false;
905 state->m_has_atv = true;
906 state->m_has_audio = false;
907 state->m_has_dvbt = true;
908 state->m_has_dvbc = false;
909 state->m_has_sawsw = true;
910 state->m_has_gpio2 = true;
911 state->m_has_gpio1 = true;
912 state->m_has_irqn = false;
913 break;
914 case 0x16:
915
916 state->m_has_lna = false;
917 state->m_has_oob = false;
918 state->m_has_atv = true;
919 state->m_has_audio = false;
920 state->m_has_dvbt = true;
921 state->m_has_dvbc = false;
922 state->m_has_sawsw = true;
923 state->m_has_gpio2 = true;
924 state->m_has_gpio1 = true;
925 state->m_has_irqn = false;
926 break;
927 case 0x18:
928
929 state->m_has_lna = false;
930 state->m_has_oob = false;
931 state->m_has_atv = true;
932 state->m_has_audio = true;
933 state->m_has_dvbt = true;
934 state->m_has_dvbc = false;
935 state->m_has_sawsw = true;
936 state->m_has_gpio2 = true;
937 state->m_has_gpio1 = true;
938 state->m_has_irqn = false;
939 break;
940 case 0x21:
941
942 state->m_has_lna = false;
943 state->m_has_oob = false;
944 state->m_has_atv = true;
945 state->m_has_audio = true;
946 state->m_has_dvbt = true;
947 state->m_has_dvbc = true;
948 state->m_has_sawsw = true;
949 state->m_has_gpio2 = true;
950 state->m_has_gpio1 = true;
951 state->m_has_irqn = false;
952 break;
953 case 0x23:
954
955 state->m_has_lna = false;
956 state->m_has_oob = false;
957 state->m_has_atv = true;
958 state->m_has_audio = true;
959 state->m_has_dvbt = true;
960 state->m_has_dvbc = true;
961 state->m_has_sawsw = true;
962 state->m_has_gpio2 = true;
963 state->m_has_gpio1 = true;
964 state->m_has_irqn = false;
965 break;
966 case 0x25:
967
968 state->m_has_lna = false;
969 state->m_has_oob = false;
970 state->m_has_atv = true;
971 state->m_has_audio = true;
972 state->m_has_dvbt = true;
973 state->m_has_dvbc = true;
974 state->m_has_sawsw = true;
975 state->m_has_gpio2 = true;
976 state->m_has_gpio1 = true;
977 state->m_has_irqn = false;
978 break;
979 case 0x26:
980
981 state->m_has_lna = false;
982 state->m_has_oob = false;
983 state->m_has_atv = true;
984 state->m_has_audio = false;
985 state->m_has_dvbt = true;
986 state->m_has_dvbc = true;
987 state->m_has_sawsw = true;
988 state->m_has_gpio2 = true;
989 state->m_has_gpio1 = true;
990 state->m_has_irqn = false;
991 break;
992 default:
993 pr_err("DeviceID 0x%02x not supported\n",
994 ((sio_top_jtagid_lo >> 12) & 0xFF));
995 status = -EINVAL;
996 goto error2;
997 }
998
999 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1000 ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
1001 state->m_osc_clock_freq / 1000,
1002 state->m_osc_clock_freq % 1000);
1003
1004error:
1005 if (status < 0)
1006 pr_err("Error %d on %s\n", status, __func__);
1007
1008error2:
1009 return status;
1010}
1011
1012static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
1013{
1014 int status;
1015 bool powerdown_cmd;
1016
1017 dprintk(1, "\n");
1018
1019
1020 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1021 if (status < 0)
1022 goto error;
1023 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1024 usleep_range(1000, 2000);
1025
1026 powerdown_cmd =
1027 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1028 ((state->m_hi_cfg_ctrl) &
1029 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1030 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1031 if (powerdown_cmd == false) {
1032
1033 u32 retry_count = 0;
1034 u16 wait_cmd;
1035
1036 do {
1037 usleep_range(1000, 2000);
1038 retry_count += 1;
1039 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1040 &wait_cmd);
1041 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1042 && (wait_cmd != 0));
1043 if (status < 0)
1044 goto error;
1045 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1046 }
1047error:
1048 if (status < 0)
1049 pr_err("Error %d on %s\n", status, __func__);
1050
1051 return status;
1052}
1053
1054static int hi_cfg_command(struct drxk_state *state)
1055{
1056 int status;
1057
1058 dprintk(1, "\n");
1059
1060 mutex_lock(&state->mutex);
1061
1062 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1063 state->m_hi_cfg_timeout);
1064 if (status < 0)
1065 goto error;
1066 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1067 state->m_hi_cfg_ctrl);
1068 if (status < 0)
1069 goto error;
1070 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1071 state->m_hi_cfg_wake_up_key);
1072 if (status < 0)
1073 goto error;
1074 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1075 state->m_hi_cfg_bridge_delay);
1076 if (status < 0)
1077 goto error;
1078 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1079 state->m_hi_cfg_timing_div);
1080 if (status < 0)
1081 goto error;
1082 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1083 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1084 if (status < 0)
1085 goto error;
1086 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1087 if (status < 0)
1088 goto error;
1089
1090 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1091error:
1092 mutex_unlock(&state->mutex);
1093 if (status < 0)
1094 pr_err("Error %d on %s\n", status, __func__);
1095 return status;
1096}
1097
1098static int init_hi(struct drxk_state *state)
1099{
1100 dprintk(1, "\n");
1101
1102 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1103 state->m_hi_cfg_timeout = 0x96FF;
1104
1105 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1106
1107 return hi_cfg_command(state);
1108}
1109
1110static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1111{
1112 int status = -1;
1113 u16 sio_pdr_mclk_cfg = 0;
1114 u16 sio_pdr_mdx_cfg = 0;
1115 u16 err_cfg = 0;
1116
1117 dprintk(1, ": mpeg %s, %s mode\n",
1118 mpeg_enable ? "enable" : "disable",
1119 state->m_enable_parallel ? "parallel" : "serial");
1120
1121
1122 status = write16(state, SCU_RAM_GPIO__A,
1123 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1124 if (status < 0)
1125 goto error;
1126
1127
1128 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1129 if (status < 0)
1130 goto error;
1131
1132 if (mpeg_enable == false) {
1133
1134 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1135 if (status < 0)
1136 goto error;
1137 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1138 if (status < 0)
1139 goto error;
1140 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1141 if (status < 0)
1142 goto error;
1143 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1144 if (status < 0)
1145 goto error;
1146 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1147 if (status < 0)
1148 goto error;
1149 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1150 if (status < 0)
1151 goto error;
1152 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1153 if (status < 0)
1154 goto error;
1155 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1156 if (status < 0)
1157 goto error;
1158 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1159 if (status < 0)
1160 goto error;
1161 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1162 if (status < 0)
1163 goto error;
1164 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1165 if (status < 0)
1166 goto error;
1167 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1168 if (status < 0)
1169 goto error;
1170 } else {
1171
1172 sio_pdr_mdx_cfg =
1173 ((state->m_ts_data_strength <<
1174 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1175 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1176 SIO_PDR_MCLK_CFG_DRIVE__B) |
1177 0x0003);
1178
1179 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1180 if (status < 0)
1181 goto error;
1182
1183 if (state->enable_merr_cfg)
1184 err_cfg = sio_pdr_mdx_cfg;
1185
1186 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1187 if (status < 0)
1188 goto error;
1189 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1190 if (status < 0)
1191 goto error;
1192
1193 if (state->m_enable_parallel == true) {
1194
1195 status = write16(state, SIO_PDR_MD1_CFG__A,
1196 sio_pdr_mdx_cfg);
1197 if (status < 0)
1198 goto error;
1199 status = write16(state, SIO_PDR_MD2_CFG__A,
1200 sio_pdr_mdx_cfg);
1201 if (status < 0)
1202 goto error;
1203 status = write16(state, SIO_PDR_MD3_CFG__A,
1204 sio_pdr_mdx_cfg);
1205 if (status < 0)
1206 goto error;
1207 status = write16(state, SIO_PDR_MD4_CFG__A,
1208 sio_pdr_mdx_cfg);
1209 if (status < 0)
1210 goto error;
1211 status = write16(state, SIO_PDR_MD5_CFG__A,
1212 sio_pdr_mdx_cfg);
1213 if (status < 0)
1214 goto error;
1215 status = write16(state, SIO_PDR_MD6_CFG__A,
1216 sio_pdr_mdx_cfg);
1217 if (status < 0)
1218 goto error;
1219 status = write16(state, SIO_PDR_MD7_CFG__A,
1220 sio_pdr_mdx_cfg);
1221 if (status < 0)
1222 goto error;
1223 } else {
1224 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1225 SIO_PDR_MD0_CFG_DRIVE__B)
1226 | 0x0003);
1227
1228 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1229 if (status < 0)
1230 goto error;
1231 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1232 if (status < 0)
1233 goto error;
1234 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1235 if (status < 0)
1236 goto error;
1237 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1238 if (status < 0)
1239 goto error;
1240 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1241 if (status < 0)
1242 goto error;
1243 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1244 if (status < 0)
1245 goto error;
1246 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1247 if (status < 0)
1248 goto error;
1249 }
1250 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1251 if (status < 0)
1252 goto error;
1253 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1254 if (status < 0)
1255 goto error;
1256 }
1257
1258 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1259 if (status < 0)
1260 goto error;
1261
1262 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1263error:
1264 if (status < 0)
1265 pr_err("Error %d on %s\n", status, __func__);
1266 return status;
1267}
1268
1269static int mpegts_disable(struct drxk_state *state)
1270{
1271 dprintk(1, "\n");
1272
1273 return mpegts_configure_pins(state, false);
1274}
1275
1276static int bl_chain_cmd(struct drxk_state *state,
1277 u16 rom_offset, u16 nr_of_elements, u32 time_out)
1278{
1279 u16 bl_status = 0;
1280 int status;
1281 unsigned long end;
1282
1283 dprintk(1, "\n");
1284 mutex_lock(&state->mutex);
1285 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1286 if (status < 0)
1287 goto error;
1288 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1289 if (status < 0)
1290 goto error;
1291 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1292 if (status < 0)
1293 goto error;
1294 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1295 if (status < 0)
1296 goto error;
1297
1298 end = jiffies + msecs_to_jiffies(time_out);
1299 do {
1300 usleep_range(1000, 2000);
1301 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1302 if (status < 0)
1303 goto error;
1304 } while ((bl_status == 0x1) &&
1305 ((time_is_after_jiffies(end))));
1306
1307 if (bl_status == 0x1) {
1308 pr_err("SIO not ready\n");
1309 status = -EINVAL;
1310 goto error2;
1311 }
1312error:
1313 if (status < 0)
1314 pr_err("Error %d on %s\n", status, __func__);
1315error2:
1316 mutex_unlock(&state->mutex);
1317 return status;
1318}
1319
1320
1321static int download_microcode(struct drxk_state *state,
1322 const u8 p_mc_image[], u32 length)
1323{
1324 const u8 *p_src = p_mc_image;
1325 u32 address;
1326 u16 n_blocks;
1327 u16 block_size;
1328 u32 offset = 0;
1329 u32 i;
1330 int status = 0;
1331
1332 dprintk(1, "\n");
1333
1334
1335#if 0
1336
1337 drain = (p_src[0] << 8) | p_src[1];
1338#endif
1339 p_src += sizeof(u16);
1340 offset += sizeof(u16);
1341 n_blocks = (p_src[0] << 8) | p_src[1];
1342 p_src += sizeof(u16);
1343 offset += sizeof(u16);
1344
1345 for (i = 0; i < n_blocks; i += 1) {
1346 address = (p_src[0] << 24) | (p_src[1] << 16) |
1347 (p_src[2] << 8) | p_src[3];
1348 p_src += sizeof(u32);
1349 offset += sizeof(u32);
1350
1351 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1352 p_src += sizeof(u16);
1353 offset += sizeof(u16);
1354
1355#if 0
1356
1357 flags = (p_src[0] << 8) | p_src[1];
1358#endif
1359 p_src += sizeof(u16);
1360 offset += sizeof(u16);
1361
1362#if 0
1363
1364 block_crc = (p_src[0] << 8) | p_src[1];
1365#endif
1366 p_src += sizeof(u16);
1367 offset += sizeof(u16);
1368
1369 if (offset + block_size > length) {
1370 pr_err("Firmware is corrupted.\n");
1371 return -EINVAL;
1372 }
1373
1374 status = write_block(state, address, block_size, p_src);
1375 if (status < 0) {
1376 pr_err("Error %d while loading firmware\n", status);
1377 break;
1378 }
1379 p_src += block_size;
1380 offset += block_size;
1381 }
1382 return status;
1383}
1384
1385static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1386{
1387 int status;
1388 u16 data = 0;
1389 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1390 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1391 unsigned long end;
1392
1393 dprintk(1, "\n");
1394
1395 if (enable == false) {
1396 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1397 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1398 }
1399
1400 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1401 if (status >= 0 && data == desired_status) {
1402
1403 return status;
1404 }
1405
1406 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1407
1408 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1409 do {
1410 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1411 if ((status >= 0 && data == desired_status)
1412 || time_is_after_jiffies(end))
1413 break;
1414 usleep_range(1000, 2000);
1415 } while (1);
1416 if (data != desired_status) {
1417 pr_err("SIO not ready\n");
1418 return -EINVAL;
1419 }
1420 return status;
1421}
1422
1423static int mpegts_stop(struct drxk_state *state)
1424{
1425 int status = 0;
1426 u16 fec_oc_snc_mode = 0;
1427 u16 fec_oc_ipr_mode = 0;
1428
1429 dprintk(1, "\n");
1430
1431
1432 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1433 if (status < 0)
1434 goto error;
1435 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1436 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1437 if (status < 0)
1438 goto error;
1439
1440
1441 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1442 if (status < 0)
1443 goto error;
1444 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1445 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1446
1447error:
1448 if (status < 0)
1449 pr_err("Error %d on %s\n", status, __func__);
1450
1451 return status;
1452}
1453
1454static int scu_command(struct drxk_state *state,
1455 u16 cmd, u8 parameter_len,
1456 u16 *parameter, u8 result_len, u16 *result)
1457{
1458#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1459#error DRXK register mapping no longer compatible with this routine!
1460#endif
1461 u16 cur_cmd = 0;
1462 int status = -EINVAL;
1463 unsigned long end;
1464 u8 buffer[34];
1465 int cnt = 0, ii;
1466 const char *p;
1467 char errname[30];
1468
1469 dprintk(1, "\n");
1470
1471 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1472 ((result_len > 0) && (result == NULL))) {
1473 pr_err("Error %d on %s\n", status, __func__);
1474 return status;
1475 }
1476
1477 mutex_lock(&state->mutex);
1478
1479
1480
1481 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1482 buffer[cnt++] = (parameter[ii] & 0xFF);
1483 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1484 }
1485 buffer[cnt++] = (cmd & 0xFF);
1486 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1487
1488 write_block(state, SCU_RAM_PARAM_0__A -
1489 (parameter_len - 1), cnt, buffer);
1490
1491 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1492 do {
1493 usleep_range(1000, 2000);
1494 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1495 if (status < 0)
1496 goto error;
1497 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1498 if (cur_cmd != DRX_SCU_READY) {
1499 pr_err("SCU not ready\n");
1500 status = -EIO;
1501 goto error2;
1502 }
1503
1504 if ((result_len > 0) && (result != NULL)) {
1505 s16 err;
1506 int ii;
1507
1508 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1509 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1510 &result[ii]);
1511 if (status < 0)
1512 goto error;
1513 }
1514
1515
1516 err = (s16)result[0];
1517 if (err >= 0)
1518 goto error;
1519
1520
1521 switch (err) {
1522 case SCU_RESULT_UNKCMD:
1523 p = "SCU_RESULT_UNKCMD";
1524 break;
1525 case SCU_RESULT_UNKSTD:
1526 p = "SCU_RESULT_UNKSTD";
1527 break;
1528 case SCU_RESULT_SIZE:
1529 p = "SCU_RESULT_SIZE";
1530 break;
1531 case SCU_RESULT_INVPAR:
1532 p = "SCU_RESULT_INVPAR";
1533 break;
1534 default:
1535 sprintf(errname, "ERROR: %d\n", err);
1536 p = errname;
1537 }
1538 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1539 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1540 status = -EINVAL;
1541 goto error2;
1542 }
1543
1544error:
1545 if (status < 0)
1546 pr_err("Error %d on %s\n", status, __func__);
1547error2:
1548 mutex_unlock(&state->mutex);
1549 return status;
1550}
1551
1552static int set_iqm_af(struct drxk_state *state, bool active)
1553{
1554 u16 data = 0;
1555 int status;
1556
1557 dprintk(1, "\n");
1558
1559
1560 status = read16(state, IQM_AF_STDBY__A, &data);
1561 if (status < 0)
1562 goto error;
1563
1564 if (!active) {
1565 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1566 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1567 | IQM_AF_STDBY_STDBY_PD_STANDBY
1568 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1569 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1570 } else {
1571 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1572 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1573 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1574 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1575 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1576 );
1577 }
1578 status = write16(state, IQM_AF_STDBY__A, data);
1579
1580error:
1581 if (status < 0)
1582 pr_err("Error %d on %s\n", status, __func__);
1583 return status;
1584}
1585
1586static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1587{
1588 int status = 0;
1589 u16 sio_cc_pwd_mode = 0;
1590
1591 dprintk(1, "\n");
1592
1593
1594 if (mode == NULL)
1595 return -EINVAL;
1596
1597 switch (*mode) {
1598 case DRX_POWER_UP:
1599 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1600 break;
1601 case DRXK_POWER_DOWN_OFDM:
1602 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1603 break;
1604 case DRXK_POWER_DOWN_CORE:
1605 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1606 break;
1607 case DRXK_POWER_DOWN_PLL:
1608 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1609 break;
1610 case DRX_POWER_DOWN:
1611 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1612 break;
1613 default:
1614
1615 return -EINVAL;
1616 }
1617
1618
1619 if (state->m_current_power_mode == *mode)
1620 return 0;
1621
1622
1623 if (state->m_current_power_mode != DRX_POWER_UP) {
1624 status = power_up_device(state);
1625 if (status < 0)
1626 goto error;
1627 status = dvbt_enable_ofdm_token_ring(state, true);
1628 if (status < 0)
1629 goto error;
1630 }
1631
1632 if (*mode == DRX_POWER_UP) {
1633
1634 } else {
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644 switch (state->m_operation_mode) {
1645 case OM_DVBT:
1646 status = mpegts_stop(state);
1647 if (status < 0)
1648 goto error;
1649 status = power_down_dvbt(state, false);
1650 if (status < 0)
1651 goto error;
1652 break;
1653 case OM_QAM_ITU_A:
1654 case OM_QAM_ITU_C:
1655 status = mpegts_stop(state);
1656 if (status < 0)
1657 goto error;
1658 status = power_down_qam(state);
1659 if (status < 0)
1660 goto error;
1661 break;
1662 default:
1663 break;
1664 }
1665 status = dvbt_enable_ofdm_token_ring(state, false);
1666 if (status < 0)
1667 goto error;
1668 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1669 if (status < 0)
1670 goto error;
1671 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1672 if (status < 0)
1673 goto error;
1674
1675 if (*mode != DRXK_POWER_DOWN_OFDM) {
1676 state->m_hi_cfg_ctrl |=
1677 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1678 status = hi_cfg_command(state);
1679 if (status < 0)
1680 goto error;
1681 }
1682 }
1683 state->m_current_power_mode = *mode;
1684
1685error:
1686 if (status < 0)
1687 pr_err("Error %d on %s\n", status, __func__);
1688
1689 return status;
1690}
1691
1692static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1693{
1694 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1695 u16 cmd_result = 0;
1696 u16 data = 0;
1697 int status;
1698
1699 dprintk(1, "\n");
1700
1701 status = read16(state, SCU_COMM_EXEC__A, &data);
1702 if (status < 0)
1703 goto error;
1704 if (data == SCU_COMM_EXEC_ACTIVE) {
1705
1706 status = scu_command(state,
1707 SCU_RAM_COMMAND_STANDARD_OFDM
1708 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1709 0, NULL, 1, &cmd_result);
1710 if (status < 0)
1711 goto error;
1712
1713 status = scu_command(state,
1714 SCU_RAM_COMMAND_STANDARD_OFDM
1715 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1716 0, NULL, 1, &cmd_result);
1717 if (status < 0)
1718 goto error;
1719 }
1720
1721
1722 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1723 if (status < 0)
1724 goto error;
1725 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1726 if (status < 0)
1727 goto error;
1728 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1729 if (status < 0)
1730 goto error;
1731
1732
1733 status = set_iqm_af(state, false);
1734 if (status < 0)
1735 goto error;
1736
1737
1738 if (set_power_mode) {
1739 status = ctrl_power_mode(state, &power_mode);
1740 if (status < 0)
1741 goto error;
1742 }
1743error:
1744 if (status < 0)
1745 pr_err("Error %d on %s\n", status, __func__);
1746 return status;
1747}
1748
1749static int setoperation_mode(struct drxk_state *state,
1750 enum operation_mode o_mode)
1751{
1752 int status = 0;
1753
1754 dprintk(1, "\n");
1755
1756
1757
1758
1759
1760
1761
1762 status = write16(state, SCU_RAM_GPIO__A,
1763 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1764 if (status < 0)
1765 goto error;
1766
1767
1768 if (state->m_operation_mode == o_mode)
1769 return 0;
1770
1771 switch (state->m_operation_mode) {
1772
1773 case OM_NONE:
1774 break;
1775 case OM_DVBT:
1776 status = mpegts_stop(state);
1777 if (status < 0)
1778 goto error;
1779 status = power_down_dvbt(state, true);
1780 if (status < 0)
1781 goto error;
1782 state->m_operation_mode = OM_NONE;
1783 break;
1784 case OM_QAM_ITU_A:
1785 case OM_QAM_ITU_C:
1786 status = mpegts_stop(state);
1787 if (status < 0)
1788 goto error;
1789 status = power_down_qam(state);
1790 if (status < 0)
1791 goto error;
1792 state->m_operation_mode = OM_NONE;
1793 break;
1794 case OM_QAM_ITU_B:
1795 default:
1796 status = -EINVAL;
1797 goto error;
1798 }
1799
1800
1801
1802
1803 switch (o_mode) {
1804 case OM_DVBT:
1805 dprintk(1, ": DVB-T\n");
1806 state->m_operation_mode = o_mode;
1807 status = set_dvbt_standard(state, o_mode);
1808 if (status < 0)
1809 goto error;
1810 break;
1811 case OM_QAM_ITU_A:
1812 case OM_QAM_ITU_C:
1813 dprintk(1, ": DVB-C Annex %c\n",
1814 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1815 state->m_operation_mode = o_mode;
1816 status = set_qam_standard(state, o_mode);
1817 if (status < 0)
1818 goto error;
1819 break;
1820 case OM_QAM_ITU_B:
1821 default:
1822 status = -EINVAL;
1823 }
1824error:
1825 if (status < 0)
1826 pr_err("Error %d on %s\n", status, __func__);
1827 return status;
1828}
1829
1830static int start(struct drxk_state *state, s32 offset_freq,
1831 s32 intermediate_frequency)
1832{
1833 int status = -EINVAL;
1834
1835 u16 i_freqk_hz;
1836 s32 offsetk_hz = offset_freq / 1000;
1837
1838 dprintk(1, "\n");
1839 if (state->m_drxk_state != DRXK_STOPPED &&
1840 state->m_drxk_state != DRXK_DTV_STARTED)
1841 goto error;
1842
1843 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1844
1845 if (intermediate_frequency < 0) {
1846 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1847 intermediate_frequency = -intermediate_frequency;
1848 }
1849
1850 switch (state->m_operation_mode) {
1851 case OM_QAM_ITU_A:
1852 case OM_QAM_ITU_C:
1853 i_freqk_hz = (intermediate_frequency / 1000);
1854 status = set_qam(state, i_freqk_hz, offsetk_hz);
1855 if (status < 0)
1856 goto error;
1857 state->m_drxk_state = DRXK_DTV_STARTED;
1858 break;
1859 case OM_DVBT:
1860 i_freqk_hz = (intermediate_frequency / 1000);
1861 status = mpegts_stop(state);
1862 if (status < 0)
1863 goto error;
1864 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1865 if (status < 0)
1866 goto error;
1867 status = dvbt_start(state);
1868 if (status < 0)
1869 goto error;
1870 state->m_drxk_state = DRXK_DTV_STARTED;
1871 break;
1872 default:
1873 break;
1874 }
1875error:
1876 if (status < 0)
1877 pr_err("Error %d on %s\n", status, __func__);
1878 return status;
1879}
1880
1881static int shut_down(struct drxk_state *state)
1882{
1883 dprintk(1, "\n");
1884
1885 mpegts_stop(state);
1886 return 0;
1887}
1888
1889static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1890{
1891 int status = -EINVAL;
1892
1893 dprintk(1, "\n");
1894
1895 if (p_lock_status == NULL)
1896 goto error;
1897
1898 *p_lock_status = NOT_LOCKED;
1899
1900
1901 switch (state->m_operation_mode) {
1902 case OM_QAM_ITU_A:
1903 case OM_QAM_ITU_B:
1904 case OM_QAM_ITU_C:
1905 status = get_qam_lock_status(state, p_lock_status);
1906 break;
1907 case OM_DVBT:
1908 status = get_dvbt_lock_status(state, p_lock_status);
1909 break;
1910 default:
1911 break;
1912 }
1913error:
1914 if (status < 0)
1915 pr_err("Error %d on %s\n", status, __func__);
1916 return status;
1917}
1918
1919static int mpegts_start(struct drxk_state *state)
1920{
1921 int status;
1922
1923 u16 fec_oc_snc_mode = 0;
1924
1925
1926 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1927 if (status < 0)
1928 goto error;
1929 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1930 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1931 if (status < 0)
1932 goto error;
1933 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1934error:
1935 if (status < 0)
1936 pr_err("Error %d on %s\n", status, __func__);
1937 return status;
1938}
1939
1940static int mpegts_dto_init(struct drxk_state *state)
1941{
1942 int status;
1943
1944 dprintk(1, "\n");
1945
1946
1947 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1948 if (status < 0)
1949 goto error;
1950 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1951 if (status < 0)
1952 goto error;
1953 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1954 if (status < 0)
1955 goto error;
1956 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1957 if (status < 0)
1958 goto error;
1959 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1960 if (status < 0)
1961 goto error;
1962 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1963 if (status < 0)
1964 goto error;
1965 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1966 if (status < 0)
1967 goto error;
1968 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1969 if (status < 0)
1970 goto error;
1971
1972
1973 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1974 if (status < 0)
1975 goto error;
1976 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1977 if (status < 0)
1978 goto error;
1979 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1980error:
1981 if (status < 0)
1982 pr_err("Error %d on %s\n", status, __func__);
1983
1984 return status;
1985}
1986
1987static int mpegts_dto_setup(struct drxk_state *state,
1988 enum operation_mode o_mode)
1989{
1990 int status;
1991
1992 u16 fec_oc_reg_mode = 0;
1993 u16 fec_oc_reg_ipr_mode = 0;
1994 u16 fec_oc_dto_mode = 0;
1995 u16 fec_oc_fct_mode = 0;
1996 u16 fec_oc_dto_period = 2;
1997 u16 fec_oc_dto_burst_len = 188;
1998 u32 fec_oc_rcn_ctl_rate = 0;
1999 u16 fec_oc_tmd_mode = 0;
2000 u16 fec_oc_tmd_int_upd_rate = 0;
2001 u32 max_bit_rate = 0;
2002 bool static_clk = false;
2003
2004 dprintk(1, "\n");
2005
2006
2007 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
2008 if (status < 0)
2009 goto error;
2010 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
2011 if (status < 0)
2012 goto error;
2013 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2014 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2015 if (state->m_insert_rs_byte == true) {
2016
2017 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2018
2019 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2020
2021 fec_oc_dto_burst_len = 204;
2022 }
2023
2024
2025 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2026 if (state->m_enable_parallel == false) {
2027
2028 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2029 }
2030
2031 switch (o_mode) {
2032 case OM_DVBT:
2033 max_bit_rate = state->m_dvbt_bitrate;
2034 fec_oc_tmd_mode = 3;
2035 fec_oc_rcn_ctl_rate = 0xC00000;
2036 static_clk = state->m_dvbt_static_clk;
2037 break;
2038 case OM_QAM_ITU_A:
2039 case OM_QAM_ITU_C:
2040 fec_oc_tmd_mode = 0x0004;
2041 fec_oc_rcn_ctl_rate = 0xD2B4EE;
2042 max_bit_rate = state->m_dvbc_bitrate;
2043 static_clk = state->m_dvbc_static_clk;
2044 break;
2045 default:
2046 status = -EINVAL;
2047 }
2048 if (status < 0)
2049 goto error;
2050
2051
2052 if (static_clk) {
2053 u32 bit_rate = 0;
2054
2055
2056
2057
2058
2059 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2060 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2061 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2062 FEC_OC_FCT_MODE_VIRT_ENA__M);
2063
2064
2065 bit_rate = max_bit_rate;
2066 if (bit_rate > 75900000UL) {
2067 bit_rate = 75900000UL;
2068 }
2069
2070
2071
2072
2073
2074
2075 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2076 * 1000) / bit_rate);
2077 if (fec_oc_dto_period <= 2)
2078 fec_oc_dto_period = 0;
2079 else
2080 fec_oc_dto_period -= 2;
2081 fec_oc_tmd_int_upd_rate = 8;
2082 } else {
2083
2084 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2085 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2086 fec_oc_tmd_int_upd_rate = 5;
2087 }
2088
2089
2090 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2091 if (status < 0)
2092 goto error;
2093 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2094 if (status < 0)
2095 goto error;
2096 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2097 if (status < 0)
2098 goto error;
2099 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2100 if (status < 0)
2101 goto error;
2102 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2103 if (status < 0)
2104 goto error;
2105 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2106 if (status < 0)
2107 goto error;
2108
2109
2110 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2111 if (status < 0)
2112 goto error;
2113 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2114 fec_oc_tmd_int_upd_rate);
2115 if (status < 0)
2116 goto error;
2117 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2118error:
2119 if (status < 0)
2120 pr_err("Error %d on %s\n", status, __func__);
2121 return status;
2122}
2123
2124static int mpegts_configure_polarity(struct drxk_state *state)
2125{
2126 u16 fec_oc_reg_ipr_invert = 0;
2127
2128
2129 u16 invert_data_mask =
2130 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2131 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2132 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2133 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2134
2135 dprintk(1, "\n");
2136
2137
2138 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2139 if (state->m_invert_data == true)
2140 fec_oc_reg_ipr_invert |= invert_data_mask;
2141 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2142 if (state->m_invert_err == true)
2143 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2144 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2145 if (state->m_invert_str == true)
2146 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2147 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2148 if (state->m_invert_val == true)
2149 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2150 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2151 if (state->m_invert_clk == true)
2152 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2153
2154 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2155}
2156
2157#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2158
2159static int set_agc_rf(struct drxk_state *state,
2160 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2161{
2162 int status = -EINVAL;
2163 u16 data = 0;
2164 struct s_cfg_agc *p_if_agc_settings;
2165
2166 dprintk(1, "\n");
2167
2168 if (p_agc_cfg == NULL)
2169 goto error;
2170
2171 switch (p_agc_cfg->ctrl_mode) {
2172 case DRXK_AGC_CTRL_AUTO:
2173
2174 status = read16(state, IQM_AF_STDBY__A, &data);
2175 if (status < 0)
2176 goto error;
2177 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2178 status = write16(state, IQM_AF_STDBY__A, data);
2179 if (status < 0)
2180 goto error;
2181 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2182 if (status < 0)
2183 goto error;
2184
2185
2186 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2187
2188
2189 if (state->m_rf_agc_pol)
2190 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2191 else
2192 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2193 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2194 if (status < 0)
2195 goto error;
2196
2197
2198 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2199 if (status < 0)
2200 goto error;
2201
2202 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2203 data |= (~(p_agc_cfg->speed <<
2204 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2205 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2206
2207 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2208 if (status < 0)
2209 goto error;
2210
2211 if (is_dvbt(state))
2212 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2213 else if (is_qam(state))
2214 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2215 else
2216 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2217 if (p_if_agc_settings == NULL) {
2218 status = -EINVAL;
2219 goto error;
2220 }
2221
2222
2223 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO)
2224 status = write16(state,
2225 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2226 p_agc_cfg->top);
2227 if (status < 0)
2228 goto error;
2229
2230
2231 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2232 p_agc_cfg->cut_off_current);
2233 if (status < 0)
2234 goto error;
2235
2236
2237 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2238 p_agc_cfg->max_output_level);
2239 if (status < 0)
2240 goto error;
2241
2242 break;
2243
2244 case DRXK_AGC_CTRL_USER:
2245
2246 status = read16(state, IQM_AF_STDBY__A, &data);
2247 if (status < 0)
2248 goto error;
2249 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2250 status = write16(state, IQM_AF_STDBY__A, data);
2251 if (status < 0)
2252 goto error;
2253
2254
2255 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2256 if (status < 0)
2257 goto error;
2258 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2259 if (state->m_rf_agc_pol)
2260 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2261 else
2262 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2263 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2264 if (status < 0)
2265 goto error;
2266
2267
2268 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2269 if (status < 0)
2270 goto error;
2271
2272
2273 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2274 p_agc_cfg->output_level);
2275 if (status < 0)
2276 goto error;
2277 break;
2278
2279 case DRXK_AGC_CTRL_OFF:
2280
2281 status = read16(state, IQM_AF_STDBY__A, &data);
2282 if (status < 0)
2283 goto error;
2284 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2285 status = write16(state, IQM_AF_STDBY__A, data);
2286 if (status < 0)
2287 goto error;
2288
2289
2290 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2291 if (status < 0)
2292 goto error;
2293 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2294 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2295 if (status < 0)
2296 goto error;
2297 break;
2298
2299 default:
2300 status = -EINVAL;
2301
2302 }
2303error:
2304 if (status < 0)
2305 pr_err("Error %d on %s\n", status, __func__);
2306 return status;
2307}
2308
2309#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2310
2311static int set_agc_if(struct drxk_state *state,
2312 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2313{
2314 u16 data = 0;
2315 int status = 0;
2316 struct s_cfg_agc *p_rf_agc_settings;
2317
2318 dprintk(1, "\n");
2319
2320 switch (p_agc_cfg->ctrl_mode) {
2321 case DRXK_AGC_CTRL_AUTO:
2322
2323
2324 status = read16(state, IQM_AF_STDBY__A, &data);
2325 if (status < 0)
2326 goto error;
2327 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2328 status = write16(state, IQM_AF_STDBY__A, data);
2329 if (status < 0)
2330 goto error;
2331
2332 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2333 if (status < 0)
2334 goto error;
2335
2336
2337 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2338
2339
2340 if (state->m_if_agc_pol)
2341 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2342 else
2343 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2344 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2345 if (status < 0)
2346 goto error;
2347
2348
2349 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2350 if (status < 0)
2351 goto error;
2352 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2353 data |= (~(p_agc_cfg->speed <<
2354 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2355 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2356
2357 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2358 if (status < 0)
2359 goto error;
2360
2361 if (is_qam(state))
2362 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2363 else
2364 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2365 if (p_rf_agc_settings == NULL)
2366 return -1;
2367
2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2369 p_rf_agc_settings->top);
2370 if (status < 0)
2371 goto error;
2372 break;
2373
2374 case DRXK_AGC_CTRL_USER:
2375
2376
2377 status = read16(state, IQM_AF_STDBY__A, &data);
2378 if (status < 0)
2379 goto error;
2380 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2381 status = write16(state, IQM_AF_STDBY__A, data);
2382 if (status < 0)
2383 goto error;
2384
2385 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2386 if (status < 0)
2387 goto error;
2388
2389
2390 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2391
2392
2393 if (state->m_if_agc_pol)
2394 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2395 else
2396 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2397 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2398 if (status < 0)
2399 goto error;
2400
2401
2402 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2403 p_agc_cfg->output_level);
2404 if (status < 0)
2405 goto error;
2406 break;
2407
2408 case DRXK_AGC_CTRL_OFF:
2409
2410
2411 status = read16(state, IQM_AF_STDBY__A, &data);
2412 if (status < 0)
2413 goto error;
2414 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2415 status = write16(state, IQM_AF_STDBY__A, data);
2416 if (status < 0)
2417 goto error;
2418
2419
2420 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2421 if (status < 0)
2422 goto error;
2423 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2424 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2425 if (status < 0)
2426 goto error;
2427 break;
2428 }
2429
2430
2431
2432 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2433error:
2434 if (status < 0)
2435 pr_err("Error %d on %s\n", status, __func__);
2436 return status;
2437}
2438
2439static int get_qam_signal_to_noise(struct drxk_state *state,
2440 s32 *p_signal_to_noise)
2441{
2442 int status = 0;
2443 u16 qam_sl_err_power = 0;
2444
2445 u32 qam_sl_sig_power = 0;
2446
2447 u32 qam_sl_mer = 0;
2448
2449 dprintk(1, "\n");
2450
2451
2452
2453
2454 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2455 if (status < 0) {
2456 pr_err("Error %d on %s\n", status, __func__);
2457 return -EINVAL;
2458 }
2459
2460 switch (state->props.modulation) {
2461 case QAM_16:
2462 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2463 break;
2464 case QAM_32:
2465 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2466 break;
2467 case QAM_64:
2468 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2469 break;
2470 case QAM_128:
2471 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2472 break;
2473 default:
2474 case QAM_256:
2475 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2476 break;
2477 }
2478
2479 if (qam_sl_err_power > 0) {
2480 qam_sl_mer = log10times100(qam_sl_sig_power) -
2481 log10times100((u32) qam_sl_err_power);
2482 }
2483 *p_signal_to_noise = qam_sl_mer;
2484
2485 return status;
2486}
2487
2488static int get_dvbt_signal_to_noise(struct drxk_state *state,
2489 s32 *p_signal_to_noise)
2490{
2491 int status;
2492 u16 reg_data = 0;
2493 u32 eq_reg_td_sqr_err_i = 0;
2494 u32 eq_reg_td_sqr_err_q = 0;
2495 u16 eq_reg_td_sqr_err_exp = 0;
2496 u16 eq_reg_td_tps_pwr_ofs = 0;
2497 u16 eq_reg_td_req_smb_cnt = 0;
2498 u32 tps_cnt = 0;
2499 u32 sqr_err_iq = 0;
2500 u32 a = 0;
2501 u32 b = 0;
2502 u32 c = 0;
2503 u32 i_mer = 0;
2504 u16 transmission_params = 0;
2505
2506 dprintk(1, "\n");
2507
2508 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2509 &eq_reg_td_tps_pwr_ofs);
2510 if (status < 0)
2511 goto error;
2512 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2513 &eq_reg_td_req_smb_cnt);
2514 if (status < 0)
2515 goto error;
2516 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2517 &eq_reg_td_sqr_err_exp);
2518 if (status < 0)
2519 goto error;
2520 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2521 ®_data);
2522 if (status < 0)
2523 goto error;
2524
2525 eq_reg_td_sqr_err_i = (u32) reg_data;
2526 if ((eq_reg_td_sqr_err_exp > 11) &&
2527 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2528 eq_reg_td_sqr_err_i += 0x00010000UL;
2529 }
2530 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2531 if (status < 0)
2532 goto error;
2533
2534 eq_reg_td_sqr_err_q = (u32) reg_data;
2535 if ((eq_reg_td_sqr_err_exp > 11) &&
2536 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2537 eq_reg_td_sqr_err_q += 0x00010000UL;
2538
2539 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2540 &transmission_params);
2541 if (status < 0)
2542 goto error;
2543
2544
2545
2546
2547 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2548 i_mer = 0;
2549 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2550
2551
2552
2553 i_mer = 0;
2554 } else {
2555 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2556 eq_reg_td_sqr_err_exp;
2557 if ((transmission_params &
2558 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2559 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2560 tps_cnt = 17;
2561 else
2562 tps_cnt = 68;
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575 a = log10times100(eq_reg_td_tps_pwr_ofs *
2576 eq_reg_td_tps_pwr_ofs);
2577
2578 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2579
2580 c = log10times100(sqr_err_iq);
2581
2582 i_mer = a + b - c;
2583 }
2584 *p_signal_to_noise = i_mer;
2585
2586error:
2587 if (status < 0)
2588 pr_err("Error %d on %s\n", status, __func__);
2589 return status;
2590}
2591
2592static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2593{
2594 dprintk(1, "\n");
2595
2596 *p_signal_to_noise = 0;
2597 switch (state->m_operation_mode) {
2598 case OM_DVBT:
2599 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2600 case OM_QAM_ITU_A:
2601 case OM_QAM_ITU_C:
2602 return get_qam_signal_to_noise(state, p_signal_to_noise);
2603 default:
2604 break;
2605 }
2606 return 0;
2607}
2608
2609#if 0
2610static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2611{
2612
2613 int status = 0;
2614
2615 dprintk(1, "\n");
2616
2617 static s32 QE_SN[] = {
2618 51,
2619 69,
2620 79,
2621 89,
2622 97,
2623 108,
2624 131,
2625 146,
2626 156,
2627 160,
2628 165,
2629 187,
2630 202,
2631 216,
2632 225,
2633 };
2634
2635 *p_quality = 0;
2636
2637 do {
2638 s32 signal_to_noise = 0;
2639 u16 constellation = 0;
2640 u16 code_rate = 0;
2641 u32 signal_to_noise_rel;
2642 u32 ber_quality;
2643
2644 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2645 if (status < 0)
2646 break;
2647 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2648 &constellation);
2649 if (status < 0)
2650 break;
2651 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2652
2653 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2654 &code_rate);
2655 if (status < 0)
2656 break;
2657 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2658
2659 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2660 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2661 break;
2662 signal_to_noise_rel = signal_to_noise -
2663 QE_SN[constellation * 5 + code_rate];
2664 ber_quality = 100;
2665
2666 if (signal_to_noise_rel < -70)
2667 *p_quality = 0;
2668 else if (signal_to_noise_rel < 30)
2669 *p_quality = ((signal_to_noise_rel + 70) *
2670 ber_quality) / 100;
2671 else
2672 *p_quality = ber_quality;
2673 } while (0);
2674 return 0;
2675};
2676
2677static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2678{
2679 int status = 0;
2680 *p_quality = 0;
2681
2682 dprintk(1, "\n");
2683
2684 do {
2685 u32 signal_to_noise = 0;
2686 u32 ber_quality = 100;
2687 u32 signal_to_noise_rel = 0;
2688
2689 status = get_qam_signal_to_noise(state, &signal_to_noise);
2690 if (status < 0)
2691 break;
2692
2693 switch (state->props.modulation) {
2694 case QAM_16:
2695 signal_to_noise_rel = signal_to_noise - 200;
2696 break;
2697 case QAM_32:
2698 signal_to_noise_rel = signal_to_noise - 230;
2699 break;
2700 case QAM_64:
2701 signal_to_noise_rel = signal_to_noise - 260;
2702 break;
2703 case QAM_128:
2704 signal_to_noise_rel = signal_to_noise - 290;
2705 break;
2706 default:
2707 case QAM_256:
2708 signal_to_noise_rel = signal_to_noise - 320;
2709 break;
2710 }
2711
2712 if (signal_to_noise_rel < -70)
2713 *p_quality = 0;
2714 else if (signal_to_noise_rel < 30)
2715 *p_quality = ((signal_to_noise_rel + 70) *
2716 ber_quality) / 100;
2717 else
2718 *p_quality = ber_quality;
2719 } while (0);
2720
2721 return status;
2722}
2723
2724static int get_quality(struct drxk_state *state, s32 *p_quality)
2725{
2726 dprintk(1, "\n");
2727
2728 switch (state->m_operation_mode) {
2729 case OM_DVBT:
2730 return get_dvbt_quality(state, p_quality);
2731 case OM_QAM_ITU_A:
2732 return get_dvbc_quality(state, p_quality);
2733 default:
2734 break;
2735 }
2736
2737 return 0;
2738}
2739#endif
2740
2741
2742#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2743#define SIO_HI_RA_RAM_USR_END__A 0x420060
2744
2745#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2746#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2747#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2748#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2749
2750#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2751#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2752#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2753
2754static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2755{
2756 int status = -EINVAL;
2757
2758 dprintk(1, "\n");
2759
2760 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2761 return 0;
2762 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2763 goto error;
2764
2765 if (state->no_i2c_bridge)
2766 return 0;
2767
2768 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2769 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2770 if (status < 0)
2771 goto error;
2772 if (b_enable_bridge) {
2773 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2774 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2775 if (status < 0)
2776 goto error;
2777 } else {
2778 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2779 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2780 if (status < 0)
2781 goto error;
2782 }
2783
2784 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2785
2786error:
2787 if (status < 0)
2788 pr_err("Error %d on %s\n", status, __func__);
2789 return status;
2790}
2791
2792static int set_pre_saw(struct drxk_state *state,
2793 struct s_cfg_pre_saw *p_pre_saw_cfg)
2794{
2795 int status = -EINVAL;
2796
2797 dprintk(1, "\n");
2798
2799 if ((p_pre_saw_cfg == NULL)
2800 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2801 goto error;
2802
2803 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2804error:
2805 if (status < 0)
2806 pr_err("Error %d on %s\n", status, __func__);
2807 return status;
2808}
2809
2810static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2811 u16 rom_offset, u16 nr_of_elements, u32 time_out)
2812{
2813 u16 bl_status = 0;
2814 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2815 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2816 int status;
2817 unsigned long end;
2818
2819 dprintk(1, "\n");
2820
2821 mutex_lock(&state->mutex);
2822 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2823 if (status < 0)
2824 goto error;
2825 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2826 if (status < 0)
2827 goto error;
2828 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2829 if (status < 0)
2830 goto error;
2831 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2832 if (status < 0)
2833 goto error;
2834 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2835 if (status < 0)
2836 goto error;
2837 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2838 if (status < 0)
2839 goto error;
2840
2841 end = jiffies + msecs_to_jiffies(time_out);
2842 do {
2843 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2844 if (status < 0)
2845 goto error;
2846 } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2847 if (bl_status == 0x1) {
2848 pr_err("SIO not ready\n");
2849 status = -EINVAL;
2850 goto error2;
2851 }
2852error:
2853 if (status < 0)
2854 pr_err("Error %d on %s\n", status, __func__);
2855error2:
2856 mutex_unlock(&state->mutex);
2857 return status;
2858
2859}
2860
2861static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2862{
2863 u16 data = 0;
2864 int status;
2865
2866 dprintk(1, "\n");
2867
2868
2869 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2870 if (status < 0)
2871 goto error;
2872 status = write16(state, IQM_AF_START_LOCK__A, 1);
2873 if (status < 0)
2874 goto error;
2875
2876 *count = 0;
2877 status = read16(state, IQM_AF_PHASE0__A, &data);
2878 if (status < 0)
2879 goto error;
2880 if (data == 127)
2881 *count = *count + 1;
2882 status = read16(state, IQM_AF_PHASE1__A, &data);
2883 if (status < 0)
2884 goto error;
2885 if (data == 127)
2886 *count = *count + 1;
2887 status = read16(state, IQM_AF_PHASE2__A, &data);
2888 if (status < 0)
2889 goto error;
2890 if (data == 127)
2891 *count = *count + 1;
2892
2893error:
2894 if (status < 0)
2895 pr_err("Error %d on %s\n", status, __func__);
2896 return status;
2897}
2898
2899static int adc_synchronization(struct drxk_state *state)
2900{
2901 u16 count = 0;
2902 int status;
2903
2904 dprintk(1, "\n");
2905
2906 status = adc_sync_measurement(state, &count);
2907 if (status < 0)
2908 goto error;
2909
2910 if (count == 1) {
2911
2912 u16 clk_neg = 0;
2913
2914 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2915 if (status < 0)
2916 goto error;
2917 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2918 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2919 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2920 clk_neg |=
2921 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2922 } else {
2923 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2924 clk_neg |=
2925 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2926 }
2927 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2928 if (status < 0)
2929 goto error;
2930 status = adc_sync_measurement(state, &count);
2931 if (status < 0)
2932 goto error;
2933 }
2934
2935 if (count < 2)
2936 status = -EINVAL;
2937error:
2938 if (status < 0)
2939 pr_err("Error %d on %s\n", status, __func__);
2940 return status;
2941}
2942
2943static int set_frequency_shifter(struct drxk_state *state,
2944 u16 intermediate_freqk_hz,
2945 s32 tuner_freq_offset, bool is_dtv)
2946{
2947 bool select_pos_image = false;
2948 u32 rf_freq_residual = tuner_freq_offset;
2949 u32 fm_frequency_shift = 0;
2950 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2951 u32 adc_freq;
2952 bool adc_flip;
2953 int status;
2954 u32 if_freq_actual;
2955 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2956 u32 frequency_shift;
2957 bool image_to_select;
2958
2959 dprintk(1, "\n");
2960
2961
2962
2963
2964
2965 if (is_dtv) {
2966 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2967 (state->m_operation_mode == OM_QAM_ITU_C) ||
2968 (state->m_operation_mode == OM_DVBT))
2969 select_pos_image = true;
2970 else
2971 select_pos_image = false;
2972 }
2973 if (tuner_mirror)
2974
2975 if_freq_actual = intermediate_freqk_hz +
2976 rf_freq_residual + fm_frequency_shift;
2977 else
2978
2979 if_freq_actual = intermediate_freqk_hz -
2980 rf_freq_residual - fm_frequency_shift;
2981 if (if_freq_actual > sampling_frequency / 2) {
2982
2983 adc_freq = sampling_frequency - if_freq_actual;
2984 adc_flip = true;
2985 } else {
2986
2987 adc_freq = if_freq_actual;
2988 adc_flip = false;
2989 }
2990
2991 frequency_shift = adc_freq;
2992 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2993 adc_flip ^ select_pos_image;
2994 state->m_iqm_fs_rate_ofs =
2995 Frac28a((frequency_shift), sampling_frequency);
2996
2997 if (image_to_select)
2998 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2999
3000
3001
3002 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3003 state->m_iqm_fs_rate_ofs);
3004 if (status < 0)
3005 pr_err("Error %d on %s\n", status, __func__);
3006 return status;
3007}
3008
3009static int init_agc(struct drxk_state *state, bool is_dtv)
3010{
3011 u16 ingain_tgt = 0;
3012 u16 ingain_tgt_min = 0;
3013 u16 ingain_tgt_max = 0;
3014 u16 clp_cyclen = 0;
3015 u16 clp_sum_min = 0;
3016 u16 clp_dir_to = 0;
3017 u16 sns_sum_min = 0;
3018 u16 sns_sum_max = 0;
3019 u16 clp_sum_max = 0;
3020 u16 sns_dir_to = 0;
3021 u16 ki_innergain_min = 0;
3022 u16 if_iaccu_hi_tgt = 0;
3023 u16 if_iaccu_hi_tgt_min = 0;
3024 u16 if_iaccu_hi_tgt_max = 0;
3025 u16 data = 0;
3026 u16 fast_clp_ctrl_delay = 0;
3027 u16 clp_ctrl_mode = 0;
3028 int status = 0;
3029
3030 dprintk(1, "\n");
3031
3032
3033 sns_sum_max = 1023;
3034 if_iaccu_hi_tgt_min = 2047;
3035 clp_cyclen = 500;
3036 clp_sum_max = 1023;
3037
3038
3039 if (!is_qam(state)) {
3040 pr_err("%s: mode %d is not DVB-C\n",
3041 __func__, state->m_operation_mode);
3042 return -EINVAL;
3043 }
3044
3045
3046
3047
3048 clp_sum_min = 8;
3049 clp_dir_to = (u16) -9;
3050 clp_ctrl_mode = 0;
3051 sns_sum_min = 8;
3052 sns_dir_to = (u16) -9;
3053 ki_innergain_min = (u16) -1030;
3054 if_iaccu_hi_tgt_max = 0x2380;
3055 if_iaccu_hi_tgt = 0x2380;
3056 ingain_tgt_min = 0x0511;
3057 ingain_tgt = 0x0511;
3058 ingain_tgt_max = 5119;
3059 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3060
3061 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3062 fast_clp_ctrl_delay);
3063 if (status < 0)
3064 goto error;
3065
3066 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3067 if (status < 0)
3068 goto error;
3069 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3070 if (status < 0)
3071 goto error;
3072 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3073 if (status < 0)
3074 goto error;
3075 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3076 if (status < 0)
3077 goto error;
3078 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3079 if_iaccu_hi_tgt_min);
3080 if (status < 0)
3081 goto error;
3082 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3083 if_iaccu_hi_tgt_max);
3084 if (status < 0)
3085 goto error;
3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3087 if (status < 0)
3088 goto error;
3089 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3090 if (status < 0)
3091 goto error;
3092 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3093 if (status < 0)
3094 goto error;
3095 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3096 if (status < 0)
3097 goto error;
3098 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3099 if (status < 0)
3100 goto error;
3101 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3102 if (status < 0)
3103 goto error;
3104
3105 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3106 ki_innergain_min);
3107 if (status < 0)
3108 goto error;
3109 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3110 if_iaccu_hi_tgt);
3111 if (status < 0)
3112 goto error;
3113 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3114 if (status < 0)
3115 goto error;
3116
3117 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3118 if (status < 0)
3119 goto error;
3120 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3121 if (status < 0)
3122 goto error;
3123 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3124 if (status < 0)
3125 goto error;
3126
3127 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3128 if (status < 0)
3129 goto error;
3130 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3131 if (status < 0)
3132 goto error;
3133 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3134 if (status < 0)
3135 goto error;
3136 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3137 if (status < 0)
3138 goto error;
3139 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3140 if (status < 0)
3141 goto error;
3142 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3143 if (status < 0)
3144 goto error;
3145 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3146 if (status < 0)
3147 goto error;
3148 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3149 if (status < 0)
3150 goto error;
3151 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3152 if (status < 0)
3153 goto error;
3154 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3155 if (status < 0)
3156 goto error;
3157 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3158 if (status < 0)
3159 goto error;
3160 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3161 if (status < 0)
3162 goto error;
3163 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3164 if (status < 0)
3165 goto error;
3166 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3167 if (status < 0)
3168 goto error;
3169 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3170 if (status < 0)
3171 goto error;
3172 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3173 if (status < 0)
3174 goto error;
3175 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3176 if (status < 0)
3177 goto error;
3178 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3179 if (status < 0)
3180 goto error;
3181 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3182 if (status < 0)
3183 goto error;
3184
3185
3186 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3187 if (status < 0)
3188 goto error;
3189
3190 data = 0x0657;
3191 data &= ~SCU_RAM_AGC_KI_RF__M;
3192 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3193 data &= ~SCU_RAM_AGC_KI_IF__M;
3194 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3195
3196 status = write16(state, SCU_RAM_AGC_KI__A, data);
3197error:
3198 if (status < 0)
3199 pr_err("Error %d on %s\n", status, __func__);
3200 return status;
3201}
3202
3203static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3204{
3205 int status;
3206
3207 dprintk(1, "\n");
3208 if (packet_err == NULL)
3209 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3210 else
3211 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3212 packet_err);
3213 if (status < 0)
3214 pr_err("Error %d on %s\n", status, __func__);
3215 return status;
3216}
3217
3218static int dvbt_sc_command(struct drxk_state *state,
3219 u16 cmd, u16 subcmd,
3220 u16 param0, u16 param1, u16 param2,
3221 u16 param3, u16 param4)
3222{
3223 u16 cur_cmd = 0;
3224 u16 err_code = 0;
3225 u16 retry_cnt = 0;
3226 u16 sc_exec = 0;
3227 int status;
3228
3229 dprintk(1, "\n");
3230 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3231 if (sc_exec != 1) {
3232
3233 status = -EINVAL;
3234 }
3235 if (status < 0)
3236 goto error;
3237
3238
3239 retry_cnt = 0;
3240 do {
3241 usleep_range(1000, 2000);
3242 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3243 retry_cnt++;
3244 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3245 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3246 goto error;
3247
3248
3249 switch (cmd) {
3250
3251 case OFDM_SC_RA_RAM_CMD_PROC_START:
3252 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3253 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3254 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3255 if (status < 0)
3256 goto error;
3257 break;
3258 default:
3259
3260 break;
3261 }
3262
3263
3264 switch (cmd) {
3265
3266
3267
3268
3269 case OFDM_SC_RA_RAM_CMD_PROC_START:
3270 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3271 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3272 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3273
3274 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3275 case OFDM_SC_RA_RAM_CMD_USER_IO:
3276 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3277
3278 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3279 case OFDM_SC_RA_RAM_CMD_NULL:
3280
3281 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3282 break;
3283 default:
3284
3285 status = -EINVAL;
3286 }
3287 if (status < 0)
3288 goto error;
3289
3290
3291 retry_cnt = 0;
3292 do {
3293 usleep_range(1000, 2000);
3294 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3295 retry_cnt++;
3296 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3297 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3298 goto error;
3299
3300
3301 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3302 if (err_code == 0xFFFF) {
3303
3304 status = -EINVAL;
3305 }
3306 if (status < 0)
3307 goto error;
3308
3309
3310 switch (cmd) {
3311
3312
3313
3314
3315
3316 case OFDM_SC_RA_RAM_CMD_USER_IO:
3317 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3318 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3319
3320 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3321 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3322 case OFDM_SC_RA_RAM_CMD_PROC_START:
3323 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3324 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3325 case OFDM_SC_RA_RAM_CMD_NULL:
3326 break;
3327 default:
3328
3329 status = -EINVAL;
3330 break;
3331 }
3332error:
3333 if (status < 0)
3334 pr_err("Error %d on %s\n", status, __func__);
3335 return status;
3336}
3337
3338static int power_up_dvbt(struct drxk_state *state)
3339{
3340 enum drx_power_mode power_mode = DRX_POWER_UP;
3341 int status;
3342
3343 dprintk(1, "\n");
3344 status = ctrl_power_mode(state, &power_mode);
3345 if (status < 0)
3346 pr_err("Error %d on %s\n", status, __func__);
3347 return status;
3348}
3349
3350static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3351{
3352 int status;
3353
3354 dprintk(1, "\n");
3355 if (*enabled == true)
3356 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3357 else
3358 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3359 if (status < 0)
3360 pr_err("Error %d on %s\n", status, __func__);
3361 return status;
3362}
3363
3364#define DEFAULT_FR_THRES_8K 4000
3365static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3366{
3367
3368 int status;
3369
3370 dprintk(1, "\n");
3371 if (*enabled == true) {
3372
3373 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3374 DEFAULT_FR_THRES_8K);
3375 } else {
3376
3377 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3378 }
3379 if (status < 0)
3380 pr_err("Error %d on %s\n", status, __func__);
3381
3382 return status;
3383}
3384
3385static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3386 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3387{
3388 u16 data = 0;
3389 int status;
3390
3391 dprintk(1, "\n");
3392 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3393 if (status < 0)
3394 goto error;
3395
3396 switch (echo_thres->fft_mode) {
3397 case DRX_FFTMODE_2K:
3398 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3399 data |= ((echo_thres->threshold <<
3400 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3401 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3402 break;
3403 case DRX_FFTMODE_8K:
3404 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3405 data |= ((echo_thres->threshold <<
3406 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3407 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3408 break;
3409 default:
3410 return -EINVAL;
3411 }
3412
3413 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3414error:
3415 if (status < 0)
3416 pr_err("Error %d on %s\n", status, __func__);
3417 return status;
3418}
3419
3420static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3421 enum drxk_cfg_dvbt_sqi_speed *speed)
3422{
3423 int status = -EINVAL;
3424
3425 dprintk(1, "\n");
3426
3427 switch (*speed) {
3428 case DRXK_DVBT_SQI_SPEED_FAST:
3429 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3430 case DRXK_DVBT_SQI_SPEED_SLOW:
3431 break;
3432 default:
3433 goto error;
3434 }
3435 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3436 (u16) *speed);
3437error:
3438 if (status < 0)
3439 pr_err("Error %d on %s\n", status, __func__);
3440 return status;
3441}
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453static int dvbt_activate_presets(struct drxk_state *state)
3454{
3455 int status;
3456 bool setincenable = false;
3457 bool setfrenable = true;
3458
3459 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3460 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3461
3462 dprintk(1, "\n");
3463 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3464 if (status < 0)
3465 goto error;
3466 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3467 if (status < 0)
3468 goto error;
3469 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3470 if (status < 0)
3471 goto error;
3472 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3473 if (status < 0)
3474 goto error;
3475 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3476 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3477error:
3478 if (status < 0)
3479 pr_err("Error %d on %s\n", status, __func__);
3480 return status;
3481}
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493static int set_dvbt_standard(struct drxk_state *state,
3494 enum operation_mode o_mode)
3495{
3496 u16 cmd_result = 0;
3497 u16 data = 0;
3498 int status;
3499
3500 dprintk(1, "\n");
3501
3502 power_up_dvbt(state);
3503
3504 switch_antenna_to_dvbt(state);
3505
3506 status = scu_command(state,
3507 SCU_RAM_COMMAND_STANDARD_OFDM
3508 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3509 0, NULL, 1, &cmd_result);
3510 if (status < 0)
3511 goto error;
3512
3513
3514 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3515 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3516 0, NULL, 1, &cmd_result);
3517 if (status < 0)
3518 goto error;
3519
3520
3521 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3522 if (status < 0)
3523 goto error;
3524 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3525 if (status < 0)
3526 goto error;
3527 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3528 if (status < 0)
3529 goto error;
3530
3531
3532
3533 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3534 if (status < 0)
3535 goto error;
3536
3537 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3538 if (status < 0)
3539 goto error;
3540
3541 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3542 if (status < 0)
3543 goto error;
3544
3545 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3546 if (status < 0)
3547 goto error;
3548 status = set_iqm_af(state, true);
3549 if (status < 0)
3550 goto error;
3551
3552 status = write16(state, IQM_AF_AGC_RF__A, 0);
3553 if (status < 0)
3554 goto error;
3555
3556
3557 status = write16(state, IQM_AF_INC_LCT__A, 0);
3558 if (status < 0)
3559 goto error;
3560 status = write16(state, IQM_CF_DET_LCT__A, 0);
3561 if (status < 0)
3562 goto error;
3563 status = write16(state, IQM_CF_WND_LEN__A, 3);
3564 if (status < 0)
3565 goto error;
3566
3567 status = write16(state, IQM_RC_STRETCH__A, 16);
3568 if (status < 0)
3569 goto error;
3570 status = write16(state, IQM_CF_OUT_ENA__A, 0x4);
3571 if (status < 0)
3572 goto error;
3573 status = write16(state, IQM_CF_DS_ENA__A, 0x4);
3574 if (status < 0)
3575 goto error;
3576 status = write16(state, IQM_CF_SCALE__A, 1600);
3577 if (status < 0)
3578 goto error;
3579 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3580 if (status < 0)
3581 goto error;
3582
3583
3584 status = write16(state, IQM_AF_CLP_TH__A, 448);
3585 if (status < 0)
3586 goto error;
3587 status = write16(state, IQM_CF_DATATH__A, 495);
3588 if (status < 0)
3589 goto error;
3590
3591 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3592 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3593 if (status < 0)
3594 goto error;
3595
3596 status = write16(state, IQM_CF_PKDTH__A, 2);
3597 if (status < 0)
3598 goto error;
3599 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3600 if (status < 0)
3601 goto error;
3602
3603 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3604 if (status < 0)
3605 goto error;
3606 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3607 if (status < 0)
3608 goto error;
3609
3610
3611 status = adc_synchronization(state);
3612 if (status < 0)
3613 goto error;
3614 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3615 if (status < 0)
3616 goto error;
3617
3618
3619 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3620 if (status < 0)
3621 goto error;
3622
3623 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3624 if (status < 0)
3625 goto error;
3626 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3627 if (status < 0)
3628 goto error;
3629
3630
3631 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3632 if (status < 0)
3633 goto error;
3634 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3635 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3636 if (status < 0)
3637 goto error;
3638
3639
3640 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3641 if (status < 0)
3642 goto error;
3643
3644 if (!state->m_drxk_a3_rom_code) {
3645
3646 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3647 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3648 if (status < 0)
3649 goto error;
3650 }
3651
3652
3653#ifdef COMPILE_FOR_NONRT
3654 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3655 if (status < 0)
3656 goto error;
3657 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3658 if (status < 0)
3659 goto error;
3660#endif
3661
3662
3663 status = write16(state, FEC_DI_INPUT_CTL__A, 1);
3664 if (status < 0)
3665 goto error;
3666
3667
3668#ifdef COMPILE_FOR_NONRT
3669 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3670 if (status < 0)
3671 goto error;
3672#else
3673 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3674 if (status < 0)
3675 goto error;
3676#endif
3677 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3678 if (status < 0)
3679 goto error;
3680
3681
3682 status = mpegts_dto_setup(state, OM_DVBT);
3683 if (status < 0)
3684 goto error;
3685
3686 status = dvbt_activate_presets(state);
3687 if (status < 0)
3688 goto error;
3689
3690error:
3691 if (status < 0)
3692 pr_err("Error %d on %s\n", status, __func__);
3693 return status;
3694}
3695
3696
3697
3698
3699
3700
3701
3702static int dvbt_start(struct drxk_state *state)
3703{
3704 u16 param1;
3705 int status;
3706
3707
3708 dprintk(1, "\n");
3709
3710
3711 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3712 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3713 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3714 0, 0, 0);
3715 if (status < 0)
3716 goto error;
3717
3718 status = mpegts_start(state);
3719 if (status < 0)
3720 goto error;
3721 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3722 if (status < 0)
3723 goto error;
3724error:
3725 if (status < 0)
3726 pr_err("Error %d on %s\n", status, __func__);
3727 return status;
3728}
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3740 s32 tuner_freq_offset)
3741{
3742 u16 cmd_result = 0;
3743 u16 transmission_params = 0;
3744 u16 operation_mode = 0;
3745 u32 iqm_rc_rate_ofs = 0;
3746 u32 bandwidth = 0;
3747 u16 param1;
3748 int status;
3749
3750 dprintk(1, "IF =%d, TFO = %d\n",
3751 intermediate_freqk_hz, tuner_freq_offset);
3752
3753 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3754 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3755 0, NULL, 1, &cmd_result);
3756 if (status < 0)
3757 goto error;
3758
3759
3760 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3761 if (status < 0)
3762 goto error;
3763
3764
3765 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3766 if (status < 0)
3767 goto error;
3768 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3769 if (status < 0)
3770 goto error;
3771
3772
3773
3774 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3775 if (status < 0)
3776 goto error;
3777
3778
3779
3780
3781 switch (state->props.transmission_mode) {
3782 case TRANSMISSION_MODE_AUTO:
3783 default:
3784 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3785
3786 case TRANSMISSION_MODE_8K:
3787 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3788 break;
3789 case TRANSMISSION_MODE_2K:
3790 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3791 break;
3792 }
3793
3794
3795 switch (state->props.guard_interval) {
3796 default:
3797 case GUARD_INTERVAL_AUTO:
3798 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3799
3800 case GUARD_INTERVAL_1_4:
3801 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3802 break;
3803 case GUARD_INTERVAL_1_32:
3804 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3805 break;
3806 case GUARD_INTERVAL_1_16:
3807 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3808 break;
3809 case GUARD_INTERVAL_1_8:
3810 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3811 break;
3812 }
3813
3814
3815 switch (state->props.hierarchy) {
3816 case HIERARCHY_AUTO:
3817 case HIERARCHY_NONE:
3818 default:
3819 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3820
3821
3822
3823 case HIERARCHY_1:
3824 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3825 break;
3826 case HIERARCHY_2:
3827 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3828 break;
3829 case HIERARCHY_4:
3830 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3831 break;
3832 }
3833
3834
3835
3836 switch (state->props.modulation) {
3837 case QAM_AUTO:
3838 default:
3839 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3840
3841 case QAM_64:
3842 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3843 break;
3844 case QPSK:
3845 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3846 break;
3847 case QAM_16:
3848 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3849 break;
3850 }
3851#if 0
3852
3853
3854 switch (channel->priority) {
3855 case DRX_PRIORITY_LOW:
3856 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3857 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3858 OFDM_EC_SB_PRIOR_LO);
3859 break;
3860 case DRX_PRIORITY_HIGH:
3861 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3862 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3863 OFDM_EC_SB_PRIOR_HI));
3864 break;
3865 case DRX_PRIORITY_UNKNOWN:
3866 default:
3867 status = -EINVAL;
3868 goto error;
3869 }
3870#else
3871
3872 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3873 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3874 if (status < 0)
3875 goto error;
3876#endif
3877
3878
3879 switch (state->props.code_rate_HP) {
3880 case FEC_AUTO:
3881 default:
3882 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3883
3884 case FEC_2_3:
3885 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3886 break;
3887 case FEC_1_2:
3888 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3889 break;
3890 case FEC_3_4:
3891 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3892 break;
3893 case FEC_5_6:
3894 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3895 break;
3896 case FEC_7_8:
3897 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3898 break;
3899 }
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914 switch (state->props.bandwidth_hz) {
3915 case 0:
3916 state->props.bandwidth_hz = 8000000;
3917
3918 case 8000000:
3919 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3920 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3921 3052);
3922 if (status < 0)
3923 goto error;
3924
3925 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3926 7);
3927 if (status < 0)
3928 goto error;
3929 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3930 7);
3931 if (status < 0)
3932 goto error;
3933 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3934 7);
3935 if (status < 0)
3936 goto error;
3937 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3938 1);
3939 if (status < 0)
3940 goto error;
3941 break;
3942 case 7000000:
3943 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3944 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3945 3491);
3946 if (status < 0)
3947 goto error;
3948
3949 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3950 8);
3951 if (status < 0)
3952 goto error;
3953 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3954 8);
3955 if (status < 0)
3956 goto error;
3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3958 4);
3959 if (status < 0)
3960 goto error;
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3962 1);
3963 if (status < 0)
3964 goto error;
3965 break;
3966 case 6000000:
3967 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3968 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3969 4073);
3970 if (status < 0)
3971 goto error;
3972
3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3974 19);
3975 if (status < 0)
3976 goto error;
3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3978 19);
3979 if (status < 0)
3980 goto error;
3981 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3982 14);
3983 if (status < 0)
3984 goto error;
3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3986 1);
3987 if (status < 0)
3988 goto error;
3989 break;
3990 default:
3991 status = -EINVAL;
3992 goto error;
3993 }
3994
3995 if (iqm_rc_rate_ofs == 0) {
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008 iqm_rc_rate_ofs = Frac28a((u32)
4009 ((state->m_sys_clock_freq *
4010 1000) / 3), bandwidth);
4011
4012 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
4013 iqm_rc_rate_ofs += 0x80L;
4014 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
4015
4016 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
4017 }
4018
4019 iqm_rc_rate_ofs &=
4020 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4021 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4022 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4023 if (status < 0)
4024 goto error;
4025
4026
4027
4028#if 0
4029 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4030 if (status < 0)
4031 goto error;
4032#endif
4033 status = set_frequency_shifter(state, intermediate_freqk_hz,
4034 tuner_freq_offset, true);
4035 if (status < 0)
4036 goto error;
4037
4038
4039
4040
4041 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4042 if (status < 0)
4043 goto error;
4044
4045
4046 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4047 if (status < 0)
4048 goto error;
4049 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4050 if (status < 0)
4051 goto error;
4052
4053
4054 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4055 | SCU_RAM_COMMAND_CMD_DEMOD_START,
4056 0, NULL, 1, &cmd_result);
4057 if (status < 0)
4058 goto error;
4059
4060
4061 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4062 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4063 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4064 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4065 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4066 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4067 0, transmission_params, param1, 0, 0, 0);
4068 if (status < 0)
4069 goto error;
4070
4071 if (!state->m_drxk_a3_rom_code)
4072 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4073error:
4074 if (status < 0)
4075 pr_err("Error %d on %s\n", status, __func__);
4076
4077 return status;
4078}
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4091{
4092 int status;
4093 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4094 OFDM_SC_RA_RAM_LOCK_FEC__M);
4095 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4096 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4097
4098 u16 sc_ra_ram_lock = 0;
4099 u16 sc_comm_exec = 0;
4100
4101 dprintk(1, "\n");
4102
4103 *p_lock_status = NOT_LOCKED;
4104
4105
4106 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4107 if (status < 0)
4108 goto end;
4109 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4110 goto end;
4111
4112 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4113 if (status < 0)
4114 goto end;
4115
4116 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4117 *p_lock_status = MPEG_LOCK;
4118 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4119 *p_lock_status = FEC_LOCK;
4120 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4121 *p_lock_status = DEMOD_LOCK;
4122 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4123 *p_lock_status = NEVER_LOCK;
4124end:
4125 if (status < 0)
4126 pr_err("Error %d on %s\n", status, __func__);
4127
4128 return status;
4129}
4130
4131static int power_up_qam(struct drxk_state *state)
4132{
4133 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4134 int status;
4135
4136 dprintk(1, "\n");
4137 status = ctrl_power_mode(state, &power_mode);
4138 if (status < 0)
4139 pr_err("Error %d on %s\n", status, __func__);
4140
4141 return status;
4142}
4143
4144
4145
4146static int power_down_qam(struct drxk_state *state)
4147{
4148 u16 data = 0;
4149 u16 cmd_result;
4150 int status = 0;
4151
4152 dprintk(1, "\n");
4153 status = read16(state, SCU_COMM_EXEC__A, &data);
4154 if (status < 0)
4155 goto error;
4156 if (data == SCU_COMM_EXEC_ACTIVE) {
4157
4158
4159
4160
4161
4162 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4163 if (status < 0)
4164 goto error;
4165 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4166 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4167 0, NULL, 1, &cmd_result);
4168 if (status < 0)
4169 goto error;
4170 }
4171
4172 status = set_iqm_af(state, false);
4173
4174error:
4175 if (status < 0)
4176 pr_err("Error %d on %s\n", status, __func__);
4177
4178 return status;
4179}
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194static int set_qam_measurement(struct drxk_state *state,
4195 enum e_drxk_constellation modulation,
4196 u32 symbol_rate)
4197{
4198 u32 fec_bits_desired = 0;
4199 u32 fec_rs_period_total = 0;
4200 u16 fec_rs_prescale = 0;
4201 u16 fec_rs_period = 0;
4202 int status = 0;
4203
4204 dprintk(1, "\n");
4205
4206 fec_rs_prescale = 1;
4207
4208
4209
4210
4211
4212
4213 switch (modulation) {
4214 case DRX_CONSTELLATION_QAM16:
4215 fec_bits_desired = 4 * symbol_rate;
4216 break;
4217 case DRX_CONSTELLATION_QAM32:
4218 fec_bits_desired = 5 * symbol_rate;
4219 break;
4220 case DRX_CONSTELLATION_QAM64:
4221 fec_bits_desired = 6 * symbol_rate;
4222 break;
4223 case DRX_CONSTELLATION_QAM128:
4224 fec_bits_desired = 7 * symbol_rate;
4225 break;
4226 case DRX_CONSTELLATION_QAM256:
4227 fec_bits_desired = 8 * symbol_rate;
4228 break;
4229 default:
4230 status = -EINVAL;
4231 }
4232 if (status < 0)
4233 goto error;
4234
4235 fec_bits_desired /= 1000;
4236 fec_bits_desired *= 500;
4237
4238
4239
4240 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;
4241
4242
4243 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4244 if (fec_rs_prescale == 0) {
4245
4246 status = -EINVAL;
4247 if (status < 0)
4248 goto error;
4249 }
4250 fec_rs_period =
4251 ((u16) fec_rs_period_total +
4252 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4253
4254
4255 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4256 if (status < 0)
4257 goto error;
4258 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4259 fec_rs_prescale);
4260 if (status < 0)
4261 goto error;
4262 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4263error:
4264 if (status < 0)
4265 pr_err("Error %d on %s\n", status, __func__);
4266 return status;
4267}
4268
4269static int set_qam16(struct drxk_state *state)
4270{
4271 int status = 0;
4272
4273 dprintk(1, "\n");
4274
4275
4276 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4277 if (status < 0)
4278 goto error;
4279 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4280 if (status < 0)
4281 goto error;
4282 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4283 if (status < 0)
4284 goto error;
4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4286 if (status < 0)
4287 goto error;
4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4289 if (status < 0)
4290 goto error;
4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4292 if (status < 0)
4293 goto error;
4294
4295 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4296 if (status < 0)
4297 goto error;
4298 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4299 if (status < 0)
4300 goto error;
4301 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4302 if (status < 0)
4303 goto error;
4304 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4305 if (status < 0)
4306 goto error;
4307 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4308 if (status < 0)
4309 goto error;
4310 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4311 if (status < 0)
4312 goto error;
4313
4314 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4315 if (status < 0)
4316 goto error;
4317 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4318 if (status < 0)
4319 goto error;
4320 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4321 if (status < 0)
4322 goto error;
4323
4324
4325 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4326 DRXK_QAM_SL_SIG_POWER_QAM16);
4327 if (status < 0)
4328 goto error;
4329
4330
4331 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4332 if (status < 0)
4333 goto error;
4334 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4335 if (status < 0)
4336 goto error;
4337 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4338 if (status < 0)
4339 goto error;
4340 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4341 if (status < 0)
4342 goto error;
4343 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4344 if (status < 0)
4345 goto error;
4346 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4347 if (status < 0)
4348 goto error;
4349 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4350 if (status < 0)
4351 goto error;
4352 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4353 if (status < 0)
4354 goto error;
4355
4356 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4357 if (status < 0)
4358 goto error;
4359 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4360 if (status < 0)
4361 goto error;
4362 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4363 if (status < 0)
4364 goto error;
4365 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4366 if (status < 0)
4367 goto error;
4368 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4369 if (status < 0)
4370 goto error;
4371 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4372 if (status < 0)
4373 goto error;
4374 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4375 if (status < 0)
4376 goto error;
4377 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4378 if (status < 0)
4379 goto error;
4380 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4381 if (status < 0)
4382 goto error;
4383 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4384 if (status < 0)
4385 goto error;
4386 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4387 if (status < 0)
4388 goto error;
4389 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4390 if (status < 0)
4391 goto error;
4392
4393
4394
4395
4396 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4397 if (status < 0)
4398 goto error;
4399 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4400 if (status < 0)
4401 goto error;
4402 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4403 if (status < 0)
4404 goto error;
4405 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4406 if (status < 0)
4407 goto error;
4408 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4409 if (status < 0)
4410 goto error;
4411 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4412 if (status < 0)
4413 goto error;
4414
4415 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4416 if (status < 0)
4417 goto error;
4418 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4419 if (status < 0)
4420 goto error;
4421 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4422 if (status < 0)
4423 goto error;
4424
4425
4426
4427
4428 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4429 if (status < 0)
4430 goto error;
4431 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4432 if (status < 0)
4433 goto error;
4434 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4435 if (status < 0)
4436 goto error;
4437 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4438 if (status < 0)
4439 goto error;
4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4441 if (status < 0)
4442 goto error;
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4444 if (status < 0)
4445 goto error;
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4447 if (status < 0)
4448 goto error;
4449
4450error:
4451 if (status < 0)
4452 pr_err("Error %d on %s\n", status, __func__);
4453 return status;
4454}
4455
4456
4457
4458
4459
4460
4461
4462
4463static int set_qam32(struct drxk_state *state)
4464{
4465 int status = 0;
4466
4467 dprintk(1, "\n");
4468
4469
4470
4471 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4472 if (status < 0)
4473 goto error;
4474 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4475 if (status < 0)
4476 goto error;
4477 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4478 if (status < 0)
4479 goto error;
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4481 if (status < 0)
4482 goto error;
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4484 if (status < 0)
4485 goto error;
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4487 if (status < 0)
4488 goto error;
4489
4490
4491 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4492 if (status < 0)
4493 goto error;
4494 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4495 if (status < 0)
4496 goto error;
4497 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4498 if (status < 0)
4499 goto error;
4500 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4501 if (status < 0)
4502 goto error;
4503 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4504 if (status < 0)
4505 goto error;
4506 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4507 if (status < 0)
4508 goto error;
4509
4510 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4511 if (status < 0)
4512 goto error;
4513 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4514 if (status < 0)
4515 goto error;
4516 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4517 if (status < 0)
4518 goto error;
4519
4520
4521
4522 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4523 DRXK_QAM_SL_SIG_POWER_QAM32);
4524 if (status < 0)
4525 goto error;
4526
4527
4528
4529
4530 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4531 if (status < 0)
4532 goto error;
4533 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4534 if (status < 0)
4535 goto error;
4536 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4537 if (status < 0)
4538 goto error;
4539 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4540 if (status < 0)
4541 goto error;
4542 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4543 if (status < 0)
4544 goto error;
4545 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4546 if (status < 0)
4547 goto error;
4548 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4549 if (status < 0)
4550 goto error;
4551 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4552 if (status < 0)
4553 goto error;
4554
4555 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4556 if (status < 0)
4557 goto error;
4558 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4559 if (status < 0)
4560 goto error;
4561 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4562 if (status < 0)
4563 goto error;
4564 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4565 if (status < 0)
4566 goto error;
4567 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4568 if (status < 0)
4569 goto error;
4570 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4571 if (status < 0)
4572 goto error;
4573 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4574 if (status < 0)
4575 goto error;
4576 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4577 if (status < 0)
4578 goto error;
4579 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4580 if (status < 0)
4581 goto error;
4582 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4583 if (status < 0)
4584 goto error;
4585 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4586 if (status < 0)
4587 goto error;
4588 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4589 if (status < 0)
4590 goto error;
4591
4592
4593
4594
4595 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4596 if (status < 0)
4597 goto error;
4598 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4599 if (status < 0)
4600 goto error;
4601 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4602 if (status < 0)
4603 goto error;
4604 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4605 if (status < 0)
4606 goto error;
4607 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4608 if (status < 0)
4609 goto error;
4610 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4611 if (status < 0)
4612 goto error;
4613
4614 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4615 if (status < 0)
4616 goto error;
4617 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4618 if (status < 0)
4619 goto error;
4620 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4621 if (status < 0)
4622 goto error;
4623
4624
4625
4626
4627 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4628 if (status < 0)
4629 goto error;
4630 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4631 if (status < 0)
4632 goto error;
4633 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4634 if (status < 0)
4635 goto error;
4636 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4637 if (status < 0)
4638 goto error;
4639 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4640 if (status < 0)
4641 goto error;
4642 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4643 if (status < 0)
4644 goto error;
4645 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4646error:
4647 if (status < 0)
4648 pr_err("Error %d on %s\n", status, __func__);
4649 return status;
4650}
4651
4652
4653
4654
4655
4656
4657
4658
4659static int set_qam64(struct drxk_state *state)
4660{
4661 int status = 0;
4662
4663 dprintk(1, "\n");
4664
4665
4666 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4667 if (status < 0)
4668 goto error;
4669 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4670 if (status < 0)
4671 goto error;
4672 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4673 if (status < 0)
4674 goto error;
4675 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4676 if (status < 0)
4677 goto error;
4678 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4679 if (status < 0)
4680 goto error;
4681 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4682 if (status < 0)
4683 goto error;
4684
4685
4686 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4687 if (status < 0)
4688 goto error;
4689 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4690 if (status < 0)
4691 goto error;
4692 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4693 if (status < 0)
4694 goto error;
4695 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4696 if (status < 0)
4697 goto error;
4698 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4699 if (status < 0)
4700 goto error;
4701 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4702 if (status < 0)
4703 goto error;
4704
4705 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4706 if (status < 0)
4707 goto error;
4708 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4709 if (status < 0)
4710 goto error;
4711 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4712 if (status < 0)
4713 goto error;
4714
4715
4716 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4717 DRXK_QAM_SL_SIG_POWER_QAM64);
4718 if (status < 0)
4719 goto error;
4720
4721
4722
4723
4724 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4725 if (status < 0)
4726 goto error;
4727 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4728 if (status < 0)
4729 goto error;
4730 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4731 if (status < 0)
4732 goto error;
4733 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4734 if (status < 0)
4735 goto error;
4736 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4737 if (status < 0)
4738 goto error;
4739 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4740 if (status < 0)
4741 goto error;
4742 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4743 if (status < 0)
4744 goto error;
4745 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4746 if (status < 0)
4747 goto error;
4748
4749 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4750 if (status < 0)
4751 goto error;
4752 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4753 if (status < 0)
4754 goto error;
4755 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4756 if (status < 0)
4757 goto error;
4758 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4759 if (status < 0)
4760 goto error;
4761 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4762 if (status < 0)
4763 goto error;
4764 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4765 if (status < 0)
4766 goto error;
4767 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4768 if (status < 0)
4769 goto error;
4770 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4771 if (status < 0)
4772 goto error;
4773 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4774 if (status < 0)
4775 goto error;
4776 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4777 if (status < 0)
4778 goto error;
4779 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4780 if (status < 0)
4781 goto error;
4782 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4783 if (status < 0)
4784 goto error;
4785
4786
4787
4788
4789 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4790 if (status < 0)
4791 goto error;
4792 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4793 if (status < 0)
4794 goto error;
4795 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4796 if (status < 0)
4797 goto error;
4798 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4799 if (status < 0)
4800 goto error;
4801 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4802 if (status < 0)
4803 goto error;
4804 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4805 if (status < 0)
4806 goto error;
4807
4808 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4809 if (status < 0)
4810 goto error;
4811 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4812 if (status < 0)
4813 goto error;
4814 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4815 if (status < 0)
4816 goto error;
4817
4818
4819
4820
4821 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4822 if (status < 0)
4823 goto error;
4824 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4825 if (status < 0)
4826 goto error;
4827 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4828 if (status < 0)
4829 goto error;
4830 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4831 if (status < 0)
4832 goto error;
4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4834 if (status < 0)
4835 goto error;
4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4837 if (status < 0)
4838 goto error;
4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4840error:
4841 if (status < 0)
4842 pr_err("Error %d on %s\n", status, __func__);
4843
4844 return status;
4845}
4846
4847
4848
4849
4850
4851
4852
4853
4854static int set_qam128(struct drxk_state *state)
4855{
4856 int status = 0;
4857
4858 dprintk(1, "\n");
4859
4860
4861 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4862 if (status < 0)
4863 goto error;
4864 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4865 if (status < 0)
4866 goto error;
4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4868 if (status < 0)
4869 goto error;
4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4871 if (status < 0)
4872 goto error;
4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4874 if (status < 0)
4875 goto error;
4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4877 if (status < 0)
4878 goto error;
4879
4880
4881 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4882 if (status < 0)
4883 goto error;
4884 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4885 if (status < 0)
4886 goto error;
4887 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4888 if (status < 0)
4889 goto error;
4890 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4891 if (status < 0)
4892 goto error;
4893 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4894 if (status < 0)
4895 goto error;
4896 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4897 if (status < 0)
4898 goto error;
4899
4900 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4901 if (status < 0)
4902 goto error;
4903 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4904 if (status < 0)
4905 goto error;
4906 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4907 if (status < 0)
4908 goto error;
4909
4910
4911
4912
4913 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4914 DRXK_QAM_SL_SIG_POWER_QAM128);
4915 if (status < 0)
4916 goto error;
4917
4918
4919
4920
4921 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4922 if (status < 0)
4923 goto error;
4924 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4925 if (status < 0)
4926 goto error;
4927 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4928 if (status < 0)
4929 goto error;
4930 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4931 if (status < 0)
4932 goto error;
4933 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4934 if (status < 0)
4935 goto error;
4936 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4937 if (status < 0)
4938 goto error;
4939 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4940 if (status < 0)
4941 goto error;
4942 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4943 if (status < 0)
4944 goto error;
4945
4946 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4947 if (status < 0)
4948 goto error;
4949 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4950 if (status < 0)
4951 goto error;
4952 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4953 if (status < 0)
4954 goto error;
4955 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4956 if (status < 0)
4957 goto error;
4958 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4959 if (status < 0)
4960 goto error;
4961 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4962 if (status < 0)
4963 goto error;
4964 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4965 if (status < 0)
4966 goto error;
4967 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4968 if (status < 0)
4969 goto error;
4970 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4971 if (status < 0)
4972 goto error;
4973 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4974 if (status < 0)
4975 goto error;
4976 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4977 if (status < 0)
4978 goto error;
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4980 if (status < 0)
4981 goto error;
4982
4983
4984
4985
4986 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4987 if (status < 0)
4988 goto error;
4989 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4990 if (status < 0)
4991 goto error;
4992 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4993 if (status < 0)
4994 goto error;
4995 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4996 if (status < 0)
4997 goto error;
4998 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4999 if (status < 0)
5000 goto error;
5001 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5002 if (status < 0)
5003 goto error;
5004
5005 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5006 if (status < 0)
5007 goto error;
5008 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5009 if (status < 0)
5010 goto error;
5011
5012 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5013 if (status < 0)
5014 goto error;
5015
5016
5017
5018 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5019 if (status < 0)
5020 goto error;
5021 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5022 if (status < 0)
5023 goto error;
5024 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5025 if (status < 0)
5026 goto error;
5027 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5028 if (status < 0)
5029 goto error;
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5031 if (status < 0)
5032 goto error;
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5034 if (status < 0)
5035 goto error;
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5037error:
5038 if (status < 0)
5039 pr_err("Error %d on %s\n", status, __func__);
5040
5041 return status;
5042}
5043
5044
5045
5046
5047
5048
5049
5050
5051static int set_qam256(struct drxk_state *state)
5052{
5053 int status = 0;
5054
5055 dprintk(1, "\n");
5056
5057
5058 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5059 if (status < 0)
5060 goto error;
5061 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5062 if (status < 0)
5063 goto error;
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5065 if (status < 0)
5066 goto error;
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5068 if (status < 0)
5069 goto error;
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5071 if (status < 0)
5072 goto error;
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5074 if (status < 0)
5075 goto error;
5076
5077
5078 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5079 if (status < 0)
5080 goto error;
5081 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5082 if (status < 0)
5083 goto error;
5084 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5085 if (status < 0)
5086 goto error;
5087 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5088 if (status < 0)
5089 goto error;
5090 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5091 if (status < 0)
5092 goto error;
5093 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5094 if (status < 0)
5095 goto error;
5096
5097 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5098 if (status < 0)
5099 goto error;
5100 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5101 if (status < 0)
5102 goto error;
5103 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5104 if (status < 0)
5105 goto error;
5106
5107
5108
5109 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5110 DRXK_QAM_SL_SIG_POWER_QAM256);
5111 if (status < 0)
5112 goto error;
5113
5114
5115
5116
5117 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5118 if (status < 0)
5119 goto error;
5120 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5121 if (status < 0)
5122 goto error;
5123 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5124 if (status < 0)
5125 goto error;
5126 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5127 if (status < 0)
5128 goto error;
5129 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5130 if (status < 0)
5131 goto error;
5132 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5133 if (status < 0)
5134 goto error;
5135 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5136 if (status < 0)
5137 goto error;
5138 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5139 if (status < 0)
5140 goto error;
5141
5142 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5143 if (status < 0)
5144 goto error;
5145 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5146 if (status < 0)
5147 goto error;
5148 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5149 if (status < 0)
5150 goto error;
5151 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5152 if (status < 0)
5153 goto error;
5154 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5155 if (status < 0)
5156 goto error;
5157 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5158 if (status < 0)
5159 goto error;
5160 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5161 if (status < 0)
5162 goto error;
5163 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5164 if (status < 0)
5165 goto error;
5166 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5167 if (status < 0)
5168 goto error;
5169 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5170 if (status < 0)
5171 goto error;
5172 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5173 if (status < 0)
5174 goto error;
5175 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5176 if (status < 0)
5177 goto error;
5178
5179
5180
5181
5182 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5183 if (status < 0)
5184 goto error;
5185 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5186 if (status < 0)
5187 goto error;
5188 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5189 if (status < 0)
5190 goto error;
5191 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5192 if (status < 0)
5193 goto error;
5194 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5195 if (status < 0)
5196 goto error;
5197 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5198 if (status < 0)
5199 goto error;
5200
5201 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5202 if (status < 0)
5203 goto error;
5204 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5205 if (status < 0)
5206 goto error;
5207 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5208 if (status < 0)
5209 goto error;
5210
5211
5212
5213
5214 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5215 if (status < 0)
5216 goto error;
5217 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5218 if (status < 0)
5219 goto error;
5220 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5221 if (status < 0)
5222 goto error;
5223 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5224 if (status < 0)
5225 goto error;
5226 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5227 if (status < 0)
5228 goto error;
5229 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5230 if (status < 0)
5231 goto error;
5232 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5233error:
5234 if (status < 0)
5235 pr_err("Error %d on %s\n", status, __func__);
5236 return status;
5237}
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247static int qam_reset_qam(struct drxk_state *state)
5248{
5249 int status;
5250 u16 cmd_result;
5251
5252 dprintk(1, "\n");
5253
5254 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5255 if (status < 0)
5256 goto error;
5257
5258 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5259 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5260 0, NULL, 1, &cmd_result);
5261error:
5262 if (status < 0)
5263 pr_err("Error %d on %s\n", status, __func__);
5264 return status;
5265}
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275static int qam_set_symbolrate(struct drxk_state *state)
5276{
5277 u32 adc_frequency = 0;
5278 u32 symb_freq = 0;
5279 u32 iqm_rc_rate = 0;
5280 u16 ratesel = 0;
5281 u32 lc_symb_rate = 0;
5282 int status;
5283
5284 dprintk(1, "\n");
5285
5286 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5287 ratesel = 0;
5288
5289 if (state->props.symbol_rate <= 1188750)
5290 ratesel = 3;
5291 else if (state->props.symbol_rate <= 2377500)
5292 ratesel = 2;
5293 else if (state->props.symbol_rate <= 4755000)
5294 ratesel = 1;
5295 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5296 if (status < 0)
5297 goto error;
5298
5299
5300
5301
5302 symb_freq = state->props.symbol_rate * (1 << ratesel);
5303 if (symb_freq == 0) {
5304
5305 status = -EINVAL;
5306 goto error;
5307 }
5308 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5309 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5310 (1 << 23);
5311 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5312 if (status < 0)
5313 goto error;
5314 state->m_iqm_rc_rate = iqm_rc_rate;
5315
5316
5317
5318 symb_freq = state->props.symbol_rate;
5319 if (adc_frequency == 0) {
5320
5321 status = -EINVAL;
5322 goto error;
5323 }
5324 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5325 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5326 16);
5327 if (lc_symb_rate > 511)
5328 lc_symb_rate = 511;
5329 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5330
5331error:
5332 if (status < 0)
5333 pr_err("Error %d on %s\n", status, __func__);
5334 return status;
5335}
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5347{
5348 int status;
5349 u16 result[2] = { 0, 0 };
5350
5351 dprintk(1, "\n");
5352 *p_lock_status = NOT_LOCKED;
5353 status = scu_command(state,
5354 SCU_RAM_COMMAND_STANDARD_QAM |
5355 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5356 result);
5357 if (status < 0)
5358 pr_err("Error %d on %s\n", status, __func__);
5359
5360 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5361
5362 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5363
5364 *p_lock_status = DEMOD_LOCK;
5365 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5366
5367 *p_lock_status = MPEG_LOCK;
5368 } else {
5369
5370
5371
5372
5373
5374
5375 *p_lock_status = NEVER_LOCK;
5376 }
5377 return status;
5378}
5379
5380#define QAM_MIRROR__M 0x03
5381#define QAM_MIRROR_NORMAL 0x00
5382#define QAM_MIRRORED 0x01
5383#define QAM_MIRROR_AUTO_ON 0x02
5384#define QAM_LOCKRANGE__M 0x10
5385#define QAM_LOCKRANGE_NORMAL 0x10
5386
5387static int qam_demodulator_command(struct drxk_state *state,
5388 int number_of_parameters)
5389{
5390 int status;
5391 u16 cmd_result;
5392 u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5393
5394 set_param_parameters[0] = state->m_constellation;
5395 set_param_parameters[1] = DRXK_QAM_I12_J17;
5396
5397 if (number_of_parameters == 2) {
5398 u16 set_env_parameters[1] = { 0 };
5399
5400 if (state->m_operation_mode == OM_QAM_ITU_C)
5401 set_env_parameters[0] = QAM_TOP_ANNEX_C;
5402 else
5403 set_env_parameters[0] = QAM_TOP_ANNEX_A;
5404
5405 status = scu_command(state,
5406 SCU_RAM_COMMAND_STANDARD_QAM
5407 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5408 1, set_env_parameters, 1, &cmd_result);
5409 if (status < 0)
5410 goto error;
5411
5412 status = scu_command(state,
5413 SCU_RAM_COMMAND_STANDARD_QAM
5414 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5415 number_of_parameters, set_param_parameters,
5416 1, &cmd_result);
5417 } else if (number_of_parameters == 4) {
5418 if (state->m_operation_mode == OM_QAM_ITU_C)
5419 set_param_parameters[2] = QAM_TOP_ANNEX_C;
5420 else
5421 set_param_parameters[2] = QAM_TOP_ANNEX_A;
5422
5423 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5424
5425
5426
5427
5428 status = scu_command(state,
5429 SCU_RAM_COMMAND_STANDARD_QAM
5430 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5431 number_of_parameters, set_param_parameters,
5432 1, &cmd_result);
5433 } else {
5434 pr_warn("Unknown QAM demodulator parameter count %d\n",
5435 number_of_parameters);
5436 status = -EINVAL;
5437 }
5438
5439error:
5440 if (status < 0)
5441 pr_warn("Warning %d on %s\n", status, __func__);
5442 return status;
5443}
5444
5445static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5446 s32 tuner_freq_offset)
5447{
5448 int status;
5449 u16 cmd_result;
5450 int qam_demod_param_count = state->qam_demod_parameter_count;
5451
5452 dprintk(1, "\n");
5453
5454
5455
5456
5457
5458
5459 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5460 if (status < 0)
5461 goto error;
5462 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5463 if (status < 0)
5464 goto error;
5465 status = qam_reset_qam(state);
5466 if (status < 0)
5467 goto error;
5468
5469
5470
5471
5472
5473
5474 status = qam_set_symbolrate(state);
5475 if (status < 0)
5476 goto error;
5477
5478
5479 switch (state->props.modulation) {
5480 case QAM_256:
5481 state->m_constellation = DRX_CONSTELLATION_QAM256;
5482 break;
5483 case QAM_AUTO:
5484 case QAM_64:
5485 state->m_constellation = DRX_CONSTELLATION_QAM64;
5486 break;
5487 case QAM_16:
5488 state->m_constellation = DRX_CONSTELLATION_QAM16;
5489 break;
5490 case QAM_32:
5491 state->m_constellation = DRX_CONSTELLATION_QAM32;
5492 break;
5493 case QAM_128:
5494 state->m_constellation = DRX_CONSTELLATION_QAM128;
5495 break;
5496 default:
5497 status = -EINVAL;
5498 break;
5499 }
5500 if (status < 0)
5501 goto error;
5502
5503
5504
5505 if (state->qam_demod_parameter_count == 4
5506 || !state->qam_demod_parameter_count) {
5507 qam_demod_param_count = 4;
5508 status = qam_demodulator_command(state, qam_demod_param_count);
5509 }
5510
5511
5512
5513
5514 if (state->qam_demod_parameter_count == 2
5515 || (!state->qam_demod_parameter_count && status < 0)) {
5516 qam_demod_param_count = 2;
5517 status = qam_demodulator_command(state, qam_demod_param_count);
5518 }
5519
5520 if (status < 0) {
5521 dprintk(1, "Could not set demodulator parameters.\n");
5522 dprintk(1,
5523 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5524 state->qam_demod_parameter_count,
5525 state->microcode_name);
5526 goto error;
5527 } else if (!state->qam_demod_parameter_count) {
5528 dprintk(1,
5529 "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5530 qam_demod_param_count);
5531
5532
5533
5534
5535
5536 state->qam_demod_parameter_count = qam_demod_param_count;
5537 }
5538
5539
5540
5541
5542
5543#if 0
5544 status = set_frequency(channel, tuner_freq_offset));
5545 if (status < 0)
5546 goto error;
5547#endif
5548 status = set_frequency_shifter(state, intermediate_freqk_hz,
5549 tuner_freq_offset, true);
5550 if (status < 0)
5551 goto error;
5552
5553
5554 status = set_qam_measurement(state, state->m_constellation,
5555 state->props.symbol_rate);
5556 if (status < 0)
5557 goto error;
5558
5559
5560 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5561 if (status < 0)
5562 goto error;
5563 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5564 if (status < 0)
5565 goto error;
5566
5567
5568 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5569 if (status < 0)
5570 goto error;
5571 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5572 if (status < 0)
5573 goto error;
5574 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5575 if (status < 0)
5576 goto error;
5577 status = write16(state, QAM_LC_MODE__A, 7);
5578 if (status < 0)
5579 goto error;
5580
5581 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5582 if (status < 0)
5583 goto error;
5584 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5585 if (status < 0)
5586 goto error;
5587 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5588 if (status < 0)
5589 goto error;
5590 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5591 if (status < 0)
5592 goto error;
5593 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5594 if (status < 0)
5595 goto error;
5596 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5597 if (status < 0)
5598 goto error;
5599 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5600 if (status < 0)
5601 goto error;
5602 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5603 if (status < 0)
5604 goto error;
5605 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5606 if (status < 0)
5607 goto error;
5608 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5609 if (status < 0)
5610 goto error;
5611 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5612 if (status < 0)
5613 goto error;
5614 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5615 if (status < 0)
5616 goto error;
5617 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5618 if (status < 0)
5619 goto error;
5620 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5621 if (status < 0)
5622 goto error;
5623 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5624 if (status < 0)
5625 goto error;
5626
5627
5628 status = write16(state, QAM_SY_SP_INV__A,
5629 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5630 if (status < 0)
5631 goto error;
5632
5633
5634 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5635 if (status < 0)
5636 goto error;
5637
5638
5639 switch (state->props.modulation) {
5640 case QAM_16:
5641 status = set_qam16(state);
5642 break;
5643 case QAM_32:
5644 status = set_qam32(state);
5645 break;
5646 case QAM_AUTO:
5647 case QAM_64:
5648 status = set_qam64(state);
5649 break;
5650 case QAM_128:
5651 status = set_qam128(state);
5652 break;
5653 case QAM_256:
5654 status = set_qam256(state);
5655 break;
5656 default:
5657 status = -EINVAL;
5658 break;
5659 }
5660 if (status < 0)
5661 goto error;
5662
5663
5664 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5665 if (status < 0)
5666 goto error;
5667
5668
5669
5670
5671 status = mpegts_dto_setup(state, state->m_operation_mode);
5672 if (status < 0)
5673 goto error;
5674
5675
5676 status = mpegts_start(state);
5677 if (status < 0)
5678 goto error;
5679 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5680 if (status < 0)
5681 goto error;
5682 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5683 if (status < 0)
5684 goto error;
5685 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5686 if (status < 0)
5687 goto error;
5688
5689
5690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5691 | SCU_RAM_COMMAND_CMD_DEMOD_START,
5692 0, NULL, 1, &cmd_result);
5693 if (status < 0)
5694 goto error;
5695
5696
5697
5698
5699error:
5700 if (status < 0)
5701 pr_err("Error %d on %s\n", status, __func__);
5702 return status;
5703}
5704
5705static int set_qam_standard(struct drxk_state *state,
5706 enum operation_mode o_mode)
5707{
5708 int status;
5709#ifdef DRXK_QAM_TAPS
5710#define DRXK_QAMA_TAPS_SELECT
5711#include "drxk_filters.h"
5712#undef DRXK_QAMA_TAPS_SELECT
5713#endif
5714
5715 dprintk(1, "\n");
5716
5717
5718 switch_antenna_to_qam(state);
5719
5720
5721 status = power_up_qam(state);
5722 if (status < 0)
5723 goto error;
5724
5725 status = qam_reset_qam(state);
5726 if (status < 0)
5727 goto error;
5728
5729
5730
5731 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5732 if (status < 0)
5733 goto error;
5734 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5735 if (status < 0)
5736 goto error;
5737
5738
5739
5740 switch (o_mode) {
5741 case OM_QAM_ITU_A:
5742 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5743 DRXK_BLCC_NR_ELEMENTS_TAPS,
5744 DRXK_BLC_TIMEOUT);
5745 break;
5746 case OM_QAM_ITU_C:
5747 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5748 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5749 DRXK_BLDC_NR_ELEMENTS_TAPS,
5750 DRXK_BLC_TIMEOUT);
5751 if (status < 0)
5752 goto error;
5753 status = bl_direct_cmd(state,
5754 IQM_CF_TAP_IM0__A,
5755 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5756 DRXK_BLDC_NR_ELEMENTS_TAPS,
5757 DRXK_BLC_TIMEOUT);
5758 break;
5759 default:
5760 status = -EINVAL;
5761 }
5762 if (status < 0)
5763 goto error;
5764
5765 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5766 if (status < 0)
5767 goto error;
5768 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5769 if (status < 0)
5770 goto error;
5771 status = write16(state, IQM_CF_MIDTAP__A,
5772 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5773 if (status < 0)
5774 goto error;
5775
5776 status = write16(state, IQM_RC_STRETCH__A, 21);
5777 if (status < 0)
5778 goto error;
5779 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5780 if (status < 0)
5781 goto error;
5782 status = write16(state, IQM_AF_CLP_TH__A, 448);
5783 if (status < 0)
5784 goto error;
5785 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5786 if (status < 0)
5787 goto error;
5788 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5789 if (status < 0)
5790 goto error;
5791
5792 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5793 if (status < 0)
5794 goto error;
5795 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5796 if (status < 0)
5797 goto error;
5798 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5799 if (status < 0)
5800 goto error;
5801 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5802 if (status < 0)
5803 goto error;
5804
5805
5806 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5807 if (status < 0)
5808 goto error;
5809 status = write16(state, IQM_CF_DATATH__A, 1000);
5810 if (status < 0)
5811 goto error;
5812 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5813 if (status < 0)
5814 goto error;
5815 status = write16(state, IQM_CF_DET_LCT__A, 0);
5816 if (status < 0)
5817 goto error;
5818 status = write16(state, IQM_CF_WND_LEN__A, 1);
5819 if (status < 0)
5820 goto error;
5821 status = write16(state, IQM_CF_PKDTH__A, 1);
5822 if (status < 0)
5823 goto error;
5824 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5825 if (status < 0)
5826 goto error;
5827
5828
5829 status = set_iqm_af(state, true);
5830 if (status < 0)
5831 goto error;
5832 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5833 if (status < 0)
5834 goto error;
5835
5836
5837 status = adc_synchronization(state);
5838 if (status < 0)
5839 goto error;
5840
5841
5842 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5843 if (status < 0)
5844 goto error;
5845
5846
5847 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5848 if (status < 0)
5849 goto error;
5850
5851
5852
5853
5854 status = init_agc(state, true);
5855 if (status < 0)
5856 goto error;
5857 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5858 if (status < 0)
5859 goto error;
5860
5861
5862 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5863 if (status < 0)
5864 goto error;
5865 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5866 if (status < 0)
5867 goto error;
5868
5869
5870 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5871error:
5872 if (status < 0)
5873 pr_err("Error %d on %s\n", status, __func__);
5874 return status;
5875}
5876
5877static int write_gpio(struct drxk_state *state)
5878{
5879 int status;
5880 u16 value = 0;
5881
5882 dprintk(1, "\n");
5883
5884 status = write16(state, SCU_RAM_GPIO__A,
5885 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5886 if (status < 0)
5887 goto error;
5888
5889
5890 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5891 if (status < 0)
5892 goto error;
5893
5894 if (state->m_has_sawsw) {
5895 if (state->uio_mask & 0x0001) {
5896
5897 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5898 state->m_gpio_cfg);
5899 if (status < 0)
5900 goto error;
5901
5902
5903 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5904 if (status < 0)
5905 goto error;
5906 if ((state->m_gpio & 0x0001) == 0)
5907 value &= 0x7FFF;
5908 else
5909 value |= 0x8000;
5910
5911 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5912 if (status < 0)
5913 goto error;
5914 }
5915 if (state->uio_mask & 0x0002) {
5916
5917 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5918 state->m_gpio_cfg);
5919 if (status < 0)
5920 goto error;
5921
5922
5923 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5924 if (status < 0)
5925 goto error;
5926 if ((state->m_gpio & 0x0002) == 0)
5927 value &= 0xBFFF;
5928 else
5929 value |= 0x4000;
5930
5931 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5932 if (status < 0)
5933 goto error;
5934 }
5935 if (state->uio_mask & 0x0004) {
5936
5937 status = write16(state, SIO_PDR_GPIO_CFG__A,
5938 state->m_gpio_cfg);
5939 if (status < 0)
5940 goto error;
5941
5942
5943 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5944 if (status < 0)
5945 goto error;
5946 if ((state->m_gpio & 0x0004) == 0)
5947 value &= 0xFFFB;
5948 else
5949 value |= 0x0004;
5950
5951 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5952 if (status < 0)
5953 goto error;
5954 }
5955 }
5956
5957 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5958error:
5959 if (status < 0)
5960 pr_err("Error %d on %s\n", status, __func__);
5961 return status;
5962}
5963
5964static int switch_antenna_to_qam(struct drxk_state *state)
5965{
5966 int status = 0;
5967 bool gpio_state;
5968
5969 dprintk(1, "\n");
5970
5971 if (!state->antenna_gpio)
5972 return 0;
5973
5974 gpio_state = state->m_gpio & state->antenna_gpio;
5975
5976 if (state->antenna_dvbt ^ gpio_state) {
5977
5978 if (state->antenna_dvbt)
5979 state->m_gpio &= ~state->antenna_gpio;
5980 else
5981 state->m_gpio |= state->antenna_gpio;
5982 status = write_gpio(state);
5983 }
5984 if (status < 0)
5985 pr_err("Error %d on %s\n", status, __func__);
5986 return status;
5987}
5988
5989static int switch_antenna_to_dvbt(struct drxk_state *state)
5990{
5991 int status = 0;
5992 bool gpio_state;
5993
5994 dprintk(1, "\n");
5995
5996 if (!state->antenna_gpio)
5997 return 0;
5998
5999 gpio_state = state->m_gpio & state->antenna_gpio;
6000
6001 if (!(state->antenna_dvbt ^ gpio_state)) {
6002
6003 if (state->antenna_dvbt)
6004 state->m_gpio |= state->antenna_gpio;
6005 else
6006 state->m_gpio &= ~state->antenna_gpio;
6007 status = write_gpio(state);
6008 }
6009 if (status < 0)
6010 pr_err("Error %d on %s\n", status, __func__);
6011 return status;
6012}
6013
6014
6015static int power_down_device(struct drxk_state *state)
6016{
6017
6018
6019
6020
6021
6022
6023 int status;
6024
6025 dprintk(1, "\n");
6026 if (state->m_b_p_down_open_bridge) {
6027
6028 status = ConfigureI2CBridge(state, true);
6029 if (status < 0)
6030 goto error;
6031 }
6032
6033 status = dvbt_enable_ofdm_token_ring(state, false);
6034 if (status < 0)
6035 goto error;
6036
6037 status = write16(state, SIO_CC_PWD_MODE__A,
6038 SIO_CC_PWD_MODE_LEVEL_CLOCK);
6039 if (status < 0)
6040 goto error;
6041 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6042 if (status < 0)
6043 goto error;
6044 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6045 status = hi_cfg_command(state);
6046error:
6047 if (status < 0)
6048 pr_err("Error %d on %s\n", status, __func__);
6049
6050 return status;
6051}
6052
6053static int init_drxk(struct drxk_state *state)
6054{
6055 int status = 0, n = 0;
6056 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6057 u16 driver_version;
6058
6059 dprintk(1, "\n");
6060 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {
6061 drxk_i2c_lock(state);
6062 status = power_up_device(state);
6063 if (status < 0)
6064 goto error;
6065 status = drxx_open(state);
6066 if (status < 0)
6067 goto error;
6068
6069 status = write16(state, SIO_CC_SOFT_RST__A,
6070 SIO_CC_SOFT_RST_OFDM__M
6071 | SIO_CC_SOFT_RST_SYS__M
6072 | SIO_CC_SOFT_RST_OSC__M);
6073 if (status < 0)
6074 goto error;
6075 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6076 if (status < 0)
6077 goto error;
6078
6079
6080
6081
6082 usleep_range(1000, 2000);
6083 state->m_drxk_a3_patch_code = true;
6084 status = get_device_capabilities(state);
6085 if (status < 0)
6086 goto error;
6087
6088
6089
6090
6091 state->m_hi_cfg_bridge_delay =
6092 (u16) ((state->m_osc_clock_freq / 1000) *
6093 HI_I2C_BRIDGE_DELAY) / 1000;
6094
6095 if (state->m_hi_cfg_bridge_delay >
6096 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6097 state->m_hi_cfg_bridge_delay =
6098 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6099 }
6100
6101 state->m_hi_cfg_bridge_delay +=
6102 state->m_hi_cfg_bridge_delay <<
6103 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6104
6105 status = init_hi(state);
6106 if (status < 0)
6107 goto error;
6108
6109#if NOA1ROM
6110 if (!(state->m_DRXK_A1_ROM_CODE)
6111 && !(state->m_DRXK_A2_ROM_CODE))
6112#endif
6113 {
6114 status = write16(state, SCU_RAM_GPIO__A,
6115 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6116 if (status < 0)
6117 goto error;
6118 }
6119
6120
6121 status = mpegts_disable(state);
6122 if (status < 0)
6123 goto error;
6124
6125
6126 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6127 if (status < 0)
6128 goto error;
6129 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6130 if (status < 0)
6131 goto error;
6132
6133
6134 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6135 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6136 if (status < 0)
6137 goto error;
6138
6139
6140 status = write16(state, SIO_BL_COMM_EXEC__A,
6141 SIO_BL_COMM_EXEC_ACTIVE);
6142 if (status < 0)
6143 goto error;
6144 status = bl_chain_cmd(state, 0, 6, 100);
6145 if (status < 0)
6146 goto error;
6147
6148 if (state->fw) {
6149 status = download_microcode(state, state->fw->data,
6150 state->fw->size);
6151 if (status < 0)
6152 goto error;
6153 }
6154
6155
6156 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6157 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6158 if (status < 0)
6159 goto error;
6160
6161
6162 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6163 if (status < 0)
6164 goto error;
6165 status = drxx_open(state);
6166 if (status < 0)
6167 goto error;
6168
6169 msleep(30);
6170
6171 power_mode = DRXK_POWER_DOWN_OFDM;
6172 status = ctrl_power_mode(state, &power_mode);
6173 if (status < 0)
6174 goto error;
6175
6176
6177
6178
6179
6180
6181
6182 driver_version =
6183 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6184 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6185 ((DRXK_VERSION_MAJOR % 10) << 4) +
6186 (DRXK_VERSION_MINOR % 10);
6187 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6188 driver_version);
6189 if (status < 0)
6190 goto error;
6191 driver_version =
6192 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6193 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6194 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6195 (DRXK_VERSION_PATCH % 10);
6196 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6197 driver_version);
6198 if (status < 0)
6199 goto error;
6200
6201 pr_info("DRXK driver version %d.%d.%d\n",
6202 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6203 DRXK_VERSION_PATCH);
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6217 if (status < 0)
6218 goto error;
6219
6220
6221
6222 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6223 if (status < 0)
6224 goto error;
6225
6226 status = mpegts_dto_init(state);
6227 if (status < 0)
6228 goto error;
6229 status = mpegts_stop(state);
6230 if (status < 0)
6231 goto error;
6232 status = mpegts_configure_polarity(state);
6233 if (status < 0)
6234 goto error;
6235 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6236 if (status < 0)
6237 goto error;
6238
6239 status = write_gpio(state);
6240 if (status < 0)
6241 goto error;
6242
6243 state->m_drxk_state = DRXK_STOPPED;
6244
6245 if (state->m_b_power_down) {
6246 status = power_down_device(state);
6247 if (status < 0)
6248 goto error;
6249 state->m_drxk_state = DRXK_POWERED_DOWN;
6250 } else
6251 state->m_drxk_state = DRXK_STOPPED;
6252
6253
6254 n = 0;
6255 if (state->m_has_dvbc) {
6256 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6257 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6258 strlcat(state->frontend.ops.info.name, " DVB-C",
6259 sizeof(state->frontend.ops.info.name));
6260 }
6261 if (state->m_has_dvbt) {
6262 state->frontend.ops.delsys[n++] = SYS_DVBT;
6263 strlcat(state->frontend.ops.info.name, " DVB-T",
6264 sizeof(state->frontend.ops.info.name));
6265 }
6266 drxk_i2c_unlock(state);
6267 }
6268error:
6269 if (status < 0) {
6270 state->m_drxk_state = DRXK_NO_DEV;
6271 drxk_i2c_unlock(state);
6272 pr_err("Error %d on %s\n", status, __func__);
6273 }
6274
6275 return status;
6276}
6277
6278static void load_firmware_cb(const struct firmware *fw,
6279 void *context)
6280{
6281 struct drxk_state *state = context;
6282
6283 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6284 if (!fw) {
6285 pr_err("Could not load firmware file %s.\n",
6286 state->microcode_name);
6287 pr_info("Copy %s to your hotplug directory!\n",
6288 state->microcode_name);
6289 state->microcode_name = NULL;
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301 }
6302 state->fw = fw;
6303
6304 init_drxk(state);
6305}
6306
6307static void drxk_release(struct dvb_frontend *fe)
6308{
6309 struct drxk_state *state = fe->demodulator_priv;
6310
6311 dprintk(1, "\n");
6312 if (state->fw)
6313 release_firmware(state->fw);
6314
6315 kfree(state);
6316}
6317
6318static int drxk_sleep(struct dvb_frontend *fe)
6319{
6320 struct drxk_state *state = fe->demodulator_priv;
6321
6322 dprintk(1, "\n");
6323
6324 if (state->m_drxk_state == DRXK_NO_DEV)
6325 return -ENODEV;
6326 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6327 return 0;
6328
6329 shut_down(state);
6330 return 0;
6331}
6332
6333static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6334{
6335 struct drxk_state *state = fe->demodulator_priv;
6336
6337 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6338
6339 if (state->m_drxk_state == DRXK_NO_DEV)
6340 return -ENODEV;
6341
6342 return ConfigureI2CBridge(state, enable ? true : false);
6343}
6344
6345static int drxk_set_parameters(struct dvb_frontend *fe)
6346{
6347 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6348 u32 delsys = p->delivery_system, old_delsys;
6349 struct drxk_state *state = fe->demodulator_priv;
6350 u32 IF;
6351
6352 dprintk(1, "\n");
6353
6354 if (state->m_drxk_state == DRXK_NO_DEV)
6355 return -ENODEV;
6356
6357 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6358 return -EAGAIN;
6359
6360 if (!fe->ops.tuner_ops.get_if_frequency) {
6361 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6362 return -EINVAL;
6363 }
6364
6365 if (fe->ops.i2c_gate_ctrl)
6366 fe->ops.i2c_gate_ctrl(fe, 1);
6367 if (fe->ops.tuner_ops.set_params)
6368 fe->ops.tuner_ops.set_params(fe);
6369 if (fe->ops.i2c_gate_ctrl)
6370 fe->ops.i2c_gate_ctrl(fe, 0);
6371
6372 old_delsys = state->props.delivery_system;
6373 state->props = *p;
6374
6375 if (old_delsys != delsys) {
6376 shut_down(state);
6377 switch (delsys) {
6378 case SYS_DVBC_ANNEX_A:
6379 case SYS_DVBC_ANNEX_C:
6380 if (!state->m_has_dvbc)
6381 return -EINVAL;
6382 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6383 true : false;
6384 if (state->m_itut_annex_c)
6385 setoperation_mode(state, OM_QAM_ITU_C);
6386 else
6387 setoperation_mode(state, OM_QAM_ITU_A);
6388 break;
6389 case SYS_DVBT:
6390 if (!state->m_has_dvbt)
6391 return -EINVAL;
6392 setoperation_mode(state, OM_DVBT);
6393 break;
6394 default:
6395 return -EINVAL;
6396 }
6397 }
6398
6399 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6400 start(state, 0, IF);
6401
6402
6403 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6404 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6405 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6406 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6407 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6408 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6409 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6410 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6411
6412
6413
6414 return 0;
6415}
6416
6417static int get_strength(struct drxk_state *state, u64 *strength)
6418{
6419 int status;
6420 struct s_cfg_agc rf_agc, if_agc;
6421 u32 total_gain = 0;
6422 u32 atten = 0;
6423 u32 agc_range = 0;
6424 u16 scu_lvl = 0;
6425 u16 scu_coc = 0;
6426
6427 u16 tuner_rf_gain = 50;
6428 u16 tuner_if_gain = 40;
6429
6430 *strength = 0;
6431
6432 if (is_dvbt(state)) {
6433 rf_agc = state->m_dvbt_rf_agc_cfg;
6434 if_agc = state->m_dvbt_if_agc_cfg;
6435 } else if (is_qam(state)) {
6436 rf_agc = state->m_qam_rf_agc_cfg;
6437 if_agc = state->m_qam_if_agc_cfg;
6438 } else {
6439 rf_agc = state->m_atv_rf_agc_cfg;
6440 if_agc = state->m_atv_if_agc_cfg;
6441 }
6442
6443 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6444
6445 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6446 if (status < 0)
6447 return status;
6448
6449
6450 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6451 if (status < 0)
6452 return status;
6453
6454 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6455 rf_agc.output_level = scu_lvl + scu_coc;
6456 else
6457 rf_agc.output_level = 0xffff;
6458
6459
6460 total_gain += tuner_rf_gain;
6461
6462
6463 if (rf_agc.output_level < rf_agc.min_output_level)
6464 rf_agc.output_level = rf_agc.min_output_level;
6465 if (rf_agc.output_level > rf_agc.max_output_level)
6466 rf_agc.output_level = rf_agc.max_output_level;
6467
6468 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6469 if (agc_range > 0) {
6470 atten += 100UL *
6471 ((u32)(tuner_rf_gain)) *
6472 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6473 / agc_range;
6474 }
6475 }
6476
6477 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6478 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6479 &if_agc.output_level);
6480 if (status < 0)
6481 return status;
6482
6483 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6484 &if_agc.top);
6485 if (status < 0)
6486 return status;
6487
6488
6489 total_gain += (u32) tuner_if_gain;
6490
6491
6492 if (if_agc.output_level < if_agc.min_output_level)
6493 if_agc.output_level = if_agc.min_output_level;
6494 if (if_agc.output_level > if_agc.max_output_level)
6495 if_agc.output_level = if_agc.max_output_level;
6496
6497 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6498 if (agc_range > 0) {
6499 atten += 100UL *
6500 ((u32)(tuner_if_gain)) *
6501 ((u32)(if_agc.output_level - if_agc.min_output_level))
6502 / agc_range;
6503 }
6504 }
6505
6506
6507
6508
6509
6510 if (total_gain > 0)
6511 *strength = (65535UL * atten / total_gain / 100);
6512 else
6513 *strength = 65535;
6514
6515 return 0;
6516}
6517
6518static int drxk_get_stats(struct dvb_frontend *fe)
6519{
6520 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6521 struct drxk_state *state = fe->demodulator_priv;
6522 int status;
6523 u32 stat;
6524 u16 reg16;
6525 u32 post_bit_count;
6526 u32 post_bit_err_count;
6527 u32 post_bit_error_scale;
6528 u32 pre_bit_err_count;
6529 u32 pre_bit_count;
6530 u32 pkt_count;
6531 u32 pkt_error_count;
6532 s32 cnr;
6533
6534 if (state->m_drxk_state == DRXK_NO_DEV)
6535 return -ENODEV;
6536 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6537 return -EAGAIN;
6538
6539
6540 state->fe_status = 0;
6541 get_lock_status(state, &stat);
6542 if (stat == MPEG_LOCK)
6543 state->fe_status |= 0x1f;
6544 if (stat == FEC_LOCK)
6545 state->fe_status |= 0x0f;
6546 if (stat == DEMOD_LOCK)
6547 state->fe_status |= 0x07;
6548
6549
6550
6551
6552 get_strength(state, &c->strength.stat[0].uvalue);
6553 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6554
6555
6556 if (stat >= DEMOD_LOCK) {
6557 get_signal_to_noise(state, &cnr);
6558 c->cnr.stat[0].svalue = cnr * 100;
6559 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6560 } else {
6561 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6562 }
6563
6564 if (stat < FEC_LOCK) {
6565 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6566 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6567 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6568 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6569 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6570 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6571 return 0;
6572 }
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6586 if (status < 0)
6587 goto error;
6588 pre_bit_err_count = reg16;
6589
6590 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6591 if (status < 0)
6592 goto error;
6593 pre_bit_count = reg16;
6594
6595
6596 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6597 if (status < 0)
6598 goto error;
6599 post_bit_err_count = reg16;
6600
6601 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6602 if (status < 0)
6603 goto error;
6604 post_bit_error_scale = reg16;
6605
6606 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6607 if (status < 0)
6608 goto error;
6609 pkt_count = reg16;
6610
6611 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6612 if (status < 0)
6613 goto error;
6614 pkt_error_count = reg16;
6615 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6616
6617 post_bit_err_count *= post_bit_error_scale;
6618
6619 post_bit_count = pkt_count * 204 * 8;
6620
6621
6622 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6623 c->block_error.stat[0].uvalue += pkt_error_count;
6624 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6625 c->block_count.stat[0].uvalue += pkt_count;
6626
6627 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6628 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6629 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6630 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6631
6632 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6633 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6634 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6635 c->post_bit_count.stat[0].uvalue += post_bit_count;
6636
6637error:
6638 return status;
6639}
6640
6641
6642static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6643{
6644 struct drxk_state *state = fe->demodulator_priv;
6645 int rc;
6646
6647 dprintk(1, "\n");
6648
6649 rc = drxk_get_stats(fe);
6650 if (rc < 0)
6651 return rc;
6652
6653 *status = state->fe_status;
6654
6655 return 0;
6656}
6657
6658static int drxk_read_signal_strength(struct dvb_frontend *fe,
6659 u16 *strength)
6660{
6661 struct drxk_state *state = fe->demodulator_priv;
6662 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6663
6664 dprintk(1, "\n");
6665
6666 if (state->m_drxk_state == DRXK_NO_DEV)
6667 return -ENODEV;
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6669 return -EAGAIN;
6670
6671 *strength = c->strength.stat[0].uvalue;
6672 return 0;
6673}
6674
6675static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6676{
6677 struct drxk_state *state = fe->demodulator_priv;
6678 s32 snr2;
6679
6680 dprintk(1, "\n");
6681
6682 if (state->m_drxk_state == DRXK_NO_DEV)
6683 return -ENODEV;
6684 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6685 return -EAGAIN;
6686
6687 get_signal_to_noise(state, &snr2);
6688
6689
6690 if (snr2 < 0)
6691 snr2 = 0;
6692 *snr = snr2 & 0xffff;
6693 return 0;
6694}
6695
6696static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6697{
6698 struct drxk_state *state = fe->demodulator_priv;
6699 u16 err;
6700
6701 dprintk(1, "\n");
6702
6703 if (state->m_drxk_state == DRXK_NO_DEV)
6704 return -ENODEV;
6705 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6706 return -EAGAIN;
6707
6708 dvbtqam_get_acc_pkt_err(state, &err);
6709 *ucblocks = (u32) err;
6710 return 0;
6711}
6712
6713static int drxk_get_tune_settings(struct dvb_frontend *fe,
6714 struct dvb_frontend_tune_settings *sets)
6715{
6716 struct drxk_state *state = fe->demodulator_priv;
6717 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6718
6719 dprintk(1, "\n");
6720
6721 if (state->m_drxk_state == DRXK_NO_DEV)
6722 return -ENODEV;
6723 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6724 return -EAGAIN;
6725
6726 switch (p->delivery_system) {
6727 case SYS_DVBC_ANNEX_A:
6728 case SYS_DVBC_ANNEX_C:
6729 case SYS_DVBT:
6730 sets->min_delay_ms = 3000;
6731 sets->max_drift = 0;
6732 sets->step_size = 0;
6733 return 0;
6734 default:
6735 return -EINVAL;
6736 }
6737}
6738
6739static struct dvb_frontend_ops drxk_ops = {
6740
6741 .info = {
6742 .name = "DRXK",
6743 .frequency_min = 47000000,
6744 .frequency_max = 865000000,
6745
6746 .symbol_rate_min = 870000,
6747 .symbol_rate_max = 11700000,
6748
6749 .frequency_stepsize = 166667,
6750
6751 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6752 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6753 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6754 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6755 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6756 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6757 },
6758
6759 .release = drxk_release,
6760 .sleep = drxk_sleep,
6761 .i2c_gate_ctrl = drxk_gate_ctrl,
6762
6763 .set_frontend = drxk_set_parameters,
6764 .get_tune_settings = drxk_get_tune_settings,
6765
6766 .read_status = drxk_read_status,
6767 .read_signal_strength = drxk_read_signal_strength,
6768 .read_snr = drxk_read_snr,
6769 .read_ucblocks = drxk_read_ucblocks,
6770};
6771
6772struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6773 struct i2c_adapter *i2c)
6774{
6775 struct dtv_frontend_properties *p;
6776 struct drxk_state *state = NULL;
6777 u8 adr = config->adr;
6778 int status;
6779
6780 dprintk(1, "\n");
6781 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6782 if (!state)
6783 return NULL;
6784
6785 state->i2c = i2c;
6786 state->demod_address = adr;
6787 state->single_master = config->single_master;
6788 state->microcode_name = config->microcode_name;
6789 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6790 state->no_i2c_bridge = config->no_i2c_bridge;
6791 state->antenna_gpio = config->antenna_gpio;
6792 state->antenna_dvbt = config->antenna_dvbt;
6793 state->m_chunk_size = config->chunk_size;
6794 state->enable_merr_cfg = config->enable_merr_cfg;
6795
6796 if (config->dynamic_clk) {
6797 state->m_dvbt_static_clk = 0;
6798 state->m_dvbc_static_clk = 0;
6799 } else {
6800 state->m_dvbt_static_clk = 1;
6801 state->m_dvbc_static_clk = 1;
6802 }
6803
6804
6805 if (config->mpeg_out_clk_strength)
6806 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6807 else
6808 state->m_ts_clockk_strength = 0x06;
6809
6810 if (config->parallel_ts)
6811 state->m_enable_parallel = true;
6812 else
6813 state->m_enable_parallel = false;
6814
6815
6816 state->uio_mask = config->antenna_gpio;
6817
6818
6819 if (!state->antenna_dvbt && state->antenna_gpio)
6820 state->m_gpio |= state->antenna_gpio;
6821 else
6822 state->m_gpio &= ~state->antenna_gpio;
6823
6824 mutex_init(&state->mutex);
6825
6826 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6827 state->frontend.demodulator_priv = state;
6828
6829 init_state(state);
6830
6831
6832 if (state->microcode_name) {
6833 if (config->load_firmware_sync) {
6834 const struct firmware *fw = NULL;
6835
6836 status = request_firmware(&fw, state->microcode_name,
6837 state->i2c->dev.parent);
6838 if (status < 0)
6839 fw = NULL;
6840 load_firmware_cb(fw, state);
6841 } else {
6842 status = request_firmware_nowait(THIS_MODULE, 1,
6843 state->microcode_name,
6844 state->i2c->dev.parent,
6845 GFP_KERNEL,
6846 state, load_firmware_cb);
6847 if (status < 0) {
6848 pr_err("failed to request a firmware\n");
6849 return NULL;
6850 }
6851 }
6852 } else if (init_drxk(state) < 0)
6853 goto error;
6854
6855
6856
6857 p = &state->frontend.dtv_property_cache;
6858 p->strength.len = 1;
6859 p->cnr.len = 1;
6860 p->block_error.len = 1;
6861 p->block_count.len = 1;
6862 p->pre_bit_error.len = 1;
6863 p->pre_bit_count.len = 1;
6864 p->post_bit_error.len = 1;
6865 p->post_bit_count.len = 1;
6866
6867 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6868 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6869 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6870 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6871 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6872 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6873 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6874 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6875
6876 pr_info("frontend initialized.\n");
6877 return &state->frontend;
6878
6879error:
6880 pr_err("not found\n");
6881 kfree(state);
6882 return NULL;
6883}
6884EXPORT_SYMBOL(drxk_attach);
6885
6886MODULE_DESCRIPTION("DRX-K driver");
6887MODULE_AUTHOR("Ralph Metzler");
6888MODULE_LICENSE("GPL");
6889
