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22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/firmware.h>
28
29#include "dvb_frontend.h"
30#include "ts2020.h"
31#include "ds3000.h"
32
33static int debug;
34
35#define dprintk(args...) \
36 do { \
37 if (debug) \
38 printk(args); \
39 } while (0)
40
41
42
43#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
44
45#define DS3000_SAMPLE_RATE 96000
46
47
48static u8 ds3000_dvbs_init_tab[] = {
49 0x23, 0x05,
50 0x08, 0x03,
51 0x0c, 0x00,
52 0x21, 0x54,
53 0x25, 0x82,
54 0x27, 0x31,
55 0x30, 0x08,
56 0x31, 0x40,
57 0x32, 0x32,
58 0x33, 0x35,
59 0x35, 0xff,
60 0x3a, 0x00,
61 0x37, 0x10,
62 0x38, 0x10,
63 0x39, 0x02,
64 0x42, 0x60,
65 0x4a, 0x40,
66 0x4b, 0x04,
67 0x4d, 0x91,
68 0x5d, 0xc8,
69 0x50, 0x77,
70 0x51, 0x77,
71 0x52, 0x36,
72 0x53, 0x36,
73 0x56, 0x01,
74 0x63, 0x43,
75 0x64, 0x30,
76 0x65, 0x40,
77 0x68, 0x26,
78 0x69, 0x4c,
79 0x70, 0x20,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0x40,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x60,
88 0x71, 0x70,
89 0x72, 0x04,
90 0x73, 0x00,
91 0x70, 0x80,
92 0x71, 0x70,
93 0x72, 0x04,
94 0x73, 0x00,
95 0x70, 0xa0,
96 0x71, 0x70,
97 0x72, 0x04,
98 0x73, 0x00,
99 0x70, 0x1f,
100 0x76, 0x00,
101 0x77, 0xd1,
102 0x78, 0x0c,
103 0x79, 0x80,
104 0x7f, 0x04,
105 0x7c, 0x00,
106 0x80, 0x86,
107 0x81, 0xa6,
108 0x85, 0x04,
109 0xcd, 0xf4,
110 0x90, 0x33,
111 0xa0, 0x44,
112 0xc0, 0x18,
113 0xc3, 0x10,
114 0xc4, 0x08,
115 0xc5, 0x80,
116 0xc6, 0x80,
117 0xc7, 0x0a,
118 0xc8, 0x1a,
119 0xc9, 0x80,
120 0xfe, 0x92,
121 0xe0, 0xf8,
122 0xe6, 0x8b,
123 0xd0, 0x40,
124 0xf8, 0x20,
125 0xfa, 0x0f,
126 0xfd, 0x20,
127 0xad, 0x20,
128 0xae, 0x07,
129 0xb8, 0x00,
130};
131
132
133static u8 ds3000_dvbs2_init_tab[] = {
134 0x23, 0x0f,
135 0x08, 0x07,
136 0x0c, 0x00,
137 0x21, 0x54,
138 0x25, 0x82,
139 0x27, 0x31,
140 0x30, 0x08,
141 0x31, 0x32,
142 0x32, 0x32,
143 0x33, 0x35,
144 0x35, 0xff,
145 0x3a, 0x00,
146 0x37, 0x10,
147 0x38, 0x10,
148 0x39, 0x02,
149 0x42, 0x60,
150 0x4a, 0x80,
151 0x4b, 0x04,
152 0x4d, 0x81,
153 0x5d, 0x88,
154 0x50, 0x36,
155 0x51, 0x36,
156 0x52, 0x36,
157 0x53, 0x36,
158 0x63, 0x60,
159 0x64, 0x10,
160 0x65, 0x10,
161 0x68, 0x04,
162 0x69, 0x29,
163 0x70, 0x20,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0x40,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x60,
172 0x71, 0x70,
173 0x72, 0x04,
174 0x73, 0x00,
175 0x70, 0x80,
176 0x71, 0x70,
177 0x72, 0x04,
178 0x73, 0x00,
179 0x70, 0xa0,
180 0x71, 0x70,
181 0x72, 0x04,
182 0x73, 0x00,
183 0x70, 0x1f,
184 0xa0, 0x44,
185 0xc0, 0x08,
186 0xc1, 0x10,
187 0xc2, 0x08,
188 0xc3, 0x10,
189 0xc4, 0x08,
190 0xc5, 0xf0,
191 0xc6, 0xf0,
192 0xc7, 0x0a,
193 0xc8, 0x1a,
194 0xc9, 0x80,
195 0xca, 0x23,
196 0xcb, 0x24,
197 0xce, 0x74,
198 0x90, 0x03,
199 0x76, 0x80,
200 0x77, 0x42,
201 0x78, 0x0a,
202 0x79, 0x80,
203 0xad, 0x40,
204 0xae, 0x07,
205 0x7f, 0xd4,
206 0x7c, 0x00,
207 0x80, 0xa8,
208 0x81, 0xda,
209 0x7c, 0x01,
210 0x80, 0xda,
211 0x81, 0xec,
212 0x7c, 0x02,
213 0x80, 0xca,
214 0x81, 0xeb,
215 0x7c, 0x03,
216 0x80, 0xba,
217 0x81, 0xdb,
218 0x85, 0x08,
219 0x86, 0x00,
220 0x87, 0x02,
221 0x89, 0x80,
222 0x8b, 0x44,
223 0x8c, 0xaa,
224 0x8a, 0x10,
225 0xba, 0x00,
226 0xf5, 0x04,
227 0xfe, 0x44,
228 0xd2, 0x32,
229 0xb8, 0x00,
230};
231
232struct ds3000_state {
233 struct i2c_adapter *i2c;
234 const struct ds3000_config *config;
235 struct dvb_frontend frontend;
236
237 u16 prevUCBS2;
238};
239
240static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
241{
242 u8 buf[] = { reg, data };
243 struct i2c_msg msg = { .addr = state->config->demod_address,
244 .flags = 0, .buf = buf, .len = 2 };
245 int err;
246
247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
248
249 err = i2c_transfer(state->i2c, &msg, 1);
250 if (err != 1) {
251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
252 " value == 0x%02x)\n", __func__, err, reg, data);
253 return -EREMOTEIO;
254 }
255
256 return 0;
257}
258
259static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
260{
261 struct ds3000_state *state = fe->demodulator_priv;
262
263 if (enable)
264 ds3000_writereg(state, 0x03, 0x12);
265 else
266 ds3000_writereg(state, 0x03, 0x02);
267
268 return 0;
269}
270
271
272static int ds3000_writeFW(struct ds3000_state *state, int reg,
273 const u8 *data, u16 len)
274{
275 int i, ret = 0;
276 struct i2c_msg msg;
277 u8 *buf;
278
279 buf = kmalloc(33, GFP_KERNEL);
280 if (buf == NULL) {
281 printk(KERN_ERR "Unable to kmalloc\n");
282 return -ENOMEM;
283 }
284
285 *(buf) = reg;
286
287 msg.addr = state->config->demod_address;
288 msg.flags = 0;
289 msg.buf = buf;
290 msg.len = 33;
291
292 for (i = 0; i < len; i += 32) {
293 memcpy(buf + 1, data + i, 32);
294
295 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
296
297 ret = i2c_transfer(state->i2c, &msg, 1);
298 if (ret != 1) {
299 printk(KERN_ERR "%s: write error(err == %i, "
300 "reg == 0x%02x\n", __func__, ret, reg);
301 ret = -EREMOTEIO;
302 goto error;
303 }
304 }
305 ret = 0;
306
307error:
308 kfree(buf);
309
310 return ret;
311}
312
313static int ds3000_readreg(struct ds3000_state *state, u8 reg)
314{
315 int ret;
316 u8 b0[] = { reg };
317 u8 b1[] = { 0 };
318 struct i2c_msg msg[] = {
319 {
320 .addr = state->config->demod_address,
321 .flags = 0,
322 .buf = b0,
323 .len = 1
324 }, {
325 .addr = state->config->demod_address,
326 .flags = I2C_M_RD,
327 .buf = b1,
328 .len = 1
329 }
330 };
331
332 ret = i2c_transfer(state->i2c, msg, 2);
333
334 if (ret != 2) {
335 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
336 return ret;
337 }
338
339 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
340
341 return b1[0];
342}
343
344static int ds3000_load_firmware(struct dvb_frontend *fe,
345 const struct firmware *fw);
346
347static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
348{
349 struct ds3000_state *state = fe->demodulator_priv;
350 const struct firmware *fw;
351 int ret = 0;
352
353 dprintk("%s()\n", __func__);
354
355 ret = ds3000_readreg(state, 0xb2);
356 if (ret < 0)
357 return ret;
358
359
360
361 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
362 DS3000_DEFAULT_FIRMWARE);
363 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
364 state->i2c->dev.parent);
365 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
366 if (ret) {
367 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
368 "found?)\n", __func__);
369 return ret;
370 }
371
372 ret = ds3000_load_firmware(fe, fw);
373 if (ret)
374 printk("%s: Writing firmware to device failed\n", __func__);
375
376 release_firmware(fw);
377
378 dprintk("%s: Firmware upload %s\n", __func__,
379 ret == 0 ? "complete" : "failed");
380
381 return ret;
382}
383
384static int ds3000_load_firmware(struct dvb_frontend *fe,
385 const struct firmware *fw)
386{
387 struct ds3000_state *state = fe->demodulator_priv;
388 int ret = 0;
389
390 dprintk("%s\n", __func__);
391 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
392 fw->size,
393 fw->data[0],
394 fw->data[1],
395 fw->data[fw->size - 2],
396 fw->data[fw->size - 1]);
397
398
399 ds3000_writereg(state, 0xb2, 0x01);
400
401 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
402 ds3000_writereg(state, 0xb2, 0x00);
403
404 return ret;
405}
406
407static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
408{
409 struct ds3000_state *state = fe->demodulator_priv;
410 u8 data;
411
412 dprintk("%s(%d)\n", __func__, voltage);
413
414 data = ds3000_readreg(state, 0xa2);
415 data |= 0x03;
416
417 switch (voltage) {
418 case SEC_VOLTAGE_18:
419 data &= ~0x03;
420 break;
421 case SEC_VOLTAGE_13:
422 data &= ~0x03;
423 data |= 0x01;
424 break;
425 case SEC_VOLTAGE_OFF:
426 break;
427 }
428
429 ds3000_writereg(state, 0xa2, data);
430
431 return 0;
432}
433
434static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
435{
436 struct ds3000_state *state = fe->demodulator_priv;
437 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
438 int lock;
439
440 *status = 0;
441
442 switch (c->delivery_system) {
443 case SYS_DVBS:
444 lock = ds3000_readreg(state, 0xd1);
445 if ((lock & 0x07) == 0x07)
446 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
447 FE_HAS_VITERBI | FE_HAS_SYNC |
448 FE_HAS_LOCK;
449
450 break;
451 case SYS_DVBS2:
452 lock = ds3000_readreg(state, 0x0d);
453 if ((lock & 0x8f) == 0x8f)
454 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
455 FE_HAS_VITERBI | FE_HAS_SYNC |
456 FE_HAS_LOCK;
457
458 break;
459 default:
460 return 1;
461 }
462
463 if (state->config->set_lock_led)
464 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
465
466 dprintk("%s: status = 0x%02x\n", __func__, lock);
467
468 return 0;
469}
470
471
472static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
473{
474 struct ds3000_state *state = fe->demodulator_priv;
475 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
476 u8 data;
477 u32 ber_reading, lpdc_frames;
478
479 dprintk("%s()\n", __func__);
480
481 switch (c->delivery_system) {
482 case SYS_DVBS:
483
484
485 ds3000_writereg(state, 0xf9, 0x04);
486
487 data = ds3000_readreg(state, 0xf8);
488
489 if ((data & 0x10) == 0) {
490
491
492
493 *ber = (ds3000_readreg(state, 0xf7) << 8) |
494 ds3000_readreg(state, 0xf6);
495
496
497
498 data |= 0x10;
499 ds3000_writereg(state, 0xf8, data);
500 ds3000_writereg(state, 0xf8, data);
501 } else
502
503
504 *ber = 0xffffffff;
505 break;
506 case SYS_DVBS2:
507
508 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
509 (ds3000_readreg(state, 0xd6) << 8) |
510 ds3000_readreg(state, 0xd5);
511
512 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
513 ds3000_readreg(state, 0xf7);
514 if (lpdc_frames > 750) {
515
516 ds3000_writereg(state, 0xd1, 0x01);
517
518 ds3000_writereg(state, 0xf9, 0x01);
519
520 ds3000_writereg(state, 0xf9, 0x00);
521
522 ds3000_writereg(state, 0xd1, 0x00);
523 *ber = ber_reading;
524 } else
525
526
527 *ber = 0xffffffff;
528 break;
529 default:
530 return 1;
531 }
532
533 return 0;
534}
535
536static int ds3000_read_signal_strength(struct dvb_frontend *fe,
537 u16 *signal_strength)
538{
539 if (fe->ops.tuner_ops.get_rf_strength)
540 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
541
542 return 0;
543}
544
545
546static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
547{
548 struct ds3000_state *state = fe->demodulator_priv;
549 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
550 u8 snr_reading, snr_value;
551 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
552 static const u16 dvbs_snr_tab[] = {
553 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
554 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
555 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
556 };
557 static const u16 dvbs2_snr_tab[] = {
558 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
559 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
560 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
561 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
562 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
563 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
564 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
565 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
566 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
567 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
568 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
569 0x49e9, 0x4a20, 0x4a57
570 };
571
572 dprintk("%s()\n", __func__);
573
574 switch (c->delivery_system) {
575 case SYS_DVBS:
576 snr_reading = ds3000_readreg(state, 0xff);
577 snr_reading /= 8;
578 if (snr_reading == 0)
579 *snr = 0x0000;
580 else {
581 if (snr_reading > 20)
582 snr_reading = 20;
583 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
584
585
586 *snr = snr_value * 8 * 655;
587 }
588 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
589 snr_reading, *snr);
590 break;
591 case SYS_DVBS2:
592 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
593 (ds3000_readreg(state, 0x8d) << 4);
594 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
595 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
596 if (tmp == 0) {
597 *snr = 0x0000;
598 return 0;
599 }
600 if (dvbs2_noise_reading == 0) {
601 snr_value = 0x0013;
602
603
604 *snr = 0xffff;
605 return 0;
606 }
607 if (tmp > dvbs2_noise_reading) {
608 snr_reading = tmp / dvbs2_noise_reading;
609 if (snr_reading > 80)
610 snr_reading = 80;
611 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
612
613
614 *snr = snr_value * 5 * 655;
615 } else {
616 snr_reading = dvbs2_noise_reading / tmp;
617 if (snr_reading > 80)
618 snr_reading = 80;
619 *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
620 }
621 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
622 snr_reading, *snr);
623 break;
624 default:
625 return 1;
626 }
627
628 return 0;
629}
630
631
632static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
633{
634 struct ds3000_state *state = fe->demodulator_priv;
635 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
636 u8 data;
637 u16 _ucblocks;
638
639 dprintk("%s()\n", __func__);
640
641 switch (c->delivery_system) {
642 case SYS_DVBS:
643 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
644 ds3000_readreg(state, 0xf4);
645 data = ds3000_readreg(state, 0xf8);
646
647 data &= ~0x20;
648 ds3000_writereg(state, 0xf8, data);
649
650 data |= 0x20;
651 ds3000_writereg(state, 0xf8, data);
652 break;
653 case SYS_DVBS2:
654 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
655 ds3000_readreg(state, 0xe1);
656 if (_ucblocks > state->prevUCBS2)
657 *ucblocks = _ucblocks - state->prevUCBS2;
658 else
659 *ucblocks = state->prevUCBS2 - _ucblocks;
660 state->prevUCBS2 = _ucblocks;
661 break;
662 default:
663 return 1;
664 }
665
666 return 0;
667}
668
669static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
670{
671 struct ds3000_state *state = fe->demodulator_priv;
672 u8 data;
673
674 dprintk("%s(%d)\n", __func__, tone);
675 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
676 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
677 return -EINVAL;
678 }
679
680 data = ds3000_readreg(state, 0xa2);
681 data &= ~0xc0;
682 ds3000_writereg(state, 0xa2, data);
683
684 switch (tone) {
685 case SEC_TONE_ON:
686 dprintk("%s: setting tone on\n", __func__);
687 data = ds3000_readreg(state, 0xa1);
688 data &= ~0x43;
689 data |= 0x04;
690 ds3000_writereg(state, 0xa1, data);
691 break;
692 case SEC_TONE_OFF:
693 dprintk("%s: setting tone off\n", __func__);
694 data = ds3000_readreg(state, 0xa2);
695 data |= 0x80;
696 ds3000_writereg(state, 0xa2, data);
697 break;
698 }
699
700 return 0;
701}
702
703static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
704 struct dvb_diseqc_master_cmd *d)
705{
706 struct ds3000_state *state = fe->demodulator_priv;
707 int i;
708 u8 data;
709
710
711 dprintk("%s(", __func__);
712 for (i = 0 ; i < d->msg_len;) {
713 dprintk("0x%02x", d->msg[i]);
714 if (++i < d->msg_len)
715 dprintk(", ");
716 }
717
718
719 data = ds3000_readreg(state, 0xa2);
720 data &= ~0xc0;
721 ds3000_writereg(state, 0xa2, data);
722
723
724 for (i = 0; i < d->msg_len; i++)
725 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
726
727 data = ds3000_readreg(state, 0xa1);
728
729
730 data &= ~0xf8;
731
732
733 data |= ((d->msg_len - 1) << 3) | 0x07;
734 ds3000_writereg(state, 0xa1, data);
735
736
737 for (i = 0; i < 15; i++) {
738 data = ds3000_readreg(state, 0xa1);
739 if ((data & 0x40) == 0)
740 break;
741 msleep(10);
742 }
743
744
745 if (i == 15) {
746 data = ds3000_readreg(state, 0xa1);
747 data &= ~0x80;
748 data |= 0x40;
749 ds3000_writereg(state, 0xa1, data);
750
751 data = ds3000_readreg(state, 0xa2);
752 data &= ~0xc0;
753 data |= 0x80;
754 ds3000_writereg(state, 0xa2, data);
755
756 return 1;
757 }
758
759 data = ds3000_readreg(state, 0xa2);
760 data &= ~0xc0;
761 data |= 0x80;
762 ds3000_writereg(state, 0xa2, data);
763
764 return 0;
765}
766
767
768static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
769 fe_sec_mini_cmd_t burst)
770{
771 struct ds3000_state *state = fe->demodulator_priv;
772 int i;
773 u8 data;
774
775 dprintk("%s()\n", __func__);
776
777 data = ds3000_readreg(state, 0xa2);
778 data &= ~0xc0;
779 ds3000_writereg(state, 0xa2, data);
780
781
782 if (burst == SEC_MINI_A)
783
784 ds3000_writereg(state, 0xa1, 0x02);
785 else if (burst == SEC_MINI_B)
786
787 ds3000_writereg(state, 0xa1, 0x01);
788 else
789 return -EINVAL;
790
791 msleep(13);
792 for (i = 0; i < 5; i++) {
793 data = ds3000_readreg(state, 0xa1);
794 if ((data & 0x40) == 0)
795 break;
796 msleep(1);
797 }
798
799 if (i == 5) {
800 data = ds3000_readreg(state, 0xa1);
801 data &= ~0x80;
802 data |= 0x40;
803 ds3000_writereg(state, 0xa1, data);
804
805 data = ds3000_readreg(state, 0xa2);
806 data &= ~0xc0;
807 data |= 0x80;
808 ds3000_writereg(state, 0xa2, data);
809
810 return 1;
811 }
812
813 data = ds3000_readreg(state, 0xa2);
814 data &= ~0xc0;
815 data |= 0x80;
816 ds3000_writereg(state, 0xa2, data);
817
818 return 0;
819}
820
821static void ds3000_release(struct dvb_frontend *fe)
822{
823 struct ds3000_state *state = fe->demodulator_priv;
824
825 if (state->config->set_lock_led)
826 state->config->set_lock_led(fe, 0);
827
828 dprintk("%s\n", __func__);
829 kfree(state);
830}
831
832static struct dvb_frontend_ops ds3000_ops;
833
834struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
835 struct i2c_adapter *i2c)
836{
837 struct ds3000_state *state = NULL;
838 int ret;
839
840 dprintk("%s\n", __func__);
841
842
843 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
844 if (state == NULL) {
845 printk(KERN_ERR "Unable to kmalloc\n");
846 goto error2;
847 }
848
849 state->config = config;
850 state->i2c = i2c;
851 state->prevUCBS2 = 0;
852
853
854 ret = ds3000_readreg(state, 0x00) & 0xfe;
855 if (ret != 0xe0) {
856 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
857 goto error3;
858 }
859
860 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
861 ds3000_readreg(state, 0x02),
862 ds3000_readreg(state, 0x01));
863
864 memcpy(&state->frontend.ops, &ds3000_ops,
865 sizeof(struct dvb_frontend_ops));
866 state->frontend.demodulator_priv = state;
867 return &state->frontend;
868
869error3:
870 kfree(state);
871error2:
872 return NULL;
873}
874EXPORT_SYMBOL(ds3000_attach);
875
876static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
877 s32 carrier_offset_khz)
878{
879 struct ds3000_state *state = fe->demodulator_priv;
880 s32 tmp;
881
882 tmp = carrier_offset_khz;
883 tmp *= 65536;
884 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
885
886 if (tmp < 0)
887 tmp += 65536;
888
889 ds3000_writereg(state, 0x5f, tmp >> 8);
890 ds3000_writereg(state, 0x5e, tmp & 0xff);
891
892 return 0;
893}
894
895static int ds3000_set_frontend(struct dvb_frontend *fe)
896{
897 struct ds3000_state *state = fe->demodulator_priv;
898 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
899
900 int i;
901 fe_status_t status;
902 s32 offset_khz;
903 u32 frequency;
904 u16 value;
905
906 dprintk("%s() ", __func__);
907
908 if (state->config->set_ts_params)
909 state->config->set_ts_params(fe, 0);
910
911 if (fe->ops.tuner_ops.set_params)
912 fe->ops.tuner_ops.set_params(fe);
913
914
915 ds3000_writereg(state, 0x07, 0x80);
916 ds3000_writereg(state, 0x07, 0x00);
917
918 ds3000_writereg(state, 0xb2, 0x01);
919
920 ds3000_writereg(state, 0x00, 0x01);
921
922 switch (c->delivery_system) {
923 case SYS_DVBS:
924
925 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
926 ds3000_writereg(state,
927 ds3000_dvbs_init_tab[i],
928 ds3000_dvbs_init_tab[i + 1]);
929 value = ds3000_readreg(state, 0xfe);
930 value &= 0xc0;
931 value |= 0x1b;
932 ds3000_writereg(state, 0xfe, value);
933 break;
934 case SYS_DVBS2:
935
936 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
937 ds3000_writereg(state,
938 ds3000_dvbs2_init_tab[i],
939 ds3000_dvbs2_init_tab[i + 1]);
940 if (c->symbol_rate >= 30000000)
941 ds3000_writereg(state, 0xfe, 0x54);
942 else
943 ds3000_writereg(state, 0xfe, 0x98);
944 break;
945 default:
946 return 1;
947 }
948
949
950 ds3000_writereg(state, 0x29, 0x80);
951
952 ds3000_writereg(state, 0x25, 0x8a);
953
954
955 if ((c->symbol_rate / 1000) <= 5000) {
956 value = 29777 / (c->symbol_rate / 1000) + 1;
957 if (value % 2 != 0)
958 value++;
959 ds3000_writereg(state, 0xc3, 0x0d);
960 ds3000_writereg(state, 0xc8, value);
961 ds3000_writereg(state, 0xc4, 0x10);
962 ds3000_writereg(state, 0xc7, 0x0e);
963 } else if ((c->symbol_rate / 1000) <= 10000) {
964 value = 92166 / (c->symbol_rate / 1000) + 1;
965 if (value % 2 != 0)
966 value++;
967 ds3000_writereg(state, 0xc3, 0x07);
968 ds3000_writereg(state, 0xc8, value);
969 ds3000_writereg(state, 0xc4, 0x09);
970 ds3000_writereg(state, 0xc7, 0x12);
971 } else if ((c->symbol_rate / 1000) <= 20000) {
972 value = 64516 / (c->symbol_rate / 1000) + 1;
973 ds3000_writereg(state, 0xc3, value);
974 ds3000_writereg(state, 0xc8, 0x0e);
975 ds3000_writereg(state, 0xc4, 0x07);
976 ds3000_writereg(state, 0xc7, 0x18);
977 } else {
978 value = 129032 / (c->symbol_rate / 1000) + 1;
979 ds3000_writereg(state, 0xc3, value);
980 ds3000_writereg(state, 0xc8, 0x0a);
981 ds3000_writereg(state, 0xc4, 0x05);
982 ds3000_writereg(state, 0xc7, 0x24);
983 }
984
985
986 value = (((c->symbol_rate / 1000) << 16) +
987 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
988 ds3000_writereg(state, 0x61, value & 0x00ff);
989 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
990
991
992 ds3000_writereg(state, 0x56, 0x00);
993
994
995 ds3000_writereg(state, 0x76, 0x00);
996
997
998
999
1000
1001
1002
1003 if (state->config->ci_mode) {
1004 switch (c->delivery_system) {
1005 case SYS_DVBS:
1006 default:
1007 ds3000_writereg(state, 0xfd, 0x80);
1008 break;
1009 case SYS_DVBS2:
1010 ds3000_writereg(state, 0xfd, 0x01);
1011 break;
1012 }
1013 }
1014
1015
1016 ds3000_writereg(state, 0x00, 0x00);
1017
1018 ds3000_writereg(state, 0xb2, 0x00);
1019
1020 if (fe->ops.tuner_ops.get_frequency) {
1021 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1022 offset_khz = frequency - c->frequency;
1023 ds3000_set_carrier_offset(fe, offset_khz);
1024 }
1025
1026 for (i = 0; i < 30 ; i++) {
1027 ds3000_read_status(fe, &status);
1028 if (status & FE_HAS_LOCK)
1029 break;
1030
1031 msleep(10);
1032 }
1033
1034 return 0;
1035}
1036
1037static int ds3000_tune(struct dvb_frontend *fe,
1038 bool re_tune,
1039 unsigned int mode_flags,
1040 unsigned int *delay,
1041 fe_status_t *status)
1042{
1043 if (re_tune) {
1044 int ret = ds3000_set_frontend(fe);
1045 if (ret)
1046 return ret;
1047 }
1048
1049 *delay = HZ / 5;
1050
1051 return ds3000_read_status(fe, status);
1052}
1053
1054static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1055{
1056 struct ds3000_state *state = fe->demodulator_priv;
1057
1058 if (state->config->set_lock_led)
1059 state->config->set_lock_led(fe, 0);
1060
1061 dprintk("%s()\n", __func__);
1062 return DVBFE_ALGO_HW;
1063}
1064
1065
1066
1067
1068
1069
1070static int ds3000_initfe(struct dvb_frontend *fe)
1071{
1072 struct ds3000_state *state = fe->demodulator_priv;
1073 int ret;
1074
1075 dprintk("%s()\n", __func__);
1076
1077 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1078 msleep(1);
1079
1080
1081 ret = ds3000_firmware_ondemand(fe);
1082 if (ret != 0) {
1083 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1084 return ret;
1085 }
1086
1087 return 0;
1088}
1089
1090static struct dvb_frontend_ops ds3000_ops = {
1091 .delsys = { SYS_DVBS, SYS_DVBS2 },
1092 .info = {
1093 .name = "Montage Technology DS3000",
1094 .frequency_min = 950000,
1095 .frequency_max = 2150000,
1096 .frequency_stepsize = 1011,
1097 .frequency_tolerance = 5000,
1098 .symbol_rate_min = 1000000,
1099 .symbol_rate_max = 45000000,
1100 .caps = FE_CAN_INVERSION_AUTO |
1101 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1102 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1103 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1104 FE_CAN_2G_MODULATION |
1105 FE_CAN_QPSK | FE_CAN_RECOVER
1106 },
1107
1108 .release = ds3000_release,
1109
1110 .init = ds3000_initfe,
1111 .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1112 .read_status = ds3000_read_status,
1113 .read_ber = ds3000_read_ber,
1114 .read_signal_strength = ds3000_read_signal_strength,
1115 .read_snr = ds3000_read_snr,
1116 .read_ucblocks = ds3000_read_ucblocks,
1117 .set_voltage = ds3000_set_voltage,
1118 .set_tone = ds3000_set_tone,
1119 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1120 .diseqc_send_burst = ds3000_diseqc_send_burst,
1121 .get_frontend_algo = ds3000_get_algo,
1122
1123 .set_frontend = ds3000_set_frontend,
1124 .tune = ds3000_tune,
1125};
1126
1127module_param(debug, int, 0644);
1128MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1129
1130MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1131 "DS3000 hardware");
1132MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1133MODULE_LICENSE("GPL");
1134MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);
1135
