LXR linux/drivers/media/i2c/tvp7002.c

   1/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
   2 * Digitizer with Horizontal PLL registers
   3 *
   4 * Copyright (C) 2009 Texas Instruments Inc
   5 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
   6 *
   7 * This code is partially based upon the TVP5150 driver
   8 * written by Mauro Carvalho Chehab (mchehab@infradead.org),
   9 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10 * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  11 * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  12 *
  13 * This program is free software; you can redistribute it and/or modify
  14 * it under the terms of the GNU General Public License as published by
  15 * the Free Software Foundation; either version 2 of the License, or
  16 * (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27#include <linux/delay.h>
  28#include <linux/i2c.h>
  29#include <linux/slab.h>
  30#include <linux/videodev2.h>
  31#include <linux/module.h>
  32#include <linux/v4l2-dv-timings.h>
  33#include <media/tvp7002.h>
  34#include <media/v4l2-device.h>
  35#include <media/v4l2-common.h>
  36#include <media/v4l2-ctrls.h>
  37#include "tvp7002_reg.h"
  38
  39MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  40MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  41MODULE_LICENSE("GPL");
  42
  43/* I2C retry attempts */
  44#define I2C_RETRY_COUNT         (5)
  45
  46/* End of registers */
  47#define TVP7002_EOR             0x5c
  48
  49/* Read write definition for registers */
  50#define TVP7002_READ            0
  51#define TVP7002_WRITE           1
  52#define TVP7002_RESERVED        2
  53
  54/* Interlaced vs progressive mask and shift */
  55#define TVP7002_IP_SHIFT        5
  56#define TVP7002_INPR_MASK       (0x01 << TVP7002_IP_SHIFT)
  57
  58/* Shift for CPL and LPF registers */
  59#define TVP7002_CL_SHIFT        8
  60#define TVP7002_CL_MASK         0x0f
  61
  62/* Debug functions */
  63static bool debug;
  64module_param(debug, bool, 0644);
  65MODULE_PARM_DESC(debug, "Debug level (0-2)");
  66
  67/* Structure for register values */
  68struct i2c_reg_value {
  69        u8 reg;
  70        u8 value;
  71        u8 type;
  72};
  73
  74/*
  75 * Register default values (according to tvp7002 datasheet)
  76 * In the case of read-only registers, the value (0xff) is
  77 * never written. R/W functionality is controlled by the
  78 * writable bit in the register struct definition.
  79 */
  80static const struct i2c_reg_value tvp7002_init_default[] = {
  81        { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  82        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  83        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  84        { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  85        { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  86        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  87        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  88        { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  89        { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  90        { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  91        { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  92        { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  93        { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  94        { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  95        { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  96        { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  97        { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  98        { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  99        { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
 100        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 101        { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
 102        { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
 103        { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
 104        { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
 105        { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
 106        { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
 107        { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
 108        { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
 109        { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
 110        { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
 111        { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
 112        { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
 113        { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
 114        { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
 115        { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
 116        { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 117        { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 118        { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 119        { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
 120        { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
 121        { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
 122        { 0x29, 0x08, TVP7002_RESERVED },
 123        { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
 124        /* PWR_CTL is controlled only by the probe and reset functions */
 125        { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
 126        { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
 127        { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
 128        { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
 129        { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
 130        { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
 131        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 132        { 0x32, 0x18, TVP7002_RESERVED },
 133        { 0x33, 0x60, TVP7002_RESERVED },
 134        { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
 135        { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
 136        { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
 137        { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
 138        { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
 139        { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
 140        { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
 141        { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
 142        { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
 143        { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
 144        { 0x3e, 0x60, TVP7002_RESERVED },
 145        { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
 146        { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
 147        { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 148        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 149        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 150        { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 151        { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 152        { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
 153        { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 154        { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 155        { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 156        { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
 157        { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
 158        { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
 159        { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
 160        { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
 161        { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
 162        { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
 163        { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
 164        { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
 165        { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
 166        { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
 167        { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
 168        { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
 169        { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
 170        { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
 171        { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
 172        { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
 173        { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
 174        /* This signals end of register values */
 175        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 176};
 177
 178/* Register parameters for 480P */
 179static const struct i2c_reg_value tvp7002_parms_480P[] = {
 180        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
 181        { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
 182        { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
 183        { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
 184        { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 185        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
 186        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 187        { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
 188        { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
 189        { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
 190        { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
 191        { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 192        { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 193        { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 194        { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 195        { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 196        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 197};
 198
 199/* Register parameters for 576P */
 200static const struct i2c_reg_value tvp7002_parms_576P[] = {
 201        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
 202        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 203        { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
 204        { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
 205        { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 206        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
 207        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 208        { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 209        { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 210        { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 211        { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 212        { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 213        { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 214        { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 215        { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 216        { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 217        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 218};
 219
 220/* Register parameters for 1080I60 */
 221static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
 222        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 223        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 224        { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 225        { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 226        { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 227        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 228        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 229        { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 230        { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 231        { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 232        { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 233        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 234        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 235        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 236        { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 237        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 238        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 239};
 240
 241/* Register parameters for 1080P60 */
 242static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
 243        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 244        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 245        { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
 246        { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 247        { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 248        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 249        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 250        { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 251        { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 252        { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 253        { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 254        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 255        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 256        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 257        { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 258        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 259        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 260};
 261
 262/* Register parameters for 1080I50 */
 263static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
 264        { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
 265        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 266        { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 267        { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 268        { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 269        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 270        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 271        { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 272        { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 273        { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 274        { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 275        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 276        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 277        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 278        { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 279        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 280        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 281};
 282
 283/* Register parameters for 720P60 */
 284static const struct i2c_reg_value tvp7002_parms_720P60[] = {
 285        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
 286        { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
 287        { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
 288        { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 289        { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 290        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 291        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 292        { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 293        { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 294        { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 295        { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 296        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 297        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 298        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 299        { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
 300        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 301        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 302};
 303
 304/* Register parameters for 720P50 */
 305static const struct i2c_reg_value tvp7002_parms_720P50[] = {
 306        { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
 307        { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
 308        { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 309        { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 310        { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 311        { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 312        { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 313        { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 314        { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 315        { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 316        { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 317        { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 318        { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 319        { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 320        { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 321        { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 322        { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 323};
 324
 325/* Timings definition for handling device operation */
 326struct tvp7002_timings_definition {
 327        struct v4l2_dv_timings timings;
 328        const struct i2c_reg_value *p_settings;
 329        enum v4l2_colorspace color_space;
 330        enum v4l2_field scanmode;
 331        u16 progressive;
 332        u16 lines_per_frame;
 333        u16 cpl_min;
 334        u16 cpl_max;
 335};
 336
 337/* Struct list for digital video timings */
 338static const struct tvp7002_timings_definition tvp7002_timings[] = {
 339        {
 340                V4L2_DV_BT_CEA_1280X720P60,
 341                tvp7002_parms_720P60,
 342                V4L2_COLORSPACE_REC709,
 343                V4L2_FIELD_NONE,
 344                1,
 345                0x2EE,
 346                135,
 347                153
 348        },
 349        {
 350                V4L2_DV_BT_CEA_1920X1080I60,
 351                tvp7002_parms_1080I60,
 352                V4L2_COLORSPACE_REC709,
 353                V4L2_FIELD_INTERLACED,
 354                0,
 355                0x465,
 356                181,
 357                205
 358        },
 359        {
 360                V4L2_DV_BT_CEA_1920X1080I50,
 361                tvp7002_parms_1080I50,
 362                V4L2_COLORSPACE_REC709,
 363                V4L2_FIELD_INTERLACED,
 364                0,
 365                0x465,
 366                217,
 367                245
 368        },
 369        {
 370                V4L2_DV_BT_CEA_1280X720P50,
 371                tvp7002_parms_720P50,
 372                V4L2_COLORSPACE_REC709,
 373                V4L2_FIELD_NONE,
 374                1,
 375                0x2EE,
 376                163,
 377                183
 378        },
 379        {
 380                V4L2_DV_BT_CEA_1920X1080P60,
 381                tvp7002_parms_1080P60,
 382                V4L2_COLORSPACE_REC709,
 383                V4L2_FIELD_NONE,
 384                1,
 385                0x465,
 386                90,
 387                102
 388        },
 389        {
 390                V4L2_DV_BT_CEA_720X480P59_94,
 391                tvp7002_parms_480P,
 392                V4L2_COLORSPACE_SMPTE170M,
 393                V4L2_FIELD_NONE,
 394                1,
 395                0x20D,
 396                0xffff,
 397                0xffff
 398        },
 399        {
 400                V4L2_DV_BT_CEA_720X576P50,
 401                tvp7002_parms_576P,
 402                V4L2_COLORSPACE_SMPTE170M,
 403                V4L2_FIELD_NONE,
 404                1,
 405                0x271,
 406                0xffff,
 407                0xffff
 408        }
 409};
 410
 411#define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
 412
 413/* Device definition */
 414struct tvp7002 {
 415        struct v4l2_subdev sd;
 416        struct v4l2_ctrl_handler hdl;
 417        const struct tvp7002_config *pdata;
 418
 419        int ver;
 420        int streaming;
 421
 422        const struct tvp7002_timings_definition *current_timings;
 423        struct media_pad pad;
 424};
 425
 426/*
 427 * to_tvp7002 - Obtain device handler TVP7002
 428 * @sd: ptr to v4l2_subdev struct
 429 *
 430 * Returns device handler tvp7002.
 431 */
 432static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
 433{
 434        return container_of(sd, struct tvp7002, sd);
 435}
 436
 437static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 438{
 439        return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
 440}
 441
 442/*
 443 * tvp7002_read - Read a value from a register in an TVP7002
 444 * @sd: ptr to v4l2_subdev struct
 445 * @addr: TVP7002 register address
 446 * @dst: pointer to 8-bit destination
 447 *
 448 * Returns value read if successful, or non-zero (-1) otherwise.
 449 */
 450static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
 451{
 452        struct i2c_client *c = v4l2_get_subdevdata(sd);
 453        int retry;
 454        int error;
 455
 456        for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 457                error = i2c_smbus_read_byte_data(c, addr);
 458
 459                if (error >= 0) {
 460                        *dst = (u8)error;
 461                        return 0;
 462                }
 463
 464                msleep_interruptible(10);
 465        }
 466        v4l2_err(sd, "TVP7002 read error %d\n", error);
 467        return error;
 468}
 469
 470/*
 471 * tvp7002_read_err() - Read a register value with error code
 472 * @sd: pointer to standard V4L2 sub-device structure
 473 * @reg: destination register
 474 * @val: value to be read
 475 * @err: pointer to error value
 476 *
 477 * Read a value in a register and save error value in pointer.
 478 * Also update the register table if successful
 479 */
 480static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
 481                                                        u8 *dst, int *err)
 482{
 483        if (!*err)
 484                *err = tvp7002_read(sd, reg, dst);
 485}
 486
 487/*
 488 * tvp7002_write() - Write a value to a register in TVP7002
 489 * @sd: ptr to v4l2_subdev struct
 490 * @addr: TVP7002 register address
 491 * @value: value to be written to the register
 492 *
 493 * Write a value to a register in an TVP7002 decoder device.
 494 * Returns zero if successful, or non-zero otherwise.
 495 */
 496static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
 497{
 498        struct i2c_client *c;
 499        int retry;
 500        int error;
 501
 502        c = v4l2_get_subdevdata(sd);
 503
 504        for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 505                error = i2c_smbus_write_byte_data(c, addr, value);
 506
 507                if (error >= 0)
 508                        return 0;
 509
 510                v4l2_warn(sd, "Write: retry ... %d\n", retry);
 511                msleep_interruptible(10);
 512        }
 513        v4l2_err(sd, "TVP7002 write error %d\n", error);
 514        return error;
 515}
 516
 517/*
 518 * tvp7002_write_err() - Write a register value with error code
 519 * @sd: pointer to standard V4L2 sub-device structure
 520 * @reg: destination register
 521 * @val: value to be written
 522 * @err: pointer to error value
 523 *
 524 * Write a value in a register and save error value in pointer.
 525 * Also update the register table if successful
 526 */
 527static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
 528                                                        u8 val, int *err)
 529{
 530        if (!*err)
 531                *err = tvp7002_write(sd, reg, val);
 532}
 533
 534/*
 535 * tvp7002_write_inittab() - Write initialization values
 536 * @sd: ptr to v4l2_subdev struct
 537 * @regs: ptr to i2c_reg_value struct
 538 *
 539 * Write initialization values.
 540 * Returns zero or -EINVAL if read operation fails.
 541 */
 542static int tvp7002_write_inittab(struct v4l2_subdev *sd,
 543                                        const struct i2c_reg_value *regs)
 544{
 545        int error = 0;
 546
 547        /* Initialize the first (defined) registers */
 548        while (TVP7002_EOR != regs->reg) {
 549                if (TVP7002_WRITE == regs->type)
 550                        tvp7002_write_err(sd, regs->reg, regs->value, &error);
 551                regs++;
 552        }
 553
 554        return error;
 555}
 556
 557static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
 558                                        struct v4l2_dv_timings *dv_timings)
 559{
 560        struct tvp7002 *device = to_tvp7002(sd);
 561        const struct v4l2_bt_timings *bt = &dv_timings->bt;
 562        int i;
 563
 564        if (dv_timings->type != V4L2_DV_BT_656_1120)
 565                return -EINVAL;
 566        for (i = 0; i < NUM_TIMINGS; i++) {
 567                const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
 568
 569                if (!memcmp(bt, t, &bt->standards - &bt->width)) {
 570                        device->current_timings = &tvp7002_timings[i];
 571                        return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
 572                }
 573        }
 574        return -EINVAL;
 575}
 576
 577static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
 578                                        struct v4l2_dv_timings *dv_timings)
 579{
 580        struct tvp7002 *device = to_tvp7002(sd);
 581
 582        *dv_timings = device->current_timings->timings;
 583        return 0;
 584}
 585
 586/*
 587 * tvp7002_s_ctrl() - Set a control
 588 * @ctrl: ptr to v4l2_ctrl struct
 589 *
 590 * Set a control in TVP7002 decoder device.
 591 * Returns zero when successful or -EINVAL if register access fails.
 592 */
 593static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
 594{
 595        struct v4l2_subdev *sd = to_sd(ctrl);
 596        int error = 0;
 597
 598        switch (ctrl->id) {
 599        case V4L2_CID_GAIN:
 600                tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
 601                tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
 602                tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
 603                return error;
 604        }
 605        return -EINVAL;
 606}
 607
 608/*
 609 * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
 610 * @sd: pointer to standard V4L2 sub-device structure
 611 * @f: pointer to mediabus format structure
 612 *
 613 * Negotiate the image capture size and mediabus format.
 614 * There is only one possible format, so this single function works for
 615 * get, set and try.
 616 */
 617static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
 618{
 619        struct tvp7002 *device = to_tvp7002(sd);
 620        const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt;
 621
 622        f->width = bt->width;
 623        f->height = bt->height;
 624        f->code = V4L2_MBUS_FMT_YUYV10_1X20;
 625        f->field = device->current_timings->scanmode;
 626        f->colorspace = device->current_timings->color_space;
 627
 628        v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
 629                        f->width, f->height);
 630        return 0;
 631}
 632
 633/*
 634 * tvp7002_query_dv() - query DV timings
 635 * @sd: pointer to standard V4L2 sub-device structure
 636 * @index: index into the tvp7002_timings array
 637 *
 638 * Returns the current DV timings detected by TVP7002. If no active input is
 639 * detected, returns -EINVAL
 640 */
 641static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
 642{
 643        const struct tvp7002_timings_definition *timings = tvp7002_timings;
 644        u8 progressive;
 645        u32 lpfr;
 646        u32 cpln;
 647        int error = 0;
 648        u8 lpf_lsb;
 649        u8 lpf_msb;
 650        u8 cpl_lsb;
 651        u8 cpl_msb;
 652
 653        /* Return invalid index if no active input is detected */
 654        *index = NUM_TIMINGS;
 655
 656        /* Read standards from device registers */
 657        tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
 658        tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
 659
 660        if (error < 0)
 661                return error;
 662
 663        tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
 664        tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
 665
 666        if (error < 0)
 667                return error;
 668
 669        /* Get lines per frame, clocks per line and interlaced/progresive */
 670        lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
 671        cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
 672        progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
 673
 674        /* Do checking of video modes */
 675        for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
 676                if (lpfr == timings->lines_per_frame &&
 677                        progressive == timings->progressive) {
 678                        if (timings->cpl_min == 0xffff)
 679                                break;
 680                        if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
 681                                break;
 682                }
 683
 684        if (*index == NUM_TIMINGS) {
 685                v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
 686                                                                lpfr, cpln);
 687                return -ENOLINK;
 688        }
 689
 690        /* Update lines per frame and clocks per line info */
 691        v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
 692        return 0;
 693}
 694
 695static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
 696                                        struct v4l2_dv_timings *timings)
 697{
 698        int index;
 699        int err = tvp7002_query_dv(sd, &index);
 700
 701        if (err)
 702                return err;
 703        *timings = tvp7002_timings[index].timings;
 704        return 0;
 705}
 706
 707#ifdef CONFIG_VIDEO_ADV_DEBUG
 708/*
 709 * tvp7002_g_register() - Get the value of a register
 710 * @sd: ptr to v4l2_subdev struct
 711 * @reg: ptr to v4l2_dbg_register struct
 712 *
 713 * Get the value of a TVP7002 decoder device register.
 714 * Returns zero when successful, -EINVAL if register read fails or
 715 * access to I2C client fails.
 716 */
 717static int tvp7002_g_register(struct v4l2_subdev *sd,
 718                                                struct v4l2_dbg_register *reg)
 719{
 720        u8 val;
 721        int ret;
 722
 723        ret = tvp7002_read(sd, reg->reg & 0xff, &val);
 724        reg->val = val;
 725        reg->size = 1;
 726        return ret;
 727}
 728
 729/*
 730 * tvp7002_s_register() - set a control
 731 * @sd: ptr to v4l2_subdev struct
 732 * @reg: ptr to v4l2_dbg_register struct
 733 *
 734 * Get the value of a TVP7002 decoder device register.
 735 * Returns zero when successful, -EINVAL if register read fails.
 736 */
 737static int tvp7002_s_register(struct v4l2_subdev *sd,
 738                                                const struct v4l2_dbg_register *reg)
 739{
 740        return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
 741}
 742#endif
 743
 744/*
 745 * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats
 746 * @sd: pointer to standard V4L2 sub-device structure
 747 * @index: format index
 748 * @code: pointer to mediabus format
 749 *
 750 * Enumerate supported mediabus formats.
 751 */
 752
 753static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
 754                                        enum v4l2_mbus_pixelcode *code)
 755{
 756        /* Check requested format index is within range */
 757        if (index)
 758                return -EINVAL;
 759        *code = V4L2_MBUS_FMT_YUYV10_1X20;
 760        return 0;
 761}
 762
 763/*
 764 * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
 765 * @sd: pointer to standard V4L2 sub-device structure
 766 * @enable: streaming enable or disable
 767 *
 768 * Sets streaming to enable or disable, if possible.
 769 */
 770static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
 771{
 772        struct tvp7002 *device = to_tvp7002(sd);
 773        int error = 0;
 774
 775        if (device->streaming == enable)
 776                return 0;
 777
 778        if (enable) {
 779                /* Set output state on (low impedance means stream on) */
 780                error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00);
 781                device->streaming = enable;
 782        } else {
 783                /* Set output state off (high impedance means stream off) */
 784                error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03);
 785                if (error)
 786                        v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");
 787
 788                device->streaming = enable;
 789        }
 790
 791        return error;
 792}
 793
 794/*
 795 * tvp7002_log_status() - Print information about register settings
 796 * @sd: ptr to v4l2_subdev struct
 797 *
 798 * Log register values of a TVP7002 decoder device.
 799 * Returns zero or -EINVAL if read operation fails.
 800 */
 801static int tvp7002_log_status(struct v4l2_subdev *sd)
 802{
 803        struct tvp7002 *device = to_tvp7002(sd);
 804        const struct v4l2_bt_timings *bt;
 805        int detected;
 806
 807        /* Find my current timings */
 808        tvp7002_query_dv(sd, &detected);
 809
 810        bt = &device->current_timings->timings.bt;
 811        v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
 812        if (detected == NUM_TIMINGS) {
 813                v4l2_info(sd, "Detected DV Timings: None\n");
 814        } else {
 815                bt = &tvp7002_timings[detected].timings.bt;
 816                v4l2_info(sd, "Detected DV Timings: %ux%u\n",
 817                                bt->width, bt->height);
 818        }
 819        v4l2_info(sd, "Streaming enabled: %s\n",
 820                                        device->streaming ? "yes" : "no");
 821
 822        /* Print the current value of the gain control */
 823        v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
 824
 825        return 0;
 826}
 827
 828static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
 829                struct v4l2_enum_dv_timings *timings)
 830{
 831        /* Check requested format index is within range */
 832        if (timings->index >= NUM_TIMINGS)
 833                return -EINVAL;
 834
 835        timings->timings = tvp7002_timings[timings->index].timings;
 836        return 0;
 837}
 838
 839static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
 840        .s_ctrl = tvp7002_s_ctrl,
 841};
 842
 843/*
 844 * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
 845 * @sd: pointer to standard V4L2 sub-device structure
 846 * @fh: file handle for the subdev
 847 * @code: pointer to subdev enum mbus code struct
 848 *
 849 * Enumerate supported digital video formats for pad.
 850 */
 851static int
 852tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 853                       struct v4l2_subdev_mbus_code_enum *code)
 854{
 855        /* Check requested format index is within range */
 856        if (code->index != 0)
 857                return -EINVAL;
 858
 859        code->code = V4L2_MBUS_FMT_YUYV10_1X20;
 860
 861        return 0;
 862}
 863
 864/*
 865 * tvp7002_get_pad_format() - get video format on pad
 866 * @sd: pointer to standard V4L2 sub-device structure
 867 * @fh: file handle for the subdev
 868 * @fmt: pointer to subdev format struct
 869 *
 870 * get video format for pad.
 871 */
 872static int
 873tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 874                       struct v4l2_subdev_format *fmt)
 875{
 876        struct tvp7002 *tvp7002 = to_tvp7002(sd);
 877
 878        fmt->format.code = V4L2_MBUS_FMT_YUYV10_1X20;
 879        fmt->format.width = tvp7002->current_timings->timings.bt.width;
 880        fmt->format.height = tvp7002->current_timings->timings.bt.height;
 881        fmt->format.field = tvp7002->current_timings->scanmode;
 882        fmt->format.colorspace = tvp7002->current_timings->color_space;
 883
 884        return 0;
 885}
 886
 887/*
 888 * tvp7002_set_pad_format() - set video format on pad
 889 * @sd: pointer to standard V4L2 sub-device structure
 890 * @fh: file handle for the subdev
 891 * @fmt: pointer to subdev format struct
 892 *
 893 * set video format for pad.
 894 */
 895static int
 896tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 897                       struct v4l2_subdev_format *fmt)
 898{
 899        return tvp7002_get_pad_format(sd, fh, fmt);
 900}
 901
 902/* V4L2 core operation handlers */
 903static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
 904        .log_status = tvp7002_log_status,
 905        .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
 906        .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
 907        .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
 908        .g_ctrl = v4l2_subdev_g_ctrl,
 909        .s_ctrl = v4l2_subdev_s_ctrl,
 910        .queryctrl = v4l2_subdev_queryctrl,
 911        .querymenu = v4l2_subdev_querymenu,
 912#ifdef CONFIG_VIDEO_ADV_DEBUG
 913        .g_register = tvp7002_g_register,
 914        .s_register = tvp7002_s_register,
 915#endif
 916};
 917
 918/* Specific video subsystem operation handlers */
 919static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
 920        .g_dv_timings = tvp7002_g_dv_timings,
 921        .s_dv_timings = tvp7002_s_dv_timings,
 922        .enum_dv_timings = tvp7002_enum_dv_timings,
 923        .query_dv_timings = tvp7002_query_dv_timings,
 924        .s_stream = tvp7002_s_stream,
 925        .g_mbus_fmt = tvp7002_mbus_fmt,
 926        .try_mbus_fmt = tvp7002_mbus_fmt,
 927        .s_mbus_fmt = tvp7002_mbus_fmt,
 928        .enum_mbus_fmt = tvp7002_enum_mbus_fmt,
 929};
 930
 931/* media pad related operation handlers */
 932static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
 933        .enum_mbus_code = tvp7002_enum_mbus_code,
 934        .get_fmt = tvp7002_get_pad_format,
 935        .set_fmt = tvp7002_set_pad_format,
 936};
 937
 938/* V4L2 top level operation handlers */
 939static const struct v4l2_subdev_ops tvp7002_ops = {
 940        .core = &tvp7002_core_ops,
 941        .video = &tvp7002_video_ops,
 942        .pad = &tvp7002_pad_ops,
 943};
 944
 945/*
 946 * tvp7002_probe - Probe a TVP7002 device
 947 * @c: ptr to i2c_client struct
 948 * @id: ptr to i2c_device_id struct
 949 *
 950 * Initialize the TVP7002 device
 951 * Returns zero when successful, -EINVAL if register read fails or
 952 * -EIO if i2c access is not available.
 953 */
 954static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id)
 955{
 956        struct v4l2_subdev *sd;
 957        struct tvp7002 *device;
 958        struct v4l2_dv_timings timings;
 959        int polarity_a;
 960        int polarity_b;
 961        u8 revision;
 962
 963        int error;
 964
 965        /* Check if the adapter supports the needed features */
 966        if (!i2c_check_functionality(c->adapter,
 967                I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
 968                return -EIO;
 969
 970        if (!c->dev.platform_data) {
 971                v4l_err(c, "No platform data!!\n");
 972                return -ENODEV;
 973        }
 974
 975        device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
 976
 977        if (!device)
 978                return -ENOMEM;
 979
 980        sd = &device->sd;
 981        device->pdata = c->dev.platform_data;
 982        device->current_timings = tvp7002_timings;
 983
 984        /* Tell v4l2 the device is ready */
 985        v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
 986        v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
 987                                        c->addr, c->adapter->name);
 988
 989        error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
 990        if (error < 0)
 991                return error;
 992
 993        /* Get revision number */
 994        v4l2_info(sd, "Rev. %02x detected.\n", revision);
 995        if (revision != 0x02)
 996                v4l2_info(sd, "Unknown revision detected.\n");
 997
 998        /* Initializes TVP7002 to its default values */
 999        error = tvp7002_write_inittab(sd, tvp7002_init_default);
1000

1001        if (error < 0)
1002                return error;
1003
1004        /* Set polarity information after registers have been set */
1005        polarity_a = 0x20 | device->pdata->hs_polarity << 5
1006                        | device->pdata->vs_polarity << 2;
1007        error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
1008        if (error < 0)
1009                return error;
1010
1011        polarity_b = 0x01  | device->pdata->fid_polarity << 2
1012                        | device->pdata->sog_polarity << 1
1013                        | device->pdata->clk_polarity;
1014        error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
1015        if (error < 0)
1016                return error;
1017
1018        /* Set registers according to default video mode */
1019        timings = device->current_timings->timings;
1020        error = tvp7002_s_dv_timings(sd, &timings);
1021
1022#if defined(CONFIG_MEDIA_CONTROLLER)
1023        device->pad.flags = MEDIA_PAD_FL_SOURCE;
1024        device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1025        device->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
1026
1027        error = media_entity_init(&device->sd.entity, 1, &device->pad, 0);
1028        if (error < 0)
1029                return error;
1030#endif
1031
1032        v4l2_ctrl_handler_init(&device->hdl, 1);
1033        v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
1034                        V4L2_CID_GAIN, 0, 255, 1, 0);
1035        sd->ctrl_handler = &device->hdl;
1036        if (device->hdl.error) {
1037                error = device->hdl.error;
1038                goto error;
1039        }
1040        v4l2_ctrl_handler_setup(&device->hdl);
1041
1042        return 0;
1043
1044error:
1045        v4l2_ctrl_handler_free(&device->hdl);
1046#if defined(CONFIG_MEDIA_CONTROLLER)
1047        media_entity_cleanup(&device->sd.entity);
1048#endif
1049        return error;
1050}
1051
1052/*
1053 * tvp7002_remove - Remove TVP7002 device support
1054 * @c: ptr to i2c_client struct
1055 *
1056 * Reset the TVP7002 device
1057 * Returns zero.
1058 */
1059static int tvp7002_remove(struct i2c_client *c)
1060{
1061        struct v4l2_subdev *sd = i2c_get_clientdata(c);
1062        struct tvp7002 *device = to_tvp7002(sd);
1063
1064        v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
1065                                "on address 0x%x\n", c->addr);
1066#if defined(CONFIG_MEDIA_CONTROLLER)
1067        media_entity_cleanup(&device->sd.entity);
1068#endif
1069        v4l2_device_unregister_subdev(sd);
1070        v4l2_ctrl_handler_free(&device->hdl);
1071        return 0;
1072}
1073
1074/* I2C Device ID table */
1075static const struct i2c_device_id tvp7002_id[] = {
1076        { "tvp7002", 0 },
1077        { }
1078};
1079MODULE_DEVICE_TABLE(i2c, tvp7002_id);
1080
1081/* I2C driver data */
1082static struct i2c_driver tvp7002_driver = {
1083        .driver = {
1084                .owner = THIS_MODULE,
1085                .name = TVP7002_MODULE_NAME,
1086        },
1087        .probe = tvp7002_probe,
1088        .remove = tvp7002_remove,
1089        .id_table = tvp7002_id,
1090};
1091
1092module_i2c_driver(tvp7002_driver);
1093