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9#ifndef FIMC_CORE_H_
10#define FIMC_CORE_H_
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14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16#include <linux/sched.h>
17#include <linux/spinlock.h>
18#include <linux/mfd/syscon.h>
19#include <linux/types.h>
20#include <linux/videodev2.h>
21#include <linux/io.h>
22#include <linux/sizes.h>
23
24#include <media/media-entity.h>
25#include <media/videobuf2-core.h>
26#include <media/v4l2-ctrls.h>
27#include <media/v4l2-device.h>
28#include <media/v4l2-mem2mem.h>
29#include <media/v4l2-mediabus.h>
30#include <media/s5p_fimc.h>
31
32#define dbg(fmt, args...) \
33 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34
35
36#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
37#define MAX_FIMC_CLOCKS 2
38#define FIMC_DRIVER_NAME "exynos4-fimc"
39#define FIMC_MAX_DEVS 4
40#define FIMC_MAX_OUT_BUFS 4
41#define SCALER_MAX_HRATIO 64
42#define SCALER_MAX_VRATIO 64
43#define DMA_MIN_SIZE 8
44#define FIMC_CAMIF_MAX_HEIGHT 0x2000
45#define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
46#define FIMC_MAX_PLANES 3
47#define FIMC_PIX_LIMITS_MAX 4
48#define FIMC_DEF_MIN_SIZE 16
49#define FIMC_DEF_HEIGHT_ALIGN 2
50#define FIMC_DEF_HOR_OFFS_ALIGN 1
51#define FIMC_DEFAULT_WIDTH 640
52#define FIMC_DEFAULT_HEIGHT 480
53
54
55enum {
56 CLK_BUS,
57 CLK_GATE,
58};
59
60enum fimc_dev_flags {
61 ST_LPM,
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63 ST_M2M_RUN,
64 ST_M2M_PEND,
65 ST_M2M_SUSPENDING,
66 ST_M2M_SUSPENDED,
67
68 ST_CAPT_PEND,
69 ST_CAPT_RUN,
70 ST_CAPT_STREAM,
71 ST_CAPT_ISP_STREAM,
72 ST_CAPT_SUSPENDED,
73 ST_CAPT_SHUT,
74 ST_CAPT_BUSY,
75 ST_CAPT_APPLY_CFG,
76 ST_CAPT_JPEG,
77};
78
79#define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
80#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
81
82#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
83#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
84#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
85
86enum fimc_datapath {
87 FIMC_IO_NONE,
88 FIMC_IO_CAMERA,
89 FIMC_IO_DMA,
90 FIMC_IO_LCDFIFO,
91 FIMC_IO_WRITEBACK,
92 FIMC_IO_ISP,
93};
94
95enum fimc_color_fmt {
96 FIMC_FMT_RGB444 = 0x10,
97 FIMC_FMT_RGB555,
98 FIMC_FMT_RGB565,
99 FIMC_FMT_RGB666,
100 FIMC_FMT_RGB888,
101 FIMC_FMT_RGB30_LOCAL,
102 FIMC_FMT_YCBCR420 = 0x20,
103 FIMC_FMT_YCBYCR422,
104 FIMC_FMT_YCRYCB422,
105 FIMC_FMT_CBYCRY422,
106 FIMC_FMT_CRYCBY422,
107 FIMC_FMT_YCBCR444_LOCAL,
108 FIMC_FMT_RAW8 = 0x40,
109 FIMC_FMT_RAW10,
110 FIMC_FMT_RAW12,
111 FIMC_FMT_JPEG = 0x80,
112 FIMC_FMT_YUYV_JPEG = 0x100,
113};
114
115#define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
116#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
117
118#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
119 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
120
121
122#define FIMC_PARAMS (1 << 0)
123#define FIMC_COMPOSE (1 << 1)
124#define FIMC_CTX_M2M (1 << 16)
125#define FIMC_CTX_CAP (1 << 17)
126#define FIMC_CTX_SHUT (1 << 18)
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128
129#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
130#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
131#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
132#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
133#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
134#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
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138#define FIMC_COLOR_RANGE_WIDE (0 << 3)
139
140#define FIMC_COLOR_RANGE_NARROW (1 << 3)
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151struct fimc_dma_offset {
152 int y_h;
153 int y_v;
154 int cb_h;
155 int cb_v;
156 int cr_h;
157 int cr_v;
158};
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166struct fimc_effect {
167 u32 type;
168 u8 pat_cb;
169 u8 pat_cr;
170};
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190struct fimc_scaler {
191 unsigned int scaleup_h:1;
192 unsigned int scaleup_v:1;
193 unsigned int copy_mode:1;
194 unsigned int enabled:1;
195 u32 hfactor;
196 u32 vfactor;
197 u32 pre_hratio;
198 u32 pre_vratio;
199 u32 pre_dst_width;
200 u32 pre_dst_height;
201 u32 main_hratio;
202 u32 main_vratio;
203 u32 real_width;
204 u32 real_height;
205};
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213struct fimc_addr {
214 u32 y;
215 u32 cb;
216 u32 cr;
217};
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226struct fimc_vid_buffer {
227 struct vb2_buffer vb;
228 struct list_head list;
229 struct fimc_addr paddr;
230 int index;
231};
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249struct fimc_frame {
250 u32 f_width;
251 u32 f_height;
252 u32 o_width;
253 u32 o_height;
254 u32 offs_h;
255 u32 offs_v;
256 u32 width;
257 u32 height;
258 unsigned int payload[VIDEO_MAX_PLANES];
259 unsigned int bytesperline[VIDEO_MAX_PLANES];
260 struct fimc_addr paddr;
261 struct fimc_dma_offset dma_offset;
262 struct fimc_fmt *fmt;
263 u8 alpha;
264};
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273struct fimc_m2m_device {
274 struct video_device vfd;
275 struct v4l2_m2m_dev *m2m_dev;
276 struct fimc_ctx *ctx;
277 int refcnt;
278};
279
280#define FIMC_SD_PAD_SINK_CAM 0
281#define FIMC_SD_PAD_SINK_FIFO 1
282#define FIMC_SD_PAD_SOURCE 2
283#define FIMC_SD_PADS_NUM 3
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308struct fimc_vid_cap {
309 struct fimc_ctx *ctx;
310 struct vb2_alloc_ctx *alloc_ctx;
311 struct v4l2_subdev subdev;
312 struct exynos_video_entity ve;
313 struct media_pad vd_pad;
314 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
315 struct v4l2_mbus_framefmt ci_fmt;
316 struct v4l2_mbus_framefmt wb_fmt;
317 struct fimc_source_info source_config;
318 struct list_head pending_buf_q;
319 struct list_head active_buf_q;
320 struct vb2_queue vbq;
321 int active_buf_cnt;
322 int buf_index;
323 unsigned int frame_count;
324 unsigned int reqbufs_count;
325 bool streaming;
326 int input_index;
327 u32 input;
328 bool user_subdev_api;
329 bool inh_sensor_ctrls;
330};
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342struct fimc_pix_limit {
343 u16 scaler_en_w;
344 u16 scaler_dis_w;
345 u16 in_rot_en_h;
346 u16 in_rot_dis_w;
347 u16 out_rot_en_w;
348 u16 out_rot_dis_w;
349};
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365struct fimc_variant {
366 unsigned int has_inp_rot:1;
367 unsigned int has_out_rot:1;
368 unsigned int has_mainscaler_ext:1;
369 unsigned int has_cam_if:1;
370 unsigned int has_isp_wb:1;
371 const struct fimc_pix_limit *pix_limit;
372 u16 min_inp_pixsize;
373 u16 min_out_pixsize;
374 u16 hor_offs_align;
375 u16 min_vsize_align;
376};
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388struct fimc_drvdata {
389 const struct fimc_variant *variant[FIMC_MAX_DEVS];
390 int num_entities;
391 unsigned long lclk_frequency;
392
393 u8 cistatus2;
394 u8 dma_pix_hoff;
395 u8 alpha_color;
396 u8 out_buf_count;
397};
398
399#define fimc_get_drvdata(_pdev) \
400 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
401
402struct fimc_ctx;
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423struct fimc_dev {
424 spinlock_t slock;
425 struct mutex lock;
426 struct platform_device *pdev;
427 struct s5p_platform_fimc *pdata;
428 struct regmap *sysreg;
429 const struct fimc_variant *variant;
430 const struct fimc_drvdata *drv_data;
431 int id;
432 struct clk *clock[MAX_FIMC_CLOCKS];
433 void __iomem *regs;
434 wait_queue_head_t irq_queue;
435 struct v4l2_device *v4l2_dev;
436 struct fimc_m2m_device m2m;
437 struct fimc_vid_cap vid_cap;
438 unsigned long state;
439 struct vb2_alloc_ctx *alloc_ctx;
440};
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453struct fimc_ctrls {
454 struct v4l2_ctrl_handler handler;
455 struct {
456 struct v4l2_ctrl *colorfx;
457 struct v4l2_ctrl *colorfx_cbcr;
458 };
459 struct v4l2_ctrl *rotate;
460 struct v4l2_ctrl *hflip;
461 struct v4l2_ctrl *vflip;
462 struct v4l2_ctrl *alpha;
463 bool ready;
464};
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488struct fimc_ctx {
489 struct fimc_frame s_frame;
490 struct fimc_frame d_frame;
491 u32 out_order_1p;
492 u32 out_order_2p;
493 u32 in_order_1p;
494 u32 in_order_2p;
495 enum fimc_datapath in_path;
496 enum fimc_datapath out_path;
497 struct fimc_scaler scaler;
498 struct fimc_effect effect;
499 int rotation;
500 unsigned int hflip:1;
501 unsigned int vflip:1;
502 u32 flags;
503 u32 state;
504 struct fimc_dev *fimc_dev;
505 struct v4l2_m2m_ctx *m2m_ctx;
506 struct v4l2_fh fh;
507 struct fimc_ctrls ctrls;
508};
509
510#define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
511
512static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
513{
514 f->o_width = width;
515 f->o_height = height;
516 f->f_width = width;
517 f->f_height = height;
518}
519
520static inline void set_frame_crop(struct fimc_frame *f,
521 u32 left, u32 top, u32 width, u32 height)
522{
523 f->offs_h = left;
524 f->offs_v = top;
525 f->width = width;
526 f->height = height;
527}
528
529static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
530{
531 u32 i, depth = 0;
532
533 if (ff != NULL)
534 for (i = 0; i < ff->colplanes; i++)
535 depth += ff->depth[i];
536 return depth;
537}
538
539static inline bool fimc_capture_active(struct fimc_dev *fimc)
540{
541 unsigned long flags;
542 bool ret;
543
544 spin_lock_irqsave(&fimc->slock, flags);
545 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
546 fimc->state & (1 << ST_CAPT_PEND));
547 spin_unlock_irqrestore(&fimc->slock, flags);
548 return ret;
549}
550
551static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
552{
553 unsigned long flags;
554
555 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
556 ctx->state |= state;
557 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
558}
559
560static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
561{
562 unsigned long flags;
563 bool ret;
564
565 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
566 ret = (ctx->state & mask) == mask;
567 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
568 return ret;
569}
570
571static inline int tiled_fmt(struct fimc_fmt *fmt)
572{
573 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
574}
575
576static inline bool fimc_jpeg_fourcc(u32 pixelformat)
577{
578 return (pixelformat == V4L2_PIX_FMT_JPEG ||
579 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
580}
581
582static inline bool fimc_user_defined_mbus_fmt(u32 code)
583{
584 return (code == V4L2_MBUS_FMT_JPEG_1X8 ||
585 code == V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8);
586}
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588
589static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
590{
591 switch (fmt->color) {
592 case FIMC_FMT_RGB444: return 0x0f;
593 case FIMC_FMT_RGB555: return 0x01;
594 case FIMC_FMT_RGB888: return 0xff;
595 default: return 0;
596 };
597}
598
599static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
600 enum v4l2_buf_type type)
601{
602 struct fimc_frame *frame;
603
604 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
605 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
606 frame = &ctx->s_frame;
607 else
608 return ERR_PTR(-EINVAL);
609 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
610 frame = &ctx->d_frame;
611 } else {
612 v4l2_err(ctx->fimc_dev->v4l2_dev,
613 "Wrong buffer/video queue type (%d)\n", type);
614 return ERR_PTR(-EINVAL);
615 }
616
617 return frame;
618}
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621
622int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
623 struct v4l2_fmtdesc *f);
624int fimc_ctrls_create(struct fimc_ctx *ctx);
625void fimc_ctrls_delete(struct fimc_ctx *ctx);
626void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
627void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
628void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
629void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
630 struct v4l2_pix_format_mplane *pix);
631struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
632 unsigned int mask, int index);
633struct fimc_fmt *fimc_get_format(unsigned int index);
634
635int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
636 int dw, int dh, int rotation);
637int fimc_set_scaler_info(struct fimc_ctx *ctx);
638int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
639int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
640 struct fimc_frame *frame, struct fimc_addr *paddr);
641void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
642void fimc_set_yuv_order(struct fimc_ctx *ctx);
643void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
644
645int fimc_register_m2m_device(struct fimc_dev *fimc,
646 struct v4l2_device *v4l2_dev);
647void fimc_unregister_m2m_device(struct fimc_dev *fimc);
648int fimc_register_driver(void);
649void fimc_unregister_driver(void);
650
651#ifdef CONFIG_MFD_SYSCON
652static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
653{
654 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
655}
656#else
657#define fimc_get_sysreg_regmap(node) (NULL)
658#endif
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662void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
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666int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
667void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
668int fimc_capture_ctrls_create(struct fimc_dev *fimc);
669void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
670 void *arg);
671int fimc_capture_suspend(struct fimc_dev *fimc);
672int fimc_capture_resume(struct fimc_dev *fimc);
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682static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
683 struct fimc_vid_buffer *buf)
684{
685 list_add_tail(&buf->list, &vid_cap->active_buf_q);
686 vid_cap->active_buf_cnt++;
687}
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694static inline struct fimc_vid_buffer *fimc_active_queue_pop(
695 struct fimc_vid_cap *vid_cap)
696{
697 struct fimc_vid_buffer *buf;
698 buf = list_entry(vid_cap->active_buf_q.next,
699 struct fimc_vid_buffer, list);
700 list_del(&buf->list);
701 vid_cap->active_buf_cnt--;
702 return buf;
703}
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709static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
710 struct fimc_vid_buffer *buf)
711{
712 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
713}
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719
720static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
721 struct fimc_vid_cap *vid_cap)
722{
723 struct fimc_vid_buffer *buf;
724 buf = list_entry(vid_cap->pending_buf_q.next,
725 struct fimc_vid_buffer, list);
726 list_del(&buf->list);
727 return buf;
728}
729
730#endif
731