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5
6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/fs.h>
10#include <linux/mm.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
14#include <linux/slab.h>
15#include <linux/device.h>
16#include <linux/wait.h>
17#include <linux/list.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/vmalloc.h>
21#include <linux/io.h>
22#include <linux/videodev2.h>
23#include <media/v4l2-device.h>
24#include <media/v4l2-ioctl.h>
25#include <media/v4l2-ctrls.h>
26#include <media/ov7670.h>
27#include <media/videobuf2-vmalloc.h>
28#include <media/videobuf2-dma-contig.h>
29#include <media/videobuf2-dma-sg.h>
30
31#include "mcam-core.h"
32
33#ifdef MCAM_MODE_VMALLOC
34
35
36
37
38
39
40
41
42
43
44
45
46
47static bool alloc_bufs_at_read;
48module_param(alloc_bufs_at_read, bool, 0444);
49MODULE_PARM_DESC(alloc_bufs_at_read,
50 "Non-zero value causes DMA buffers to be allocated when the "
51 "video capture device is read, rather than at module load "
52 "time. This saves memory, but decreases the chances of "
53 "successfully getting those buffers. This parameter is "
54 "only used in the vmalloc buffer mode");
55
56static int n_dma_bufs = 3;
57module_param(n_dma_bufs, uint, 0644);
58MODULE_PARM_DESC(n_dma_bufs,
59 "The number of DMA buffers to allocate. Can be either two "
60 "(saves memory, makes timing tighter) or three.");
61
62static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2;
63module_param(dma_buf_size, uint, 0444);
64MODULE_PARM_DESC(dma_buf_size,
65 "The size of the allocated DMA buffers. If actual operating "
66 "parameters require larger buffers, an attempt to reallocate "
67 "will be made.");
68#else
69static const bool alloc_bufs_at_read = 0;
70static const int n_dma_bufs = 3;
71#endif
72
73static bool flip;
74module_param(flip, bool, 0444);
75MODULE_PARM_DESC(flip,
76 "If set, the sensor will be instructed to flip the image "
77 "vertically.");
78
79static int buffer_mode = -1;
80module_param(buffer_mode, int, 0444);
81MODULE_PARM_DESC(buffer_mode,
82 "Set the buffer mode to be used; default is to go with what "
83 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
84 "DMA contiguous.");
85
86
87
88
89#define CF_BUF0_VALID 0
90#define CF_BUF1_VALID 1
91#define CF_BUF2_VALID 2
92#define CF_DMA_ACTIVE 3
93#define CF_CONFIG_NEEDED 4
94#define CF_SINGLE_BUFFER 5
95#define CF_SG_RESTART 6
96
97#define sensor_call(cam, o, f, args...) \
98 v4l2_subdev_call(cam->sensor, o, f, ##args)
99
100static struct mcam_format_struct {
101 __u8 *desc;
102 __u32 pixelformat;
103 int bpp;
104 enum v4l2_mbus_pixelcode mbus_code;
105} mcam_formats[] = {
106 {
107 .desc = "YUYV 4:2:2",
108 .pixelformat = V4L2_PIX_FMT_YUYV,
109 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
110 .bpp = 2,
111 },
112 {
113 .desc = "RGB 444",
114 .pixelformat = V4L2_PIX_FMT_RGB444,
115 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
116 .bpp = 2,
117 },
118 {
119 .desc = "RGB 565",
120 .pixelformat = V4L2_PIX_FMT_RGB565,
121 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE,
122 .bpp = 2,
123 },
124 {
125 .desc = "Raw RGB Bayer",
126 .pixelformat = V4L2_PIX_FMT_SBGGR8,
127 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,
128 .bpp = 1
129 },
130};
131#define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
132
133static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
134{
135 unsigned i;
136
137 for (i = 0; i < N_MCAM_FMTS; i++)
138 if (mcam_formats[i].pixelformat == pixelformat)
139 return mcam_formats + i;
140
141 return mcam_formats;
142}
143
144
145
146
147static const struct v4l2_pix_format mcam_def_pix_format = {
148 .width = VGA_WIDTH,
149 .height = VGA_HEIGHT,
150 .pixelformat = V4L2_PIX_FMT_YUYV,
151 .field = V4L2_FIELD_NONE,
152 .bytesperline = VGA_WIDTH*2,
153 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
154};
155
156static const enum v4l2_mbus_pixelcode mcam_def_mbus_code =
157 V4L2_MBUS_FMT_YUYV8_2X8;
158
159
160
161
162
163
164
165
166struct mcam_dma_desc {
167 u32 dma_addr;
168 u32 segment_len;
169};
170
171
172
173
174
175
176struct mcam_vb_buffer {
177 struct vb2_buffer vb_buf;
178 struct list_head queue;
179 struct mcam_dma_desc *dma_desc;
180 dma_addr_t dma_desc_pa;
181 int dma_desc_nent;
182};
183
184static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
185{
186 return container_of(vb, struct mcam_vb_buffer, vb_buf);
187}
188
189
190
191
192static void mcam_buffer_done(struct mcam_camera *cam, int frame,
193 struct vb2_buffer *vbuf)
194{
195 vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
196 vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
197 vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
198 vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
199}
200
201
202
203
204
205
206#define cam_err(cam, fmt, arg...) \
207 dev_err((cam)->dev, fmt, ##arg);
208#define cam_warn(cam, fmt, arg...) \
209 dev_warn((cam)->dev, fmt, ##arg);
210#define cam_dbg(cam, fmt, arg...) \
211 dev_dbg((cam)->dev, fmt, ##arg);
212
213
214
215
216
217static void mcam_reset_buffers(struct mcam_camera *cam)
218{
219 int i;
220
221 cam->next_buf = -1;
222 for (i = 0; i < cam->nbufs; i++)
223 clear_bit(i, &cam->flags);
224}
225
226static inline int mcam_needs_config(struct mcam_camera *cam)
227{
228 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
229}
230
231static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
232{
233 if (needed)
234 set_bit(CF_CONFIG_NEEDED, &cam->flags);
235 else
236 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
237}
238
239
240
241
242
243
244static void mcam_ctlr_start(struct mcam_camera *cam)
245{
246
247
248 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
249}
250
251static void mcam_ctlr_stop(struct mcam_camera *cam)
252{
253 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
254}
255
256
257
258#ifdef MCAM_MODE_VMALLOC
259
260
261
262
263
264
265
266static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
267{
268 int i;
269
270 mcam_set_config_needed(cam, 1);
271 if (loadtime)
272 cam->dma_buf_size = dma_buf_size;
273 else
274 cam->dma_buf_size = cam->pix_format.sizeimage;
275 if (n_dma_bufs > 3)
276 n_dma_bufs = 3;
277
278 cam->nbufs = 0;
279 for (i = 0; i < n_dma_bufs; i++) {
280 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
281 cam->dma_buf_size, cam->dma_handles + i,
282 GFP_KERNEL);
283 if (cam->dma_bufs[i] == NULL) {
284 cam_warn(cam, "Failed to allocate DMA buffer\n");
285 break;
286 }
287 (cam->nbufs)++;
288 }
289
290 switch (cam->nbufs) {
291 case 1:
292 dma_free_coherent(cam->dev, cam->dma_buf_size,
293 cam->dma_bufs[0], cam->dma_handles[0]);
294 cam->nbufs = 0;
295 case 0:
296 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
297 return -ENOMEM;
298
299 case 2:
300 if (n_dma_bufs > 2)
301 cam_warn(cam, "Will limp along with only 2 buffers\n");
302 break;
303 }
304 return 0;
305}
306
307static void mcam_free_dma_bufs(struct mcam_camera *cam)
308{
309 int i;
310
311 for (i = 0; i < cam->nbufs; i++) {
312 dma_free_coherent(cam->dev, cam->dma_buf_size,
313 cam->dma_bufs[i], cam->dma_handles[i]);
314 cam->dma_bufs[i] = NULL;
315 }
316 cam->nbufs = 0;
317}
318
319
320
321
322
323static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
324{
325
326
327
328
329
330
331 mcam_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
332 mcam_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
333 if (cam->nbufs > 2) {
334 mcam_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
335 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
336 } else
337 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
338 if (cam->chip_id == MCAM_CAFE)
339 mcam_reg_write(cam, REG_UBAR, 0);
340}
341
342
343
344
345static void mcam_frame_tasklet(unsigned long data)
346{
347 struct mcam_camera *cam = (struct mcam_camera *) data;
348 int i;
349 unsigned long flags;
350 struct mcam_vb_buffer *buf;
351
352 spin_lock_irqsave(&cam->dev_lock, flags);
353 for (i = 0; i < cam->nbufs; i++) {
354 int bufno = cam->next_buf;
355
356 if (cam->state != S_STREAMING || bufno < 0)
357 break;
358 if (++(cam->next_buf) >= cam->nbufs)
359 cam->next_buf = 0;
360 if (!test_bit(bufno, &cam->flags))
361 continue;
362 if (list_empty(&cam->buffers)) {
363 cam->frame_state.singles++;
364 break;
365 }
366 cam->frame_state.delivered++;
367 clear_bit(bufno, &cam->flags);
368 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
369 queue);
370 list_del_init(&buf->queue);
371
372
373
374 spin_unlock_irqrestore(&cam->dev_lock, flags);
375 memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno],
376 cam->pix_format.sizeimage);
377 mcam_buffer_done(cam, bufno, &buf->vb_buf);
378 spin_lock_irqsave(&cam->dev_lock, flags);
379 }
380 spin_unlock_irqrestore(&cam->dev_lock, flags);
381}
382
383
384
385
386
387static int mcam_check_dma_buffers(struct mcam_camera *cam)
388{
389 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
390 mcam_free_dma_bufs(cam);
391 if (cam->nbufs == 0)
392 return mcam_alloc_dma_bufs(cam, 0);
393 return 0;
394}
395
396static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
397{
398 tasklet_schedule(&cam->s_tasklet);
399}
400
401#else
402
403static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
404{
405 return 0;
406}
407
408static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
409{
410 return;
411}
412
413static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
414{
415 return 0;
416}
417
418
419
420#endif
421
422
423#ifdef MCAM_MODE_DMA_CONTIG
424
425
426
427
428
429
430
431
432
433
434
435
436static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
437{
438 struct mcam_vb_buffer *buf;
439
440
441
442 if (list_empty(&cam->buffers)) {
443 buf = cam->vb_bufs[frame ^ 0x1];
444 cam->vb_bufs[frame] = buf;
445 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
446 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
447 set_bit(CF_SINGLE_BUFFER, &cam->flags);
448 cam->frame_state.singles++;
449 return;
450 }
451
452
453
454 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
455 list_del_init(&buf->queue);
456 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
457 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
458 cam->vb_bufs[frame] = buf;
459 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
460}
461
462
463
464
465static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
466{
467 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
468 cam->nbufs = 2;
469 mcam_set_contig_buffer(cam, 0);
470 mcam_set_contig_buffer(cam, 1);
471}
472
473
474
475
476static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
477{
478 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
479
480 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
481 cam->frame_state.delivered++;
482 mcam_buffer_done(cam, frame, &buf->vb_buf);
483 }
484 mcam_set_contig_buffer(cam, frame);
485}
486
487#endif
488
489#ifdef MCAM_MODE_DMA_SG
490
491
492
493
494
495
496
497
498
499static void mcam_sg_next_buffer(struct mcam_camera *cam)
500{
501 struct mcam_vb_buffer *buf;
502
503 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
504 list_del_init(&buf->queue);
505
506
507
508
509 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
510 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
511 mcam_reg_write(cam, REG_DESC_LEN_Y,
512 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
513 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
514 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
515 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
516 cam->vb_bufs[0] = buf;
517}
518
519
520
521
522static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
523{
524
525
526
527
528 if (list_empty(&cam->buffers)) {
529 set_bit(CF_SG_RESTART, &cam->flags);
530 return;
531 }
532
533 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
534 mcam_sg_next_buffer(cam);
535 cam->nbufs = 3;
536}
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
553{
554 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
555
556
557
558
559 if (cam->state != S_STREAMING)
560 return;
561
562
563
564
565 if (!list_empty(&cam->buffers)) {
566 mcam_sg_next_buffer(cam);
567 mcam_ctlr_start(cam);
568
569
570
571
572 } else {
573 set_bit(CF_SG_RESTART, &cam->flags);
574 cam->frame_state.singles++;
575 cam->vb_bufs[0] = NULL;
576 }
577
578
579
580 cam->frame_state.delivered++;
581 mcam_buffer_done(cam, frame, &buf->vb_buf);
582}
583
584
585
586
587
588
589
590
591static void mcam_sg_restart(struct mcam_camera *cam)
592{
593 mcam_ctlr_dma_sg(cam);
594 mcam_ctlr_start(cam);
595 clear_bit(CF_SG_RESTART, &cam->flags);
596}
597
598#else
599
600static inline void mcam_sg_restart(struct mcam_camera *cam)
601{
602 return;
603}
604
605#endif
606
607
608
609
610
611
612
613
614
615static void mcam_ctlr_image(struct mcam_camera *cam)
616{
617 int imgsz;
618 struct v4l2_pix_format *fmt = &cam->pix_format;
619
620 imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) |
621 (fmt->bytesperline & IMGSZ_H_MASK);
622 mcam_reg_write(cam, REG_IMGSIZE, imgsz);
623 mcam_reg_write(cam, REG_IMGOFFSET, 0);
624
625 mcam_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline,
626 IMGP_YP_MASK);
627
628
629
630 switch (cam->pix_format.pixelformat) {
631 case V4L2_PIX_FMT_YUYV:
632 mcam_reg_write_mask(cam, REG_CTRL0,
633 C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV,
634 C0_DF_MASK);
635 break;
636
637 case V4L2_PIX_FMT_RGB444:
638 mcam_reg_write_mask(cam, REG_CTRL0,
639 C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB,
640 C0_DF_MASK);
641
642 break;
643
644 case V4L2_PIX_FMT_RGB565:
645 mcam_reg_write_mask(cam, REG_CTRL0,
646 C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR,
647 C0_DF_MASK);
648 break;
649
650 default:
651 cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat);
652 break;
653 }
654
655
656
657 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC,
658 C0_SIFM_MASK);
659}
660
661
662
663
664
665
666static int mcam_ctlr_configure(struct mcam_camera *cam)
667{
668 unsigned long flags;
669
670 spin_lock_irqsave(&cam->dev_lock, flags);
671 clear_bit(CF_SG_RESTART, &cam->flags);
672 cam->dma_setup(cam);
673 mcam_ctlr_image(cam);
674 mcam_set_config_needed(cam, 0);
675 spin_unlock_irqrestore(&cam->dev_lock, flags);
676 return 0;
677}
678
679static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
680{
681
682
683
684
685 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
686 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
687}
688
689static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
690{
691 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
692}
693
694
695
696static void mcam_ctlr_init(struct mcam_camera *cam)
697{
698 unsigned long flags;
699
700 spin_lock_irqsave(&cam->dev_lock, flags);
701
702
703
704 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
705
706
707
708
709 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
710
711
712
713
714 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
715 spin_unlock_irqrestore(&cam->dev_lock, flags);
716}
717
718
719
720
721
722
723static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
724{
725 unsigned long flags;
726
727
728
729
730
731
732 spin_lock_irqsave(&cam->dev_lock, flags);
733 clear_bit(CF_SG_RESTART, &cam->flags);
734 mcam_ctlr_stop(cam);
735 cam->state = S_IDLE;
736 spin_unlock_irqrestore(&cam->dev_lock, flags);
737
738
739
740
741
742
743
744 msleep(150);
745 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
746 cam_err(cam, "Timeout waiting for DMA to end\n");
747
748 spin_lock_irqsave(&cam->dev_lock, flags);
749 mcam_ctlr_irq_disable(cam);
750 spin_unlock_irqrestore(&cam->dev_lock, flags);
751}
752
753
754
755
756static void mcam_ctlr_power_up(struct mcam_camera *cam)
757{
758 unsigned long flags;
759
760 spin_lock_irqsave(&cam->dev_lock, flags);
761 cam->plat_power_up(cam);
762 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
763 spin_unlock_irqrestore(&cam->dev_lock, flags);
764 msleep(5);
765}
766
767static void mcam_ctlr_power_down(struct mcam_camera *cam)
768{
769 unsigned long flags;
770
771 spin_lock_irqsave(&cam->dev_lock, flags);
772
773
774
775
776
777 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
778 cam->plat_power_down(cam);
779 spin_unlock_irqrestore(&cam->dev_lock, flags);
780}
781
782
783
784
785
786
787static int __mcam_cam_reset(struct mcam_camera *cam)
788{
789 return sensor_call(cam, core, reset, 0);
790}
791
792
793
794
795
796static int mcam_cam_init(struct mcam_camera *cam)
797{
798 int ret;
799
800 mutex_lock(&cam->s_mutex);
801 if (cam->state != S_NOTREADY)
802 cam_warn(cam, "Cam init with device in funky state %d",
803 cam->state);
804 ret = __mcam_cam_reset(cam);
805
806 cam->state = S_IDLE;
807 mcam_ctlr_power_down(cam);
808 mutex_unlock(&cam->s_mutex);
809 return ret;
810}
811
812
813
814
815
816static int mcam_cam_set_flip(struct mcam_camera *cam)
817{
818 struct v4l2_control ctrl;
819
820 memset(&ctrl, 0, sizeof(ctrl));
821 ctrl.id = V4L2_CID_VFLIP;
822 ctrl.value = flip;
823 return sensor_call(cam, core, s_ctrl, &ctrl);
824}
825
826
827static int mcam_cam_configure(struct mcam_camera *cam)
828{
829 struct v4l2_mbus_framefmt mbus_fmt;
830 int ret;
831
832 v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code);
833 ret = sensor_call(cam, core, init, 0);
834 if (ret == 0)
835 ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt);
836
837
838
839 ret += mcam_cam_set_flip(cam);
840 return ret;
841}
842
843
844
845
846static int mcam_read_setup(struct mcam_camera *cam)
847{
848 int ret;
849 unsigned long flags;
850
851
852
853
854
855 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
856 mcam_alloc_dma_bufs(cam, 0))
857 return -ENOMEM;
858
859 if (mcam_needs_config(cam)) {
860 mcam_cam_configure(cam);
861 ret = mcam_ctlr_configure(cam);
862 if (ret)
863 return ret;
864 }
865
866
867
868
869 spin_lock_irqsave(&cam->dev_lock, flags);
870 clear_bit(CF_DMA_ACTIVE, &cam->flags);
871 mcam_reset_buffers(cam);
872 mcam_ctlr_irq_enable(cam);
873 cam->state = S_STREAMING;
874 if (!test_bit(CF_SG_RESTART, &cam->flags))
875 mcam_ctlr_start(cam);
876 spin_unlock_irqrestore(&cam->dev_lock, flags);
877 return 0;
878}
879
880
881
882
883
884
885static int mcam_vb_queue_setup(struct vb2_queue *vq,
886 const struct v4l2_format *fmt, unsigned int *nbufs,
887 unsigned int *num_planes, unsigned int sizes[],
888 void *alloc_ctxs[])
889{
890 struct mcam_camera *cam = vb2_get_drv_priv(vq);
891 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
892
893 sizes[0] = cam->pix_format.sizeimage;
894 *num_planes = 1;
895 if (*nbufs < minbufs)
896 *nbufs = minbufs;
897 if (cam->buffer_mode == B_DMA_contig)
898 alloc_ctxs[0] = cam->vb_alloc_ctx;
899 return 0;
900}
901
902
903static void mcam_vb_buf_queue(struct vb2_buffer *vb)
904{
905 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
906 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
907 unsigned long flags;
908 int start;
909
910 spin_lock_irqsave(&cam->dev_lock, flags);
911 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
912 list_add(&mvb->queue, &cam->buffers);
913 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
914 mcam_sg_restart(cam);
915 spin_unlock_irqrestore(&cam->dev_lock, flags);
916 if (start)
917 mcam_read_setup(cam);
918}
919
920
921
922
923
924
925
926static void mcam_vb_wait_prepare(struct vb2_queue *vq)
927{
928 struct mcam_camera *cam = vb2_get_drv_priv(vq);
929
930 mutex_unlock(&cam->s_mutex);
931}
932
933static void mcam_vb_wait_finish(struct vb2_queue *vq)
934{
935 struct mcam_camera *cam = vb2_get_drv_priv(vq);
936
937 mutex_lock(&cam->s_mutex);
938}
939
940
941
942
943static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
944{
945 struct mcam_camera *cam = vb2_get_drv_priv(vq);
946
947 if (cam->state != S_IDLE) {
948 INIT_LIST_HEAD(&cam->buffers);
949 return -EINVAL;
950 }
951 cam->sequence = 0;
952
953
954
955
956
957
958
959 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
960 cam->state = S_BUFWAIT;
961 return 0;
962 }
963 return mcam_read_setup(cam);
964}
965
966static int mcam_vb_stop_streaming(struct vb2_queue *vq)
967{
968 struct mcam_camera *cam = vb2_get_drv_priv(vq);
969 unsigned long flags;
970
971 if (cam->state == S_BUFWAIT) {
972
973 cam->state = S_IDLE;
974 return 0;
975 }
976 if (cam->state != S_STREAMING)
977 return -EINVAL;
978 mcam_ctlr_stop_dma(cam);
979
980
981
982
983 spin_lock_irqsave(&cam->dev_lock, flags);
984 INIT_LIST_HEAD(&cam->buffers);
985 spin_unlock_irqrestore(&cam->dev_lock, flags);
986 return 0;
987}
988
989
990static const struct vb2_ops mcam_vb2_ops = {
991 .queue_setup = mcam_vb_queue_setup,
992 .buf_queue = mcam_vb_buf_queue,
993 .start_streaming = mcam_vb_start_streaming,
994 .stop_streaming = mcam_vb_stop_streaming,
995 .wait_prepare = mcam_vb_wait_prepare,
996 .wait_finish = mcam_vb_wait_finish,
997};
998
999
1000#ifdef MCAM_MODE_DMA_SG
1001
1002
1003
1004
1005static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1006{
1007 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1008 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1009 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1010
1011 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1012 ndesc * sizeof(struct mcam_dma_desc),
1013 &mvb->dma_desc_pa, GFP_KERNEL);
1014 if (mvb->dma_desc == NULL) {
1015 cam_err(cam, "Unable to get DMA descriptor array\n");
1016 return -ENOMEM;
1017 }
1018 return 0;
1019}
1020
1021static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1022{
1023 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1024 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1025 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1026 struct mcam_dma_desc *desc = mvb->dma_desc;
1027 struct scatterlist *sg;
1028 int i;
1029
1030 mvb->dma_desc_nent = dma_map_sg(cam->dev, sgd->sglist, sgd->num_pages,
1031 DMA_FROM_DEVICE);
1032 if (mvb->dma_desc_nent <= 0)
1033 return -EIO;
1034 for_each_sg(sgd->sglist, sg, mvb->dma_desc_nent, i) {
1035 desc->dma_addr = sg_dma_address(sg);
1036 desc->segment_len = sg_dma_len(sg);
1037 desc++;
1038 }
1039 return 0;
1040}
1041
1042static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb)
1043{
1044 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1045 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1046
1047 dma_unmap_sg(cam->dev, sgd->sglist, sgd->num_pages, DMA_FROM_DEVICE);
1048 return 0;
1049}
1050
1051static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1052{
1053 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1054 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1055 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1056
1057 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1058 mvb->dma_desc, mvb->dma_desc_pa);
1059}
1060
1061
1062static const struct vb2_ops mcam_vb2_sg_ops = {
1063 .queue_setup = mcam_vb_queue_setup,
1064 .buf_init = mcam_vb_sg_buf_init,
1065 .buf_prepare = mcam_vb_sg_buf_prepare,
1066 .buf_queue = mcam_vb_buf_queue,
1067 .buf_finish = mcam_vb_sg_buf_finish,
1068 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1069 .start_streaming = mcam_vb_start_streaming,
1070 .stop_streaming = mcam_vb_stop_streaming,
1071 .wait_prepare = mcam_vb_wait_prepare,
1072 .wait_finish = mcam_vb_wait_finish,
1073};
1074
1075#endif
1076
1077static int mcam_setup_vb2(struct mcam_camera *cam)
1078{
1079 struct vb2_queue *vq = &cam->vb_queue;
1080
1081 memset(vq, 0, sizeof(*vq));
1082 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1083 vq->drv_priv = cam;
1084 INIT_LIST_HEAD(&cam->buffers);
1085 switch (cam->buffer_mode) {
1086 case B_DMA_contig:
1087#ifdef MCAM_MODE_DMA_CONTIG
1088 vq->ops = &mcam_vb2_ops;
1089 vq->mem_ops = &vb2_dma_contig_memops;
1090 cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
1091 vq->io_modes = VB2_MMAP | VB2_USERPTR;
1092 cam->dma_setup = mcam_ctlr_dma_contig;
1093 cam->frame_complete = mcam_dma_contig_done;
1094#endif
1095 break;
1096 case B_DMA_sg:
1097#ifdef MCAM_MODE_DMA_SG
1098 vq->ops = &mcam_vb2_sg_ops;
1099 vq->mem_ops = &vb2_dma_sg_memops;
1100 vq->io_modes = VB2_MMAP | VB2_USERPTR;
1101 cam->dma_setup = mcam_ctlr_dma_sg;
1102 cam->frame_complete = mcam_dma_sg_done;
1103#endif
1104 break;
1105 case B_vmalloc:
1106#ifdef MCAM_MODE_VMALLOC
1107 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1108 (unsigned long) cam);
1109 vq->ops = &mcam_vb2_ops;
1110 vq->mem_ops = &vb2_vmalloc_memops;
1111 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1112 vq->io_modes = VB2_MMAP;
1113 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1114 cam->frame_complete = mcam_vmalloc_done;
1115#endif
1116 break;
1117 }
1118 return vb2_queue_init(vq);
1119}
1120
1121static void mcam_cleanup_vb2(struct mcam_camera *cam)
1122{
1123 vb2_queue_release(&cam->vb_queue);
1124#ifdef MCAM_MODE_DMA_CONTIG
1125 if (cam->buffer_mode == B_DMA_contig)
1126 vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx);
1127#endif
1128}
1129
1130
1131
1132
1133
1134
1135
1136static int mcam_vidioc_streamon(struct file *filp, void *priv,
1137 enum v4l2_buf_type type)
1138{
1139 struct mcam_camera *cam = filp->private_data;
1140 int ret;
1141
1142 mutex_lock(&cam->s_mutex);
1143 ret = vb2_streamon(&cam->vb_queue, type);
1144 mutex_unlock(&cam->s_mutex);
1145 return ret;
1146}
1147
1148
1149static int mcam_vidioc_streamoff(struct file *filp, void *priv,
1150 enum v4l2_buf_type type)
1151{
1152 struct mcam_camera *cam = filp->private_data;
1153 int ret;
1154
1155 mutex_lock(&cam->s_mutex);
1156 ret = vb2_streamoff(&cam->vb_queue, type);
1157 mutex_unlock(&cam->s_mutex);
1158 return ret;
1159}
1160
1161
1162static int mcam_vidioc_reqbufs(struct file *filp, void *priv,
1163 struct v4l2_requestbuffers *req)
1164{
1165 struct mcam_camera *cam = filp->private_data;
1166 int ret;
1167
1168 mutex_lock(&cam->s_mutex);
1169 ret = vb2_reqbufs(&cam->vb_queue, req);
1170 mutex_unlock(&cam->s_mutex);
1171 return ret;
1172}
1173
1174
1175static int mcam_vidioc_querybuf(struct file *filp, void *priv,
1176 struct v4l2_buffer *buf)
1177{
1178 struct mcam_camera *cam = filp->private_data;
1179 int ret;
1180
1181 mutex_lock(&cam->s_mutex);
1182 ret = vb2_querybuf(&cam->vb_queue, buf);
1183 mutex_unlock(&cam->s_mutex);
1184 return ret;
1185}
1186
1187static int mcam_vidioc_qbuf(struct file *filp, void *priv,
1188 struct v4l2_buffer *buf)
1189{
1190 struct mcam_camera *cam = filp->private_data;
1191 int ret;
1192
1193 mutex_lock(&cam->s_mutex);
1194 ret = vb2_qbuf(&cam->vb_queue, buf);
1195 mutex_unlock(&cam->s_mutex);
1196 return ret;
1197}
1198
1199static int mcam_vidioc_dqbuf(struct file *filp, void *priv,
1200 struct v4l2_buffer *buf)
1201{
1202 struct mcam_camera *cam = filp->private_data;
1203 int ret;
1204
1205 mutex_lock(&cam->s_mutex);
1206 ret = vb2_dqbuf(&cam->vb_queue, buf, filp->f_flags & O_NONBLOCK);
1207 mutex_unlock(&cam->s_mutex);
1208 return ret;
1209}
1210
1211static int mcam_vidioc_querycap(struct file *file, void *priv,
1212 struct v4l2_capability *cap)
1213{
1214 strcpy(cap->driver, "marvell_ccic");
1215 strcpy(cap->card, "marvell_ccic");
1216 cap->version = 1;
1217 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
1218 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1219 return 0;
1220}
1221
1222
1223static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1224 void *priv, struct v4l2_fmtdesc *fmt)
1225{
1226 if (fmt->index >= N_MCAM_FMTS)
1227 return -EINVAL;
1228 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1229 sizeof(fmt->description));
1230 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1231 return 0;
1232}
1233
1234static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1235 struct v4l2_format *fmt)
1236{
1237 struct mcam_camera *cam = priv;
1238 struct mcam_format_struct *f;
1239 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1240 struct v4l2_mbus_framefmt mbus_fmt;
1241 int ret;
1242
1243 f = mcam_find_format(pix->pixelformat);
1244 pix->pixelformat = f->pixelformat;
1245 v4l2_fill_mbus_format(&mbus_fmt, pix, f->mbus_code);
1246 mutex_lock(&cam->s_mutex);
1247 ret = sensor_call(cam, video, try_mbus_fmt, &mbus_fmt);
1248 mutex_unlock(&cam->s_mutex);
1249 v4l2_fill_pix_format(pix, &mbus_fmt);
1250 pix->bytesperline = pix->width * f->bpp;
1251 pix->sizeimage = pix->height * pix->bytesperline;
1252 return ret;
1253}
1254
1255static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1256 struct v4l2_format *fmt)
1257{
1258 struct mcam_camera *cam = priv;
1259 struct mcam_format_struct *f;
1260 int ret;
1261
1262
1263
1264
1265
1266 if (cam->state != S_IDLE || cam->vb_queue.num_buffers > 0)
1267 return -EBUSY;
1268
1269 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1270
1271
1272
1273
1274 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1275 if (ret)
1276 return ret;
1277
1278
1279
1280
1281 mutex_lock(&cam->s_mutex);
1282 cam->pix_format = fmt->fmt.pix;
1283 cam->mbus_code = f->mbus_code;
1284
1285
1286
1287
1288 if (cam->buffer_mode == B_vmalloc) {
1289 ret = mcam_check_dma_buffers(cam);
1290 if (ret)
1291 goto out;
1292 }
1293 mcam_set_config_needed(cam, 1);
1294out:
1295 mutex_unlock(&cam->s_mutex);
1296 return ret;
1297}
1298
1299
1300
1301
1302
1303
1304static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1305 struct v4l2_format *f)
1306{
1307 struct mcam_camera *cam = priv;
1308
1309 f->fmt.pix = cam->pix_format;
1310 return 0;
1311}
1312
1313
1314
1315
1316static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1317 struct v4l2_input *input)
1318{
1319 if (input->index != 0)
1320 return -EINVAL;
1321
1322 input->type = V4L2_INPUT_TYPE_CAMERA;
1323 input->std = V4L2_STD_ALL;
1324 strcpy(input->name, "Camera");
1325 return 0;
1326}
1327
1328static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1329{
1330 *i = 0;
1331 return 0;
1332}
1333
1334static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1335{
1336 if (i != 0)
1337 return -EINVAL;
1338 return 0;
1339}
1340
1341
1342static int mcam_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id a)
1343{
1344 return 0;
1345}
1346
1347static int mcam_vidioc_g_std(struct file *filp, void *priv, v4l2_std_id *a)
1348{
1349 *a = V4L2_STD_NTSC_M;
1350 return 0;
1351}
1352
1353
1354
1355
1356
1357static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1358 struct v4l2_streamparm *parms)
1359{
1360 struct mcam_camera *cam = priv;
1361 int ret;
1362
1363 mutex_lock(&cam->s_mutex);
1364 ret = sensor_call(cam, video, g_parm, parms);
1365 mutex_unlock(&cam->s_mutex);
1366 parms->parm.capture.readbuffers = n_dma_bufs;
1367 return ret;
1368}
1369
1370static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1371 struct v4l2_streamparm *parms)
1372{
1373 struct mcam_camera *cam = priv;
1374 int ret;
1375
1376 mutex_lock(&cam->s_mutex);
1377 ret = sensor_call(cam, video, s_parm, parms);
1378 mutex_unlock(&cam->s_mutex);
1379 parms->parm.capture.readbuffers = n_dma_bufs;
1380 return ret;
1381}
1382
1383static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1384 struct v4l2_frmsizeenum *sizes)
1385{
1386 struct mcam_camera *cam = priv;
1387 int ret;
1388
1389 mutex_lock(&cam->s_mutex);
1390 ret = sensor_call(cam, video, enum_framesizes, sizes);
1391 mutex_unlock(&cam->s_mutex);
1392 return ret;
1393}
1394
1395static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1396 struct v4l2_frmivalenum *interval)
1397{
1398 struct mcam_camera *cam = priv;
1399 int ret;
1400
1401 mutex_lock(&cam->s_mutex);
1402 ret = sensor_call(cam, video, enum_frameintervals, interval);
1403 mutex_unlock(&cam->s_mutex);
1404 return ret;
1405}
1406
1407#ifdef CONFIG_VIDEO_ADV_DEBUG
1408static int mcam_vidioc_g_register(struct file *file, void *priv,
1409 struct v4l2_dbg_register *reg)
1410{
1411 struct mcam_camera *cam = priv;
1412
1413 if (reg->reg > cam->regs_size - 4)
1414 return -EINVAL;
1415 reg->val = mcam_reg_read(cam, reg->reg);
1416 reg->size = 4;
1417 return 0;
1418}
1419
1420static int mcam_vidioc_s_register(struct file *file, void *priv,
1421 const struct v4l2_dbg_register *reg)
1422{
1423 struct mcam_camera *cam = priv;
1424
1425 if (reg->reg > cam->regs_size - 4)
1426 return -EINVAL;
1427 mcam_reg_write(cam, reg->reg, reg->val);
1428 return 0;
1429}
1430#endif
1431
1432static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1433 .vidioc_querycap = mcam_vidioc_querycap,
1434 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1435 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1436 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1437 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1438 .vidioc_enum_input = mcam_vidioc_enum_input,
1439 .vidioc_g_input = mcam_vidioc_g_input,
1440 .vidioc_s_input = mcam_vidioc_s_input,
1441 .vidioc_s_std = mcam_vidioc_s_std,
1442 .vidioc_g_std = mcam_vidioc_g_std,
1443 .vidioc_reqbufs = mcam_vidioc_reqbufs,
1444 .vidioc_querybuf = mcam_vidioc_querybuf,
1445 .vidioc_qbuf = mcam_vidioc_qbuf,
1446 .vidioc_dqbuf = mcam_vidioc_dqbuf,
1447 .vidioc_streamon = mcam_vidioc_streamon,
1448 .vidioc_streamoff = mcam_vidioc_streamoff,
1449 .vidioc_g_parm = mcam_vidioc_g_parm,
1450 .vidioc_s_parm = mcam_vidioc_s_parm,
1451 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1452 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1453#ifdef CONFIG_VIDEO_ADV_DEBUG
1454 .vidioc_g_register = mcam_vidioc_g_register,
1455 .vidioc_s_register = mcam_vidioc_s_register,
1456#endif
1457};
1458
1459
1460
1461
1462
1463static int mcam_v4l_open(struct file *filp)
1464{
1465 struct mcam_camera *cam = video_drvdata(filp);
1466 int ret = 0;
1467
1468 filp->private_data = cam;
1469
1470 cam->frame_state.frames = 0;
1471 cam->frame_state.singles = 0;
1472 cam->frame_state.delivered = 0;
1473 mutex_lock(&cam->s_mutex);
1474 if (cam->users == 0) {
1475 ret = mcam_setup_vb2(cam);
1476 if (ret)
1477 goto out;
1478 mcam_ctlr_power_up(cam);
1479 __mcam_cam_reset(cam);
1480 mcam_set_config_needed(cam, 1);
1481 }
1482 (cam->users)++;
1483out:
1484 mutex_unlock(&cam->s_mutex);
1485 return ret;
1486}
1487
1488
1489static int mcam_v4l_release(struct file *filp)
1490{
1491 struct mcam_camera *cam = filp->private_data;
1492
1493 cam_dbg(cam, "Release, %d frames, %d singles, %d delivered\n",
1494 cam->frame_state.frames, cam->frame_state.singles,
1495 cam->frame_state.delivered);
1496 mutex_lock(&cam->s_mutex);
1497 (cam->users)--;
1498 if (cam->users == 0) {
1499 mcam_ctlr_stop_dma(cam);
1500 mcam_cleanup_vb2(cam);
1501 mcam_ctlr_power_down(cam);
1502 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1503 mcam_free_dma_bufs(cam);
1504 }
1505 mutex_unlock(&cam->s_mutex);
1506 return 0;
1507}
1508
1509static ssize_t mcam_v4l_read(struct file *filp,
1510 char __user *buffer, size_t len, loff_t *pos)
1511{
1512 struct mcam_camera *cam = filp->private_data;
1513 int ret;
1514
1515 mutex_lock(&cam->s_mutex);
1516 ret = vb2_read(&cam->vb_queue, buffer, len, pos,
1517 filp->f_flags & O_NONBLOCK);
1518 mutex_unlock(&cam->s_mutex);
1519 return ret;
1520}
1521
1522
1523
1524static unsigned int mcam_v4l_poll(struct file *filp,
1525 struct poll_table_struct *pt)
1526{
1527 struct mcam_camera *cam = filp->private_data;
1528 int ret;
1529
1530 mutex_lock(&cam->s_mutex);
1531 ret = vb2_poll(&cam->vb_queue, filp, pt);
1532 mutex_unlock(&cam->s_mutex);
1533 return ret;
1534}
1535
1536
1537static int mcam_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
1538{
1539 struct mcam_camera *cam = filp->private_data;
1540 int ret;
1541
1542 mutex_lock(&cam->s_mutex);
1543 ret = vb2_mmap(&cam->vb_queue, vma);
1544 mutex_unlock(&cam->s_mutex);
1545 return ret;
1546}
1547
1548
1549
1550static const struct v4l2_file_operations mcam_v4l_fops = {
1551 .owner = THIS_MODULE,
1552 .open = mcam_v4l_open,
1553 .release = mcam_v4l_release,
1554 .read = mcam_v4l_read,
1555 .poll = mcam_v4l_poll,
1556 .mmap = mcam_v4l_mmap,
1557 .unlocked_ioctl = video_ioctl2,
1558};
1559
1560
1561
1562
1563
1564
1565static struct video_device mcam_v4l_template = {
1566 .name = "mcam",
1567 .tvnorms = V4L2_STD_NTSC_M,
1568
1569 .fops = &mcam_v4l_fops,
1570 .ioctl_ops = &mcam_v4l_ioctl_ops,
1571 .release = video_device_release_empty,
1572};
1573
1574
1575
1576
1577
1578static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1579{
1580
1581
1582
1583 set_bit(frame, &cam->flags);
1584 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1585 cam->next_buf = frame;
1586 cam->buf_seq[frame] = ++(cam->sequence);
1587 cam->frame_state.frames++;
1588
1589
1590
1591 if (cam->state != S_STREAMING)
1592 return;
1593
1594
1595
1596 cam->frame_complete(cam, frame);
1597}
1598
1599
1600
1601
1602
1603
1604int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1605{
1606 unsigned int frame, handled = 0;
1607
1608 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619 for (frame = 0; frame < cam->nbufs; frame++)
1620 if (irqs & (IRQ_EOF0 << frame)) {
1621 mcam_frame_complete(cam, frame);
1622 handled = 1;
1623 if (cam->buffer_mode == B_DMA_sg)
1624 break;
1625 }
1626
1627
1628
1629
1630
1631 if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2)) {
1632 set_bit(CF_DMA_ACTIVE, &cam->flags);
1633 handled = 1;
1634 if (cam->buffer_mode == B_DMA_sg)
1635 mcam_ctlr_stop(cam);
1636 }
1637 return handled;
1638}
1639
1640
1641
1642
1643
1644static struct ov7670_config sensor_cfg = {
1645
1646
1647
1648
1649 .min_width = 320,
1650 .min_height = 240,
1651};
1652
1653
1654int mccic_register(struct mcam_camera *cam)
1655{
1656 struct i2c_board_info ov7670_info = {
1657 .type = "ov7670",
1658 .addr = 0x42 >> 1,
1659 .platform_data = &sensor_cfg,
1660 };
1661 int ret;
1662
1663
1664
1665
1666 if (buffer_mode >= 0)
1667 cam->buffer_mode = buffer_mode;
1668 if (cam->buffer_mode == B_DMA_sg &&
1669 cam->chip_id == MCAM_CAFE) {
1670 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1671 "attempting vmalloc mode instead\n");
1672 cam->buffer_mode = B_vmalloc;
1673 }
1674 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1675 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1676 cam->buffer_mode);
1677 return -EINVAL;
1678 }
1679
1680
1681
1682 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1683 if (ret)
1684 return ret;
1685
1686 mutex_init(&cam->s_mutex);
1687 cam->state = S_NOTREADY;
1688 mcam_set_config_needed(cam, 1);
1689 cam->pix_format = mcam_def_pix_format;
1690 cam->mbus_code = mcam_def_mbus_code;
1691 INIT_LIST_HEAD(&cam->buffers);
1692 mcam_ctlr_init(cam);
1693
1694
1695
1696
1697 sensor_cfg.clock_speed = cam->clock_speed;
1698 sensor_cfg.use_smbus = cam->use_smbus;
1699 cam->sensor_addr = ov7670_info.addr;
1700 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
1701 cam->i2c_adapter, &ov7670_info, NULL);
1702 if (cam->sensor == NULL) {
1703 ret = -ENODEV;
1704 goto out_unregister;
1705 }
1706
1707 ret = mcam_cam_init(cam);
1708 if (ret)
1709 goto out_unregister;
1710
1711
1712
1713 ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1714 if (ret)
1715 goto out_unregister;
1716 cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1717
1718 mutex_lock(&cam->s_mutex);
1719 cam->vdev = mcam_v4l_template;
1720 cam->vdev.debug = 0;
1721 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1722 video_set_drvdata(&cam->vdev, cam);
1723 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1724 if (ret)
1725 goto out;
1726
1727
1728
1729
1730 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
1731 if (mcam_alloc_dma_bufs(cam, 1))
1732 cam_warn(cam, "Unable to alloc DMA buffers at load"
1733 " will try again later.");
1734 }
1735
1736out:
1737 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1738 mutex_unlock(&cam->s_mutex);
1739 return ret;
1740out_unregister:
1741 v4l2_device_unregister(&cam->v4l2_dev);
1742 return ret;
1743}
1744
1745
1746void mccic_shutdown(struct mcam_camera *cam)
1747{
1748
1749
1750
1751
1752
1753
1754 if (cam->users > 0) {
1755 cam_warn(cam, "Removing a device with users!\n");
1756 mcam_ctlr_power_down(cam);
1757 }
1758 vb2_queue_release(&cam->vb_queue);
1759 if (cam->buffer_mode == B_vmalloc)
1760 mcam_free_dma_bufs(cam);
1761 video_unregister_device(&cam->vdev);
1762 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1763 v4l2_device_unregister(&cam->v4l2_dev);
1764}
1765
1766
1767
1768
1769#ifdef CONFIG_PM
1770
1771void mccic_suspend(struct mcam_camera *cam)
1772{
1773 mutex_lock(&cam->s_mutex);
1774 if (cam->users > 0) {
1775 enum mcam_state cstate = cam->state;
1776
1777 mcam_ctlr_stop_dma(cam);
1778 mcam_ctlr_power_down(cam);
1779 cam->state = cstate;
1780 }
1781 mutex_unlock(&cam->s_mutex);
1782}
1783
1784int mccic_resume(struct mcam_camera *cam)
1785{
1786 int ret = 0;
1787
1788 mutex_lock(&cam->s_mutex);
1789 if (cam->users > 0) {
1790 mcam_ctlr_power_up(cam);
1791 __mcam_cam_reset(cam);
1792 } else {
1793 mcam_ctlr_power_down(cam);
1794 }
1795 mutex_unlock(&cam->s_mutex);
1796
1797 set_bit(CF_CONFIG_NEEDED, &cam->flags);
1798 if (cam->state == S_STREAMING) {
1799
1800
1801
1802
1803 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1804 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
1805 ret = mcam_read_setup(cam);
1806 }
1807 return ret;
1808}
1809#endif
1810