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42
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/module.h>
46#include <linux/pnp.h>
47#include <linux/interrupt.h>
48#include <linux/timer.h>
49#include <linux/leds.h>
50#include <linux/spinlock.h>
51#include <linux/pci_ids.h>
52#include <linux/io.h>
53#include <linux/bitrev.h>
54#include <linux/slab.h>
55#include <linux/wait.h>
56#include <linux/sched.h>
57#include <media/rc-core.h>
58
59#define DRVNAME "winbond-cir"
60
61
62#define WBCIR_REG_WCEIR_CTL 0x03
63#define WBCIR_REG_WCEIR_STS 0x04
64#define WBCIR_REG_WCEIR_EV_EN 0x05
65#define WBCIR_REG_WCEIR_CNTL 0x06
66#define WBCIR_REG_WCEIR_CNTH 0x07
67#define WBCIR_REG_WCEIR_INDEX 0x08
68#define WBCIR_REG_WCEIR_DATA 0x09
69#define WBCIR_REG_WCEIR_CSL 0x0A
70#define WBCIR_REG_WCEIR_CFG1 0x0B
71#define WBCIR_REG_WCEIR_CFG2 0x0C
72
73
74#define WBCIR_REG_ECEIR_CTS 0x00
75#define WBCIR_REG_ECEIR_CCTL 0x01
76#define WBCIR_REG_ECEIR_CNT_LO 0x02
77#define WBCIR_REG_ECEIR_CNT_HI 0x03
78#define WBCIR_REG_ECEIR_IREM 0x04
79
80
81#define WBCIR_REG_SP3_BSR 0x03
82
83#define WBCIR_REG_SP3_RXDATA 0x00
84#define WBCIR_REG_SP3_TXDATA 0x00
85#define WBCIR_REG_SP3_IER 0x01
86#define WBCIR_REG_SP3_EIR 0x02
87#define WBCIR_REG_SP3_FCR 0x02
88#define WBCIR_REG_SP3_MCR 0x04
89#define WBCIR_REG_SP3_LSR 0x05
90#define WBCIR_REG_SP3_MSR 0x06
91#define WBCIR_REG_SP3_ASCR 0x07
92
93#define WBCIR_REG_SP3_BGDL 0x00
94#define WBCIR_REG_SP3_BGDH 0x01
95#define WBCIR_REG_SP3_EXCR1 0x02
96#define WBCIR_REG_SP3_EXCR2 0x04
97#define WBCIR_REG_SP3_TXFLV 0x06
98#define WBCIR_REG_SP3_RXFLV 0x07
99
100#define WBCIR_REG_SP3_MRID 0x00
101#define WBCIR_REG_SP3_SH_LCR 0x01
102#define WBCIR_REG_SP3_SH_FCR 0x02
103
104#define WBCIR_REG_SP3_IRCR1 0x02
105
106#define WBCIR_REG_SP3_IRCR2 0x04
107
108#define WBCIR_REG_SP3_IRCR3 0x00
109#define WBCIR_REG_SP3_SIR_PW 0x02
110
111#define WBCIR_REG_SP3_IRRXDC 0x00
112#define WBCIR_REG_SP3_IRTXMC 0x01
113#define WBCIR_REG_SP3_RCCFG 0x02
114#define WBCIR_REG_SP3_IRCFG1 0x04
115#define WBCIR_REG_SP3_IRCFG4 0x07
116
117
118
119
120
121
122#define WBCIR_IRQ_NONE 0x00
123
124#define WBCIR_IRQ_RX 0x01
125
126#define WBCIR_IRQ_TX_LOW 0x02
127
128#define WBCIR_IRQ_ERR 0x04
129
130#define WBCIR_IRQ_TX_EMPTY 0x20
131
132#define WBCIR_LED_ENABLE 0x80
133
134#define WBCIR_RX_AVAIL 0x01
135
136#define WBCIR_RX_OVERRUN 0x02
137
138#define WBCIR_TX_EOT 0x04
139
140#define WBCIR_RX_DISABLE 0x20
141
142#define WBCIR_TX_UNDERRUN 0x40
143
144#define WBCIR_EXT_ENABLE 0x01
145
146#define WBCIR_REGSEL_COMPARE 0x10
147
148#define WBCIR_REGSEL_MASK 0x20
149
150#define WBCIR_REG_ADDR0 0x00
151
152#define WBCIR_CNTR_EN 0x01
153
154#define WBCIR_CNTR_R 0x02
155
156#define WBCIR_IRTX_INV 0x04
157
158#define WBCIR_RX_T_OV 0x40
159
160
161enum wbcir_bank {
162 WBCIR_BANK_0 = 0x00,
163 WBCIR_BANK_1 = 0x80,
164 WBCIR_BANK_2 = 0xE0,
165 WBCIR_BANK_3 = 0xE4,
166 WBCIR_BANK_4 = 0xE8,
167 WBCIR_BANK_5 = 0xEC,
168 WBCIR_BANK_6 = 0xF0,
169 WBCIR_BANK_7 = 0xF4,
170};
171
172
173enum wbcir_protocol {
174 IR_PROTOCOL_RC5 = 0x0,
175 IR_PROTOCOL_NEC = 0x1,
176 IR_PROTOCOL_RC6 = 0x2,
177};
178
179
180enum wbcir_rxstate {
181 WBCIR_RXSTATE_INACTIVE = 0,
182 WBCIR_RXSTATE_ACTIVE,
183 WBCIR_RXSTATE_ERROR
184};
185
186
187enum wbcir_txstate {
188 WBCIR_TXSTATE_INACTIVE = 0,
189 WBCIR_TXSTATE_ACTIVE,
190 WBCIR_TXSTATE_ERROR
191};
192
193
194#define WBCIR_NAME "Winbond CIR"
195#define WBCIR_ID_FAMILY 0xF1
196#define WBCIR_ID_CHIP 0x04
197#define INVALID_SCANCODE 0x7FFFFFFF
198#define WAKEUP_IOMEM_LEN 0x10
199#define EHFUNC_IOMEM_LEN 0x10
200#define SP_IOMEM_LEN 0x08
201
202
203struct wbcir_data {
204 spinlock_t spinlock;
205 struct rc_dev *dev;
206 struct led_classdev led;
207
208 unsigned long wbase;
209 unsigned long ebase;
210 unsigned long sbase;
211 unsigned int irq;
212 u8 irqmask;
213
214
215 enum wbcir_rxstate rxstate;
216 struct led_trigger *rxtrigger;
217 int carrier_report_enabled;
218 u32 pulse_duration;
219
220
221 enum wbcir_txstate txstate;
222 struct led_trigger *txtrigger;
223 u32 txlen;
224 u32 txoff;
225 u32 *txbuf;
226 u8 txmask;
227 u32 txcarrier;
228};
229
230static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
231module_param(protocol, uint, 0444);
232MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
233 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
234
235static bool invert;
236module_param(invert, bool, 0444);
237MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
238
239static bool txandrx;
240module_param(txandrx, bool, 0444);
241MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
242
243static unsigned int wake_sc = 0x800F040C;
244module_param(wake_sc, uint, 0644);
245MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
246
247static unsigned int wake_rc6mode = 6;
248module_param(wake_rc6mode, uint, 0644);
249MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
250 "(0 = 0, 6 = 6A, default)");
251
252
253
254
255
256
257
258
259
260
261static void
262wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
263{
264 u8 val;
265
266 val = inb(addr);
267 val = ((val & ~mask) | (bits & mask));
268 outb(val, addr);
269}
270
271
272static inline void
273wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
274{
275 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
276}
277
278static inline void
279wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
280{
281 if (data->irqmask == irqmask)
282 return;
283
284 wbcir_select_bank(data, WBCIR_BANK_0);
285 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
286 data->irqmask = irqmask;
287}
288
289static enum led_brightness
290wbcir_led_brightness_get(struct led_classdev *led_cdev)
291{
292 struct wbcir_data *data = container_of(led_cdev,
293 struct wbcir_data,
294 led);
295
296 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
297 return LED_FULL;
298 else
299 return LED_OFF;
300}
301
302static void
303wbcir_led_brightness_set(struct led_classdev *led_cdev,
304 enum led_brightness brightness)
305{
306 struct wbcir_data *data = container_of(led_cdev,
307 struct wbcir_data,
308 led);
309
310 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
311 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
312 WBCIR_LED_ENABLE);
313}
314
315
316static u8
317wbcir_to_rc6cells(u8 val)
318{
319 u8 coded = 0x00;
320 int i;
321
322 val &= 0x0F;
323 for (i = 0; i < 4; i++) {
324 if (val & 0x01)
325 coded |= 0x02 << (i * 2);
326 else
327 coded |= 0x01 << (i * 2);
328 val >>= 1;
329 }
330
331 return coded;
332}
333
334
335
336
337
338
339
340static void
341wbcir_carrier_report(struct wbcir_data *data)
342{
343 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
344 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
345
346 if (counter > 0 && counter < 0xffff) {
347 DEFINE_IR_RAW_EVENT(ev);
348
349 ev.carrier_report = 1;
350 ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u,
351 data->pulse_duration);
352
353 ir_raw_event_store(data->dev, &ev);
354 }
355
356
357 data->pulse_duration = 0;
358 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
359 WBCIR_CNTR_EN | WBCIR_CNTR_R);
360 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
361 WBCIR_CNTR_EN | WBCIR_CNTR_R);
362}
363
364static void
365wbcir_idle_rx(struct rc_dev *dev, bool idle)
366{
367 struct wbcir_data *data = dev->priv;
368
369 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
370 data->rxstate = WBCIR_RXSTATE_ACTIVE;
371 led_trigger_event(data->rxtrigger, LED_FULL);
372 }
373
374 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
375 data->rxstate = WBCIR_RXSTATE_INACTIVE;
376 led_trigger_event(data->rxtrigger, LED_OFF);
377
378 if (data->carrier_report_enabled)
379 wbcir_carrier_report(data);
380
381
382 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
383 }
384}
385
386static void
387wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
388{
389 u8 irdata;
390 DEFINE_IR_RAW_EVENT(rawir);
391 unsigned duration;
392
393
394 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
395 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
396 if (data->rxstate == WBCIR_RXSTATE_ERROR)
397 continue;
398
399 duration = ((irdata & 0x7F) + 1) *
400 (data->carrier_report_enabled ? 2 : 10);
401 rawir.pulse = irdata & 0x80 ? false : true;
402 rawir.duration = US_TO_NS(duration);
403
404 if (rawir.pulse)
405 data->pulse_duration += duration;
406
407 ir_raw_event_store_with_filter(data->dev, &rawir);
408 }
409
410 ir_raw_event_handle(data->dev);
411}
412
413static void
414wbcir_irq_tx(struct wbcir_data *data)
415{
416 unsigned int space;
417 unsigned int used;
418 u8 bytes[16];
419 u8 byte;
420
421 if (!data->txbuf)
422 return;
423
424 switch (data->txstate) {
425 case WBCIR_TXSTATE_INACTIVE:
426
427 space = 16;
428 led_trigger_event(data->txtrigger, LED_FULL);
429 break;
430 case WBCIR_TXSTATE_ACTIVE:
431
432 space = 13;
433 break;
434 case WBCIR_TXSTATE_ERROR:
435 space = 0;
436 break;
437 default:
438 return;
439 }
440
441
442
443
444
445
446 for (used = 0; used < space && data->txoff != data->txlen; used++) {
447 if (data->txbuf[data->txoff] == 0) {
448 data->txoff++;
449 continue;
450 }
451 byte = min((u32)0x80, data->txbuf[data->txoff]);
452 data->txbuf[data->txoff] -= byte;
453 byte--;
454 byte |= (data->txoff % 2 ? 0x80 : 0x00);
455 bytes[used] = byte;
456 }
457
458 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
459 data->txoff++;
460
461 if (used == 0) {
462
463 if (data->txstate == WBCIR_TXSTATE_ERROR)
464
465 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
466 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
467 led_trigger_event(data->txtrigger, LED_OFF);
468 kfree(data->txbuf);
469 data->txbuf = NULL;
470 data->txstate = WBCIR_TXSTATE_INACTIVE;
471 } else if (data->txoff == data->txlen) {
472
473 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
474 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
475 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
476 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
477 WBCIR_IRQ_TX_EMPTY);
478 } else {
479
480 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
481 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
482 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
483 WBCIR_IRQ_TX_LOW);
484 data->txstate = WBCIR_TXSTATE_ACTIVE;
485 }
486 }
487}
488
489static irqreturn_t
490wbcir_irq_handler(int irqno, void *cookie)
491{
492 struct pnp_dev *device = cookie;
493 struct wbcir_data *data = pnp_get_drvdata(device);
494 unsigned long flags;
495 u8 status;
496
497 spin_lock_irqsave(&data->spinlock, flags);
498 wbcir_select_bank(data, WBCIR_BANK_0);
499 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
500 status &= data->irqmask;
501
502 if (!status) {
503 spin_unlock_irqrestore(&data->spinlock, flags);
504 return IRQ_NONE;
505 }
506
507 if (status & WBCIR_IRQ_ERR) {
508
509 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
510 data->rxstate = WBCIR_RXSTATE_ERROR;
511 ir_raw_event_reset(data->dev);
512 }
513
514
515 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
516 data->txstate = WBCIR_TXSTATE_ERROR;
517 }
518
519 if (status & WBCIR_IRQ_RX)
520 wbcir_irq_rx(data, device);
521
522 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
523 wbcir_irq_tx(data);
524
525 spin_unlock_irqrestore(&data->spinlock, flags);
526 return IRQ_HANDLED;
527}
528
529
530
531
532
533
534
535static int
536wbcir_set_carrier_report(struct rc_dev *dev, int enable)
537{
538 struct wbcir_data *data = dev->priv;
539 unsigned long flags;
540
541 spin_lock_irqsave(&data->spinlock, flags);
542
543 if (data->carrier_report_enabled == enable) {
544 spin_unlock_irqrestore(&data->spinlock, flags);
545 return 0;
546 }
547
548 data->pulse_duration = 0;
549 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
550 WBCIR_CNTR_EN | WBCIR_CNTR_R);
551
552 if (enable && data->dev->idle)
553 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
554 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R);
555
556
557 wbcir_select_bank(data, WBCIR_BANK_2);
558 data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10);
559 outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
560 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
561
562
563 wbcir_select_bank(data, WBCIR_BANK_7);
564 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG,
565 enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV);
566
567 data->carrier_report_enabled = enable;
568 spin_unlock_irqrestore(&data->spinlock, flags);
569
570 return 0;
571}
572
573static int
574wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
575{
576 struct wbcir_data *data = dev->priv;
577 unsigned long flags;
578 u8 val;
579 u32 freq;
580
581 freq = DIV_ROUND_CLOSEST(carrier, 1000);
582 if (freq < 30 || freq > 60)
583 return -EINVAL;
584
585 switch (freq) {
586 case 58:
587 case 59:
588 case 60:
589 val = freq - 58;
590 freq *= 1000;
591 break;
592 case 57:
593 val = freq - 27;
594 freq = 56900;
595 break;
596 default:
597 val = freq - 27;
598 freq *= 1000;
599 break;
600 }
601
602 spin_lock_irqsave(&data->spinlock, flags);
603 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
604 spin_unlock_irqrestore(&data->spinlock, flags);
605 return -EBUSY;
606 }
607
608 if (data->txcarrier != freq) {
609 wbcir_select_bank(data, WBCIR_BANK_7);
610 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
611 data->txcarrier = freq;
612 }
613
614 spin_unlock_irqrestore(&data->spinlock, flags);
615 return 0;
616}
617
618static int
619wbcir_txmask(struct rc_dev *dev, u32 mask)
620{
621 struct wbcir_data *data = dev->priv;
622 unsigned long flags;
623 u8 val;
624
625
626 switch (mask) {
627 case 0x1:
628 val = 0x0;
629 break;
630 case 0x2:
631 val = 0x1;
632 break;
633 case 0x4:
634 val = 0x2;
635 break;
636 case 0x8:
637 val = 0x3;
638 break;
639 default:
640 return -EINVAL;
641 }
642
643 spin_lock_irqsave(&data->spinlock, flags);
644 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
645 spin_unlock_irqrestore(&data->spinlock, flags);
646 return -EBUSY;
647 }
648
649 if (data->txmask != mask) {
650 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
651 data->txmask = mask;
652 }
653
654 spin_unlock_irqrestore(&data->spinlock, flags);
655 return 0;
656}
657
658static int
659wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
660{
661 struct wbcir_data *data = dev->priv;
662 unsigned *buf;
663 unsigned i;
664 unsigned long flags;
665
666 buf = kmalloc(count * sizeof(*b), GFP_KERNEL);
667 if (!buf)
668 return -ENOMEM;
669
670
671 for (i = 0; i < count; i++)
672 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
673
674
675 spin_lock_irqsave(&data->spinlock, flags);
676 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
677 spin_unlock_irqrestore(&data->spinlock, flags);
678 kfree(buf);
679 return -EBUSY;
680 }
681
682
683 data->txbuf = buf;
684 data->txlen = count;
685 data->txoff = 0;
686 wbcir_irq_tx(data);
687
688
689 spin_unlock_irqrestore(&data->spinlock, flags);
690 return count;
691}
692
693
694
695
696
697
698
699static void
700wbcir_shutdown(struct pnp_dev *device)
701{
702 struct device *dev = &device->dev;
703 struct wbcir_data *data = pnp_get_drvdata(device);
704 bool do_wake = true;
705 u8 match[11];
706 u8 mask[11];
707 u8 rc6_csl = 0;
708 int i;
709
710 memset(match, 0, sizeof(match));
711 memset(mask, 0, sizeof(mask));
712
713 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
714 do_wake = false;
715 goto finish;
716 }
717
718 switch (protocol) {
719 case IR_PROTOCOL_RC5:
720 if (wake_sc > 0xFFF) {
721 do_wake = false;
722 dev_err(dev, "RC5 - Invalid wake scancode\n");
723 break;
724 }
725
726
727 mask[0] = 0xFF;
728 mask[1] = 0x17;
729
730 match[0] = (wake_sc & 0x003F);
731 match[0] |= (wake_sc & 0x0180) >> 1;
732 match[1] = (wake_sc & 0x0E00) >> 9;
733 if (!(wake_sc & 0x0040))
734 match[1] |= 0x10;
735
736 break;
737
738 case IR_PROTOCOL_NEC:
739 if (wake_sc > 0xFFFFFF) {
740 do_wake = false;
741 dev_err(dev, "NEC - Invalid wake scancode\n");
742 break;
743 }
744
745 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
746
747 match[1] = bitrev8((wake_sc & 0xFF));
748 match[0] = ~match[1];
749
750 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
751 if (wake_sc > 0xFFFF)
752 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
753 else
754 match[2] = ~match[3];
755
756 break;
757
758 case IR_PROTOCOL_RC6:
759
760 if (wake_rc6mode == 0) {
761 if (wake_sc > 0xFFFF) {
762 do_wake = false;
763 dev_err(dev, "RC6 - Invalid wake scancode\n");
764 break;
765 }
766
767
768 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
769 mask[0] = 0xFF;
770 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
771 mask[1] = 0xFF;
772
773
774 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
775 mask[2] = 0xFF;
776 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
777 mask[3] = 0xFF;
778
779
780 match[4] = 0x50;
781 mask[4] = 0xF0;
782 match[5] = 0x09;
783 mask[5] = 0x0F;
784
785 rc6_csl = 44;
786
787 } else if (wake_rc6mode == 6) {
788 i = 0;
789
790
791 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
792 mask[i++] = 0xFF;
793 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
794 mask[i++] = 0xFF;
795
796
797 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
798 mask[i++] = 0xFF;
799 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
800 mask[i++] = 0x3F;
801
802
803 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
804 mask[i++] = 0xFF;
805 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
806 mask[i++] = 0xFF;
807
808 if (wake_sc & 0x80000000) {
809
810 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
811 mask[i++] = 0xFF;
812 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
813 mask[i++] = 0xFF;
814 rc6_csl = 76;
815 } else if (wake_sc <= 0x007FFFFF) {
816 rc6_csl = 60;
817 } else {
818 do_wake = false;
819 dev_err(dev, "RC6 - Invalid wake scancode\n");
820 break;
821 }
822
823
824 match[i] = 0x93;
825 mask[i++] = 0xFF;
826 match[i] = 0x0A;
827 mask[i++] = 0x0F;
828
829 } else {
830 do_wake = false;
831 dev_err(dev, "RC6 - Invalid wake mode\n");
832 }
833
834 break;
835
836 default:
837 do_wake = false;
838 break;
839 }
840
841finish:
842 if (do_wake) {
843
844 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
845 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
846 0x3F);
847 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
848 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
849 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
850 0x3F);
851 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
852
853
854 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
855
856
857 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
858
859
860 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
861
862
863 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
864
865 } else {
866
867 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
868
869
870 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
871 }
872
873
874
875
876
877
878
879 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
880 disable_irq(data->irq);
881
882
883 led_trigger_event(data->rxtrigger, LED_OFF);
884 led_trigger_event(data->txtrigger, LED_OFF);
885}
886
887static int
888wbcir_suspend(struct pnp_dev *device, pm_message_t state)
889{
890 wbcir_shutdown(device);
891 return 0;
892}
893
894static void
895wbcir_init_hw(struct wbcir_data *data)
896{
897 u8 tmp;
898
899
900 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
901
902
903 tmp = protocol << 4;
904 if (invert)
905 tmp |= 0x08;
906 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
907
908
909 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
910
911
912 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
913
914
915 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
916
917
918 if (invert)
919 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
920 else
921 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
922
923
924
925
926
927 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
928 data->txmask = 0x1;
929
930
931 wbcir_select_bank(data, WBCIR_BANK_2);
932 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
933
934
935
936
937
938
939
940
941
942
943
944
945
946 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
947
948
949 outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
950 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
951
952
953 wbcir_select_bank(data, WBCIR_BANK_0);
954 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
955 inb(data->sbase + WBCIR_REG_SP3_LSR);
956 inb(data->sbase + WBCIR_REG_SP3_MSR);
957
958
959 wbcir_select_bank(data, WBCIR_BANK_7);
960 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
961
962
963 wbcir_select_bank(data, WBCIR_BANK_4);
964 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
965
966
967 wbcir_select_bank(data, WBCIR_BANK_5);
968 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
969
970
971 wbcir_select_bank(data, WBCIR_BANK_6);
972 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
973
974
975 wbcir_select_bank(data, WBCIR_BANK_7);
976 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
977
978
979 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
980 data->txcarrier = 36000;
981
982
983 if (invert)
984 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
985 else
986 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
987
988
989 wbcir_select_bank(data, WBCIR_BANK_0);
990 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
991
992
993 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
994
995
996 data->rxstate = WBCIR_RXSTATE_INACTIVE;
997 ir_raw_event_reset(data->dev);
998 ir_raw_event_set_idle(data->dev, true);
999
1000
1001 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
1002 kfree(data->txbuf);
1003 data->txbuf = NULL;
1004 data->txstate = WBCIR_TXSTATE_INACTIVE;
1005 }
1006
1007
1008 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
1009}
1010
1011static int
1012wbcir_resume(struct pnp_dev *device)
1013{
1014 struct wbcir_data *data = pnp_get_drvdata(device);
1015
1016 wbcir_init_hw(data);
1017 enable_irq(data->irq);
1018
1019 return 0;
1020}
1021
1022static int
1023wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
1024{
1025 struct device *dev = &device->dev;
1026 struct wbcir_data *data;
1027 int err;
1028
1029 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
1030 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
1031 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
1032 dev_err(dev, "Invalid resources\n");
1033 return -ENODEV;
1034 }
1035
1036 data = kzalloc(sizeof(*data), GFP_KERNEL);
1037 if (!data) {
1038 err = -ENOMEM;
1039 goto exit;
1040 }
1041
1042 pnp_set_drvdata(device, data);
1043
1044 spin_lock_init(&data->spinlock);
1045 data->ebase = pnp_port_start(device, 0);
1046 data->wbase = pnp_port_start(device, 1);
1047 data->sbase = pnp_port_start(device, 2);
1048 data->irq = pnp_irq(device, 0);
1049
1050 if (data->wbase == 0 || data->ebase == 0 ||
1051 data->sbase == 0 || data->irq == 0) {
1052 err = -ENODEV;
1053 dev_err(dev, "Invalid resources\n");
1054 goto exit_free_data;
1055 }
1056
1057 dev_dbg(&device->dev, "Found device "
1058 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1059 data->wbase, data->ebase, data->sbase, data->irq);
1060
1061 led_trigger_register_simple("cir-tx", &data->txtrigger);
1062 if (!data->txtrigger) {
1063 err = -ENOMEM;
1064 goto exit_free_data;
1065 }
1066
1067 led_trigger_register_simple("cir-rx", &data->rxtrigger);
1068 if (!data->rxtrigger) {
1069 err = -ENOMEM;
1070 goto exit_unregister_txtrigger;
1071 }
1072
1073 data->led.name = "cir::activity";
1074 data->led.default_trigger = "cir-rx";
1075 data->led.brightness_set = wbcir_led_brightness_set;
1076 data->led.brightness_get = wbcir_led_brightness_get;
1077 err = led_classdev_register(&device->dev, &data->led);
1078 if (err)
1079 goto exit_unregister_rxtrigger;
1080
1081 data->dev = rc_allocate_device();
1082 if (!data->dev) {
1083 err = -ENOMEM;
1084 goto exit_unregister_led;
1085 }
1086
1087 data->dev->driver_type = RC_DRIVER_IR_RAW;
1088 data->dev->driver_name = DRVNAME;
1089 data->dev->input_name = WBCIR_NAME;
1090 data->dev->input_phys = "wbcir/cir0";
1091 data->dev->input_id.bustype = BUS_HOST;
1092 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1093 data->dev->input_id.product = WBCIR_ID_FAMILY;
1094 data->dev->input_id.version = WBCIR_ID_CHIP;
1095 data->dev->map_name = RC_MAP_RC6_MCE;
1096 data->dev->s_idle = wbcir_idle_rx;
1097 data->dev->s_carrier_report = wbcir_set_carrier_report;
1098 data->dev->s_tx_mask = wbcir_txmask;
1099 data->dev->s_tx_carrier = wbcir_txcarrier;
1100 data->dev->tx_ir = wbcir_tx;
1101 data->dev->priv = data;
1102 data->dev->dev.parent = &device->dev;
1103 data->dev->timeout = MS_TO_NS(100);
1104 data->dev->rx_resolution = US_TO_NS(2);
1105 data->dev->allowed_protos = RC_BIT_ALL;
1106
1107 err = rc_register_device(data->dev);
1108 if (err)
1109 goto exit_free_rc;
1110
1111 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1112 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1113 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1114 err = -EBUSY;
1115 goto exit_unregister_device;
1116 }
1117
1118 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1119 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1120 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1121 err = -EBUSY;
1122 goto exit_release_wbase;
1123 }
1124
1125 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1126 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1127 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1128 err = -EBUSY;
1129 goto exit_release_ebase;
1130 }
1131
1132 err = request_irq(data->irq, wbcir_irq_handler,
1133 IRQF_DISABLED, DRVNAME, device);
1134 if (err) {
1135 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1136 err = -EBUSY;
1137 goto exit_release_sbase;
1138 }
1139
1140 device_init_wakeup(&device->dev, 1);
1141
1142 wbcir_init_hw(data);
1143
1144 return 0;
1145
1146exit_release_sbase:
1147 release_region(data->sbase, SP_IOMEM_LEN);
1148exit_release_ebase:
1149 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1150exit_release_wbase:
1151 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1152exit_unregister_device:
1153 rc_unregister_device(data->dev);
1154 data->dev = NULL;
1155exit_free_rc:
1156 rc_free_device(data->dev);
1157exit_unregister_led:
1158 led_classdev_unregister(&data->led);
1159exit_unregister_rxtrigger:
1160 led_trigger_unregister_simple(data->rxtrigger);
1161exit_unregister_txtrigger:
1162 led_trigger_unregister_simple(data->txtrigger);
1163exit_free_data:
1164 kfree(data);
1165 pnp_set_drvdata(device, NULL);
1166exit:
1167 return err;
1168}
1169
1170static void
1171wbcir_remove(struct pnp_dev *device)
1172{
1173 struct wbcir_data *data = pnp_get_drvdata(device);
1174
1175
1176 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1177 free_irq(data->irq, device);
1178
1179
1180 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1181
1182
1183 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1184
1185
1186 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1187
1188 rc_unregister_device(data->dev);
1189
1190 led_trigger_unregister_simple(data->rxtrigger);
1191 led_trigger_unregister_simple(data->txtrigger);
1192 led_classdev_unregister(&data->led);
1193
1194
1195 wbcir_led_brightness_set(&data->led, LED_OFF);
1196
1197 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1198 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1199 release_region(data->sbase, SP_IOMEM_LEN);
1200
1201 kfree(data);
1202
1203 pnp_set_drvdata(device, NULL);
1204}
1205
1206static const struct pnp_device_id wbcir_ids[] = {
1207 { "WEC1022", 0 },
1208 { "", 0 }
1209};
1210MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1211
1212static struct pnp_driver wbcir_driver = {
1213 .name = WBCIR_NAME,
1214 .id_table = wbcir_ids,
1215 .probe = wbcir_probe,
1216 .remove = wbcir_remove,
1217 .suspend = wbcir_suspend,
1218 .resume = wbcir_resume,
1219 .shutdown = wbcir_shutdown
1220};
1221
1222static int __init
1223wbcir_init(void)
1224{
1225 int ret;
1226
1227 switch (protocol) {
1228 case IR_PROTOCOL_RC5:
1229 case IR_PROTOCOL_NEC:
1230 case IR_PROTOCOL_RC6:
1231 break;
1232 default:
1233 pr_err("Invalid power-on protocol\n");
1234 }
1235
1236 ret = pnp_register_driver(&wbcir_driver);
1237 if (ret)
1238 pr_err("Unable to register driver\n");
1239
1240 return ret;
1241}
1242
1243static void __exit
1244wbcir_exit(void)
1245{
1246 pnp_unregister_driver(&wbcir_driver);
1247}
1248
1249module_init(wbcir_init);
1250module_exit(wbcir_exit);
1251
1252MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1253MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1254MODULE_LICENSE("GPL");
1255