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16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/dma-mapping.h>
21#include <linux/slab.h>
22#include <linux/scatterlist.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25
26#include <linux/leds.h>
27
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/card.h>
31#include <linux/mmc/slot-gpio.h>
32
33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
36
37#define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55static void sdhci_tuning_timer(unsigned long data);
56static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57
58#ifdef CONFIG_PM_RUNTIME
59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
78#endif
79
80static void sdhci_dumpregs(struct sdhci_host *host)
81{
82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
83 mmc_hostname(host->mmc));
84
85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
113 sdhci_readl(host, SDHCI_CAPABILITIES),
114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
116 sdhci_readw(host, SDHCI_COMMAND),
117 sdhci_readl(host, SDHCI_MAX_CURRENT));
118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120
121 if (host->flags & SDHCI_USE_ADMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
125
126 pr_debug(DRIVER_NAME ": ===========================================\n");
127}
128
129
130
131
132
133
134
135static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
136{
137 u32 ier;
138
139 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
140 ier &= ~clear;
141 ier |= set;
142 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
143 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
144}
145
146static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
147{
148 sdhci_clear_set_irqs(host, 0, irqs);
149}
150
151static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
152{
153 sdhci_clear_set_irqs(host, irqs, 0);
154}
155
156static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157{
158 u32 present, irqs;
159
160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
161 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
162 return;
163
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
166 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
167
168 if (enable)
169 sdhci_unmask_irqs(host, irqs);
170 else
171 sdhci_mask_irqs(host, irqs);
172}
173
174static void sdhci_enable_card_detection(struct sdhci_host *host)
175{
176 sdhci_set_card_detection(host, true);
177}
178
179static void sdhci_disable_card_detection(struct sdhci_host *host)
180{
181 sdhci_set_card_detection(host, false);
182}
183
184static void sdhci_reset(struct sdhci_host *host, u8 mask)
185{
186 unsigned long timeout;
187 u32 uninitialized_var(ier);
188
189 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
190 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
191 SDHCI_CARD_PRESENT))
192 return;
193 }
194
195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
197
198 if (host->ops->platform_reset_enter)
199 host->ops->platform_reset_enter(host, mask);
200
201 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
202
203 if (mask & SDHCI_RESET_ALL) {
204 host->clock = 0;
205
206 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
207 sdhci_runtime_pm_bus_off(host);
208 }
209
210
211 timeout = 100;
212
213
214 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
215 if (timeout == 0) {
216 pr_err("%s: Reset 0x%x never completed.\n",
217 mmc_hostname(host->mmc), (int)mask);
218 sdhci_dumpregs(host);
219 return;
220 }
221 timeout--;
222 mdelay(1);
223 }
224
225 if (host->ops->platform_reset_exit)
226 host->ops->platform_reset_exit(host, mask);
227
228 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
229 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
230
231 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
232 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
233 host->ops->enable_dma(host);
234 }
235}
236
237static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
238
239static void sdhci_init(struct sdhci_host *host, int soft)
240{
241 if (soft)
242 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
243 else
244 sdhci_reset(host, SDHCI_RESET_ALL);
245
246 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
247 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
248 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
249 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
250 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
251
252 if (soft) {
253
254 host->clock = 0;
255 sdhci_set_ios(host->mmc, &host->mmc->ios);
256 }
257}
258
259static void sdhci_reinit(struct sdhci_host *host)
260{
261 sdhci_init(host, 0);
262
263
264
265
266
267 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
268 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
269
270 del_timer_sync(&host->tuning_timer);
271 host->flags &= ~SDHCI_NEEDS_RETUNING;
272 host->mmc->max_blk_count =
273 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
274 }
275 sdhci_enable_card_detection(host);
276}
277
278static void sdhci_activate_led(struct sdhci_host *host)
279{
280 u8 ctrl;
281
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283 ctrl |= SDHCI_CTRL_LED;
284 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
285}
286
287static void sdhci_deactivate_led(struct sdhci_host *host)
288{
289 u8 ctrl;
290
291 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
292 ctrl &= ~SDHCI_CTRL_LED;
293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
294}
295
296#ifdef SDHCI_USE_LEDS_CLASS
297static void sdhci_led_control(struct led_classdev *led,
298 enum led_brightness brightness)
299{
300 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
301 unsigned long flags;
302
303 spin_lock_irqsave(&host->lock, flags);
304
305 if (host->runtime_suspended)
306 goto out;
307
308 if (brightness == LED_OFF)
309 sdhci_deactivate_led(host);
310 else
311 sdhci_activate_led(host);
312out:
313 spin_unlock_irqrestore(&host->lock, flags);
314}
315#endif
316
317
318
319
320
321
322
323static void sdhci_read_block_pio(struct sdhci_host *host)
324{
325 unsigned long flags;
326 size_t blksize, len, chunk;
327 u32 uninitialized_var(scratch);
328 u8 *buf;
329
330 DBG("PIO reading\n");
331
332 blksize = host->data->blksz;
333 chunk = 0;
334
335 local_irq_save(flags);
336
337 while (blksize) {
338 if (!sg_miter_next(&host->sg_miter))
339 BUG();
340
341 len = min(host->sg_miter.length, blksize);
342
343 blksize -= len;
344 host->sg_miter.consumed = len;
345
346 buf = host->sg_miter.addr;
347
348 while (len) {
349 if (chunk == 0) {
350 scratch = sdhci_readl(host, SDHCI_BUFFER);
351 chunk = 4;
352 }
353
354 *buf = scratch & 0xFF;
355
356 buf++;
357 scratch >>= 8;
358 chunk--;
359 len--;
360 }
361 }
362
363 sg_miter_stop(&host->sg_miter);
364
365 local_irq_restore(flags);
366}
367
368static void sdhci_write_block_pio(struct sdhci_host *host)
369{
370 unsigned long flags;
371 size_t blksize, len, chunk;
372 u32 scratch;
373 u8 *buf;
374
375 DBG("PIO writing\n");
376
377 blksize = host->data->blksz;
378 chunk = 0;
379 scratch = 0;
380
381 local_irq_save(flags);
382
383 while (blksize) {
384 if (!sg_miter_next(&host->sg_miter))
385 BUG();
386
387 len = min(host->sg_miter.length, blksize);
388
389 blksize -= len;
390 host->sg_miter.consumed = len;
391
392 buf = host->sg_miter.addr;
393
394 while (len) {
395 scratch |= (u32)*buf << (chunk * 8);
396
397 buf++;
398 chunk++;
399 len--;
400
401 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
402 sdhci_writel(host, scratch, SDHCI_BUFFER);
403 chunk = 0;
404 scratch = 0;
405 }
406 }
407 }
408
409 sg_miter_stop(&host->sg_miter);
410
411 local_irq_restore(flags);
412}
413
414static void sdhci_transfer_pio(struct sdhci_host *host)
415{
416 u32 mask;
417
418 BUG_ON(!host->data);
419
420 if (host->blocks == 0)
421 return;
422
423 if (host->data->flags & MMC_DATA_READ)
424 mask = SDHCI_DATA_AVAILABLE;
425 else
426 mask = SDHCI_SPACE_AVAILABLE;
427
428
429
430
431
432
433 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
434 (host->data->blocks == 1))
435 mask = ~0;
436
437 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
438 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
439 udelay(100);
440
441 if (host->data->flags & MMC_DATA_READ)
442 sdhci_read_block_pio(host);
443 else
444 sdhci_write_block_pio(host);
445
446 host->blocks--;
447 if (host->blocks == 0)
448 break;
449 }
450
451 DBG("PIO transfer complete.\n");
452}
453
454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
457 return kmap_atomic(sg_page(sg)) + sg->offset;
458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
462 kunmap_atomic(buffer);
463 local_irq_restore(*flags);
464}
465
466static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
467{
468 __le32 *dataddr = (__le32 __force *)(desc + 4);
469 __le16 *cmdlen = (__le16 __force *)desc;
470
471
472
473
474 cmdlen[0] = cpu_to_le16(cmd);
475 cmdlen[1] = cpu_to_le16(len);
476
477 dataddr[0] = cpu_to_le32(addr);
478}
479
480static int sdhci_adma_table_pre(struct sdhci_host *host,
481 struct mmc_data *data)
482{
483 int direction;
484
485 u8 *desc;
486 u8 *align;
487 dma_addr_t addr;
488 dma_addr_t align_addr;
489 int len, offset;
490
491 struct scatterlist *sg;
492 int i;
493 char *buffer;
494 unsigned long flags;
495
496
497
498
499
500
501 if (data->flags & MMC_DATA_READ)
502 direction = DMA_FROM_DEVICE;
503 else
504 direction = DMA_TO_DEVICE;
505
506
507
508
509
510
511 host->align_addr = dma_map_single(mmc_dev(host->mmc),
512 host->align_buffer, 128 * 4, direction);
513 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
514 goto fail;
515 BUG_ON(host->align_addr & 0x3);
516
517 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
518 data->sg, data->sg_len, direction);
519 if (host->sg_count == 0)
520 goto unmap_align;
521
522 desc = host->adma_desc;
523 align = host->align_buffer;
524
525 align_addr = host->align_addr;
526
527 for_each_sg(data->sg, sg, host->sg_count, i) {
528 addr = sg_dma_address(sg);
529 len = sg_dma_len(sg);
530
531
532
533
534
535
536
537
538 offset = (4 - (addr & 0x3)) & 0x3;
539 if (offset) {
540 if (data->flags & MMC_DATA_WRITE) {
541 buffer = sdhci_kmap_atomic(sg, &flags);
542 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
543 memcpy(align, buffer, offset);
544 sdhci_kunmap_atomic(buffer, &flags);
545 }
546
547
548 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
549
550 BUG_ON(offset > 65536);
551
552 align += 4;
553 align_addr += 4;
554
555 desc += 8;
556
557 addr += offset;
558 len -= offset;
559 }
560
561 BUG_ON(len > 65536);
562
563
564 sdhci_set_adma_desc(desc, addr, len, 0x21);
565 desc += 8;
566
567
568
569
570
571 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
572 }
573
574 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
575
576
577
578 if (desc != host->adma_desc) {
579 desc -= 8;
580 desc[0] |= 0x2;
581 }
582 } else {
583
584
585
586
587
588 sdhci_set_adma_desc(desc, 0, 0, 0x3);
589 }
590
591
592
593
594 if (data->flags & MMC_DATA_WRITE) {
595 dma_sync_single_for_device(mmc_dev(host->mmc),
596 host->align_addr, 128 * 4, direction);
597 }
598
599 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
600 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
601 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
602 goto unmap_entries;
603 BUG_ON(host->adma_addr & 0x3);
604
605 return 0;
606
607unmap_entries:
608 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
609 data->sg_len, direction);
610unmap_align:
611 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
612 128 * 4, direction);
613fail:
614 return -EINVAL;
615}
616
617static void sdhci_adma_table_post(struct sdhci_host *host,
618 struct mmc_data *data)
619{
620 int direction;
621
622 struct scatterlist *sg;
623 int i, size;
624 u8 *align;
625 char *buffer;
626 unsigned long flags;
627
628 if (data->flags & MMC_DATA_READ)
629 direction = DMA_FROM_DEVICE;
630 else
631 direction = DMA_TO_DEVICE;
632
633 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
634 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
635
636 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
637 128 * 4, direction);
638
639 if (data->flags & MMC_DATA_READ) {
640 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642
643 align = host->align_buffer;
644
645 for_each_sg(data->sg, sg, host->sg_count, i) {
646 if (sg_dma_address(sg) & 0x3) {
647 size = 4 - (sg_dma_address(sg) & 0x3);
648
649 buffer = sdhci_kmap_atomic(sg, &flags);
650 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
651 memcpy(buffer, align, size);
652 sdhci_kunmap_atomic(buffer, &flags);
653
654 align += 4;
655 }
656 }
657 }
658
659 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
660 data->sg_len, direction);
661}
662
663static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
664{
665 u8 count;
666 struct mmc_data *data = cmd->data;
667 unsigned target_timeout, current_timeout;
668
669
670
671
672
673
674
675 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
676 return 0xE;
677
678
679 if (!data && !cmd->cmd_timeout_ms)
680 return 0xE;
681
682
683 if (!data)
684 target_timeout = cmd->cmd_timeout_ms * 1000;
685 else {
686 target_timeout = data->timeout_ns / 1000;
687 if (host->clock)
688 target_timeout += data->timeout_clks / host->clock;
689 }
690
691
692
693
694
695
696
697
698
699
700
701 count = 0;
702 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
703 while (current_timeout < target_timeout) {
704 count++;
705 current_timeout <<= 1;
706 if (count >= 0xF)
707 break;
708 }
709
710 if (count >= 0xF) {
711 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
712 mmc_hostname(host->mmc), count, cmd->opcode);
713 count = 0xE;
714 }
715
716 return count;
717}
718
719static void sdhci_set_transfer_irqs(struct sdhci_host *host)
720{
721 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
722 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
723
724 if (host->flags & SDHCI_REQ_USE_DMA)
725 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
726 else
727 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
728}
729
730static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
731{
732 u8 count;
733 u8 ctrl;
734 struct mmc_data *data = cmd->data;
735 int ret;
736
737 WARN_ON(host->data);
738
739 if (data || (cmd->flags & MMC_RSP_BUSY)) {
740 count = sdhci_calc_timeout(host, cmd);
741 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
742 }
743
744 if (!data)
745 return;
746
747
748 BUG_ON(data->blksz * data->blocks > 524288);
749 BUG_ON(data->blksz > host->mmc->max_blk_size);
750 BUG_ON(data->blocks > 65535);
751
752 host->data = data;
753 host->data_early = 0;
754 host->data->bytes_xfered = 0;
755
756 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
757 host->flags |= SDHCI_REQ_USE_DMA;
758
759
760
761
762
763 if (host->flags & SDHCI_REQ_USE_DMA) {
764 int broken, i;
765 struct scatterlist *sg;
766
767 broken = 0;
768 if (host->flags & SDHCI_USE_ADMA) {
769 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
770 broken = 1;
771 } else {
772 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
773 broken = 1;
774 }
775
776 if (unlikely(broken)) {
777 for_each_sg(data->sg, sg, data->sg_len, i) {
778 if (sg->length & 0x3) {
779 DBG("Reverting to PIO because of "
780 "transfer size (%d)\n",
781 sg->length);
782 host->flags &= ~SDHCI_REQ_USE_DMA;
783 break;
784 }
785 }
786 }
787 }
788
789
790
791
792
793 if (host->flags & SDHCI_REQ_USE_DMA) {
794 int broken, i;
795 struct scatterlist *sg;
796
797 broken = 0;
798 if (host->flags & SDHCI_USE_ADMA) {
799
800
801
802
803
804 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
805 broken = 1;
806 } else {
807 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
808 broken = 1;
809 }
810
811 if (unlikely(broken)) {
812 for_each_sg(data->sg, sg, data->sg_len, i) {
813 if (sg->offset & 0x3) {
814 DBG("Reverting to PIO because of "
815 "bad alignment\n");
816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
823 if (host->flags & SDHCI_REQ_USE_DMA) {
824 if (host->flags & SDHCI_USE_ADMA) {
825 ret = sdhci_adma_table_pre(host, data);
826 if (ret) {
827
828
829
830
831 WARN_ON(1);
832 host->flags &= ~SDHCI_REQ_USE_DMA;
833 } else {
834 sdhci_writel(host, host->adma_addr,
835 SDHCI_ADMA_ADDRESS);
836 }
837 } else {
838 int sg_cnt;
839
840 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
841 data->sg, data->sg_len,
842 (data->flags & MMC_DATA_READ) ?
843 DMA_FROM_DEVICE :
844 DMA_TO_DEVICE);
845 if (sg_cnt == 0) {
846
847
848
849
850 WARN_ON(1);
851 host->flags &= ~SDHCI_REQ_USE_DMA;
852 } else {
853 WARN_ON(sg_cnt != 1);
854 sdhci_writel(host, sg_dma_address(data->sg),
855 SDHCI_DMA_ADDRESS);
856 }
857 }
858 }
859
860
861
862
863
864
865 if (host->version >= SDHCI_SPEC_200) {
866 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
867 ctrl &= ~SDHCI_CTRL_DMA_MASK;
868 if ((host->flags & SDHCI_REQ_USE_DMA) &&
869 (host->flags & SDHCI_USE_ADMA))
870 ctrl |= SDHCI_CTRL_ADMA32;
871 else
872 ctrl |= SDHCI_CTRL_SDMA;
873 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
874 }
875
876 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
877 int flags;
878
879 flags = SG_MITER_ATOMIC;
880 if (host->data->flags & MMC_DATA_READ)
881 flags |= SG_MITER_TO_SG;
882 else
883 flags |= SG_MITER_FROM_SG;
884 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
885 host->blocks = data->blocks;
886 }
887
888 sdhci_set_transfer_irqs(host);
889
890
891 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
892 data->blksz), SDHCI_BLOCK_SIZE);
893 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
894}
895
896static void sdhci_set_transfer_mode(struct sdhci_host *host,
897 struct mmc_command *cmd)
898{
899 u16 mode;
900 struct mmc_data *data = cmd->data;
901
902 if (data == NULL)
903 return;
904
905 WARN_ON(!host->data);
906
907 mode = SDHCI_TRNS_BLK_CNT_EN;
908 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
909 mode |= SDHCI_TRNS_MULTI;
910
911
912
913
914 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
915 mode |= SDHCI_TRNS_AUTO_CMD12;
916 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
917 mode |= SDHCI_TRNS_AUTO_CMD23;
918 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
919 }
920 }
921
922 if (data->flags & MMC_DATA_READ)
923 mode |= SDHCI_TRNS_READ;
924 if (host->flags & SDHCI_REQ_USE_DMA)
925 mode |= SDHCI_TRNS_DMA;
926
927 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
928}
929
930static void sdhci_finish_data(struct sdhci_host *host)
931{
932 struct mmc_data *data;
933
934 BUG_ON(!host->data);
935
936 data = host->data;
937 host->data = NULL;
938
939 if (host->flags & SDHCI_REQ_USE_DMA) {
940 if (host->flags & SDHCI_USE_ADMA)
941 sdhci_adma_table_post(host, data);
942 else {
943 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
944 data->sg_len, (data->flags & MMC_DATA_READ) ?
945 DMA_FROM_DEVICE : DMA_TO_DEVICE);
946 }
947 }
948
949
950
951
952
953
954
955
956 if (data->error)
957 data->bytes_xfered = 0;
958 else
959 data->bytes_xfered = data->blksz * data->blocks;
960
961
962
963
964
965
966 if (data->stop &&
967 (data->error ||
968 !host->mrq->sbc)) {
969
970
971
972
973
974 if (data->error) {
975 sdhci_reset(host, SDHCI_RESET_CMD);
976 sdhci_reset(host, SDHCI_RESET_DATA);
977 }
978
979 sdhci_send_command(host, data->stop);
980 } else
981 tasklet_schedule(&host->finish_tasklet);
982}
983
984static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
985{
986 int flags;
987 u32 mask;
988 unsigned long timeout;
989
990 WARN_ON(host->cmd);
991
992
993 timeout = 10;
994
995 mask = SDHCI_CMD_INHIBIT;
996 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
997 mask |= SDHCI_DATA_INHIBIT;
998
999
1000
1001 if (host->mrq->data && (cmd == host->mrq->data->stop))
1002 mask &= ~SDHCI_DATA_INHIBIT;
1003
1004 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1005 if (timeout == 0) {
1006 pr_err("%s: Controller never released "
1007 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1008 sdhci_dumpregs(host);
1009 cmd->error = -EIO;
1010 tasklet_schedule(&host->finish_tasklet);
1011 return;
1012 }
1013 timeout--;
1014 mdelay(1);
1015 }
1016
1017 mod_timer(&host->timer, jiffies + 10 * HZ);
1018
1019 host->cmd = cmd;
1020
1021 sdhci_prepare_data(host, cmd);
1022
1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024
1025 sdhci_set_transfer_mode(host, cmd);
1026
1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1028 pr_err("%s: Unsupported response type!\n",
1029 mmc_hostname(host->mmc));
1030 cmd->error = -EINVAL;
1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
1048
1049
1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1052 flags |= SDHCI_CMD_DATA;
1053
1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1055}
1056
1057static void sdhci_finish_command(struct sdhci_host *host)
1058{
1059 int i;
1060
1061 BUG_ON(host->cmd == NULL);
1062
1063 if (host->cmd->flags & MMC_RSP_PRESENT) {
1064 if (host->cmd->flags & MMC_RSP_136) {
1065
1066 for (i = 0;i < 4;i++) {
1067 host->cmd->resp[i] = sdhci_readl(host,
1068 SDHCI_RESPONSE + (3-i)*4) << 8;
1069 if (i != 3)
1070 host->cmd->resp[i] |=
1071 sdhci_readb(host,
1072 SDHCI_RESPONSE + (3-i)*4-1);
1073 }
1074 } else {
1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1076 }
1077 }
1078
1079 host->cmd->error = 0;
1080
1081
1082 if (host->cmd == host->mrq->sbc) {
1083 host->cmd = NULL;
1084 sdhci_send_command(host, host->mrq->cmd);
1085 } else {
1086
1087
1088 if (host->data && host->data_early)
1089 sdhci_finish_data(host);
1090
1091 if (!host->cmd->data)
1092 tasklet_schedule(&host->finish_tasklet);
1093
1094 host->cmd = NULL;
1095 }
1096}
1097
1098static u16 sdhci_get_preset_value(struct sdhci_host *host)
1099{
1100 u16 ctrl, preset = 0;
1101
1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103
1104 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1105 case SDHCI_CTRL_UHS_SDR12:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107 break;
1108 case SDHCI_CTRL_UHS_SDR25:
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110 break;
1111 case SDHCI_CTRL_UHS_SDR50:
1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113 break;
1114 case SDHCI_CTRL_UHS_SDR104:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case SDHCI_CTRL_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127}
1128
1129static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130{
1131 int div = 0;
1132 int real_div = div, clk_mul = 1;
1133 u16 clk = 0;
1134 unsigned long timeout;
1135
1136 if (clock && clock == host->clock)
1137 return;
1138
1139 host->mmc->actual_clock = 0;
1140
1141 if (host->ops->set_clock) {
1142 host->ops->set_clock(host, clock);
1143 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1144 return;
1145 }
1146
1147 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1148
1149 if (clock == 0)
1150 goto out;
1151
1152 if (host->version >= SDHCI_SPEC_300) {
1153 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1154 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1155 u16 pre_val;
1156
1157 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1158 pre_val = sdhci_get_preset_value(host);
1159 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1160 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1161 if (host->clk_mul &&
1162 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1163 clk = SDHCI_PROG_CLOCK_MODE;
1164 real_div = div + 1;
1165 clk_mul = host->clk_mul;
1166 } else {
1167 real_div = max_t(int, 1, div << 1);
1168 }
1169 goto clock_set;
1170 }
1171
1172
1173
1174
1175
1176 if (host->clk_mul) {
1177 for (div = 1; div <= 1024; div++) {
1178 if ((host->max_clk * host->clk_mul / div)
1179 <= clock)
1180 break;
1181 }
1182
1183
1184
1185
1186 clk = SDHCI_PROG_CLOCK_MODE;
1187 real_div = div;
1188 clk_mul = host->clk_mul;
1189 div--;
1190 } else {
1191
1192 if (host->max_clk <= clock)
1193 div = 1;
1194 else {
1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196 div += 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
1200 }
1201 real_div = div;
1202 div >>= 1;
1203 }
1204 } else {
1205
1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
1210 real_div = div;
1211 div >>= 1;
1212 }
1213
1214clock_set:
1215 if (real_div)
1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1217
1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220 << SDHCI_DIVIDER_HI_SHIFT;
1221 clk |= SDHCI_CLOCK_INT_EN;
1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1223
1224
1225 timeout = 20;
1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1227 & SDHCI_CLOCK_INT_STABLE)) {
1228 if (timeout == 0) {
1229 pr_err("%s: Internal clock never "
1230 "stabilised.\n", mmc_hostname(host->mmc));
1231 sdhci_dumpregs(host);
1232 return;
1233 }
1234 timeout--;
1235 mdelay(1);
1236 }
1237
1238 clk |= SDHCI_CLOCK_CARD_EN;
1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1240
1241out:
1242 host->clock = clock;
1243}
1244
1245static inline void sdhci_update_clock(struct sdhci_host *host)
1246{
1247 unsigned int clock;
1248
1249 clock = host->clock;
1250 host->clock = 0;
1251 sdhci_set_clock(host, clock);
1252}
1253
1254static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1255{
1256 u8 pwr = 0;
1257
1258 if (power != (unsigned short)-1) {
1259 switch (1 << power) {
1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
1272 BUG();
1273 }
1274 }
1275
1276 if (host->pwr == pwr)
1277 return -1;
1278
1279 host->pwr = pwr;
1280
1281 if (pwr == 0) {
1282 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1283 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1284 sdhci_runtime_pm_bus_off(host);
1285 return 0;
1286 }
1287
1288
1289
1290
1291
1292 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1294
1295
1296
1297
1298
1299 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1301
1302 pwr |= SDHCI_POWER_ON;
1303
1304 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1305
1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307 sdhci_runtime_pm_bus_on(host);
1308
1309
1310
1311
1312
1313 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1314 mdelay(10);
1315
1316 return power;
1317}
1318
1319
1320
1321
1322
1323
1324
1325static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326{
1327 struct sdhci_host *host;
1328 int present;
1329 unsigned long flags;
1330 u32 tuning_opcode;
1331
1332 host = mmc_priv(mmc);
1333
1334 sdhci_runtime_pm_get(host);
1335
1336 spin_lock_irqsave(&host->lock, flags);
1337
1338 WARN_ON(host->mrq != NULL);
1339
1340#ifndef SDHCI_USE_LEDS_CLASS
1341 sdhci_activate_led(host);
1342#endif
1343
1344
1345
1346
1347
1348 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1349 if (mrq->stop) {
1350 mrq->data->stop = NULL;
1351 mrq->stop = NULL;
1352 }
1353 }
1354
1355 host->mrq = mrq;
1356
1357
1358
1359
1360
1361
1362
1363
1364 present = mmc_gpio_get_cd(host->mmc);
1365 if (present < 0) {
1366
1367 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1368 present = 1;
1369 else
1370 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1371 SDHCI_CARD_PRESENT;
1372 }
1373
1374 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1375 host->mrq->cmd->error = -ENOMEDIUM;
1376 tasklet_schedule(&host->finish_tasklet);
1377 } else {
1378 u32 present_state;
1379
1380 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1381
1382
1383
1384
1385
1386 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1387 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1388 if (mmc->card) {
1389
1390 tuning_opcode =
1391 mmc->card->type == MMC_TYPE_MMC ?
1392 MMC_SEND_TUNING_BLOCK_HS200 :
1393 MMC_SEND_TUNING_BLOCK;
1394 spin_unlock_irqrestore(&host->lock, flags);
1395 sdhci_execute_tuning(mmc, tuning_opcode);
1396 spin_lock_irqsave(&host->lock, flags);
1397
1398
1399 host->mrq = mrq;
1400 }
1401 }
1402
1403 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1404 sdhci_send_command(host, mrq->sbc);
1405 else
1406 sdhci_send_command(host, mrq->cmd);
1407 }
1408
1409 mmiowb();
1410 spin_unlock_irqrestore(&host->lock, flags);
1411}
1412
1413static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1414{
1415 unsigned long flags;
1416 int vdd_bit = -1;
1417 u8 ctrl;
1418
1419 spin_lock_irqsave(&host->lock, flags);
1420
1421 if (host->flags & SDHCI_DEVICE_DEAD) {
1422 spin_unlock_irqrestore(&host->lock, flags);
1423 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1424 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1425 return;
1426 }
1427
1428
1429
1430
1431
1432 if (ios->power_mode == MMC_POWER_OFF) {
1433 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1434 sdhci_reinit(host);
1435 }
1436
1437 if (host->version >= SDHCI_SPEC_300 &&
1438 (ios->power_mode == MMC_POWER_UP))
1439 sdhci_enable_preset_value(host, false);
1440
1441 sdhci_set_clock(host, ios->clock);
1442
1443 if (ios->power_mode == MMC_POWER_OFF)
1444 vdd_bit = sdhci_set_power(host, -1);
1445 else
1446 vdd_bit = sdhci_set_power(host, ios->vdd);
1447
1448 if (host->vmmc && vdd_bit != -1) {
1449 spin_unlock_irqrestore(&host->lock, flags);
1450 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1451 spin_lock_irqsave(&host->lock, flags);
1452 }
1453
1454 if (host->ops->platform_send_init_74_clocks)
1455 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1456
1457
1458
1459
1460
1461
1462 if (host->ops->platform_bus_width) {
1463 host->ops->platform_bus_width(host, ios->bus_width);
1464 } else {
1465 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1466 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1467 ctrl &= ~SDHCI_CTRL_4BITBUS;
1468 if (host->version >= SDHCI_SPEC_300)
1469 ctrl |= SDHCI_CTRL_8BITBUS;
1470 } else {
1471 if (host->version >= SDHCI_SPEC_300)
1472 ctrl &= ~SDHCI_CTRL_8BITBUS;
1473 if (ios->bus_width == MMC_BUS_WIDTH_4)
1474 ctrl |= SDHCI_CTRL_4BITBUS;
1475 else
1476 ctrl &= ~SDHCI_CTRL_4BITBUS;
1477 }
1478 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1479 }
1480
1481 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1482
1483 if ((ios->timing == MMC_TIMING_SD_HS ||
1484 ios->timing == MMC_TIMING_MMC_HS)
1485 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1486 ctrl |= SDHCI_CTRL_HISPD;
1487 else
1488 ctrl &= ~SDHCI_CTRL_HISPD;
1489
1490 if (host->version >= SDHCI_SPEC_300) {
1491 u16 clk, ctrl_2;
1492
1493
1494 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1495 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1496 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1497 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1498 (ios->timing == MMC_TIMING_UHS_SDR25))
1499 ctrl |= SDHCI_CTRL_HISPD;
1500
1501 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1502 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1504
1505
1506
1507
1508 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1509 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1510 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1511 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1512 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513
1514 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1515 } else {
1516
1517
1518
1519
1520
1521
1522
1523
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk &= ~SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530
1531 sdhci_update_clock(host);
1532 }
1533
1534
1535
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
1540 if (host->ops->set_uhs_signaling)
1541 host->ops->set_uhs_signaling(host, ios->timing);
1542 else {
1543 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1544
1545 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1546 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR104))
1548 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1549 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1550 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1551 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1553 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1555 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1556 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1557 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1558 }
1559
1560 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1561 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1564 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1565 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1566 u16 preset;
1567
1568 sdhci_enable_preset_value(host, true);
1569 preset = sdhci_get_preset_value(host);
1570 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1571 >> SDHCI_PRESET_DRV_SHIFT;
1572 }
1573
1574
1575 sdhci_update_clock(host);
1576 } else
1577 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1578
1579
1580
1581
1582
1583
1584 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1585 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1586
1587 mmiowb();
1588 spin_unlock_irqrestore(&host->lock, flags);
1589}
1590
1591static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1592{
1593 struct sdhci_host *host = mmc_priv(mmc);
1594
1595 sdhci_runtime_pm_get(host);
1596 sdhci_do_set_ios(host, ios);
1597 sdhci_runtime_pm_put(host);
1598}
1599
1600static int sdhci_do_get_cd(struct sdhci_host *host)
1601{
1602 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1603
1604 if (host->flags & SDHCI_DEVICE_DEAD)
1605 return 0;
1606
1607
1608 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1609 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1610 return 1;
1611
1612
1613 if (!IS_ERR_VALUE(gpio_cd))
1614 return !!gpio_cd;
1615
1616
1617 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1618}
1619
1620static int sdhci_get_cd(struct mmc_host *mmc)
1621{
1622 struct sdhci_host *host = mmc_priv(mmc);
1623 int ret;
1624
1625 sdhci_runtime_pm_get(host);
1626 ret = sdhci_do_get_cd(host);
1627 sdhci_runtime_pm_put(host);
1628 return ret;
1629}
1630
1631static int sdhci_check_ro(struct sdhci_host *host)
1632{
1633 unsigned long flags;
1634 int is_readonly;
1635
1636 spin_lock_irqsave(&host->lock, flags);
1637
1638 if (host->flags & SDHCI_DEVICE_DEAD)
1639 is_readonly = 0;
1640 else if (host->ops->get_ro)
1641 is_readonly = host->ops->get_ro(host);
1642 else
1643 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1644 & SDHCI_WRITE_PROTECT);
1645
1646 spin_unlock_irqrestore(&host->lock, flags);
1647
1648
1649 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1650 !is_readonly : is_readonly;
1651}
1652
1653#define SAMPLE_COUNT 5
1654
1655static int sdhci_do_get_ro(struct sdhci_host *host)
1656{
1657 int i, ro_count;
1658
1659 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1660 return sdhci_check_ro(host);
1661
1662 ro_count = 0;
1663 for (i = 0; i < SAMPLE_COUNT; i++) {
1664 if (sdhci_check_ro(host)) {
1665 if (++ro_count > SAMPLE_COUNT / 2)
1666 return 1;
1667 }
1668 msleep(30);
1669 }
1670 return 0;
1671}
1672
1673static void sdhci_hw_reset(struct mmc_host *mmc)
1674{
1675 struct sdhci_host *host = mmc_priv(mmc);
1676
1677 if (host->ops && host->ops->hw_reset)
1678 host->ops->hw_reset(host);
1679}
1680
1681static int sdhci_get_ro(struct mmc_host *mmc)
1682{
1683 struct sdhci_host *host = mmc_priv(mmc);
1684 int ret;
1685
1686 sdhci_runtime_pm_get(host);
1687 ret = sdhci_do_get_ro(host);
1688 sdhci_runtime_pm_put(host);
1689 return ret;
1690}
1691
1692static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1693{
1694 if (host->flags & SDHCI_DEVICE_DEAD)
1695 goto out;
1696
1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
1702
1703 if (host->runtime_suspended)
1704 goto out;
1705
1706 if (enable)
1707 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1708 else
1709 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1710out:
1711 mmiowb();
1712}
1713
1714static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1715{
1716 struct sdhci_host *host = mmc_priv(mmc);
1717 unsigned long flags;
1718
1719 spin_lock_irqsave(&host->lock, flags);
1720 sdhci_enable_sdio_irq_nolock(host, enable);
1721 spin_unlock_irqrestore(&host->lock, flags);
1722}
1723
1724static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1725 struct mmc_ios *ios)
1726{
1727 u16 ctrl;
1728 int ret;
1729
1730
1731
1732
1733
1734 if (host->version < SDHCI_SPEC_300)
1735 return 0;
1736
1737 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1738
1739 switch (ios->signal_voltage) {
1740 case MMC_SIGNAL_VOLTAGE_330:
1741
1742 ctrl &= ~SDHCI_CTRL_VDD_180;
1743 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1744
1745 if (host->vqmmc) {
1746 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1747 if (ret) {
1748 pr_warning("%s: Switching to 3.3V signalling voltage "
1749 " failed\n", mmc_hostname(host->mmc));
1750 return -EIO;
1751 }
1752 }
1753
1754 usleep_range(5000, 5500);
1755
1756
1757 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1758 if (!(ctrl & SDHCI_CTRL_VDD_180))
1759 return 0;
1760
1761 pr_warning("%s: 3.3V regulator output did not became stable\n",
1762 mmc_hostname(host->mmc));
1763
1764 return -EAGAIN;
1765 case MMC_SIGNAL_VOLTAGE_180:
1766 if (host->vqmmc) {
1767 ret = regulator_set_voltage(host->vqmmc,
1768 1700000, 1950000);
1769 if (ret) {
1770 pr_warning("%s: Switching to 1.8V signalling voltage "
1771 " failed\n", mmc_hostname(host->mmc));
1772 return -EIO;
1773 }
1774 }
1775
1776
1777
1778
1779
1780 ctrl |= SDHCI_CTRL_VDD_180;
1781 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1782
1783
1784 usleep_range(5000, 5500);
1785
1786
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788 if (ctrl & SDHCI_CTRL_VDD_180)
1789 return 0;
1790
1791 pr_warning("%s: 1.8V regulator output did not became stable\n",
1792 mmc_hostname(host->mmc));
1793
1794 return -EAGAIN;
1795 case MMC_SIGNAL_VOLTAGE_120:
1796 if (host->vqmmc) {
1797 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1798 if (ret) {
1799 pr_warning("%s: Switching to 1.2V signalling voltage "
1800 " failed\n", mmc_hostname(host->mmc));
1801 return -EIO;
1802 }
1803 }
1804 return 0;
1805 default:
1806
1807 return 0;
1808 }
1809}
1810
1811static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1812 struct mmc_ios *ios)
1813{
1814 struct sdhci_host *host = mmc_priv(mmc);
1815 int err;
1816
1817 if (host->version < SDHCI_SPEC_300)
1818 return 0;
1819 sdhci_runtime_pm_get(host);
1820 err = sdhci_do_start_signal_voltage_switch(host, ios);
1821 sdhci_runtime_pm_put(host);
1822 return err;
1823}
1824
1825static int sdhci_card_busy(struct mmc_host *mmc)
1826{
1827 struct sdhci_host *host = mmc_priv(mmc);
1828 u32 present_state;
1829
1830 sdhci_runtime_pm_get(host);
1831
1832 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1833 sdhci_runtime_pm_put(host);
1834
1835 return !(present_state & SDHCI_DATA_LVL_MASK);
1836}
1837
1838static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1839{
1840 struct sdhci_host *host;
1841 u16 ctrl;
1842 u32 ier;
1843 int tuning_loop_counter = MAX_TUNING_LOOP;
1844 unsigned long timeout;
1845 int err = 0;
1846 bool requires_tuning_nonuhs = false;
1847
1848 host = mmc_priv(mmc);
1849
1850 sdhci_runtime_pm_get(host);
1851 disable_irq(host->irq);
1852 spin_lock(&host->lock);
1853
1854 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1855
1856
1857
1858
1859
1860
1861
1862
1863 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1864 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1865 host->flags & SDHCI_SDR104_NEEDS_TUNING))
1866 requires_tuning_nonuhs = true;
1867
1868 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1869 requires_tuning_nonuhs)
1870 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1871 else {
1872 spin_unlock(&host->lock);
1873 enable_irq(host->irq);
1874 sdhci_runtime_pm_put(host);
1875 return 0;
1876 }
1877
1878 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1891 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1892
1893
1894
1895
1896
1897 timeout = 150;
1898 do {
1899 struct mmc_command cmd = {0};
1900 struct mmc_request mrq = {NULL};
1901
1902 if (!tuning_loop_counter && !timeout)
1903 break;
1904
1905 cmd.opcode = opcode;
1906 cmd.arg = 0;
1907 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1908 cmd.retries = 0;
1909 cmd.data = NULL;
1910 cmd.error = 0;
1911
1912 mrq.cmd = &cmd;
1913 host->mrq = &mrq;
1914
1915
1916
1917
1918
1919
1920 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1921 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1922 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1923 SDHCI_BLOCK_SIZE);
1924 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1925 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1926 SDHCI_BLOCK_SIZE);
1927 } else {
1928 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1929 SDHCI_BLOCK_SIZE);
1930 }
1931
1932
1933
1934
1935
1936
1937
1938 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1939
1940 sdhci_send_command(host, &cmd);
1941
1942 host->cmd = NULL;
1943 host->mrq = NULL;
1944
1945 spin_unlock(&host->lock);
1946 enable_irq(host->irq);
1947
1948
1949 wait_event_interruptible_timeout(host->buf_ready_int,
1950 (host->tuning_done == 1),
1951 msecs_to_jiffies(50));
1952 disable_irq(host->irq);
1953 spin_lock(&host->lock);
1954
1955 if (!host->tuning_done) {
1956 pr_info(DRIVER_NAME ": Timeout waiting for "
1957 "Buffer Read Ready interrupt during tuning "
1958 "procedure, falling back to fixed sampling "
1959 "clock\n");
1960 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1961 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1962 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1963 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1964
1965 err = -EIO;
1966 goto out;
1967 }
1968
1969 host->tuning_done = 0;
1970
1971 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1972 tuning_loop_counter--;
1973 timeout--;
1974 mdelay(1);
1975 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1976
1977
1978
1979
1980
1981 if (!tuning_loop_counter || !timeout) {
1982 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1983 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1984 } else {
1985 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1986 pr_info(DRIVER_NAME ": Tuning procedure"
1987 " failed, falling back to fixed sampling"
1988 " clock\n");
1989 err = -EIO;
1990 }
1991 }
1992
1993out:
1994
1995
1996
1997
1998
1999
2000 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2001 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2002 host->flags |= SDHCI_USING_RETUNING_TIMER;
2003 mod_timer(&host->tuning_timer, jiffies +
2004 host->tuning_count * HZ);
2005
2006 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2007 } else {
2008 host->flags &= ~SDHCI_NEEDS_RETUNING;
2009
2010 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2011 mod_timer(&host->tuning_timer, jiffies +
2012 host->tuning_count * HZ);
2013 }
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2024 err = 0;
2025
2026 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2027 spin_unlock(&host->lock);
2028 enable_irq(host->irq);
2029 sdhci_runtime_pm_put(host);
2030
2031 return err;
2032}
2033
2034
2035static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2036{
2037 u16 ctrl;
2038
2039
2040 if (host->version < SDHCI_SPEC_300)
2041 return;
2042
2043 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2044
2045
2046
2047
2048
2049 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2050 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2051 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2052 host->flags |= SDHCI_PV_ENABLED;
2053 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2054 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2055 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2056 host->flags &= ~SDHCI_PV_ENABLED;
2057 }
2058}
2059
2060static void sdhci_card_event(struct mmc_host *mmc)
2061{
2062 struct sdhci_host *host = mmc_priv(mmc);
2063 unsigned long flags;
2064
2065
2066 if (host->ops->card_event)
2067 host->ops->card_event(host);
2068
2069 spin_lock_irqsave(&host->lock, flags);
2070
2071
2072 if (host->mrq && !sdhci_do_get_cd(host)) {
2073 pr_err("%s: Card removed during transfer!\n",
2074 mmc_hostname(host->mmc));
2075 pr_err("%s: Resetting controller.\n",
2076 mmc_hostname(host->mmc));
2077
2078 sdhci_reset(host, SDHCI_RESET_CMD);
2079 sdhci_reset(host, SDHCI_RESET_DATA);
2080
2081 host->mrq->cmd->error = -ENOMEDIUM;
2082 tasklet_schedule(&host->finish_tasklet);
2083 }
2084
2085 spin_unlock_irqrestore(&host->lock, flags);
2086}
2087
2088static const struct mmc_host_ops sdhci_ops = {
2089 .request = sdhci_request,
2090 .set_ios = sdhci_set_ios,
2091 .get_cd = sdhci_get_cd,
2092 .get_ro = sdhci_get_ro,
2093 .hw_reset = sdhci_hw_reset,
2094 .enable_sdio_irq = sdhci_enable_sdio_irq,
2095 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2096 .execute_tuning = sdhci_execute_tuning,
2097 .card_event = sdhci_card_event,
2098 .card_busy = sdhci_card_busy,
2099};
2100
2101
2102
2103
2104
2105
2106
2107static void sdhci_tasklet_card(unsigned long param)
2108{
2109 struct sdhci_host *host = (struct sdhci_host*)param;
2110
2111 sdhci_card_event(host->mmc);
2112
2113 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2114}
2115
2116static void sdhci_tasklet_finish(unsigned long param)
2117{
2118 struct sdhci_host *host;
2119 unsigned long flags;
2120 struct mmc_request *mrq;
2121
2122 host = (struct sdhci_host*)param;
2123
2124 spin_lock_irqsave(&host->lock, flags);
2125
2126
2127
2128
2129
2130 if (!host->mrq) {
2131 spin_unlock_irqrestore(&host->lock, flags);
2132 return;
2133 }
2134
2135 del_timer(&host->timer);
2136
2137 mrq = host->mrq;
2138
2139
2140
2141
2142
2143 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2144 ((mrq->cmd && mrq->cmd->error) ||
2145 (mrq->data && (mrq->data->error ||
2146 (mrq->data->stop && mrq->data->stop->error))) ||
2147 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2148
2149
2150 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2151
2152 sdhci_update_clock(host);
2153
2154
2155
2156 sdhci_reset(host, SDHCI_RESET_CMD);
2157 sdhci_reset(host, SDHCI_RESET_DATA);
2158 }
2159
2160 host->mrq = NULL;
2161 host->cmd = NULL;
2162 host->data = NULL;
2163
2164#ifndef SDHCI_USE_LEDS_CLASS
2165 sdhci_deactivate_led(host);
2166#endif
2167
2168 mmiowb();
2169 spin_unlock_irqrestore(&host->lock, flags);
2170
2171 mmc_request_done(host->mmc, mrq);
2172 sdhci_runtime_pm_put(host);
2173}
2174
2175static void sdhci_timeout_timer(unsigned long data)
2176{
2177 struct sdhci_host *host;
2178 unsigned long flags;
2179
2180 host = (struct sdhci_host*)data;
2181
2182 spin_lock_irqsave(&host->lock, flags);
2183
2184 if (host->mrq) {
2185 pr_err("%s: Timeout waiting for hardware "
2186 "interrupt.\n", mmc_hostname(host->mmc));
2187 sdhci_dumpregs(host);
2188
2189 if (host->data) {
2190 host->data->error = -ETIMEDOUT;
2191 sdhci_finish_data(host);
2192 } else {
2193 if (host->cmd)
2194 host->cmd->error = -ETIMEDOUT;
2195 else
2196 host->mrq->cmd->error = -ETIMEDOUT;
2197
2198 tasklet_schedule(&host->finish_tasklet);
2199 }
2200 }
2201
2202 mmiowb();
2203 spin_unlock_irqrestore(&host->lock, flags);
2204}
2205
2206static void sdhci_tuning_timer(unsigned long data)
2207{
2208 struct sdhci_host *host;
2209 unsigned long flags;
2210
2211 host = (struct sdhci_host *)data;
2212
2213 spin_lock_irqsave(&host->lock, flags);
2214
2215 host->flags |= SDHCI_NEEDS_RETUNING;
2216
2217 spin_unlock_irqrestore(&host->lock, flags);
2218}
2219
2220
2221
2222
2223
2224
2225
2226static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2227{
2228 BUG_ON(intmask == 0);
2229
2230 if (!host->cmd) {
2231 pr_err("%s: Got command interrupt 0x%08x even "
2232 "though no command operation was in progress.\n",
2233 mmc_hostname(host->mmc), (unsigned)intmask);
2234 sdhci_dumpregs(host);
2235 return;
2236 }
2237
2238 if (intmask & SDHCI_INT_TIMEOUT)
2239 host->cmd->error = -ETIMEDOUT;
2240 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2241 SDHCI_INT_INDEX))
2242 host->cmd->error = -EILSEQ;
2243
2244 if (host->cmd->error) {
2245 tasklet_schedule(&host->finish_tasklet);
2246 return;
2247 }
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260 if (host->cmd->flags & MMC_RSP_BUSY) {
2261 if (host->cmd->data)
2262 DBG("Cannot wait for busy signal when also "
2263 "doing a data transfer");
2264 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2265 return;
2266
2267
2268
2269 }
2270
2271 if (intmask & SDHCI_INT_RESPONSE)
2272 sdhci_finish_command(host);
2273}
2274
2275#ifdef CONFIG_MMC_DEBUG
2276static void sdhci_show_adma_error(struct sdhci_host *host)
2277{
2278 const char *name = mmc_hostname(host->mmc);
2279 u8 *desc = host->adma_desc;
2280 __le32 *dma;
2281 __le16 *len;
2282 u8 attr;
2283
2284 sdhci_dumpregs(host);
2285
2286 while (true) {
2287 dma = (__le32 *)(desc + 4);
2288 len = (__le16 *)(desc + 2);
2289 attr = *desc;
2290
2291 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2292 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2293
2294 desc += 8;
2295
2296 if (attr & 2)
2297 break;
2298 }
2299}
2300#else
2301static void sdhci_show_adma_error(struct sdhci_host *host) { }
2302#endif
2303
2304static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2305{
2306 u32 command;
2307 BUG_ON(intmask == 0);
2308
2309
2310 if (intmask & SDHCI_INT_DATA_AVAIL) {
2311 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2312 if (command == MMC_SEND_TUNING_BLOCK ||
2313 command == MMC_SEND_TUNING_BLOCK_HS200) {
2314 host->tuning_done = 1;
2315 wake_up(&host->buf_ready_int);
2316 return;
2317 }
2318 }
2319
2320 if (!host->data) {
2321
2322
2323
2324
2325
2326 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2327 if (intmask & SDHCI_INT_DATA_END) {
2328 sdhci_finish_command(host);
2329 return;
2330 }
2331 }
2332
2333 pr_err("%s: Got data interrupt 0x%08x even "
2334 "though no data operation was in progress.\n",
2335 mmc_hostname(host->mmc), (unsigned)intmask);
2336 sdhci_dumpregs(host);
2337
2338 return;
2339 }
2340
2341 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2342 host->data->error = -ETIMEDOUT;
2343 else if (intmask & SDHCI_INT_DATA_END_BIT)
2344 host->data->error = -EILSEQ;
2345 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2346 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2347 != MMC_BUS_TEST_R)
2348 host->data->error = -EILSEQ;
2349 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2350 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2351 sdhci_show_adma_error(host);
2352 host->data->error = -EIO;
2353 if (host->ops->adma_workaround)
2354 host->ops->adma_workaround(host, intmask);
2355 }
2356
2357 if (host->data->error)
2358 sdhci_finish_data(host);
2359 else {
2360 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2361 sdhci_transfer_pio(host);
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372 if (intmask & SDHCI_INT_DMA_END) {
2373 u32 dmastart, dmanow;
2374 dmastart = sg_dma_address(host->data->sg);
2375 dmanow = dmastart + host->data->bytes_xfered;
2376
2377
2378
2379 dmanow = (dmanow &
2380 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2381 SDHCI_DEFAULT_BOUNDARY_SIZE;
2382 host->data->bytes_xfered = dmanow - dmastart;
2383 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2384 " next 0x%08x\n",
2385 mmc_hostname(host->mmc), dmastart,
2386 host->data->bytes_xfered, dmanow);
2387 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2388 }
2389
2390 if (intmask & SDHCI_INT_DATA_END) {
2391 if (host->cmd) {
2392
2393
2394
2395
2396
2397 host->data_early = 1;
2398 } else {
2399 sdhci_finish_data(host);
2400 }
2401 }
2402 }
2403}
2404
2405static irqreturn_t sdhci_irq(int irq, void *dev_id)
2406{
2407 irqreturn_t result;
2408 struct sdhci_host *host = dev_id;
2409 u32 intmask, unexpected = 0;
2410 int cardint = 0, max_loops = 16;
2411
2412 spin_lock(&host->lock);
2413
2414 if (host->runtime_suspended) {
2415 spin_unlock(&host->lock);
2416 pr_warning("%s: got irq while runtime suspended\n",
2417 mmc_hostname(host->mmc));
2418 return IRQ_HANDLED;
2419 }
2420
2421 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2422
2423 if (!intmask || intmask == 0xffffffff) {
2424 result = IRQ_NONE;
2425 goto out;
2426 }
2427
2428again:
2429 DBG("*** %s got interrupt: 0x%08x\n",
2430 mmc_hostname(host->mmc), intmask);
2431
2432 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2433 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2434 SDHCI_CARD_PRESENT;
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2447 SDHCI_INT_CARD_REMOVE);
2448 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2449 SDHCI_INT_CARD_INSERT);
2450
2451 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2452 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2453 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2454 tasklet_schedule(&host->card_tasklet);
2455 }
2456
2457 if (intmask & SDHCI_INT_CMD_MASK) {
2458 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2459 SDHCI_INT_STATUS);
2460 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2461 }
2462
2463 if (intmask & SDHCI_INT_DATA_MASK) {
2464 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2465 SDHCI_INT_STATUS);
2466 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2467 }
2468
2469 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2470
2471 intmask &= ~SDHCI_INT_ERROR;
2472
2473 if (intmask & SDHCI_INT_BUS_POWER) {
2474 pr_err("%s: Card is consuming too much power!\n",
2475 mmc_hostname(host->mmc));
2476 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2477 }
2478
2479 intmask &= ~SDHCI_INT_BUS_POWER;
2480
2481 if (intmask & SDHCI_INT_CARD_INT)
2482 cardint = 1;
2483
2484 intmask &= ~SDHCI_INT_CARD_INT;
2485
2486 if (intmask) {
2487 unexpected |= intmask;
2488 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2489 }
2490
2491 result = IRQ_HANDLED;
2492
2493 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2494 if (intmask && --max_loops)
2495 goto again;
2496out:
2497 spin_unlock(&host->lock);
2498
2499 if (unexpected) {
2500 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2501 mmc_hostname(host->mmc), unexpected);
2502 sdhci_dumpregs(host);
2503 }
2504
2505
2506
2507 if (cardint)
2508 mmc_signal_sdio_irq(host->mmc);
2509
2510 return result;
2511}
2512
2513
2514
2515
2516
2517
2518
2519#ifdef CONFIG_PM
2520void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2521{
2522 u8 val;
2523 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2524 | SDHCI_WAKE_ON_INT;
2525
2526 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2527 val |= mask ;
2528
2529 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2530 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2531 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2532}
2533EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2534
2535void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2536{
2537 u8 val;
2538 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2539 | SDHCI_WAKE_ON_INT;
2540
2541 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2542 val &= ~mask;
2543 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2544}
2545EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2546
2547int sdhci_suspend_host(struct sdhci_host *host)
2548{
2549 int ret;
2550
2551 if (host->ops->platform_suspend)
2552 host->ops->platform_suspend(host);
2553
2554 sdhci_disable_card_detection(host);
2555
2556
2557 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2558 del_timer_sync(&host->tuning_timer);
2559 host->flags &= ~SDHCI_NEEDS_RETUNING;
2560 }
2561
2562 ret = mmc_suspend_host(host->mmc);
2563 if (ret) {
2564 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2565 host->flags |= SDHCI_NEEDS_RETUNING;
2566 mod_timer(&host->tuning_timer, jiffies +
2567 host->tuning_count * HZ);
2568 }
2569
2570 sdhci_enable_card_detection(host);
2571
2572 return ret;
2573 }
2574
2575 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2576 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2577 free_irq(host->irq, host);
2578 } else {
2579 sdhci_enable_irq_wakeups(host);
2580 enable_irq_wake(host->irq);
2581 }
2582 return ret;
2583}
2584
2585EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2586
2587int sdhci_resume_host(struct sdhci_host *host)
2588{
2589 int ret;
2590
2591 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2592 if (host->ops->enable_dma)
2593 host->ops->enable_dma(host);
2594 }
2595
2596 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2597 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2598 mmc_hostname(host->mmc), host);
2599 if (ret)
2600 return ret;
2601 } else {
2602 sdhci_disable_irq_wakeups(host);
2603 disable_irq_wake(host->irq);
2604 }
2605
2606 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2607 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2608
2609 sdhci_init(host, 0);
2610 host->pwr = 0;
2611 host->clock = 0;
2612 sdhci_do_set_ios(host, &host->mmc->ios);
2613 } else {
2614 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2615 mmiowb();
2616 }
2617
2618 ret = mmc_resume_host(host->mmc);
2619 sdhci_enable_card_detection(host);
2620
2621 if (host->ops->platform_resume)
2622 host->ops->platform_resume(host);
2623
2624
2625 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2626 host->flags |= SDHCI_NEEDS_RETUNING;
2627
2628 return ret;
2629}
2630
2631EXPORT_SYMBOL_GPL(sdhci_resume_host);
2632#endif
2633
2634#ifdef CONFIG_PM_RUNTIME
2635
2636static int sdhci_runtime_pm_get(struct sdhci_host *host)
2637{
2638 return pm_runtime_get_sync(host->mmc->parent);
2639}
2640
2641static int sdhci_runtime_pm_put(struct sdhci_host *host)
2642{
2643 pm_runtime_mark_last_busy(host->mmc->parent);
2644 return pm_runtime_put_autosuspend(host->mmc->parent);
2645}
2646
2647static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2648{
2649 if (host->runtime_suspended || host->bus_on)
2650 return;
2651 host->bus_on = true;
2652 pm_runtime_get_noresume(host->mmc->parent);
2653}
2654
2655static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2656{
2657 if (host->runtime_suspended || !host->bus_on)
2658 return;
2659 host->bus_on = false;
2660 pm_runtime_put_noidle(host->mmc->parent);
2661}
2662
2663int sdhci_runtime_suspend_host(struct sdhci_host *host)
2664{
2665 unsigned long flags;
2666 int ret = 0;
2667
2668
2669 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2670 del_timer_sync(&host->tuning_timer);
2671 host->flags &= ~SDHCI_NEEDS_RETUNING;
2672 }
2673
2674 spin_lock_irqsave(&host->lock, flags);
2675 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2676 spin_unlock_irqrestore(&host->lock, flags);
2677
2678 synchronize_irq(host->irq);
2679
2680 spin_lock_irqsave(&host->lock, flags);
2681 host->runtime_suspended = true;
2682 spin_unlock_irqrestore(&host->lock, flags);
2683
2684 return ret;
2685}
2686EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2687
2688int sdhci_runtime_resume_host(struct sdhci_host *host)
2689{
2690 unsigned long flags;
2691 int ret = 0, host_flags = host->flags;
2692
2693 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2694 if (host->ops->enable_dma)
2695 host->ops->enable_dma(host);
2696 }
2697
2698 sdhci_init(host, 0);
2699
2700
2701 host->pwr = 0;
2702 host->clock = 0;
2703 sdhci_do_set_ios(host, &host->mmc->ios);
2704
2705 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2706 if ((host_flags & SDHCI_PV_ENABLED) &&
2707 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2708 spin_lock_irqsave(&host->lock, flags);
2709 sdhci_enable_preset_value(host, true);
2710 spin_unlock_irqrestore(&host->lock, flags);
2711 }
2712
2713
2714 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2715 host->flags |= SDHCI_NEEDS_RETUNING;
2716
2717 spin_lock_irqsave(&host->lock, flags);
2718
2719 host->runtime_suspended = false;
2720
2721
2722 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2723 sdhci_enable_sdio_irq_nolock(host, true);
2724
2725
2726 sdhci_enable_card_detection(host);
2727
2728 spin_unlock_irqrestore(&host->lock, flags);
2729
2730 return ret;
2731}
2732EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2733
2734#endif
2735
2736
2737
2738
2739
2740
2741
2742struct sdhci_host *sdhci_alloc_host(struct device *dev,
2743 size_t priv_size)
2744{
2745 struct mmc_host *mmc;
2746 struct sdhci_host *host;
2747
2748 WARN_ON(dev == NULL);
2749
2750 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2751 if (!mmc)
2752 return ERR_PTR(-ENOMEM);
2753
2754 host = mmc_priv(mmc);
2755 host->mmc = mmc;
2756
2757 return host;
2758}
2759
2760EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2761
2762int sdhci_add_host(struct sdhci_host *host)
2763{
2764 struct mmc_host *mmc;
2765 u32 caps[2] = {0, 0};
2766 u32 max_current_caps;
2767 unsigned int ocr_avail;
2768 int ret;
2769
2770 WARN_ON(host == NULL);
2771 if (host == NULL)
2772 return -EINVAL;
2773
2774 mmc = host->mmc;
2775
2776 if (debug_quirks)
2777 host->quirks = debug_quirks;
2778 if (debug_quirks2)
2779 host->quirks2 = debug_quirks2;
2780
2781 sdhci_reset(host, SDHCI_RESET_ALL);
2782
2783 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2784 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2785 >> SDHCI_SPEC_VER_SHIFT;
2786 if (host->version > SDHCI_SPEC_300) {
2787 pr_err("%s: Unknown controller version (%d). "
2788 "You may experience problems.\n", mmc_hostname(mmc),
2789 host->version);
2790 }
2791
2792 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2793 sdhci_readl(host, SDHCI_CAPABILITIES);
2794
2795 if (host->version >= SDHCI_SPEC_300)
2796 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2797 host->caps1 :
2798 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2799
2800 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2801 host->flags |= SDHCI_USE_SDMA;
2802 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2803 DBG("Controller doesn't have SDMA capability\n");
2804 else
2805 host->flags |= SDHCI_USE_SDMA;
2806
2807 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2808 (host->flags & SDHCI_USE_SDMA)) {
2809 DBG("Disabling DMA as it is marked broken\n");
2810 host->flags &= ~SDHCI_USE_SDMA;
2811 }
2812
2813 if ((host->version >= SDHCI_SPEC_200) &&
2814 (caps[0] & SDHCI_CAN_DO_ADMA2))
2815 host->flags |= SDHCI_USE_ADMA;
2816
2817 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2818 (host->flags & SDHCI_USE_ADMA)) {
2819 DBG("Disabling ADMA as it is marked broken\n");
2820 host->flags &= ~SDHCI_USE_ADMA;
2821 }
2822
2823 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2824 if (host->ops->enable_dma) {
2825 if (host->ops->enable_dma(host)) {
2826 pr_warning("%s: No suitable DMA "
2827 "available. Falling back to PIO.\n",
2828 mmc_hostname(mmc));
2829 host->flags &=
2830 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2831 }
2832 }
2833 }
2834
2835 if (host->flags & SDHCI_USE_ADMA) {
2836
2837
2838
2839
2840
2841 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2842 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2843 if (!host->adma_desc || !host->align_buffer) {
2844 kfree(host->adma_desc);
2845 kfree(host->align_buffer);
2846 pr_warning("%s: Unable to allocate ADMA "
2847 "buffers. Falling back to standard DMA.\n",
2848 mmc_hostname(mmc));
2849 host->flags &= ~SDHCI_USE_ADMA;
2850 }
2851 }
2852
2853
2854
2855
2856
2857
2858 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2859 host->dma_mask = DMA_BIT_MASK(64);
2860 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2861 }
2862
2863 if (host->version >= SDHCI_SPEC_300)
2864 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2865 >> SDHCI_CLOCK_BASE_SHIFT;
2866 else
2867 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2868 >> SDHCI_CLOCK_BASE_SHIFT;
2869
2870 host->max_clk *= 1000000;
2871 if (host->max_clk == 0 || host->quirks &
2872 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2873 if (!host->ops->get_max_clock) {
2874 pr_err("%s: Hardware doesn't specify base clock "
2875 "frequency.\n", mmc_hostname(mmc));
2876 return -ENODEV;
2877 }
2878 host->max_clk = host->ops->get_max_clock(host);
2879 }
2880
2881
2882
2883
2884
2885 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2886 SDHCI_CLOCK_MUL_SHIFT;
2887
2888
2889
2890
2891
2892
2893
2894 if (host->clk_mul)
2895 host->clk_mul += 1;
2896
2897
2898
2899
2900 mmc->ops = &sdhci_ops;
2901 mmc->f_max = host->max_clk;
2902 if (host->ops->get_min_clock)
2903 mmc->f_min = host->ops->get_min_clock(host);
2904 else if (host->version >= SDHCI_SPEC_300) {
2905 if (host->clk_mul) {
2906 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2907 mmc->f_max = host->max_clk * host->clk_mul;
2908 } else
2909 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2910 } else
2911 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2912
2913 host->timeout_clk =
2914 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2915 if (host->timeout_clk == 0) {
2916 if (host->ops->get_timeout_clock) {
2917 host->timeout_clk = host->ops->get_timeout_clock(host);
2918 } else if (!(host->quirks &
2919 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2920 pr_err("%s: Hardware doesn't specify timeout clock "
2921 "frequency.\n", mmc_hostname(mmc));
2922 return -ENODEV;
2923 }
2924 }
2925 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2926 host->timeout_clk *= 1000;
2927
2928 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2929 host->timeout_clk = mmc->f_max / 1000;
2930
2931 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2932
2933 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2934
2935 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2936 host->flags |= SDHCI_AUTO_CMD12;
2937
2938
2939 if ((host->version >= SDHCI_SPEC_300) &&
2940 ((host->flags & SDHCI_USE_ADMA) ||
2941 !(host->flags & SDHCI_USE_SDMA))) {
2942 host->flags |= SDHCI_AUTO_CMD23;
2943 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2944 } else {
2945 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2946 }
2947
2948
2949
2950
2951
2952
2953
2954
2955 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2956 mmc->caps |= MMC_CAP_4_BIT_DATA;
2957
2958 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2959 mmc->caps &= ~MMC_CAP_CMD23;
2960
2961 if (caps[0] & SDHCI_CAN_DO_HISPD)
2962 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2963
2964 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2965 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2966 mmc->caps |= MMC_CAP_NEEDS_POLL;
2967
2968
2969 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2970 if (IS_ERR_OR_NULL(host->vqmmc)) {
2971 if (PTR_ERR(host->vqmmc) < 0) {
2972 pr_info("%s: no vqmmc regulator found\n",
2973 mmc_hostname(mmc));
2974 host->vqmmc = NULL;
2975 }
2976 } else {
2977 ret = regulator_enable(host->vqmmc);
2978 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2979 1950000))
2980 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2981 SDHCI_SUPPORT_SDR50 |
2982 SDHCI_SUPPORT_DDR50);
2983 if (ret) {
2984 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2985 mmc_hostname(mmc), ret);
2986 host->vqmmc = NULL;
2987 }
2988 }
2989
2990 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2991 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2992 SDHCI_SUPPORT_DDR50);
2993
2994
2995 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2996 SDHCI_SUPPORT_DDR50))
2997 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2998
2999
3000 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3001 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3002
3003
3004
3005 mmc->caps2 |= MMC_CAP2_HS200;
3006 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3007 mmc->caps |= MMC_CAP_UHS_SDR50;
3008
3009 if (caps[1] & SDHCI_SUPPORT_DDR50)
3010 mmc->caps |= MMC_CAP_UHS_DDR50;
3011
3012
3013 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3014 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3015
3016
3017 if (mmc->caps2 & MMC_CAP2_HS200)
3018 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3019
3020
3021 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3022 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3023 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3024 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3025 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3026 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3027
3028
3029 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3030 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3031
3032
3033
3034
3035
3036 if (host->tuning_count)
3037 host->tuning_count = 1 << (host->tuning_count - 1);
3038
3039
3040 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3041 SDHCI_RETUNING_MODE_SHIFT;
3042
3043 ocr_avail = 0;
3044
3045 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3046 if (IS_ERR_OR_NULL(host->vmmc)) {
3047 if (PTR_ERR(host->vmmc) < 0) {
3048 pr_info("%s: no vmmc regulator found\n",
3049 mmc_hostname(mmc));
3050 host->vmmc = NULL;
3051 }
3052 }
3053
3054#ifdef CONFIG_REGULATOR
3055
3056
3057
3058
3059 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3060 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3061 3600000);
3062 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3063 caps[0] &= ~SDHCI_CAN_VDD_330;
3064 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3065 caps[0] &= ~SDHCI_CAN_VDD_300;
3066 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3067 1950000);
3068 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3069 caps[0] &= ~SDHCI_CAN_VDD_180;
3070 }
3071#endif
3072
3073
3074
3075
3076
3077
3078
3079
3080 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3081 if (!max_current_caps && host->vmmc) {
3082 u32 curr = regulator_get_current_limit(host->vmmc);
3083 if (curr > 0) {
3084
3085
3086 curr = curr/1000;
3087 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3088
3089 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3090 max_current_caps =
3091 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3092 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3093 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3094 }
3095 }
3096
3097 if (caps[0] & SDHCI_CAN_VDD_330) {
3098 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3099
3100 mmc->max_current_330 = ((max_current_caps &
3101 SDHCI_MAX_CURRENT_330_MASK) >>
3102 SDHCI_MAX_CURRENT_330_SHIFT) *
3103 SDHCI_MAX_CURRENT_MULTIPLIER;
3104 }
3105 if (caps[0] & SDHCI_CAN_VDD_300) {
3106 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3107
3108 mmc->max_current_300 = ((max_current_caps &
3109 SDHCI_MAX_CURRENT_300_MASK) >>
3110 SDHCI_MAX_CURRENT_300_SHIFT) *
3111 SDHCI_MAX_CURRENT_MULTIPLIER;
3112 }
3113 if (caps[0] & SDHCI_CAN_VDD_180) {
3114 ocr_avail |= MMC_VDD_165_195;
3115
3116 mmc->max_current_180 = ((max_current_caps &
3117 SDHCI_MAX_CURRENT_180_MASK) >>
3118 SDHCI_MAX_CURRENT_180_SHIFT) *
3119 SDHCI_MAX_CURRENT_MULTIPLIER;
3120 }
3121
3122 mmc->ocr_avail = ocr_avail;
3123 mmc->ocr_avail_sdio = ocr_avail;
3124 if (host->ocr_avail_sdio)
3125 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3126 mmc->ocr_avail_sd = ocr_avail;
3127 if (host->ocr_avail_sd)
3128 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3129 else
3130 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3131 mmc->ocr_avail_mmc = ocr_avail;
3132 if (host->ocr_avail_mmc)
3133 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3134
3135 if (mmc->ocr_avail == 0) {
3136 pr_err("%s: Hardware doesn't report any "
3137 "support voltages.\n", mmc_hostname(mmc));
3138 return -ENODEV;
3139 }
3140
3141 spin_lock_init(&host->lock);
3142
3143
3144
3145
3146
3147 if (host->flags & SDHCI_USE_ADMA)
3148 mmc->max_segs = 128;
3149 else if (host->flags & SDHCI_USE_SDMA)
3150 mmc->max_segs = 1;
3151 else
3152 mmc->max_segs = 128;
3153
3154
3155
3156
3157
3158 mmc->max_req_size = 524288;
3159
3160
3161
3162
3163
3164
3165 if (host->flags & SDHCI_USE_ADMA) {
3166 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3167 mmc->max_seg_size = 65535;
3168 else
3169 mmc->max_seg_size = 65536;
3170 } else {
3171 mmc->max_seg_size = mmc->max_req_size;
3172 }
3173
3174
3175
3176
3177
3178 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3179 mmc->max_blk_size = 2;
3180 } else {
3181 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3182 SDHCI_MAX_BLOCK_SHIFT;
3183 if (mmc->max_blk_size >= 3) {
3184 pr_warning("%s: Invalid maximum block size, "
3185 "assuming 512 bytes\n", mmc_hostname(mmc));
3186 mmc->max_blk_size = 0;
3187 }
3188 }
3189
3190 mmc->max_blk_size = 512 << mmc->max_blk_size;
3191
3192
3193
3194
3195 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3196
3197
3198
3199
3200 tasklet_init(&host->card_tasklet,
3201 sdhci_tasklet_card, (unsigned long)host);
3202 tasklet_init(&host->finish_tasklet,
3203 sdhci_tasklet_finish, (unsigned long)host);
3204
3205 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3206
3207 if (host->version >= SDHCI_SPEC_300) {
3208 init_waitqueue_head(&host->buf_ready_int);
3209
3210
3211 init_timer(&host->tuning_timer);
3212 host->tuning_timer.data = (unsigned long)host;
3213 host->tuning_timer.function = sdhci_tuning_timer;
3214 }
3215
3216 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3217 mmc_hostname(mmc), host);
3218 if (ret) {
3219 pr_err("%s: Failed to request IRQ %d: %d\n",
3220 mmc_hostname(mmc), host->irq, ret);
3221 goto untasklet;
3222 }
3223
3224 sdhci_init(host, 0);
3225
3226#ifdef CONFIG_MMC_DEBUG
3227 sdhci_dumpregs(host);
3228#endif
3229
3230#ifdef SDHCI_USE_LEDS_CLASS
3231 snprintf(host->led_name, sizeof(host->led_name),
3232 "%s::", mmc_hostname(mmc));
3233 host->led.name = host->led_name;
3234 host->led.brightness = LED_OFF;
3235 host->led.default_trigger = mmc_hostname(mmc);
3236 host->led.brightness_set = sdhci_led_control;
3237
3238 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3239 if (ret) {
3240 pr_err("%s: Failed to register LED device: %d\n",
3241 mmc_hostname(mmc), ret);
3242 goto reset;
3243 }
3244#endif
3245
3246 mmiowb();
3247
3248 mmc_add_host(mmc);
3249
3250 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3251 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3252 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3253 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3254
3255 sdhci_enable_card_detection(host);
3256
3257 return 0;
3258
3259#ifdef SDHCI_USE_LEDS_CLASS
3260reset:
3261 sdhci_reset(host, SDHCI_RESET_ALL);
3262 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3263 free_irq(host->irq, host);
3264#endif
3265untasklet:
3266 tasklet_kill(&host->card_tasklet);
3267 tasklet_kill(&host->finish_tasklet);
3268
3269 return ret;
3270}
3271
3272EXPORT_SYMBOL_GPL(sdhci_add_host);
3273
3274void sdhci_remove_host(struct sdhci_host *host, int dead)
3275{
3276 unsigned long flags;
3277
3278 if (dead) {
3279 spin_lock_irqsave(&host->lock, flags);
3280
3281 host->flags |= SDHCI_DEVICE_DEAD;
3282
3283 if (host->mrq) {
3284 pr_err("%s: Controller removed during "
3285 " transfer!\n", mmc_hostname(host->mmc));
3286
3287 host->mrq->cmd->error = -ENOMEDIUM;
3288 tasklet_schedule(&host->finish_tasklet);
3289 }
3290
3291 spin_unlock_irqrestore(&host->lock, flags);
3292 }
3293
3294 sdhci_disable_card_detection(host);
3295
3296 mmc_remove_host(host->mmc);
3297
3298#ifdef SDHCI_USE_LEDS_CLASS
3299 led_classdev_unregister(&host->led);
3300#endif
3301
3302 if (!dead)
3303 sdhci_reset(host, SDHCI_RESET_ALL);
3304
3305 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3306 free_irq(host->irq, host);
3307
3308 del_timer_sync(&host->timer);
3309
3310 tasklet_kill(&host->card_tasklet);
3311 tasklet_kill(&host->finish_tasklet);
3312
3313 if (host->vmmc) {
3314 regulator_disable(host->vmmc);
3315 regulator_put(host->vmmc);
3316 }
3317
3318 if (host->vqmmc) {
3319 regulator_disable(host->vqmmc);
3320 regulator_put(host->vqmmc);
3321 }
3322
3323 kfree(host->adma_desc);
3324 kfree(host->align_buffer);
3325
3326 host->adma_desc = NULL;
3327 host->align_buffer = NULL;
3328}
3329
3330EXPORT_SYMBOL_GPL(sdhci_remove_host);
3331
3332void sdhci_free_host(struct sdhci_host *host)
3333{
3334 mmc_free_host(host->mmc);
3335}
3336
3337EXPORT_SYMBOL_GPL(sdhci_free_host);
3338
3339
3340
3341
3342
3343
3344
3345static int __init sdhci_drv_init(void)
3346{
3347 pr_info(DRIVER_NAME
3348 ": Secure Digital Host Controller Interface driver\n");
3349 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3350
3351 return 0;
3352}
3353
3354static void __exit sdhci_drv_exit(void)
3355{
3356}
3357
3358module_init(sdhci_drv_init);
3359module_exit(sdhci_drv_exit);
3360
3361module_param(debug_quirks, uint, 0444);
3362module_param(debug_quirks2, uint, 0444);
3363
3364MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3365MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3366MODULE_LICENSE("GPL");
3367
3368MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3369MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3370