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17#ifndef BNX2X_CMN_H
18#define BNX2X_CMN_H
19
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24
25#include "bnx2x.h"
26#include "bnx2x_sriov.h"
27
28
29extern int load_count[2][3];
30
31extern int num_queues;
32extern int int_mode;
33
34
35#define BNX2X_PCI_FREE(x, y, size) \
36 do { \
37 if (x) { \
38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
39 x = NULL; \
40 y = 0; \
41 } \
42 } while (0)
43
44#define BNX2X_FREE(x) \
45 do { \
46 if (x) { \
47 kfree((void *)x); \
48 x = NULL; \
49 } \
50 } while (0)
51
52#define BNX2X_PCI_ALLOC(x, y, size) \
53 do { \
54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \
55 GFP_KERNEL | __GFP_ZERO); \
56 if (x == NULL) \
57 goto alloc_mem_err; \
58 DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
59 (unsigned long long)(*y), x); \
60 } while (0)
61
62#define BNX2X_PCI_FALLOC(x, y, size) \
63 do { \
64 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
65 if (x == NULL) \
66 goto alloc_mem_err; \
67 memset((void *)x, 0xFFFFFFFF, size); \
68 DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\
69 (unsigned long long)(*y), x); \
70 } while (0)
71
72#define BNX2X_ALLOC(x, size) \
73 do { \
74 x = kzalloc(size, GFP_KERNEL); \
75 if (x == NULL) \
76 goto alloc_mem_err; \
77 } while (0)
78
79
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90
91
92u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
93
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97
98
99
100void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
101
102
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107
108
109
110int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
111 bool config_hash);
112
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118
119
120
121
122void bnx2x__init_func_obj(struct bnx2x *bp);
123
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130
131
132int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
133 bool leading);
134
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137
138
139
140int bnx2x_setup_leading(struct bnx2x *bp);
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149
150
151u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
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158
159int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
160
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164
165
166void bnx2x_link_set(struct bnx2x *bp);
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172
173
174void bnx2x_force_link_reset(struct bnx2x *bp);
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183
184u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
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192
193
194void bnx2x_drv_pulse(struct bnx2x *bp);
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204
205
206void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
207 u16 index, u8 op, u8 update);
208
209
210void bnx2x_pf_disable(struct bnx2x *bp);
211int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
212
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215
216
217
218void bnx2x__link_status_update(struct bnx2x *bp);
219
220
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223
224
225void bnx2x_link_report(struct bnx2x *bp);
226
227
228void __bnx2x_link_report(struct bnx2x *bp);
229
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236
237u16 bnx2x_get_mf_speed(struct bnx2x *bp);
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244
245irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
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253irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
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261int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
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266
267
268void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
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275void bnx2x_setup_cnic_info(struct bnx2x *bp);
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281
282void bnx2x_int_enable(struct bnx2x *bp);
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293void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
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305
306void bnx2x_nic_init_cnic(struct bnx2x *bp);
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317
318void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
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331void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
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336
337int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
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341
342
343int bnx2x_alloc_mem(struct bnx2x *bp);
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348
349
350void bnx2x_free_mem_cnic(struct bnx2x *bp);
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356void bnx2x_free_mem(struct bnx2x *bp);
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362
363void bnx2x_set_num_queues(struct bnx2x *bp);
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375
376void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
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382
383
384int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
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392int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
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399int bnx2x_release_leader_lock(struct bnx2x *bp);
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409int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
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419
420void bnx2x_set_rx_mode(struct net_device *dev);
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430int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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441
442int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
443 unsigned long rx_mode_flags,
444 unsigned long rx_accept_flags,
445 unsigned long tx_accept_flags,
446 unsigned long ramrod_flags);
447
448
449void bnx2x_set_pf_load(struct bnx2x *bp);
450bool bnx2x_clear_pf_load(struct bnx2x *bp);
451bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
452bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
453void bnx2x_set_reset_in_progress(struct bnx2x *bp);
454void bnx2x_set_reset_global(struct bnx2x *bp);
455void bnx2x_disable_close_the_gate(struct bnx2x *bp);
456int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
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463
464void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
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468
469
470
471void bnx2x_ilt_set_info(struct bnx2x *bp);
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477
478
479void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
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484
485
486void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
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494
495
496int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
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504void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
505
506void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
507
508
509int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
510
511
512int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
513
514
515netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
516
517
518int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
519
520int bnx2x_get_vf_config(struct net_device *dev, int vf,
521 struct ifla_vf_info *ivi);
522int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
523int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
524
525
526u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
527
528static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
529 struct bnx2x_fastpath *fp,
530 u16 bd_prod, u16 rx_comp_prod,
531 u16 rx_sge_prod)
532{
533 struct ustorm_eth_rx_producers rx_prods = {0};
534 u32 i;
535
536
537 rx_prods.bd_prod = bd_prod;
538 rx_prods.cqe_prod = rx_comp_prod;
539 rx_prods.sge_prod = rx_sge_prod;
540
541
542
543
544
545
546
547
548 wmb();
549
550 for (i = 0; i < sizeof(rx_prods)/4; i++)
551 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
552 ((u32 *)&rx_prods)[i]);
553
554 mmiowb();
555
556 DP(NETIF_MSG_RX_STATUS,
557 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
558 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
559}
560
561
562int bnx2x_reload_if_running(struct net_device *dev);
563
564int bnx2x_change_mac_addr(struct net_device *dev, void *p);
565
566
567int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
568
569
570int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
571
572
573int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
574int bnx2x_resume(struct pci_dev *pdev);
575
576
577void bnx2x_free_irq(struct bnx2x *bp);
578
579void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
580void bnx2x_free_fp_mem(struct bnx2x *bp);
581int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
582int bnx2x_alloc_fp_mem(struct bnx2x *bp);
583void bnx2x_init_rx_rings(struct bnx2x *bp);
584void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
585void bnx2x_free_skbs_cnic(struct bnx2x *bp);
586void bnx2x_free_skbs(struct bnx2x *bp);
587void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
588void bnx2x_netif_start(struct bnx2x *bp);
589int bnx2x_load_cnic(struct bnx2x *bp);
590
591
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596
597
598
599int bnx2x_enable_msix(struct bnx2x *bp);
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604
605
606int bnx2x_enable_msi(struct bnx2x *bp);
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614
615int bnx2x_poll(struct napi_struct *napi, int budget);
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617
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619
620
621
622int bnx2x_low_latency_recv(struct napi_struct *napi);
623
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628
629int bnx2x_alloc_mem_bp(struct bnx2x *bp);
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631
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633
634
635
636void bnx2x_free_mem_bp(struct bnx2x *bp);
637
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642
643
644
645int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
646
647#ifdef NETDEV_FCOE_WWNN
648
649
650
651
652
653
654
655
656int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
657#endif
658
659netdev_features_t bnx2x_fix_features(struct net_device *dev,
660 netdev_features_t features);
661int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
662
663
664
665
666
667
668void bnx2x_tx_timeout(struct net_device *dev);
669
670
671
672static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
673{
674 barrier();
675 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
676}
677
678static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
679 u8 segment, u16 index, u8 op,
680 u8 update, u32 igu_addr)
681{
682 struct igu_regular cmd_data = {0};
683
684 cmd_data.sb_id_and_flags =
685 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
686 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
687 (update << IGU_REGULAR_BUPDATE_SHIFT) |
688 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
689
690 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
691 cmd_data.sb_id_and_flags, igu_addr);
692 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
693
694
695 mmiowb();
696 barrier();
697}
698
699static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
700 u8 storm, u16 index, u8 op, u8 update)
701{
702 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
703 COMMAND_REG_INT_ACK);
704 struct igu_ack_register igu_ack;
705
706 igu_ack.status_block_index = index;
707 igu_ack.sb_id_and_flags =
708 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
709 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
710 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
711 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
712
713 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
714
715
716 mmiowb();
717 barrier();
718}
719
720static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
721 u16 index, u8 op, u8 update)
722{
723 if (bp->common.int_block == INT_BLOCK_HC)
724 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
725 else {
726 u8 segment;
727
728 if (CHIP_INT_MODE_IS_BC(bp))
729 segment = storm;
730 else if (igu_sb_id != bp->igu_dsb_id)
731 segment = IGU_SEG_ACCESS_DEF;
732 else if (storm == ATTENTION_ID)
733 segment = IGU_SEG_ACCESS_ATTN;
734 else
735 segment = IGU_SEG_ACCESS_DEF;
736 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
737 }
738}
739
740static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
741{
742 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
743 COMMAND_REG_SIMD_MASK);
744 u32 result = REG_RD(bp, hc_addr);
745
746 barrier();
747 return result;
748}
749
750static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
751{
752 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
753 u32 result = REG_RD(bp, igu_addr);
754
755 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
756 result, igu_addr);
757
758 barrier();
759 return result;
760}
761
762static inline u16 bnx2x_ack_int(struct bnx2x *bp)
763{
764 barrier();
765 if (bp->common.int_block == INT_BLOCK_HC)
766 return bnx2x_hc_ack_int(bp);
767 else
768 return bnx2x_igu_ack_int(bp);
769}
770
771static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
772{
773
774 barrier();
775 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
776}
777
778static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
779 struct bnx2x_fp_txdata *txdata)
780{
781 s16 used;
782 u16 prod;
783 u16 cons;
784
785 prod = txdata->tx_bd_prod;
786 cons = txdata->tx_bd_cons;
787
788 used = SUB_S16(prod, cons);
789
790#ifdef BNX2X_STOP_ON_ERROR
791 WARN_ON(used < 0);
792 WARN_ON(used > txdata->tx_ring_size);
793 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
794#endif
795
796 return (s16)(txdata->tx_ring_size) - used;
797}
798
799static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
800{
801 u16 hw_cons;
802
803
804 barrier();
805 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
806 return hw_cons != txdata->tx_pkt_cons;
807}
808
809static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
810{
811 u8 cos;
812 for_each_cos_in_tx_queue(fp, cos)
813 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
814 return true;
815 return false;
816}
817
818#define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
819#define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
820static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
821{
822 u16 cons;
823 union eth_rx_cqe *cqe;
824 struct eth_fast_path_rx_cqe *cqe_fp;
825
826 cons = RCQ_BD(fp->rx_comp_cons);
827 cqe = &fp->rx_comp_ring[cons];
828 cqe_fp = &cqe->fast_path_cqe;
829 return BNX2X_IS_CQE_COMPLETED(cqe_fp);
830}
831
832
833
834
835
836
837static inline void bnx2x_tx_disable(struct bnx2x *bp)
838{
839 netif_tx_disable(bp->dev);
840 netif_carrier_off(bp->dev);
841}
842
843static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
844 struct bnx2x_fastpath *fp, u16 index)
845{
846 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
847 struct page *page = sw_buf->page;
848 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
849
850
851 if (!page)
852 return;
853
854 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
855 SGE_PAGES, DMA_FROM_DEVICE);
856 __free_pages(page, PAGES_PER_SGE_SHIFT);
857
858 sw_buf->page = NULL;
859 sge->addr_hi = 0;
860 sge->addr_lo = 0;
861}
862
863static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
864{
865 int i;
866
867
868 for_each_rx_queue_cnic(bp, i) {
869 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
870 bnx2x_poll, NAPI_POLL_WEIGHT);
871 napi_hash_add(&bnx2x_fp(bp, i, napi));
872 }
873}
874
875static inline void bnx2x_add_all_napi(struct bnx2x *bp)
876{
877 int i;
878
879
880 for_each_eth_queue(bp, i) {
881 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
882 bnx2x_poll, NAPI_POLL_WEIGHT);
883 napi_hash_add(&bnx2x_fp(bp, i, napi));
884 }
885}
886
887static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
888{
889 int i;
890
891 for_each_rx_queue_cnic(bp, i) {
892 napi_hash_del(&bnx2x_fp(bp, i, napi));
893 netif_napi_del(&bnx2x_fp(bp, i, napi));
894 }
895}
896
897static inline void bnx2x_del_all_napi(struct bnx2x *bp)
898{
899 int i;
900
901 for_each_eth_queue(bp, i) {
902 napi_hash_del(&bnx2x_fp(bp, i, napi));
903 netif_napi_del(&bnx2x_fp(bp, i, napi));
904 }
905}
906
907int bnx2x_set_int_mode(struct bnx2x *bp);
908
909static inline void bnx2x_disable_msi(struct bnx2x *bp)
910{
911 if (bp->flags & USING_MSIX_FLAG) {
912 pci_disable_msix(bp->pdev);
913 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
914 } else if (bp->flags & USING_MSI_FLAG) {
915 pci_disable_msi(bp->pdev);
916 bp->flags &= ~USING_MSI_FLAG;
917 }
918}
919
920static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
921{
922 return num_queues ?
923 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
924 min_t(int, netif_get_num_default_rss_queues(),
925 BNX2X_MAX_QUEUES(bp));
926}
927
928static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
929{
930 int i, j;
931
932 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
933 int idx = RX_SGE_CNT * i - 1;
934
935 for (j = 0; j < 2; j++) {
936 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
937 idx--;
938 }
939 }
940}
941
942static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
943{
944
945 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
946
947
948
949
950
951 bnx2x_clear_sge_mask_next_elems(fp);
952}
953
954
955
956
957
958
959static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
960 u16 cons, u16 prod)
961{
962 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
963 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
964 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
965 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
966
967 dma_unmap_addr_set(prod_rx_buf, mapping,
968 dma_unmap_addr(cons_rx_buf, mapping));
969 prod_rx_buf->data = cons_rx_buf->data;
970 *prod_bd = *cons_bd;
971}
972
973
974
975
976static inline int func_by_vn(struct bnx2x *bp, int vn)
977{
978 return 2 * vn + BP_PORT(bp);
979}
980
981static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
982{
983 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash);
984}
985
986
987
988
989
990
991
992
993static inline int bnx2x_func_start(struct bnx2x *bp)
994{
995 struct bnx2x_func_state_params func_params = {NULL};
996 struct bnx2x_func_start_params *start_params =
997 &func_params.params.start;
998
999
1000 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1001
1002 func_params.f_obj = &bp->func_obj;
1003 func_params.cmd = BNX2X_F_CMD_START;
1004
1005
1006 start_params->mf_mode = bp->mf_mode;
1007 start_params->sd_vlan_tag = bp->mf_ov;
1008
1009 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
1010 start_params->network_cos_mode = STATIC_COS;
1011 else
1012 start_params->network_cos_mode = FW_WRR;
1013
1014 start_params->gre_tunnel_mode = IPGRE_TUNNEL;
1015 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
1016
1017 return bnx2x_func_state_change(bp, &func_params);
1018}
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
1029 __le16 *fw_lo, u8 *mac)
1030{
1031 ((u8 *)fw_hi)[0] = mac[1];
1032 ((u8 *)fw_hi)[1] = mac[0];
1033 ((u8 *)fw_mid)[0] = mac[3];
1034 ((u8 *)fw_mid)[1] = mac[2];
1035 ((u8 *)fw_lo)[0] = mac[5];
1036 ((u8 *)fw_lo)[1] = mac[4];
1037}
1038
1039static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1040 struct bnx2x_fastpath *fp, int last)
1041{
1042 int i;
1043
1044 if (fp->disable_tpa)
1045 return;
1046
1047 for (i = 0; i < last; i++)
1048 bnx2x_free_rx_sge(bp, fp, i);
1049}
1050
1051static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
1052{
1053 int i;
1054
1055 for (i = 1; i <= NUM_RX_RINGS; i++) {
1056 struct eth_rx_bd *rx_bd;
1057
1058 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
1059 rx_bd->addr_hi =
1060 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1061 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1062 rx_bd->addr_lo =
1063 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1064 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1065 }
1066}
1067
1068
1069
1070
1071static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1072{
1073 struct bnx2x *bp = fp->bp;
1074 if (!CHIP_IS_E1x(bp)) {
1075
1076 if (IS_FCOE_FP(fp))
1077 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1078 return fp->cl_id;
1079 }
1080 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1081}
1082
1083static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1084 bnx2x_obj_type obj_type)
1085{
1086 struct bnx2x *bp = fp->bp;
1087
1088
1089 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1090 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1091 bnx2x_sp_mapping(bp, mac_rdata),
1092 BNX2X_FILTER_MAC_PENDING,
1093 &bp->sp_state, obj_type,
1094 &bp->macs_pool);
1095}
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1106{
1107 u8 func_num = 0, i;
1108
1109
1110 if (CHIP_IS_E1(bp))
1111 return 1;
1112
1113
1114
1115
1116 if (CHIP_REV_IS_SLOW(bp)) {
1117 if (IS_MF(bp))
1118 func_num = 4;
1119 else
1120 func_num = 2;
1121 } else {
1122 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1123 u32 func_config =
1124 MF_CFG_RD(bp,
1125 func_mf_config[BP_PORT(bp) + 2 * i].
1126 config);
1127 func_num +=
1128 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1129 }
1130 }
1131
1132 WARN_ON(!func_num);
1133
1134 return func_num;
1135}
1136
1137static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1138{
1139
1140 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1141
1142
1143 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1144 BP_FUNC(bp), BP_FUNC(bp),
1145 bnx2x_sp(bp, mcast_rdata),
1146 bnx2x_sp_mapping(bp, mcast_rdata),
1147 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1148 BNX2X_OBJ_TYPE_RX);
1149
1150
1151 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1152 bnx2x_get_path_func_num(bp));
1153
1154 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,
1155 bnx2x_get_path_func_num(bp));
1156
1157
1158 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1159 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1160 bnx2x_sp(bp, rss_rdata),
1161 bnx2x_sp_mapping(bp, rss_rdata),
1162 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1163 BNX2X_OBJ_TYPE_RX);
1164}
1165
1166static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1167{
1168 if (CHIP_IS_E1x(fp->bp))
1169 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1170 else
1171 return fp->cl_id;
1172}
1173
1174u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
1175
1176static inline void bnx2x_init_txdata(struct bnx2x *bp,
1177 struct bnx2x_fp_txdata *txdata, u32 cid,
1178 int txq_index, __le16 *tx_cons_sb,
1179 struct bnx2x_fastpath *fp)
1180{
1181 txdata->cid = cid;
1182 txdata->txq_index = txq_index;
1183 txdata->tx_cons_sb = tx_cons_sb;
1184 txdata->parent_fp = fp;
1185 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1186
1187 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1188 txdata->cid, txdata->txq_index);
1189}
1190
1191static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1192{
1193 return bp->cnic_base_cl_id + cl_idx +
1194 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1195}
1196
1197static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1198{
1199
1200 return bp->base_fw_ndsb;
1201}
1202
1203static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1204{
1205 return bp->igu_base_sb;
1206}
1207
1208static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1209{
1210 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
1211 unsigned long q_type = 0;
1212
1213 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
1214 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
1215 BNX2X_FCOE_ETH_CL_ID_IDX);
1216 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
1217 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1218 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1219 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1220 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
1221 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
1222 fp);
1223
1224 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
1225
1226
1227 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
1228
1229 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
1230 bnx2x_rx_ustorm_prods_offset(fp);
1231
1232
1233 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1234 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1235
1236
1237 BUG_ON(fp->max_cos != 1);
1238
1239 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
1240 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
1241 bnx2x_sp_mapping(bp, q_rdata), q_type);
1242
1243 DP(NETIF_MSG_IFUP,
1244 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
1245 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
1246 fp->igu_sb_id);
1247}
1248
1249static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1250 struct bnx2x_fp_txdata *txdata)
1251{
1252 int cnt = 1000;
1253
1254 while (bnx2x_has_tx_work_unload(txdata)) {
1255 if (!cnt) {
1256 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1257 txdata->txq_index, txdata->tx_pkt_prod,
1258 txdata->tx_pkt_cons);
1259#ifdef BNX2X_STOP_ON_ERROR
1260 bnx2x_panic();
1261 return -EBUSY;
1262#else
1263 break;
1264#endif
1265 }
1266 cnt--;
1267 usleep_range(1000, 2000);
1268 }
1269
1270 return 0;
1271}
1272
1273int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1274
1275static inline void __storm_memset_struct(struct bnx2x *bp,
1276 u32 addr, size_t size, u32 *data)
1277{
1278 int i;
1279 for (i = 0; i < size/4; i++)
1280 REG_WR(bp, addr + (i * 4), data[i]);
1281}
1282
1283
1284
1285
1286
1287
1288
1289static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1290{
1291 int tout = 5000;
1292
1293 while (tout--) {
1294 smp_mb();
1295 netif_addr_lock_bh(bp->dev);
1296 if (!(bp->sp_state & mask)) {
1297 netif_addr_unlock_bh(bp->dev);
1298 return true;
1299 }
1300 netif_addr_unlock_bh(bp->dev);
1301
1302 usleep_range(1000, 2000);
1303 }
1304
1305 smp_mb();
1306
1307 netif_addr_lock_bh(bp->dev);
1308 if (bp->sp_state & mask) {
1309 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1310 bp->sp_state, mask);
1311 netif_addr_unlock_bh(bp->dev);
1312 return false;
1313 }
1314 netif_addr_unlock_bh(bp->dev);
1315
1316 return true;
1317}
1318
1319
1320
1321
1322
1323
1324
1325
1326void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1327 u32 cid);
1328
1329void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1330 u8 sb_index, u8 disable, u16 usec);
1331void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1332void bnx2x_release_phy_lock(struct bnx2x *bp);
1333
1334
1335
1336
1337
1338
1339
1340
1341static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1342{
1343 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1344 FUNC_MF_CFG_MAX_BW_SHIFT;
1345 if (!max_cfg) {
1346 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1347 "Max BW configured to 0 - using 100 instead\n");
1348 max_cfg = 100;
1349 }
1350 return max_cfg;
1351}
1352
1353
1354static inline bool bnx2x_mtu_allows_gro(int mtu)
1355{
1356
1357 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1358
1359
1360
1361
1362
1363 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1364}
1365
1366
1367
1368
1369
1370
1371
1372void bnx2x_get_iscsi_info(struct bnx2x *bp);
1373
1374
1375
1376
1377
1378
1379
1380static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1381{
1382 int func;
1383 int vn;
1384
1385
1386 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1387 if (vn == BP_VN(bp))
1388 continue;
1389
1390 func = func_by_vn(bp, vn);
1391 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1392 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1393 }
1394}
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1405{
1406 if (SHMEM2_HAS(bp, drv_flags)) {
1407 u32 drv_flags;
1408 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1409 drv_flags = SHMEM2_RD(bp, drv_flags);
1410
1411 if (set)
1412 SET_FLAGS(drv_flags, flags);
1413 else
1414 RESET_FLAGS(drv_flags, flags);
1415
1416 SHMEM2_WR(bp, drv_flags, drv_flags);
1417 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1418 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1419 }
1420}
1421
1422static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1423{
1424 if (is_valid_ether_addr(addr) ||
1425 (is_zero_ether_addr(addr) &&
1426 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))))
1427 return true;
1428
1429 return false;
1430}
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1441
1442int bnx2x_drain_tx_queues(struct bnx2x *bp);
1443void bnx2x_squeeze_objects(struct bnx2x *bp);
1444
1445#endif
1446