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32#ifndef __CHELSIO_COMMON_H
33#define __CHELSIO_COMMON_H
34
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/ctype.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/netdevice.h>
41#include <linux/ethtool.h>
42#include <linux/mdio.h>
43#include "version.h"
44
45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__)
46#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__)
47#define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__)
48
49
50
51
52
53#define CH_MSG(adapter, level, category, fmt, ...) do { \
54 if ((adapter)->msg_enable & NETIF_MSG_##category) \
55 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
56 ## __VA_ARGS__); \
57} while (0)
58
59#ifdef DEBUG
60# define CH_DBG(adapter, category, fmt, ...) \
61 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
62#else
63# define CH_DBG(adapter, category, fmt, ...)
64#endif
65
66
67#define NETIF_MSG_MMIO 0x8000000
68
69enum {
70 MAX_NPORTS = 2,
71 MAX_FRAME_SIZE = 10240,
72 EEPROMSIZE = 8192,
73 SERNUM_LEN = 16,
74 RSS_TABLE_SIZE = 64,
75 TCB_SIZE = 128,
76 NMTUS = 16,
77 NCCTRL_WIN = 32,
78 PROTO_SRAM_LINES = 128,
79};
80
81#define MAX_RX_COALESCING_LEN 12288U
82
83enum {
84 PAUSE_RX = 1 << 0,
85 PAUSE_TX = 1 << 1,
86 PAUSE_AUTONEG = 1 << 2
87};
88
89enum {
90 SUPPORTED_IRQ = 1 << 24
91};
92
93enum {
94 STAT_ULP_CH0_PBL_OOB,
95 STAT_ULP_CH1_PBL_OOB,
96 STAT_PCI_CORR_ECC,
97
98 IRQ_NUM_STATS
99};
100
101#define TP_VERSION_MAJOR 1
102#define TP_VERSION_MINOR 1
103#define TP_VERSION_MICRO 0
104
105#define S_TP_VERSION_MAJOR 16
106#define M_TP_VERSION_MAJOR 0xFF
107#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
108#define G_TP_VERSION_MAJOR(x) \
109 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
110
111#define S_TP_VERSION_MINOR 8
112#define M_TP_VERSION_MINOR 0xFF
113#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
114#define G_TP_VERSION_MINOR(x) \
115 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
116
117#define S_TP_VERSION_MICRO 0
118#define M_TP_VERSION_MICRO 0xFF
119#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
120#define G_TP_VERSION_MICRO(x) \
121 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
122
123enum {
124 SGE_QSETS = 8,
125 SGE_RXQ_PER_SET = 2,
126 SGE_TXQ_PER_SET = 3
127};
128
129enum sge_context_type {
130 SGE_CNTXT_RDMA = 0,
131 SGE_CNTXT_ETH = 2,
132 SGE_CNTXT_OFLD = 4,
133 SGE_CNTXT_CTRL = 5
134};
135
136enum {
137 AN_PKT_SIZE = 32,
138 IMMED_PKT_SIZE = 48
139};
140
141struct sg_ent {
142 __be32 len[2];
143 __be64 addr[2];
144};
145
146#ifndef SGE_NUM_GENBITS
147
148# define SGE_NUM_GENBITS 2
149#endif
150
151#define TX_DESC_FLITS 16U
152#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
153
154struct cphy;
155struct adapter;
156
157struct mdio_ops {
158 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
159 u16 reg_addr);
160 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
161 u16 reg_addr, u16 val);
162 unsigned mode_support;
163};
164
165struct adapter_info {
166 unsigned char nports0;
167 unsigned char nports1;
168 unsigned char phy_base_addr;
169 unsigned int gpio_out;
170 unsigned char gpio_intr[MAX_NPORTS];
171 unsigned long caps;
172 const struct mdio_ops *mdio_ops;
173 const char *desc;
174};
175
176struct mc5_stats {
177 unsigned long parity_err;
178 unsigned long active_rgn_full;
179 unsigned long nfa_srch_err;
180 unsigned long unknown_cmd;
181 unsigned long reqq_parity_err;
182 unsigned long dispq_parity_err;
183 unsigned long del_act_empty;
184};
185
186struct mc7_stats {
187 unsigned long corr_err;
188 unsigned long uncorr_err;
189 unsigned long parity_err;
190 unsigned long addr_err;
191};
192
193struct mac_stats {
194 u64 tx_octets;
195 u64 tx_octets_bad;
196 u64 tx_frames;
197 u64 tx_mcast_frames;
198 u64 tx_bcast_frames;
199 u64 tx_pause;
200 u64 tx_deferred;
201 u64 tx_late_collisions;
202 u64 tx_total_collisions;
203 u64 tx_excess_collisions;
204 u64 tx_underrun;
205 u64 tx_len_errs;
206 u64 tx_mac_internal_errs;
207 u64 tx_excess_deferral;
208 u64 tx_fcs_errs;
209
210 u64 tx_frames_64;
211 u64 tx_frames_65_127;
212 u64 tx_frames_128_255;
213 u64 tx_frames_256_511;
214 u64 tx_frames_512_1023;
215 u64 tx_frames_1024_1518;
216 u64 tx_frames_1519_max;
217
218 u64 rx_octets;
219 u64 rx_octets_bad;
220 u64 rx_frames;
221 u64 rx_mcast_frames;
222 u64 rx_bcast_frames;
223 u64 rx_pause;
224 u64 rx_fcs_errs;
225 u64 rx_align_errs;
226 u64 rx_symbol_errs;
227 u64 rx_data_errs;
228 u64 rx_sequence_errs;
229 u64 rx_runt;
230 u64 rx_jabber;
231 u64 rx_short;
232 u64 rx_too_long;
233 u64 rx_mac_internal_errs;
234
235 u64 rx_frames_64;
236 u64 rx_frames_65_127;
237 u64 rx_frames_128_255;
238 u64 rx_frames_256_511;
239 u64 rx_frames_512_1023;
240 u64 rx_frames_1024_1518;
241 u64 rx_frames_1519_max;
242
243 u64 rx_cong_drops;
244
245 unsigned long tx_fifo_parity_err;
246 unsigned long rx_fifo_parity_err;
247 unsigned long tx_fifo_urun;
248 unsigned long rx_fifo_ovfl;
249 unsigned long serdes_signal_loss;
250 unsigned long xaui_pcs_ctc_err;
251 unsigned long xaui_pcs_align_change;
252
253 unsigned long num_toggled;
254 unsigned long num_resets;
255
256 unsigned long link_faults;
257};
258
259struct tp_mib_stats {
260 u32 ipInReceive_hi;
261 u32 ipInReceive_lo;
262 u32 ipInHdrErrors_hi;
263 u32 ipInHdrErrors_lo;
264 u32 ipInAddrErrors_hi;
265 u32 ipInAddrErrors_lo;
266 u32 ipInUnknownProtos_hi;
267 u32 ipInUnknownProtos_lo;
268 u32 ipInDiscards_hi;
269 u32 ipInDiscards_lo;
270 u32 ipInDelivers_hi;
271 u32 ipInDelivers_lo;
272 u32 ipOutRequests_hi;
273 u32 ipOutRequests_lo;
274 u32 ipOutDiscards_hi;
275 u32 ipOutDiscards_lo;
276 u32 ipOutNoRoutes_hi;
277 u32 ipOutNoRoutes_lo;
278 u32 ipReasmTimeout;
279 u32 ipReasmReqds;
280 u32 ipReasmOKs;
281 u32 ipReasmFails;
282
283 u32 reserved[8];
284
285 u32 tcpActiveOpens;
286 u32 tcpPassiveOpens;
287 u32 tcpAttemptFails;
288 u32 tcpEstabResets;
289 u32 tcpOutRsts;
290 u32 tcpCurrEstab;
291 u32 tcpInSegs_hi;
292 u32 tcpInSegs_lo;
293 u32 tcpOutSegs_hi;
294 u32 tcpOutSegs_lo;
295 u32 tcpRetransSeg_hi;
296 u32 tcpRetransSeg_lo;
297 u32 tcpInErrs_hi;
298 u32 tcpInErrs_lo;
299 u32 tcpRtoMin;
300 u32 tcpRtoMax;
301};
302
303struct tp_params {
304 unsigned int nchan;
305 unsigned int pmrx_size;
306 unsigned int pmtx_size;
307 unsigned int cm_size;
308 unsigned int chan_rx_size;
309 unsigned int chan_tx_size;
310 unsigned int rx_pg_size;
311 unsigned int tx_pg_size;
312 unsigned int rx_num_pgs;
313 unsigned int tx_num_pgs;
314 unsigned int ntimer_qs;
315};
316
317struct qset_params {
318 unsigned int polling;
319 unsigned int coalesce_usecs;
320 unsigned int rspq_size;
321 unsigned int fl_size;
322 unsigned int jumbo_size;
323 unsigned int txq_size[SGE_TXQ_PER_SET];
324 unsigned int cong_thres;
325 unsigned int vector;
326};
327
328struct sge_params {
329 unsigned int max_pkt_size;
330 struct qset_params qset[SGE_QSETS];
331};
332
333struct mc5_params {
334 unsigned int mode;
335 unsigned int nservers;
336 unsigned int nfilters;
337 unsigned int nroutes;
338};
339
340
341enum {
342 DEFAULT_NSERVERS = 512,
343 DEFAULT_NFILTERS = 128
344};
345
346
347enum {
348 MC5_MODE_144_BIT = 1,
349 MC5_MODE_72_BIT = 2
350};
351
352
353enum { MC5_MIN_TIDS = 16 };
354
355struct vpd_params {
356 unsigned int cclk;
357 unsigned int mclk;
358 unsigned int uclk;
359 unsigned int mdc;
360 unsigned int mem_timing;
361 u8 sn[SERNUM_LEN + 1];
362 u8 eth_base[6];
363 u8 port_type[MAX_NPORTS];
364 unsigned short xauicfg[2];
365};
366
367struct pci_params {
368 unsigned int vpd_cap_addr;
369 unsigned short speed;
370 unsigned char width;
371 unsigned char variant;
372};
373
374enum {
375 PCI_VARIANT_PCI,
376 PCI_VARIANT_PCIX_MODE1_PARITY,
377 PCI_VARIANT_PCIX_MODE1_ECC,
378 PCI_VARIANT_PCIX_266_MODE2,
379 PCI_VARIANT_PCIE
380};
381
382struct adapter_params {
383 struct sge_params sge;
384 struct mc5_params mc5;
385 struct tp_params tp;
386 struct vpd_params vpd;
387 struct pci_params pci;
388
389 const struct adapter_info *info;
390
391 unsigned short mtus[NMTUS];
392 unsigned short a_wnd[NCCTRL_WIN];
393 unsigned short b_wnd[NCCTRL_WIN];
394
395 unsigned int nports;
396 unsigned int chan_map;
397 unsigned int stats_update_period;
398 unsigned int linkpoll_period;
399 unsigned int rev;
400 unsigned int offload;
401};
402
403enum {
404 T3_REV_A = 0,
405 T3_REV_B = 2,
406 T3_REV_B2 = 3,
407 T3_REV_C = 4,
408};
409
410struct trace_params {
411 u32 sip;
412 u32 sip_mask;
413 u32 dip;
414 u32 dip_mask;
415 u16 sport;
416 u16 sport_mask;
417 u16 dport;
418 u16 dport_mask;
419 u32 vlan:12;
420 u32 vlan_mask:12;
421 u32 intf:4;
422 u32 intf_mask:4;
423 u8 proto;
424 u8 proto_mask;
425};
426
427struct link_config {
428 unsigned int supported;
429 unsigned int advertising;
430 unsigned short requested_speed;
431 unsigned short speed;
432 unsigned char requested_duplex;
433 unsigned char duplex;
434 unsigned char requested_fc;
435 unsigned char fc;
436 unsigned char autoneg;
437 unsigned int link_ok;
438};
439
440#define SPEED_INVALID 0xffff
441#define DUPLEX_INVALID 0xff
442
443struct mc5 {
444 struct adapter *adapter;
445 unsigned int tcam_size;
446 unsigned char part_type;
447 unsigned char parity_enabled;
448 unsigned char mode;
449 struct mc5_stats stats;
450};
451
452static inline unsigned int t3_mc5_size(const struct mc5 *p)
453{
454 return p->tcam_size;
455}
456
457struct mc7 {
458 struct adapter *adapter;
459 unsigned int size;
460 unsigned int width;
461 unsigned int offset;
462 const char *name;
463 struct mc7_stats stats;
464};
465
466static inline unsigned int t3_mc7_size(const struct mc7 *p)
467{
468 return p->size;
469}
470
471struct cmac {
472 struct adapter *adapter;
473 unsigned int offset;
474 unsigned int nucast;
475 unsigned int tx_tcnt;
476 unsigned int tx_xcnt;
477 u64 tx_mcnt;
478 unsigned int rx_xcnt;
479 unsigned int rx_ocnt;
480 u64 rx_mcnt;
481 unsigned int toggle_cnt;
482 unsigned int txen;
483 u64 rx_pause;
484 struct mac_stats stats;
485};
486
487enum {
488 MAC_DIRECTION_RX = 1,
489 MAC_DIRECTION_TX = 2,
490 MAC_RXFIFO_SIZE = 32768
491};
492
493
494enum {
495 PHY_LOOPBACK_TX = 1,
496 PHY_LOOPBACK_RX = 2
497};
498
499
500enum {
501 cphy_cause_link_change = 1,
502 cphy_cause_fifo_error = 2,
503 cphy_cause_module_change = 4,
504};
505
506
507enum {
508 phy_modtype_none,
509 phy_modtype_sr,
510 phy_modtype_lr,
511 phy_modtype_lrm,
512 phy_modtype_twinax,
513 phy_modtype_twinax_long,
514 phy_modtype_unknown
515};
516
517
518struct cphy_ops {
519 int (*reset)(struct cphy *phy, int wait);
520
521 int (*intr_enable)(struct cphy *phy);
522 int (*intr_disable)(struct cphy *phy);
523 int (*intr_clear)(struct cphy *phy);
524 int (*intr_handler)(struct cphy *phy);
525
526 int (*autoneg_enable)(struct cphy *phy);
527 int (*autoneg_restart)(struct cphy *phy);
528
529 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
530 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
531 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
532 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
533 int *duplex, int *fc);
534 int (*power_down)(struct cphy *phy, int enable);
535
536 u32 mmds;
537};
538enum {
539 EDC_OPT_AEL2005 = 0,
540 EDC_OPT_AEL2005_SIZE = 1084,
541 EDC_TWX_AEL2005 = 1,
542 EDC_TWX_AEL2005_SIZE = 1464,
543 EDC_TWX_AEL2020 = 2,
544 EDC_TWX_AEL2020_SIZE = 1628,
545 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE,
546};
547
548
549struct cphy {
550 u8 modtype;
551 short priv;
552 unsigned int caps;
553 struct adapter *adapter;
554 const char *desc;
555 unsigned long fifo_errors;
556 const struct cphy_ops *ops;
557 struct mdio_if_info mdio;
558 u16 phy_cache[EDC_MAX_SIZE];
559};
560
561
562static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
563 unsigned int *valp)
564{
565 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
566 *valp = (rc >= 0) ? rc : -1;
567 return (rc >= 0) ? 0 : rc;
568}
569
570static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
571 unsigned int val)
572{
573 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
574 reg, val);
575}
576
577
578static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
579 int phy_addr, struct cphy_ops *phy_ops,
580 const struct mdio_ops *mdio_ops,
581 unsigned int caps, const char *desc)
582{
583 phy->caps = caps;
584 phy->adapter = adapter;
585 phy->desc = desc;
586 phy->ops = phy_ops;
587 if (mdio_ops) {
588 phy->mdio.prtad = phy_addr;
589 phy->mdio.mmds = phy_ops->mmds;
590 phy->mdio.mode_support = mdio_ops->mode_support;
591 phy->mdio.mdio_read = mdio_ops->read;
592 phy->mdio.mdio_write = mdio_ops->write;
593 }
594}
595
596
597#define MAC_STATS_ACCUM_SECS 180
598
599#define XGM_REG(reg_addr, idx) \
600 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
601
602struct addr_val_pair {
603 unsigned int reg_addr;
604 unsigned int val;
605};
606
607#include "adapter.h"
608
609#ifndef PCI_VENDOR_ID_CHELSIO
610# define PCI_VENDOR_ID_CHELSIO 0x1425
611#endif
612
613#define for_each_port(adapter, iter) \
614 for (iter = 0; iter < (adapter)->params.nports; ++iter)
615
616#define adapter_info(adap) ((adap)->params.info)
617
618static inline int uses_xaui(const struct adapter *adap)
619{
620 return adapter_info(adap)->caps & SUPPORTED_AUI;
621}
622
623static inline int is_10G(const struct adapter *adap)
624{
625 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
626}
627
628static inline int is_offload(const struct adapter *adap)
629{
630 return adap->params.offload;
631}
632
633static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
634{
635 return adap->params.vpd.cclk / 1000;
636}
637
638static inline unsigned int is_pcie(const struct adapter *adap)
639{
640 return adap->params.pci.variant == PCI_VARIANT_PCIE;
641}
642
643void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
644 u32 val);
645void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
646 int n, unsigned int offset);
647int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
648 int polarity, int attempts, int delay, u32 *valp);
649static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
650 int polarity, int attempts, int delay)
651{
652 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
653 delay, NULL);
654}
655int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
656 unsigned int set);
657int t3_phy_reset(struct cphy *phy, int mmd, int wait);
658int t3_phy_advertise(struct cphy *phy, unsigned int advert);
659int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
660int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
661int t3_phy_lasi_intr_enable(struct cphy *phy);
662int t3_phy_lasi_intr_disable(struct cphy *phy);
663int t3_phy_lasi_intr_clear(struct cphy *phy);
664int t3_phy_lasi_intr_handler(struct cphy *phy);
665
666void t3_intr_enable(struct adapter *adapter);
667void t3_intr_disable(struct adapter *adapter);
668void t3_intr_clear(struct adapter *adapter);
669void t3_xgm_intr_enable(struct adapter *adapter, int idx);
670void t3_xgm_intr_disable(struct adapter *adapter, int idx);
671void t3_port_intr_enable(struct adapter *adapter, int idx);
672void t3_port_intr_disable(struct adapter *adapter, int idx);
673int t3_slow_intr_handler(struct adapter *adapter);
674int t3_phy_intr_handler(struct adapter *adapter);
675
676void t3_link_changed(struct adapter *adapter, int port_id);
677void t3_link_fault(struct adapter *adapter, int port_id);
678int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
679const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
680int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
681int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
682int t3_seeprom_wp(struct adapter *adapter, int enable);
683int t3_get_tp_version(struct adapter *adapter, u32 *vers);
684int t3_check_tpsram_version(struct adapter *adapter);
685int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
686 unsigned int size);
687int t3_set_proto_sram(struct adapter *adap, const u8 *data);
688int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
689int t3_get_fw_version(struct adapter *adapter, u32 *vers);
690int t3_check_fw_version(struct adapter *adapter);
691int t3_init_hw(struct adapter *adapter, u32 fw_params);
692int t3_reset_adapter(struct adapter *adapter);
693int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
694 int reset);
695int t3_replay_prep_adapter(struct adapter *adapter);
696void t3_led_ready(struct adapter *adapter);
697void t3_fatal_err(struct adapter *adapter);
698void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
699void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
700 const u8 * cpus, const u16 *rspq);
701int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
702 unsigned int n, unsigned int *valp);
703int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
704 u64 *buf);
705
706int t3_mac_reset(struct cmac *mac);
707void t3b_pcs_reset(struct cmac *mac);
708void t3_mac_disable_exact_filters(struct cmac *mac);
709void t3_mac_enable_exact_filters(struct cmac *mac);
710int t3_mac_enable(struct cmac *mac, int which);
711int t3_mac_disable(struct cmac *mac, int which);
712int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
713int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev);
714int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
715int t3_mac_set_num_ucast(struct cmac *mac, int n);
716const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
717int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
718int t3b2_mac_watchdog_task(struct cmac *mac);
719
720void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
721int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
722 unsigned int nroutes);
723void t3_mc5_intr_handler(struct mc5 *mc5);
724
725void t3_tp_set_offload_mode(struct adapter *adap, int enable);
726void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
727void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
728 unsigned short alpha[NCCTRL_WIN],
729 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
730void t3_config_trace_filter(struct adapter *adapter,
731 const struct trace_params *tp, int filter_index,
732 int invert, int enable);
733int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
734
735void t3_sge_prep(struct adapter *adap, struct sge_params *p);
736void t3_sge_init(struct adapter *adap, struct sge_params *p);
737int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
738 enum sge_context_type type, int respq, u64 base_addr,
739 unsigned int size, unsigned int token, int gen,
740 unsigned int cidx);
741int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
742 int gts_enable, u64 base_addr, unsigned int size,
743 unsigned int esize, unsigned int cong_thres, int gen,
744 unsigned int cidx);
745int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
746 int irq_vec_idx, u64 base_addr, unsigned int size,
747 unsigned int fl_thres, int gen, unsigned int cidx);
748int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
749 unsigned int size, int rspq, int ovfl_mode,
750 unsigned int credits, unsigned int credit_thres);
751int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
752int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
753int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
754int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
755int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
756 unsigned int credits);
757
758int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
759 int phy_addr, const struct mdio_ops *mdio_ops);
760int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
761 int phy_addr, const struct mdio_ops *mdio_ops);
762int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
763 int phy_addr, const struct mdio_ops *mdio_ops);
764int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
765 int phy_addr, const struct mdio_ops *mdio_ops);
766int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
767 int phy_addr, const struct mdio_ops *mdio_ops);
768int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
769 const struct mdio_ops *mdio_ops);
770int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
771 int phy_addr, const struct mdio_ops *mdio_ops);
772int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
773 int phy_addr, const struct mdio_ops *mdio_ops);
774#endif
775