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18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
30#include <linux/firmware.h>
31#include <linux/slab.h>
32#include <linux/u64_stats_sync.h>
33
34#include "be_hw.h"
35#include "be_roce.h"
36
37#define DRV_VER "4.6.62.0u"
38#define DRV_NAME "be2net"
39#define BE_NAME "Emulex BladeEngine2"
40#define BE3_NAME "Emulex BladeEngine3"
41#define OC_NAME "Emulex OneConnect"
42#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
44#define OC_NAME_SH OC_NAME "(Skyhawk)"
45#define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
46
47#define BE_VENDOR_ID 0x19a2
48#define EMULEX_VENDOR_ID 0x10df
49#define BE_DEVICE_ID1 0x211
50#define BE_DEVICE_ID2 0x221
51#define OC_DEVICE_ID1 0x700
52#define OC_DEVICE_ID2 0x710
53#define OC_DEVICE_ID3 0xe220
54#define OC_DEVICE_ID4 0xe228
55#define OC_DEVICE_ID5 0x720
56#define OC_DEVICE_ID6 0x728
57#define OC_SUBSYS_DEVICE_ID1 0xE602
58#define OC_SUBSYS_DEVICE_ID2 0xE642
59#define OC_SUBSYS_DEVICE_ID3 0xE612
60#define OC_SUBSYS_DEVICE_ID4 0xE652
61
62static inline char *nic_name(struct pci_dev *pdev)
63{
64 switch (pdev->device) {
65 case OC_DEVICE_ID1:
66 return OC_NAME;
67 case OC_DEVICE_ID2:
68 return OC_NAME_BE;
69 case OC_DEVICE_ID3:
70 case OC_DEVICE_ID4:
71 return OC_NAME_LANCER;
72 case BE_DEVICE_ID2:
73 return BE3_NAME;
74 case OC_DEVICE_ID5:
75 case OC_DEVICE_ID6:
76 return OC_NAME_SH;
77 default:
78 return BE_NAME;
79 }
80}
81
82
83#define BE_HDR_LEN ((u16) 64)
84
85#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
86
87#define BE_MAX_JUMBO_FRAME_SIZE 9018
88#define BE_MIN_MTU 256
89
90#define BE_NUM_VLANS_SUPPORTED 64
91#define BE_MAX_EQD 96u
92#define BE_MAX_TX_FRAG_COUNT 30
93
94#define EVNT_Q_LEN 1024
95#define TX_Q_LEN 2048
96#define TX_CQ_LEN 1024
97#define RX_Q_LEN 1024
98#define RX_CQ_LEN 1024
99#define MCC_Q_LEN 128
100#define MCC_CQ_LEN 256
101
102#define BE3_MAX_RSS_QS 8
103#define BE2_MAX_RSS_QS 4
104#define MAX_RSS_QS BE3_MAX_RSS_QS
105#define MAX_RX_QS (MAX_RSS_QS + 1)
106
107#define MAX_TX_QS 8
108#define MAX_ROCE_EQS 5
109#define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS)
110#define BE_TX_BUDGET 256
111#define BE_NAPI_WEIGHT 64
112#define MAX_RX_POST BE_NAPI_WEIGHT
113#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
114
115#define MAX_VFS 30
116#define FW_VER_LEN 32
117
118struct be_dma_mem {
119 void *va;
120 dma_addr_t dma;
121 u32 size;
122};
123
124struct be_queue_info {
125 struct be_dma_mem dma_mem;
126 u16 len;
127 u16 entry_size;
128 u16 id;
129 u16 tail, head;
130 bool created;
131 atomic_t used;
132};
133
134static inline u32 MODULO(u16 val, u16 limit)
135{
136 BUG_ON(limit & (limit - 1));
137 return val & (limit - 1);
138}
139
140static inline void index_adv(u16 *index, u16 val, u16 limit)
141{
142 *index = MODULO((*index + val), limit);
143}
144
145static inline void index_inc(u16 *index, u16 limit)
146{
147 *index = MODULO((*index + 1), limit);
148}
149
150static inline void *queue_head_node(struct be_queue_info *q)
151{
152 return q->dma_mem.va + q->head * q->entry_size;
153}
154
155static inline void *queue_tail_node(struct be_queue_info *q)
156{
157 return q->dma_mem.va + q->tail * q->entry_size;
158}
159
160static inline void *queue_index_node(struct be_queue_info *q, u16 index)
161{
162 return q->dma_mem.va + index * q->entry_size;
163}
164
165static inline void queue_head_inc(struct be_queue_info *q)
166{
167 index_inc(&q->head, q->len);
168}
169
170static inline void index_dec(u16 *index, u16 limit)
171{
172 *index = MODULO((*index - 1), limit);
173}
174
175static inline void queue_tail_inc(struct be_queue_info *q)
176{
177 index_inc(&q->tail, q->len);
178}
179
180struct be_eq_obj {
181 struct be_queue_info q;
182 char desc[32];
183
184
185 bool enable_aic;
186 u32 min_eqd;
187 u32 max_eqd;
188 u32 eqd;
189 u32 cur_eqd;
190
191 u8 idx;
192 u16 tx_budget;
193 u16 spurious_intr;
194 struct napi_struct napi;
195 struct be_adapter *adapter;
196} ____cacheline_aligned_in_smp;
197
198struct be_mcc_obj {
199 struct be_queue_info q;
200 struct be_queue_info cq;
201 bool rearm_cq;
202};
203
204struct be_tx_stats {
205 u64 tx_bytes;
206 u64 tx_pkts;
207 u64 tx_reqs;
208 u64 tx_wrbs;
209 u64 tx_compl;
210 ulong tx_jiffies;
211 u32 tx_stops;
212 struct u64_stats_sync sync;
213 struct u64_stats_sync sync_compl;
214};
215
216struct be_tx_obj {
217 u32 db_offset;
218 struct be_queue_info q;
219 struct be_queue_info cq;
220
221 struct sk_buff *sent_skb_list[TX_Q_LEN];
222 struct be_tx_stats stats;
223} ____cacheline_aligned_in_smp;
224
225
226struct be_rx_page_info {
227 struct page *page;
228 DEFINE_DMA_UNMAP_ADDR(bus);
229 u16 page_offset;
230 bool last_page_user;
231};
232
233struct be_rx_stats {
234 u64 rx_bytes;
235 u64 rx_pkts;
236 u64 rx_pkts_prev;
237 ulong rx_jiffies;
238 u32 rx_drops_no_skbs;
239 u32 rx_drops_no_frags;
240 u32 rx_post_fail;
241 u32 rx_compl;
242 u32 rx_mcast_pkts;
243 u32 rx_compl_err;
244 u32 rx_pps;
245 struct u64_stats_sync sync;
246};
247
248struct be_rx_compl_info {
249 u32 rss_hash;
250 u16 vlan_tag;
251 u16 pkt_size;
252 u16 rxq_idx;
253 u16 port;
254 u8 vlanf;
255 u8 num_rcvd;
256 u8 err;
257 u8 ipf;
258 u8 tcpf;
259 u8 udpf;
260 u8 ip_csum;
261 u8 l4_csum;
262 u8 ipv6;
263 u8 vtm;
264 u8 pkt_type;
265 u8 ip_frag;
266};
267
268struct be_rx_obj {
269 struct be_adapter *adapter;
270 struct be_queue_info q;
271 struct be_queue_info cq;
272 struct be_rx_compl_info rxcp;
273 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
274 struct be_rx_stats stats;
275 u8 rss_id;
276 bool rx_post_starved;
277} ____cacheline_aligned_in_smp;
278
279struct be_drv_stats {
280 u32 be_on_die_temperature;
281 u32 eth_red_drops;
282 u32 rx_drops_no_pbuf;
283 u32 rx_drops_no_txpb;
284 u32 rx_drops_no_erx_descr;
285 u32 rx_drops_no_tpre_descr;
286 u32 rx_drops_too_many_frags;
287 u32 forwarded_packets;
288 u32 rx_drops_mtu;
289 u32 rx_crc_errors;
290 u32 rx_alignment_symbol_errors;
291 u32 rx_pause_frames;
292 u32 rx_priority_pause_frames;
293 u32 rx_control_frames;
294 u32 rx_in_range_errors;
295 u32 rx_out_range_errors;
296 u32 rx_frame_too_long;
297 u32 rx_address_filtered;
298 u32 rx_dropped_too_small;
299 u32 rx_dropped_too_short;
300 u32 rx_dropped_header_too_small;
301 u32 rx_dropped_tcp_length;
302 u32 rx_dropped_runt;
303 u32 rx_ip_checksum_errs;
304 u32 rx_tcp_checksum_errs;
305 u32 rx_udp_checksum_errs;
306 u32 tx_pauseframes;
307 u32 tx_priority_pauseframes;
308 u32 tx_controlframes;
309 u32 rxpp_fifo_overflow_drop;
310 u32 rx_input_fifo_overflow_drop;
311 u32 pmem_fifo_overflow_drop;
312 u32 jabber_events;
313};
314
315struct be_vf_cfg {
316 unsigned char mac_addr[ETH_ALEN];
317 int if_handle;
318 int pmac_id;
319 u16 def_vid;
320 u16 vlan_tag;
321 u32 tx_rate;
322};
323
324enum vf_state {
325 ENABLED = 0,
326 ASSIGNED = 1
327};
328
329#define BE_FLAGS_LINK_STATUS_INIT 1
330#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
331#define BE_FLAGS_NAPI_ENABLED (1 << 9)
332#define BE_UC_PMAC_COUNT 30
333#define BE_VF_UC_PMAC_COUNT 2
334#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11)
335
336
337#define LANCER_INITIATE_FW_DUMP 0x1
338
339struct phy_info {
340 u8 transceiver;
341 u8 autoneg;
342 u8 fc_autoneg;
343 u8 port_type;
344 u16 phy_type;
345 u16 interface_type;
346 u32 misc_params;
347 u16 auto_speeds_supported;
348 u16 fixed_speeds_supported;
349 int link_speed;
350 u32 dac_cable_len;
351 u32 advertising;
352 u32 supported;
353};
354
355struct be_adapter {
356 struct pci_dev *pdev;
357 struct net_device *netdev;
358
359 u8 __iomem *csr;
360 u8 __iomem *db;
361
362 struct mutex mbox_lock;
363 struct be_dma_mem mbox_mem;
364
365
366 struct be_dma_mem mbox_mem_alloced;
367
368 struct be_mcc_obj mcc_obj;
369 spinlock_t mcc_lock;
370 spinlock_t mcc_cq_lock;
371
372 u32 num_msix_vec;
373 u32 num_evt_qs;
374 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
375 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
376 bool isr_registered;
377
378
379 u32 num_tx_qs;
380 struct be_tx_obj tx_obj[MAX_TX_QS];
381
382
383 u32 num_rx_qs;
384 struct be_rx_obj rx_obj[MAX_RX_QS];
385 u32 big_page_size;
386
387 struct be_drv_stats drv_stats;
388 u16 vlans_added;
389 u8 vlan_tag[VLAN_N_VID];
390 u8 vlan_prio_bmap;
391 u16 recommended_prio;
392 struct be_dma_mem rx_filter;
393
394 struct be_dma_mem stats_cmd;
395
396 struct delayed_work work;
397 u16 work_counter;
398
399 struct delayed_work func_recovery_work;
400 u32 flags;
401 u32 cmd_privileges;
402
403 char fw_ver[FW_VER_LEN];
404 char fw_on_flash[FW_VER_LEN];
405 int if_handle;
406 u32 *pmac_id;
407 u32 beacon_state;
408
409 bool eeh_error;
410 bool fw_timeout;
411 bool hw_error;
412
413 u32 port_num;
414 bool promiscuous;
415 u32 function_mode;
416 u32 function_caps;
417 u32 rx_fc;
418 u32 tx_fc;
419 bool stats_cmd_sent;
420 u32 if_type;
421 struct {
422 u32 size;
423 u32 total_size;
424 u64 io_addr;
425 } roce_db;
426 u32 num_msix_roce_vec;
427 struct ocrdma_dev *ocrdma_dev;
428 struct list_head entry;
429
430 u32 flash_status;
431 struct completion flash_compl;
432
433 u32 num_vfs;
434 u32 dev_num_vfs;
435 u8 virtfn;
436 struct be_vf_cfg *vf_cfg;
437 bool be3_native;
438 u32 sli_family;
439 u8 hba_port_num;
440 u16 pvid;
441 struct phy_info phy;
442 u8 wol_cap;
443 bool wol;
444 u32 uc_macs;
445 u16 asic_rev;
446 u16 qnq_vid;
447 u32 msg_enable;
448 int be_get_temp_freq;
449 u16 max_mcast_mac;
450 u16 max_tx_queues;
451 u16 max_rss_queues;
452 u16 max_rx_queues;
453 u16 max_pmac_cnt;
454 u16 max_vlans;
455 u16 max_event_queues;
456 u32 if_cap_flags;
457 u8 pf_number;
458 u64 rss_flags;
459};
460
461#define be_physfn(adapter) (!adapter->virtfn)
462#define sriov_enabled(adapter) (adapter->num_vfs > 0)
463#define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
464 be_physfn(adapter))
465#define for_all_vfs(adapter, vf_cfg, i) \
466 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
467 i++, vf_cfg++)
468
469#define ON 1
470#define OFF 0
471
472#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
473 adapter->pdev->device == OC_DEVICE_ID4)
474
475#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
476 adapter->pdev->device == OC_DEVICE_ID6)
477
478#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
479 adapter->pdev->device == OC_DEVICE_ID2)
480
481#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
482 adapter->pdev->device == OC_DEVICE_ID1)
483
484#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
485
486#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
487 (adapter->function_mode & RDMA_ENABLED))
488
489extern const struct ethtool_ops be_ethtool_ops;
490
491#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
492#define num_irqs(adapter) (msix_enabled(adapter) ? \
493 adapter->num_msix_vec : 1)
494#define tx_stats(txo) (&(txo)->stats)
495#define rx_stats(rxo) (&(rxo)->stats)
496
497
498#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
499
500#define for_all_rx_queues(adapter, rxo, i) \
501 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
502 i++, rxo++)
503
504
505#define for_all_rss_queues(adapter, rxo, i) \
506 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
507 i++, rxo++)
508
509#define for_all_tx_queues(adapter, txo, i) \
510 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
511 i++, txo++)
512
513#define for_all_evt_queues(adapter, eqo, i) \
514 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
515 i++, eqo++)
516
517#define is_mcc_eqo(eqo) (eqo->idx == 0)
518#define mcc_eqo(adapter) (&adapter->eq_obj[0])
519
520#define PAGE_SHIFT_4K 12
521#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
522
523
524#define PAGES_4K_SPANNED(_address, size) \
525 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
526 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
527
528
529#define AMAP_BIT_OFFSET(_struct, field) \
530 (((size_t)&(((_struct *)0)->field))%32)
531
532
533static inline u32 amap_mask(u32 bitsize)
534{
535 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
536}
537
538static inline void
539amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
540{
541 u32 *dw = (u32 *) ptr + dw_offset;
542 *dw &= ~(mask << offset);
543 *dw |= (mask & value) << offset;
544}
545
546#define AMAP_SET_BITS(_struct, field, ptr, val) \
547 amap_set(ptr, \
548 offsetof(_struct, field)/32, \
549 amap_mask(sizeof(((_struct *)0)->field)), \
550 AMAP_BIT_OFFSET(_struct, field), \
551 val)
552
553static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
554{
555 u32 *dw = (u32 *) ptr;
556 return mask & (*(dw + dw_offset) >> offset);
557}
558
559#define AMAP_GET_BITS(_struct, field, ptr) \
560 amap_get(ptr, \
561 offsetof(_struct, field)/32, \
562 amap_mask(sizeof(((_struct *)0)->field)), \
563 AMAP_BIT_OFFSET(_struct, field))
564
565#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
566#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
567static inline void swap_dws(void *wrb, int len)
568{
569#ifdef __BIG_ENDIAN
570 u32 *dw = wrb;
571 BUG_ON(len % 4);
572 do {
573 *dw = cpu_to_le32(*dw);
574 dw++;
575 len -= 4;
576 } while (len);
577#endif
578}
579
580static inline u8 is_tcp_pkt(struct sk_buff *skb)
581{
582 u8 val = 0;
583
584 if (ip_hdr(skb)->version == 4)
585 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
586 else if (ip_hdr(skb)->version == 6)
587 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
588
589 return val;
590}
591
592static inline u8 is_udp_pkt(struct sk_buff *skb)
593{
594 u8 val = 0;
595
596 if (ip_hdr(skb)->version == 4)
597 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
598 else if (ip_hdr(skb)->version == 6)
599 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
600
601 return val;
602}
603
604static inline bool is_ipv4_pkt(struct sk_buff *skb)
605{
606 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
607}
608
609static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
610{
611 u32 addr;
612
613 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
614
615 mac[5] = (u8)(addr & 0xFF);
616 mac[4] = (u8)((addr >> 8) & 0xFF);
617 mac[3] = (u8)((addr >> 16) & 0xFF);
618
619 memcpy(mac, adapter->netdev->dev_addr, 3);
620}
621
622static inline bool be_multi_rxq(const struct be_adapter *adapter)
623{
624 return adapter->num_rx_qs > 1;
625}
626
627static inline bool be_error(struct be_adapter *adapter)
628{
629 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
630}
631
632static inline bool be_hw_error(struct be_adapter *adapter)
633{
634 return adapter->eeh_error || adapter->hw_error;
635}
636
637static inline void be_clear_all_error(struct be_adapter *adapter)
638{
639 adapter->eeh_error = false;
640 adapter->hw_error = false;
641 adapter->fw_timeout = false;
642}
643
644static inline bool be_is_wol_excluded(struct be_adapter *adapter)
645{
646 struct pci_dev *pdev = adapter->pdev;
647
648 if (!be_physfn(adapter))
649 return true;
650
651 switch (pdev->subsystem_device) {
652 case OC_SUBSYS_DEVICE_ID1:
653 case OC_SUBSYS_DEVICE_ID2:
654 case OC_SUBSYS_DEVICE_ID3:
655 case OC_SUBSYS_DEVICE_ID4:
656 return true;
657 default:
658 return false;
659 }
660}
661
662static inline int qnq_async_evt_rcvd(struct be_adapter *adapter)
663{
664 return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
665}
666
667extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
668 u16 num_popped);
669extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
670extern void be_parse_stats(struct be_adapter *adapter);
671extern int be_load_fw(struct be_adapter *adapter, u8 *func);
672extern bool be_is_wol_supported(struct be_adapter *adapter);
673extern bool be_pause_supported(struct be_adapter *adapter);
674extern u32 be_get_fw_log_level(struct be_adapter *adapter);
675
676
677
678
679extern void be_roce_dev_add(struct be_adapter *);
680extern void be_roce_dev_remove(struct be_adapter *);
681
682
683
684
685extern void be_roce_dev_open(struct be_adapter *);
686extern void be_roce_dev_close(struct be_adapter *);
687
688#endif
689