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27#include "ixgbe.h"
28#include <linux/export.h>
29#include <linux/ptp_classify.h>
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85
86#define IXGBE_INCVAL_10GB 0x66666666
87#define IXGBE_INCVAL_1GB 0x40000000
88#define IXGBE_INCVAL_100 0x50000000
89
90#define IXGBE_INCVAL_SHIFT_10GB 28
91#define IXGBE_INCVAL_SHIFT_1GB 24
92#define IXGBE_INCVAL_SHIFT_100 21
93
94#define IXGBE_INCVAL_SHIFT_82599 7
95#define IXGBE_INCPER_SHIFT_82599 24
96#define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
97
98#define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99#define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
100
101#ifndef NSECS_PER_SEC
102#define NSECS_PER_SEC 1000000000ULL
103#endif
104
105
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115
116
117static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
118{
119 struct ixgbe_hw *hw = &adapter->hw;
120 int shift = adapter->cc.shift;
121 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
122 u64 ns = 0, clock_edge = 0;
123
124 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
125 (hw->mac.type == ixgbe_mac_X540)) {
126
127
128 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
129 IXGBE_WRITE_FLUSH(hw);
130
131 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
132
133
134
135
136
137 esdp |= (IXGBE_ESDP_SDP0_DIR |
138 IXGBE_ESDP_SDP0_NATIVE);
139
140
141
142
143
144 tsauxc = (IXGBE_TSAUXC_EN_CLK |
145 IXGBE_TSAUXC_SYNCLK |
146 IXGBE_TSAUXC_SDP0_INT);
147
148
149 clktiml = (u32)(NSECS_PER_SEC << shift);
150 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
151
152
153
154
155
156
157 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
158 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
159 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
160
161 div_u64_rem(ns, NSECS_PER_SEC, &rem);
162 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
163
164
165 trgttiml = (u32)clock_edge;
166 trgttimh = (u32)(clock_edge >> 32);
167
168 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
169 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
170 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
171 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
172
173 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
174 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
175 } else {
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
177 }
178
179 IXGBE_WRITE_FLUSH(hw);
180}
181
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187
188
189
190static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
191{
192 struct ixgbe_adapter *adapter =
193 container_of(cc, struct ixgbe_adapter, cc);
194 struct ixgbe_hw *hw = &adapter->hw;
195 u64 stamp = 0;
196
197 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
198 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
199
200 return stamp;
201}
202
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209
210
211static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
212{
213 struct ixgbe_adapter *adapter =
214 container_of(ptp, struct ixgbe_adapter, ptp_caps);
215 struct ixgbe_hw *hw = &adapter->hw;
216 u64 freq;
217 u32 diff, incval;
218 int neg_adj = 0;
219
220 if (ppb < 0) {
221 neg_adj = 1;
222 ppb = -ppb;
223 }
224
225 smp_mb();
226 incval = ACCESS_ONCE(adapter->base_incval);
227
228 freq = incval;
229 freq *= ppb;
230 diff = div_u64(freq, 1000000000ULL);
231
232 incval = neg_adj ? (incval - diff) : (incval + diff);
233
234 switch (hw->mac.type) {
235 case ixgbe_mac_X540:
236 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
237 break;
238 case ixgbe_mac_82599EB:
239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
240 (1 << IXGBE_INCPER_SHIFT_82599) |
241 incval);
242 break;
243 default:
244 break;
245 }
246
247 return 0;
248}
249
250
251
252
253
254
255
256
257static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
258{
259 struct ixgbe_adapter *adapter =
260 container_of(ptp, struct ixgbe_adapter, ptp_caps);
261 unsigned long flags;
262 u64 now;
263
264 spin_lock_irqsave(&adapter->tmreg_lock, flags);
265
266 now = timecounter_read(&adapter->tc);
267 now += delta;
268
269
270 timecounter_init(&adapter->tc,
271 &adapter->cc,
272 now);
273
274 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
275
276 ixgbe_ptp_setup_sdp(adapter);
277
278 return 0;
279}
280
281
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287
288
289static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
290{
291 struct ixgbe_adapter *adapter =
292 container_of(ptp, struct ixgbe_adapter, ptp_caps);
293 u64 ns;
294 u32 remainder;
295 unsigned long flags;
296
297 spin_lock_irqsave(&adapter->tmreg_lock, flags);
298 ns = timecounter_read(&adapter->tc);
299 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
300
301 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
302 ts->tv_nsec = remainder;
303
304 return 0;
305}
306
307
308
309
310
311
312
313
314
315static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
316 const struct timespec *ts)
317{
318 struct ixgbe_adapter *adapter =
319 container_of(ptp, struct ixgbe_adapter, ptp_caps);
320 u64 ns;
321 unsigned long flags;
322
323 ns = ts->tv_sec * 1000000000ULL;
324 ns += ts->tv_nsec;
325
326
327 spin_lock_irqsave(&adapter->tmreg_lock, flags);
328 timecounter_init(&adapter->tc, &adapter->cc, ns);
329 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
330
331 ixgbe_ptp_setup_sdp(adapter);
332 return 0;
333}
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336
337
338
339
340
341
342
343
344static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
345 struct ptp_clock_request *rq, int on)
346{
347 struct ixgbe_adapter *adapter =
348 container_of(ptp, struct ixgbe_adapter, ptp_caps);
349
350
351
352
353
354
355
356 if (rq->type == PTP_CLK_REQ_PPS) {
357 switch (adapter->hw.mac.type) {
358 case ixgbe_mac_X540:
359 if (on)
360 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
361 else
362 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
363
364 ixgbe_ptp_setup_sdp(adapter);
365 return 0;
366 default:
367 break;
368 }
369 }
370
371 return -ENOTSUPP;
372}
373
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375
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377
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380
381
382void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
383{
384 struct ixgbe_hw *hw = &adapter->hw;
385 struct ptp_clock_event event;
386
387 event.type = PTP_CLOCK_PPS;
388
389
390
391
392
393 if (!adapter->ptp_clock)
394 return;
395
396 switch (hw->mac.type) {
397 case ixgbe_mac_X540:
398 ptp_clock_event(adapter->ptp_clock, &event);
399 break;
400 default:
401 break;
402 }
403}
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405
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411
412
413void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
414{
415 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
416 IXGBE_OVERFLOW_PERIOD);
417 struct timespec ts;
418
419 if (timeout) {
420 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
421 adapter->last_overflow_check = jiffies;
422 }
423}
424
425
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427
428
429
430
431
432
433
434void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
435{
436 struct ixgbe_hw *hw = &adapter->hw;
437 struct ixgbe_ring *rx_ring;
438 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
439 unsigned long rx_event;
440 int n;
441
442
443
444
445 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
446 adapter->last_rx_ptp_check = jiffies;
447 return;
448 }
449
450
451 rx_event = adapter->last_rx_ptp_check;
452 for (n = 0; n < adapter->num_rx_queues; n++) {
453 rx_ring = adapter->rx_ring[n];
454 if (time_after(rx_ring->last_rx_timestamp, rx_event))
455 rx_event = rx_ring->last_rx_timestamp;
456 }
457
458
459 if (time_is_before_jiffies(rx_event + 5*HZ)) {
460 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
461 adapter->last_rx_ptp_check = jiffies;
462
463 e_warn(drv, "clearing RX Timestamp hang");
464 }
465}
466
467
468
469
470
471
472
473
474
475static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
476{
477 struct ixgbe_hw *hw = &adapter->hw;
478 struct skb_shared_hwtstamps shhwtstamps;
479 u64 regval = 0, ns;
480 unsigned long flags;
481
482 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
483 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
484
485 spin_lock_irqsave(&adapter->tmreg_lock, flags);
486 ns = timecounter_cyc2time(&adapter->tc, regval);
487 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
488
489 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
490 shhwtstamps.hwtstamp = ns_to_ktime(ns);
491 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
492
493 dev_kfree_skb_any(adapter->ptp_tx_skb);
494 adapter->ptp_tx_skb = NULL;
495}
496
497
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500
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502
503
504
505static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
506{
507 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
508 ptp_tx_work);
509 struct ixgbe_hw *hw = &adapter->hw;
510 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
511 IXGBE_PTP_TX_TIMEOUT);
512 u32 tsynctxctl;
513
514
515 if (!adapter->ptp_tx_skb)
516 return;
517
518 if (timeout) {
519 dev_kfree_skb_any(adapter->ptp_tx_skb);
520 adapter->ptp_tx_skb = NULL;
521 e_warn(drv, "clearing Tx Timestamp hang");
522 return;
523 }
524
525 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
526 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
527 ixgbe_ptp_tx_hwtstamp(adapter);
528 else
529
530 schedule_work(&adapter->ptp_tx_work);
531}
532
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540
541
542void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
543 struct sk_buff *skb)
544{
545 struct ixgbe_adapter *adapter;
546 struct ixgbe_hw *hw;
547 struct skb_shared_hwtstamps *shhwtstamps;
548 u64 regval = 0, ns;
549 u32 tsyncrxctl;
550 unsigned long flags;
551
552
553 if (!q_vector || !q_vector->adapter)
554 return;
555
556 adapter = q_vector->adapter;
557 hw = &adapter->hw;
558
559
560
561
562
563 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
564 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
565 return;
566
567 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
568 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
569
570
571 spin_lock_irqsave(&adapter->tmreg_lock, flags);
572 ns = timecounter_cyc2time(&adapter->tc, regval);
573 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
574
575 shhwtstamps = skb_hwtstamps(skb);
576 shhwtstamps->hwtstamp = ns_to_ktime(ns);
577}
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601
602int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
603 struct ifreq *ifr, int cmd)
604{
605 struct ixgbe_hw *hw = &adapter->hw;
606 struct hwtstamp_config config;
607 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
608 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
609 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
610 bool is_l2 = false;
611 u32 regval;
612
613 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
614 return -EFAULT;
615
616
617 if (config.flags)
618 return -EINVAL;
619
620 switch (config.tx_type) {
621 case HWTSTAMP_TX_OFF:
622 tsync_tx_ctl = 0;
623 case HWTSTAMP_TX_ON:
624 break;
625 default:
626 return -ERANGE;
627 }
628
629 switch (config.rx_filter) {
630 case HWTSTAMP_FILTER_NONE:
631 tsync_rx_ctl = 0;
632 tsync_rx_mtrl = 0;
633 break;
634 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
635 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
636 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
637 break;
638 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
639 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
640 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
641 break;
642 case HWTSTAMP_FILTER_PTP_V2_EVENT:
643 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
644 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
647 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
648 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
649 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
650 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
651 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
652 is_l2 = true;
653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
654 break;
655 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
656 case HWTSTAMP_FILTER_ALL:
657 default:
658
659
660
661
662
663
664 config.rx_filter = HWTSTAMP_FILTER_NONE;
665 return -ERANGE;
666 }
667
668 if (hw->mac.type == ixgbe_mac_82598EB) {
669 if (tsync_rx_ctl | tsync_tx_ctl)
670 return -ERANGE;
671 return 0;
672 }
673
674
675 if (is_l2)
676 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
677 (IXGBE_ETQF_FILTER_EN |
678 IXGBE_ETQF_1588 |
679 ETH_P_1588));
680 else
681 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
682
683
684
685 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
686 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
687 regval |= tsync_tx_ctl;
688 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
689
690
691 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
692 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
693 regval |= tsync_rx_ctl;
694 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
695
696
697 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
698
699 IXGBE_WRITE_FLUSH(hw);
700
701
702 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
703 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
704
705 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
706 -EFAULT : 0;
707}
708
709
710
711
712
713
714
715
716
717
718
719void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
720{
721 struct ixgbe_hw *hw = &adapter->hw;
722 u32 incval = 0;
723 u32 shift = 0;
724 unsigned long flags;
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740 switch (adapter->link_speed) {
741 case IXGBE_LINK_SPEED_100_FULL:
742 incval = IXGBE_INCVAL_100;
743 shift = IXGBE_INCVAL_SHIFT_100;
744 break;
745 case IXGBE_LINK_SPEED_1GB_FULL:
746 incval = IXGBE_INCVAL_1GB;
747 shift = IXGBE_INCVAL_SHIFT_1GB;
748 break;
749 case IXGBE_LINK_SPEED_10GB_FULL:
750 default:
751 incval = IXGBE_INCVAL_10GB;
752 shift = IXGBE_INCVAL_SHIFT_10GB;
753 break;
754 }
755
756
757
758
759
760
761
762 switch (hw->mac.type) {
763 case ixgbe_mac_X540:
764 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
765 break;
766 case ixgbe_mac_82599EB:
767 incval >>= IXGBE_INCVAL_SHIFT_82599;
768 shift -= IXGBE_INCVAL_SHIFT_82599;
769 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
770 (1 << IXGBE_INCPER_SHIFT_82599) |
771 incval);
772 break;
773 default:
774
775 return;
776 }
777
778
779 ACCESS_ONCE(adapter->base_incval) = incval;
780 smp_mb();
781
782
783 spin_lock_irqsave(&adapter->tmreg_lock, flags);
784
785 memset(&adapter->cc, 0, sizeof(adapter->cc));
786 adapter->cc.read = ixgbe_ptp_read;
787 adapter->cc.mask = CLOCKSOURCE_MASK(64);
788 adapter->cc.shift = shift;
789 adapter->cc.mult = 1;
790
791 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
792}
793
794
795
796
797
798
799
800
801
802void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
803{
804 struct ixgbe_hw *hw = &adapter->hw;
805 unsigned long flags;
806
807
808 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
809 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
810 IXGBE_WRITE_FLUSH(hw);
811
812 ixgbe_ptp_start_cyclecounter(adapter);
813
814 spin_lock_irqsave(&adapter->tmreg_lock, flags);
815
816
817 timecounter_init(&adapter->tc, &adapter->cc,
818 ktime_to_ns(ktime_get_real()));
819
820 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
821
822
823
824
825
826 ixgbe_ptp_setup_sdp(adapter);
827}
828
829
830
831
832
833
834
835
836
837void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
838{
839 struct net_device *netdev = adapter->netdev;
840
841 switch (adapter->hw.mac.type) {
842 case ixgbe_mac_X540:
843 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
844 adapter->ptp_caps.owner = THIS_MODULE;
845 adapter->ptp_caps.max_adj = 250000000;
846 adapter->ptp_caps.n_alarm = 0;
847 adapter->ptp_caps.n_ext_ts = 0;
848 adapter->ptp_caps.n_per_out = 0;
849 adapter->ptp_caps.pps = 1;
850 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
851 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
852 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
853 adapter->ptp_caps.settime = ixgbe_ptp_settime;
854 adapter->ptp_caps.enable = ixgbe_ptp_enable;
855 break;
856 case ixgbe_mac_82599EB:
857 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
858 adapter->ptp_caps.owner = THIS_MODULE;
859 adapter->ptp_caps.max_adj = 250000000;
860 adapter->ptp_caps.n_alarm = 0;
861 adapter->ptp_caps.n_ext_ts = 0;
862 adapter->ptp_caps.n_per_out = 0;
863 adapter->ptp_caps.pps = 0;
864 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
865 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
866 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
867 adapter->ptp_caps.settime = ixgbe_ptp_settime;
868 adapter->ptp_caps.enable = ixgbe_ptp_enable;
869 break;
870 default:
871 adapter->ptp_clock = NULL;
872 return;
873 }
874
875 spin_lock_init(&adapter->tmreg_lock);
876 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
877
878 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
879 &adapter->pdev->dev);
880 if (IS_ERR(adapter->ptp_clock)) {
881 adapter->ptp_clock = NULL;
882 e_dev_err("ptp_clock_register failed\n");
883 } else
884 e_dev_info("registered PHC device on %s\n", netdev->name);
885
886 ixgbe_ptp_reset(adapter);
887
888
889 adapter->flags2 |= IXGBE_FLAG2_PTP_ENABLED;
890
891 return;
892}
893
894
895
896
897
898
899
900void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
901{
902
903 adapter->flags2 &= ~(IXGBE_FLAG2_PTP_ENABLED |
904 IXGBE_FLAG2_PTP_PPS_ENABLED);
905
906 ixgbe_ptp_setup_sdp(adapter);
907
908 cancel_work_sync(&adapter->ptp_tx_work);
909 if (adapter->ptp_tx_skb) {
910 dev_kfree_skb_any(adapter->ptp_tx_skb);
911 adapter->ptp_tx_skb = NULL;
912 }
913
914 if (adapter->ptp_clock) {
915 ptp_clock_unregister(adapter->ptp_clock);
916 adapter->ptp_clock = NULL;
917 e_dev_info("removed PHC on %s\n",
918 adapter->netdev->name);
919 }
920}
921