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34#include <linux/init.h>
35#include <linux/interrupt.h>
36#include <linux/slab.h>
37#include <linux/export.h>
38#include <linux/mm.h>
39#include <linux/dma-mapping.h>
40
41#include <linux/mlx4/cmd.h>
42#include <linux/cpu_rmap.h>
43
44#include "mlx4.h"
45#include "fw.h"
46
47enum {
48 MLX4_IRQNAME_SIZE = 32
49};
50
51enum {
52 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
55};
56
57#define MLX4_EQ_STATUS_OK ( 0 << 28)
58#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59#define MLX4_EQ_OWNER_SW ( 0 << 24)
60#define MLX4_EQ_OWNER_HW ( 1 << 24)
61#define MLX4_EQ_FLAG_EC ( 1 << 18)
62#define MLX4_EQ_FLAG_OI ( 1 << 17)
63#define MLX4_EQ_STATE_ARMED ( 9 << 8)
64#define MLX4_EQ_STATE_FIRED (10 << 8)
65#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66
67#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
81 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
85
86static u64 get_async_ev_mask(struct mlx4_dev *dev)
87{
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91
92 return async_ev_mask;
93}
94
95static void eq_set_ci(struct mlx4_eq *eq, int req_not)
96{
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
98 req_not << 31),
99 eq->doorbell);
100
101 mb();
102}
103
104static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor)
105{
106
107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor);
108
109
110
111
112
113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
114}
115
116static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor)
117{
118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
120}
121
122static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
123{
124 struct mlx4_eqe *eqe =
125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
126 return (!!(eqe->owner & 0x80) ^
127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
128 eqe : NULL;
129}
130
131void mlx4_gen_slave_eqe(struct work_struct *work)
132{
133 struct mlx4_mfunc_master_ctx *master =
134 container_of(work, struct mlx4_mfunc_master_ctx,
135 slave_event_work);
136 struct mlx4_mfunc *mfunc =
137 container_of(master, struct mlx4_mfunc, master);
138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
139 struct mlx4_dev *dev = &priv->dev;
140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
141 struct mlx4_eqe *eqe;
142 u8 slave;
143 int i;
144
145 for (eqe = next_slave_event_eqe(slave_eq); eqe;
146 eqe = next_slave_event_eqe(slave_eq)) {
147 slave = eqe->slave_id;
148
149
150 if (slave == ALL_SLAVES) {
151 for (i = 0; i < dev->num_slaves; i++) {
152 if (i != dev->caps.function &&
153 master->slave_state[i].active)
154 if (mlx4_GEN_EQE(dev, i, eqe))
155 mlx4_warn(dev, "Failed to "
156 " generate event "
157 "for slave %d\n", i);
158 }
159 } else {
160 if (mlx4_GEN_EQE(dev, slave, eqe))
161 mlx4_warn(dev, "Failed to generate event "
162 "for slave %d\n", slave);
163 }
164 ++slave_eq->cons;
165 }
166}
167
168
169static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
170{
171 struct mlx4_priv *priv = mlx4_priv(dev);
172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
173 struct mlx4_eqe *s_eqe;
174 unsigned long flags;
175
176 spin_lock_irqsave(&slave_eq->event_lock, flags);
177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
178 if ((!!(s_eqe->owner & 0x80)) ^
179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
181 "No free EQE on slave events queue\n", slave);
182 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
183 return;
184 }
185
186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
187 s_eqe->slave_id = slave;
188
189 wmb();
190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
191 ++slave_eq->prod;
192
193 queue_work(priv->mfunc.master.comm_wq,
194 &priv->mfunc.master.slave_event_work);
195 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
196}
197
198static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
199 struct mlx4_eqe *eqe)
200{
201 struct mlx4_priv *priv = mlx4_priv(dev);
202 struct mlx4_slave_state *s_slave =
203 &priv->mfunc.master.slave_state[slave];
204
205 if (!s_slave->active) {
206
207 return;
208 }
209
210 slave_event(dev, slave, eqe);
211}
212
213int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
214{
215 struct mlx4_eqe eqe;
216
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
219
220 if (!s_slave->active)
221 return 0;
222
223 memset(&eqe, 0, sizeof eqe);
224
225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
227 eqe.event.port_mgmt_change.port = port;
228
229 return mlx4_GEN_EQE(dev, slave, &eqe);
230}
231EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
232
233int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
234{
235 struct mlx4_eqe eqe;
236
237
238 if (dev->num_vfs < slave)
239 return 0;
240 memset(&eqe, 0, sizeof eqe);
241
242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
244 eqe.event.port_mgmt_change.port = port;
245
246 return mlx4_GEN_EQE(dev, slave, &eqe);
247}
248EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
249
250int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
251 u8 port_subtype_change)
252{
253 struct mlx4_eqe eqe;
254
255
256 if (dev->num_vfs < slave)
257 return 0;
258 memset(&eqe, 0, sizeof eqe);
259
260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
261 eqe.subtype = port_subtype_change;
262 eqe.event.port_change.port = cpu_to_be32(port << 28);
263
264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
265 port_subtype_change, slave, port);
266 return mlx4_GEN_EQE(dev, slave, &eqe);
267}
268EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
269
270enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
271{
272 struct mlx4_priv *priv = mlx4_priv(dev);
273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
274 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
275 pr_err("%s: Error: asking for slave:%d, port:%d\n",
276 __func__, slave, port);
277 return SLAVE_PORT_DOWN;
278 }
279 return s_state[slave].port_state[port];
280}
281EXPORT_SYMBOL(mlx4_get_slave_port_state);
282
283static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
284 enum slave_port_state state)
285{
286 struct mlx4_priv *priv = mlx4_priv(dev);
287 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
288
289 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
290 pr_err("%s: Error: asking for slave:%d, port:%d\n",
291 __func__, slave, port);
292 return -1;
293 }
294 s_state[slave].port_state[port] = state;
295
296 return 0;
297}
298
299static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
300{
301 int i;
302 enum slave_port_gen_event gen_event;
303
304 for (i = 0; i < dev->num_slaves; i++)
305 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
306}
307
308
309
310
311
312
313
314
315
316int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
317 u8 port, int event,
318 enum slave_port_gen_event *gen_event)
319{
320 struct mlx4_priv *priv = mlx4_priv(dev);
321 struct mlx4_slave_state *ctx = NULL;
322 unsigned long flags;
323 int ret = -1;
324 enum slave_port_state cur_state =
325 mlx4_get_slave_port_state(dev, slave, port);
326
327 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
328
329 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
330 pr_err("%s: Error: asking for slave:%d, port:%d\n",
331 __func__, slave, port);
332 return ret;
333 }
334
335 ctx = &priv->mfunc.master.slave_state[slave];
336 spin_lock_irqsave(&ctx->lock, flags);
337
338 switch (cur_state) {
339 case SLAVE_PORT_DOWN:
340 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
341 mlx4_set_slave_port_state(dev, slave, port,
342 SLAVE_PENDING_UP);
343 break;
344 case SLAVE_PENDING_UP:
345 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
346 mlx4_set_slave_port_state(dev, slave, port,
347 SLAVE_PORT_DOWN);
348 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
349 mlx4_set_slave_port_state(dev, slave, port,
350 SLAVE_PORT_UP);
351 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
352 }
353 break;
354 case SLAVE_PORT_UP:
355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
356 mlx4_set_slave_port_state(dev, slave, port,
357 SLAVE_PORT_DOWN);
358 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
359 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
360 event) {
361 mlx4_set_slave_port_state(dev, slave, port,
362 SLAVE_PENDING_UP);
363 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
364 }
365 break;
366 default:
367 pr_err("%s: BUG!!! UNKNOWN state: "
368 "slave:%d, port:%d\n", __func__, slave, port);
369 goto out;
370 }
371 ret = mlx4_get_slave_port_state(dev, slave, port);
372
373out:
374 spin_unlock_irqrestore(&ctx->lock, flags);
375 return ret;
376}
377
378EXPORT_SYMBOL(set_and_calc_slave_port_state);
379
380int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
381{
382 struct mlx4_eqe eqe;
383
384 memset(&eqe, 0, sizeof eqe);
385
386 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
387 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
388 eqe.event.port_mgmt_change.port = port;
389 eqe.event.port_mgmt_change.params.port_info.changed_attr =
390 cpu_to_be32((u32) attr);
391
392 slave_event(dev, ALL_SLAVES, &eqe);
393 return 0;
394}
395EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
396
397void mlx4_master_handle_slave_flr(struct work_struct *work)
398{
399 struct mlx4_mfunc_master_ctx *master =
400 container_of(work, struct mlx4_mfunc_master_ctx,
401 slave_flr_event_work);
402 struct mlx4_mfunc *mfunc =
403 container_of(master, struct mlx4_mfunc, master);
404 struct mlx4_priv *priv =
405 container_of(mfunc, struct mlx4_priv, mfunc);
406 struct mlx4_dev *dev = &priv->dev;
407 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
408 int i;
409 int err;
410 unsigned long flags;
411
412 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
413
414 for (i = 0 ; i < dev->num_slaves; i++) {
415
416 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
417 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
418 "clean slave: %d\n", i);
419
420 mlx4_delete_all_resources_for_slave(dev, i);
421
422 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
423 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
424 slave_state[i].is_slave_going_down = 0;
425 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
426
427 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
428 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
429 if (err)
430 mlx4_warn(dev, "Failed to notify FW on "
431 "FLR done (slave:%d)\n", i);
432 }
433 }
434}
435
436static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
437{
438 struct mlx4_priv *priv = mlx4_priv(dev);
439 struct mlx4_eqe *eqe;
440 int cqn;
441 int eqes_found = 0;
442 int set_ci = 0;
443 int port;
444 int slave = 0;
445 int ret;
446 u32 flr_slave;
447 u8 update_slave_state;
448 int i;
449 enum slave_port_gen_event gen_event;
450 unsigned long flags;
451 struct mlx4_vport_state *s_info;
452
453 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) {
454
455
456
457
458 rmb();
459
460 switch (eqe->type) {
461 case MLX4_EVENT_TYPE_COMP:
462 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
463 mlx4_cq_completion(dev, cqn);
464 break;
465
466 case MLX4_EVENT_TYPE_PATH_MIG:
467 case MLX4_EVENT_TYPE_COMM_EST:
468 case MLX4_EVENT_TYPE_SQ_DRAINED:
469 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
470 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
471 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
472 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
473 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
474 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
475 if (mlx4_is_master(dev)) {
476
477 ret = mlx4_get_slave_from_resource_id(dev,
478 RES_QP,
479 be32_to_cpu(eqe->event.qp.qpn)
480 & 0xffffff, &slave);
481 if (ret && ret != -ENOENT) {
482 mlx4_dbg(dev, "QP event %02x(%02x) on "
483 "EQ %d at index %u: could "
484 "not get slave id (%d)\n",
485 eqe->type, eqe->subtype,
486 eq->eqn, eq->cons_index, ret);
487 break;
488 }
489
490 if (!ret && slave != dev->caps.function) {
491 mlx4_slave_event(dev, slave, eqe);
492 break;
493 }
494
495 }
496 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
497 0xffffff, eqe->type);
498 break;
499
500 case MLX4_EVENT_TYPE_SRQ_LIMIT:
501 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
502 __func__);
503 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
504 if (mlx4_is_master(dev)) {
505
506 ret = mlx4_get_slave_from_resource_id(dev,
507 RES_SRQ,
508 be32_to_cpu(eqe->event.srq.srqn)
509 & 0xffffff,
510 &slave);
511 if (ret && ret != -ENOENT) {
512 mlx4_warn(dev, "SRQ event %02x(%02x) "
513 "on EQ %d at index %u: could"
514 " not get slave id (%d)\n",
515 eqe->type, eqe->subtype,
516 eq->eqn, eq->cons_index, ret);
517 break;
518 }
519 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
520 " event: %02x(%02x)\n", __func__,
521 slave,
522 be32_to_cpu(eqe->event.srq.srqn),
523 eqe->type, eqe->subtype);
524
525 if (!ret && slave != dev->caps.function) {
526 mlx4_warn(dev, "%s: sending event "
527 "%02x(%02x) to slave:%d\n",
528 __func__, eqe->type,
529 eqe->subtype, slave);
530 mlx4_slave_event(dev, slave, eqe);
531 break;
532 }
533 }
534 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
535 0xffffff, eqe->type);
536 break;
537
538 case MLX4_EVENT_TYPE_CMD:
539 mlx4_cmd_event(dev,
540 be16_to_cpu(eqe->event.cmd.token),
541 eqe->event.cmd.status,
542 be64_to_cpu(eqe->event.cmd.out_param));
543 break;
544
545 case MLX4_EVENT_TYPE_PORT_CHANGE:
546 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
547 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
548 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
549 port);
550 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
551 if (!mlx4_is_master(dev))
552 break;
553 for (i = 0; i < dev->num_slaves; i++) {
554 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
555 if (i == mlx4_master_func_num(dev))
556 continue;
557 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
558 " to slave: %d, port:%d\n",
559 __func__, i, port);
560 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
561 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state)
562 mlx4_slave_event(dev, i, eqe);
563 } else {
564 set_and_calc_slave_port_state(dev, i, port,
565 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
566 &gen_event);
567
568 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
569 if (i == mlx4_master_func_num(dev))
570 continue;
571 mlx4_slave_event(dev, i, eqe);
572 }
573 }
574 }
575 } else {
576 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
577
578 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
579
580 if (!mlx4_is_master(dev))
581 break;
582 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
583 for (i = 0; i < dev->num_slaves; i++) {
584 if (i == mlx4_master_func_num(dev))
585 continue;
586 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
587 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state)
588 mlx4_slave_event(dev, i, eqe);
589 }
590 else
591
592
593
594 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
595 }
596 break;
597
598 case MLX4_EVENT_TYPE_CQ_ERROR:
599 mlx4_warn(dev, "CQ %s on CQN %06x\n",
600 eqe->event.cq_err.syndrome == 1 ?
601 "overrun" : "access violation",
602 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
603 if (mlx4_is_master(dev)) {
604 ret = mlx4_get_slave_from_resource_id(dev,
605 RES_CQ,
606 be32_to_cpu(eqe->event.cq_err.cqn)
607 & 0xffffff, &slave);
608 if (ret && ret != -ENOENT) {
609 mlx4_dbg(dev, "CQ event %02x(%02x) on "
610 "EQ %d at index %u: could "
611 "not get slave id (%d)\n",
612 eqe->type, eqe->subtype,
613 eq->eqn, eq->cons_index, ret);
614 break;
615 }
616
617 if (!ret && slave != dev->caps.function) {
618 mlx4_slave_event(dev, slave, eqe);
619 break;
620 }
621 }
622 mlx4_cq_event(dev,
623 be32_to_cpu(eqe->event.cq_err.cqn)
624 & 0xffffff,
625 eqe->type);
626 break;
627
628 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
629 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
630 break;
631
632 case MLX4_EVENT_TYPE_COMM_CHANNEL:
633 if (!mlx4_is_master(dev)) {
634 mlx4_warn(dev, "Received comm channel event "
635 "for non master device\n");
636 break;
637 }
638 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
639 eqe->event.comm_channel_arm.bit_vec,
640 sizeof eqe->event.comm_channel_arm.bit_vec);
641 queue_work(priv->mfunc.master.comm_wq,
642 &priv->mfunc.master.comm_work);
643 break;
644
645 case MLX4_EVENT_TYPE_FLR_EVENT:
646 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
647 if (!mlx4_is_master(dev)) {
648 mlx4_warn(dev, "Non-master function received"
649 "FLR event\n");
650 break;
651 }
652
653 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
654
655 if (flr_slave >= dev->num_slaves) {
656 mlx4_warn(dev,
657 "Got FLR for unknown function: %d\n",
658 flr_slave);
659 update_slave_state = 0;
660 } else
661 update_slave_state = 1;
662
663 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
664 if (update_slave_state) {
665 priv->mfunc.master.slave_state[flr_slave].active = false;
666 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
667 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
668 }
669 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
670 queue_work(priv->mfunc.master.comm_wq,
671 &priv->mfunc.master.slave_flr_event_work);
672 break;
673
674 case MLX4_EVENT_TYPE_FATAL_WARNING:
675 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
676 if (mlx4_is_master(dev))
677 for (i = 0; i < dev->num_slaves; i++) {
678 mlx4_dbg(dev, "%s: Sending "
679 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
680 " to slave: %d\n", __func__, i);
681 if (i == dev->caps.function)
682 continue;
683 mlx4_slave_event(dev, i, eqe);
684 }
685 mlx4_err(dev, "Temperature Threshold was reached! "
686 "Threshold: %d celsius degrees; "
687 "Current Temperature: %d\n",
688 be16_to_cpu(eqe->event.warming.warning_threshold),
689 be16_to_cpu(eqe->event.warming.current_temperature));
690 } else
691 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
692 "subtype %02x on EQ %d at index %u. owner=%x, "
693 "nent=0x%x, slave=%x, ownership=%s\n",
694 eqe->type, eqe->subtype, eq->eqn,
695 eq->cons_index, eqe->owner, eq->nent,
696 eqe->slave_id,
697 !!(eqe->owner & 0x80) ^
698 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
699
700 break;
701
702 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
703 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
704 (unsigned long) eqe);
705 break;
706
707 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
708 case MLX4_EVENT_TYPE_ECC_DETECT:
709 default:
710 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
711 "index %u. owner=%x, nent=0x%x, slave=%x, "
712 "ownership=%s\n",
713 eqe->type, eqe->subtype, eq->eqn,
714 eq->cons_index, eqe->owner, eq->nent,
715 eqe->slave_id,
716 !!(eqe->owner & 0x80) ^
717 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
718 break;
719 };
720
721 ++eq->cons_index;
722 eqes_found = 1;
723 ++set_ci;
724
725
726
727
728
729
730
731
732 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
733 eq_set_ci(eq, 0);
734 set_ci = 0;
735 }
736 }
737
738 eq_set_ci(eq, 1);
739
740 return eqes_found;
741}
742
743static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
744{
745 struct mlx4_dev *dev = dev_ptr;
746 struct mlx4_priv *priv = mlx4_priv(dev);
747 int work = 0;
748 int i;
749
750 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
751
752 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
753 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
754
755 return IRQ_RETVAL(work);
756}
757
758static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
759{
760 struct mlx4_eq *eq = eq_ptr;
761 struct mlx4_dev *dev = eq->dev;
762
763 mlx4_eq_int(dev, eq);
764
765
766 return IRQ_HANDLED;
767}
768
769int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
770 struct mlx4_vhcr *vhcr,
771 struct mlx4_cmd_mailbox *inbox,
772 struct mlx4_cmd_mailbox *outbox,
773 struct mlx4_cmd_info *cmd)
774{
775 struct mlx4_priv *priv = mlx4_priv(dev);
776 struct mlx4_slave_event_eq_info *event_eq =
777 priv->mfunc.master.slave_state[slave].event_eq;
778 u32 in_modifier = vhcr->in_modifier;
779 u32 eqn = in_modifier & 0x3FF;
780 u64 in_param = vhcr->in_param;
781 int err = 0;
782 int i;
783
784 if (slave == dev->caps.function)
785 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
786 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
787 MLX4_CMD_NATIVE);
788 if (!err)
789 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
790 if (in_param & (1LL << i))
791 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
792
793 return err;
794}
795
796static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
797 int eq_num)
798{
799 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
800 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
801 MLX4_CMD_WRAPPED);
802}
803
804static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
805 int eq_num)
806{
807 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
808 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
809 MLX4_CMD_WRAPPED);
810}
811
812static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
813 int eq_num)
814{
815 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
816 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
817 MLX4_CMD_WRAPPED);
818}
819
820static int mlx4_num_eq_uar(struct mlx4_dev *dev)
821{
822
823
824
825
826
827 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
828 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
829}
830
831static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
832{
833 struct mlx4_priv *priv = mlx4_priv(dev);
834 int index;
835
836 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
837
838 if (!priv->eq_table.uar_map[index]) {
839 priv->eq_table.uar_map[index] =
840 ioremap(pci_resource_start(dev->pdev, 2) +
841 ((eq->eqn / 4) << PAGE_SHIFT),
842 PAGE_SIZE);
843 if (!priv->eq_table.uar_map[index]) {
844 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
845 eq->eqn);
846 return NULL;
847 }
848 }
849
850 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
851}
852
853static void mlx4_unmap_uar(struct mlx4_dev *dev)
854{
855 struct mlx4_priv *priv = mlx4_priv(dev);
856 int i;
857
858 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
859 if (priv->eq_table.uar_map[i]) {
860 iounmap(priv->eq_table.uar_map[i]);
861 priv->eq_table.uar_map[i] = NULL;
862 }
863}
864
865static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
866 u8 intr, struct mlx4_eq *eq)
867{
868 struct mlx4_priv *priv = mlx4_priv(dev);
869 struct mlx4_cmd_mailbox *mailbox;
870 struct mlx4_eq_context *eq_context;
871 int npages;
872 u64 *dma_list = NULL;
873 dma_addr_t t;
874 u64 mtt_addr;
875 int err = -ENOMEM;
876 int i;
877
878 eq->dev = dev;
879 eq->nent = roundup_pow_of_two(max(nent, 2));
880
881 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE;
882
883 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
884 GFP_KERNEL);
885 if (!eq->page_list)
886 goto err_out;
887
888 for (i = 0; i < npages; ++i)
889 eq->page_list[i].buf = NULL;
890
891 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
892 if (!dma_list)
893 goto err_out_free;
894
895 mailbox = mlx4_alloc_cmd_mailbox(dev);
896 if (IS_ERR(mailbox))
897 goto err_out_free;
898 eq_context = mailbox->buf;
899
900 for (i = 0; i < npages; ++i) {
901 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
902 PAGE_SIZE, &t, GFP_KERNEL);
903 if (!eq->page_list[i].buf)
904 goto err_out_free_pages;
905
906 dma_list[i] = t;
907 eq->page_list[i].map = t;
908
909 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
910 }
911
912 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
913 if (eq->eqn == -1)
914 goto err_out_free_pages;
915
916 eq->doorbell = mlx4_get_eq_uar(dev, eq);
917 if (!eq->doorbell) {
918 err = -ENOMEM;
919 goto err_out_free_eq;
920 }
921
922 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
923 if (err)
924 goto err_out_free_eq;
925
926 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
927 if (err)
928 goto err_out_free_mtt;
929
930 memset(eq_context, 0, sizeof *eq_context);
931 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
932 MLX4_EQ_STATE_ARMED);
933 eq_context->log_eq_size = ilog2(eq->nent);
934 eq_context->intr = intr;
935 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
936
937 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
938 eq_context->mtt_base_addr_h = mtt_addr >> 32;
939 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
940
941 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
942 if (err) {
943 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
944 goto err_out_free_mtt;
945 }
946
947 kfree(dma_list);
948 mlx4_free_cmd_mailbox(dev, mailbox);
949
950 eq->cons_index = 0;
951
952 return err;
953
954err_out_free_mtt:
955 mlx4_mtt_cleanup(dev, &eq->mtt);
956
957err_out_free_eq:
958 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
959
960err_out_free_pages:
961 for (i = 0; i < npages; ++i)
962 if (eq->page_list[i].buf)
963 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
964 eq->page_list[i].buf,
965 eq->page_list[i].map);
966
967 mlx4_free_cmd_mailbox(dev, mailbox);
968
969err_out_free:
970 kfree(eq->page_list);
971 kfree(dma_list);
972
973err_out:
974 return err;
975}
976
977static void mlx4_free_eq(struct mlx4_dev *dev,
978 struct mlx4_eq *eq)
979{
980 struct mlx4_priv *priv = mlx4_priv(dev);
981 struct mlx4_cmd_mailbox *mailbox;
982 int err;
983 int i;
984
985 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE;
986
987 mailbox = mlx4_alloc_cmd_mailbox(dev);
988 if (IS_ERR(mailbox))
989 return;
990
991 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
992 if (err)
993 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
994
995 if (0) {
996 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
997 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
998 if (i % 4 == 0)
999 pr_cont("[%02x] ", i * 4);
1000 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1001 if ((i + 1) % 4 == 0)
1002 pr_cont("\n");
1003 }
1004 }
1005
1006 mlx4_mtt_cleanup(dev, &eq->mtt);
1007 for (i = 0; i < npages; ++i)
1008 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1009 eq->page_list[i].buf,
1010 eq->page_list[i].map);
1011
1012 kfree(eq->page_list);
1013 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
1014 mlx4_free_cmd_mailbox(dev, mailbox);
1015}
1016
1017static void mlx4_free_irqs(struct mlx4_dev *dev)
1018{
1019 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1020 struct mlx4_priv *priv = mlx4_priv(dev);
1021 int i, vec;
1022
1023 if (eq_table->have_irq)
1024 free_irq(dev->pdev->irq, dev);
1025
1026 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1027 if (eq_table->eq[i].have_irq) {
1028 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1029 eq_table->eq[i].have_irq = 0;
1030 }
1031
1032 for (i = 0; i < dev->caps.comp_pool; i++) {
1033
1034
1035
1036
1037 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1038
1039 vec = dev->caps.num_comp_vectors + 1 + i;
1040 free_irq(priv->eq_table.eq[vec].irq,
1041 &priv->eq_table.eq[vec]);
1042 }
1043 }
1044
1045
1046 kfree(eq_table->irq_names);
1047}
1048
1049static int mlx4_map_clr_int(struct mlx4_dev *dev)
1050{
1051 struct mlx4_priv *priv = mlx4_priv(dev);
1052
1053 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1054 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1055 if (!priv->clr_base) {
1056 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1057 return -ENOMEM;
1058 }
1059
1060 return 0;
1061}
1062
1063static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1064{
1065 struct mlx4_priv *priv = mlx4_priv(dev);
1066
1067 iounmap(priv->clr_base);
1068}
1069
1070int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1071{
1072 struct mlx4_priv *priv = mlx4_priv(dev);
1073
1074 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1075 sizeof *priv->eq_table.eq, GFP_KERNEL);
1076 if (!priv->eq_table.eq)
1077 return -ENOMEM;
1078
1079 return 0;
1080}
1081
1082void mlx4_free_eq_table(struct mlx4_dev *dev)
1083{
1084 kfree(mlx4_priv(dev)->eq_table.eq);
1085}
1086
1087int mlx4_init_eq_table(struct mlx4_dev *dev)
1088{
1089 struct mlx4_priv *priv = mlx4_priv(dev);
1090 int err;
1091 int i;
1092
1093 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1094 sizeof *priv->eq_table.uar_map,
1095 GFP_KERNEL);
1096 if (!priv->eq_table.uar_map) {
1097 err = -ENOMEM;
1098 goto err_out_free;
1099 }
1100
1101 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1102 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1103 if (err)
1104 goto err_out_free;
1105
1106 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1107 priv->eq_table.uar_map[i] = NULL;
1108
1109 if (!mlx4_is_slave(dev)) {
1110 err = mlx4_map_clr_int(dev);
1111 if (err)
1112 goto err_out_bitmap;
1113
1114 priv->eq_table.clr_mask =
1115 swab32(1 << (priv->eq_table.inta_pin & 31));
1116 priv->eq_table.clr_int = priv->clr_base +
1117 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1118 }
1119
1120 priv->eq_table.irq_names =
1121 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1122 dev->caps.comp_pool),
1123 GFP_KERNEL);
1124 if (!priv->eq_table.irq_names) {
1125 err = -ENOMEM;
1126 goto err_out_bitmap;
1127 }
1128
1129 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1130 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1131 dev->caps.reserved_cqs +
1132 MLX4_NUM_SPARE_EQE,
1133 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1134 &priv->eq_table.eq[i]);
1135 if (err) {
1136 --i;
1137 goto err_out_unmap;
1138 }
1139 }
1140
1141 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1142 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1143 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1144 if (err)
1145 goto err_out_comp;
1146
1147
1148 for (i = dev->caps.num_comp_vectors + 1;
1149 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1150
1151 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1152 dev->caps.reserved_cqs +
1153 MLX4_NUM_SPARE_EQE,
1154 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1155 &priv->eq_table.eq[i]);
1156 if (err) {
1157 --i;
1158 goto err_out_unmap;
1159 }
1160 }
1161
1162
1163 if (dev->flags & MLX4_FLAG_MSI_X) {
1164 const char *eq_name;
1165
1166 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1167 if (i < dev->caps.num_comp_vectors) {
1168 snprintf(priv->eq_table.irq_names +
1169 i * MLX4_IRQNAME_SIZE,
1170 MLX4_IRQNAME_SIZE,
1171 "mlx4-comp-%d@pci:%s", i,
1172 pci_name(dev->pdev));
1173 } else {
1174 snprintf(priv->eq_table.irq_names +
1175 i * MLX4_IRQNAME_SIZE,
1176 MLX4_IRQNAME_SIZE,
1177 "mlx4-async@pci:%s",
1178 pci_name(dev->pdev));
1179 }
1180
1181 eq_name = priv->eq_table.irq_names +
1182 i * MLX4_IRQNAME_SIZE;
1183 err = request_irq(priv->eq_table.eq[i].irq,
1184 mlx4_msi_x_interrupt, 0, eq_name,
1185 priv->eq_table.eq + i);
1186 if (err)
1187 goto err_out_async;
1188
1189 priv->eq_table.eq[i].have_irq = 1;
1190 }
1191 } else {
1192 snprintf(priv->eq_table.irq_names,
1193 MLX4_IRQNAME_SIZE,
1194 DRV_NAME "@pci:%s",
1195 pci_name(dev->pdev));
1196 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1197 IRQF_SHARED, priv->eq_table.irq_names, dev);
1198 if (err)
1199 goto err_out_async;
1200
1201 priv->eq_table.have_irq = 1;
1202 }
1203
1204 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1205 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1206 if (err)
1207 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1208 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1209
1210 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1211 eq_set_ci(&priv->eq_table.eq[i], 1);
1212
1213 return 0;
1214
1215err_out_async:
1216 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1217
1218err_out_comp:
1219 i = dev->caps.num_comp_vectors - 1;
1220
1221err_out_unmap:
1222 while (i >= 0) {
1223 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1224 --i;
1225 }
1226 if (!mlx4_is_slave(dev))
1227 mlx4_unmap_clr_int(dev);
1228 mlx4_free_irqs(dev);
1229
1230err_out_bitmap:
1231 mlx4_unmap_uar(dev);
1232 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1233
1234err_out_free:
1235 kfree(priv->eq_table.uar_map);
1236
1237 return err;
1238}
1239
1240void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1241{
1242 struct mlx4_priv *priv = mlx4_priv(dev);
1243 int i;
1244
1245 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1246 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1247
1248 mlx4_free_irqs(dev);
1249
1250 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1251 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1252
1253 if (!mlx4_is_slave(dev))
1254 mlx4_unmap_clr_int(dev);
1255
1256 mlx4_unmap_uar(dev);
1257 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1258
1259 kfree(priv->eq_table.uar_map);
1260}
1261
1262
1263
1264
1265
1266int mlx4_test_interrupts(struct mlx4_dev *dev)
1267{
1268 struct mlx4_priv *priv = mlx4_priv(dev);
1269 int i;
1270 int err;
1271
1272 err = mlx4_NOP(dev);
1273
1274 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1275 return err;
1276
1277
1278
1279
1280
1281 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1282
1283 mlx4_cmd_use_polling(dev);
1284
1285
1286 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1287 priv->eq_table.eq[i].eqn);
1288 if (err) {
1289 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1290 mlx4_cmd_use_events(dev);
1291 break;
1292 }
1293
1294
1295 mlx4_cmd_use_events(dev);
1296 err = mlx4_NOP(dev);
1297 }
1298
1299
1300 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1301 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1302 return err;
1303}
1304EXPORT_SYMBOL(mlx4_test_interrupts);
1305
1306int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1307 int *vector)
1308{
1309
1310 struct mlx4_priv *priv = mlx4_priv(dev);
1311 int vec = 0, err = 0, i;
1312
1313 mutex_lock(&priv->msix_ctl.pool_lock);
1314 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1315 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1316 priv->msix_ctl.pool_bm |= 1ULL << i;
1317 vec = dev->caps.num_comp_vectors + 1 + i;
1318 snprintf(priv->eq_table.irq_names +
1319 vec * MLX4_IRQNAME_SIZE,
1320 MLX4_IRQNAME_SIZE, "%s", name);
1321#ifdef CONFIG_RFS_ACCEL
1322 if (rmap) {
1323 err = irq_cpu_rmap_add(rmap,
1324 priv->eq_table.eq[vec].irq);
1325 if (err)
1326 mlx4_warn(dev, "Failed adding irq rmap\n");
1327 }
1328#endif
1329 err = request_irq(priv->eq_table.eq[vec].irq,
1330 mlx4_msi_x_interrupt, 0,
1331 &priv->eq_table.irq_names[vec<<5],
1332 priv->eq_table.eq + vec);
1333 if (err) {
1334
1335 priv->msix_ctl.pool_bm ^= 1 << i;
1336 vec = 0;
1337 continue;
1338
1339 }
1340 eq_set_ci(&priv->eq_table.eq[vec], 1);
1341 }
1342 }
1343 mutex_unlock(&priv->msix_ctl.pool_lock);
1344
1345 if (vec) {
1346 *vector = vec;
1347 } else {
1348 *vector = 0;
1349 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1350 }
1351 return err;
1352}
1353EXPORT_SYMBOL(mlx4_assign_eq);
1354
1355void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1356{
1357 struct mlx4_priv *priv = mlx4_priv(dev);
1358
1359 int i = vec - dev->caps.num_comp_vectors - 1;
1360
1361 if (likely(i >= 0)) {
1362
1363
1364 mutex_lock(&priv->msix_ctl.pool_lock);
1365 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1366 free_irq(priv->eq_table.eq[vec].irq,
1367 &priv->eq_table.eq[vec]);
1368 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1369 }
1370 mutex_unlock(&priv->msix_ctl.pool_lock);
1371 }
1372
1373}
1374EXPORT_SYMBOL(mlx4_release_eq);
1375
1376
