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34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/bitops.h>
38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/netdevice.h>
42#include <linux/if_vlan.h>
43#include <linux/net_tstamp.h>
44#ifdef CONFIG_MLX4_EN_DCB
45#include <linux/dcbnl.h>
46#endif
47#include <linux/cpu_rmap.h>
48
49#include <linux/mlx4/device.h>
50#include <linux/mlx4/qp.h>
51#include <linux/mlx4/cq.h>
52#include <linux/mlx4/srq.h>
53#include <linux/mlx4/doorbell.h>
54#include <linux/mlx4/cmd.h>
55
56#include "en_port.h"
57
58#define DRV_NAME "mlx4_en"
59#define DRV_VERSION "2.0"
60#define DRV_RELDATE "Dec 2011"
61
62#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
63
64
65
66
67
68
69#define MLX4_EN_PAGE_SHIFT 12
70#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
71#define DEF_RX_RINGS 16
72#define MAX_RX_RINGS 128
73#define MIN_RX_RINGS 4
74#define TXBB_SIZE 64
75#define HEADROOM (2048 / TXBB_SIZE + 1)
76#define STAMP_STRIDE 64
77#define STAMP_DWORDS (STAMP_STRIDE / 4)
78#define STAMP_SHIFT 31
79#define STAMP_VAL 0x7fffffff
80#define STATS_DELAY (HZ / 4)
81#define SERVICE_TASK_DELAY (HZ / 4)
82#define MAX_NUM_OF_FS_RULES 256
83
84#define MLX4_EN_FILTER_HASH_SHIFT 4
85#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
86
87
88#define MAX_DESC_SIZE 512
89#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
90
91
92
93
94
95#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
96
97
98#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
99
100#define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
101
102
103
104enum {
105 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
106 FRAG_SZ1 = 4096,
107 FRAG_SZ2 = 4096,
108 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
109};
110#define MLX4_EN_MAX_RX_FRAGS 4
111
112
113#define MLX4_EN_MAX_TX_SIZE 8192
114#define MLX4_EN_MAX_RX_SIZE 8192
115
116
117#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
118#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
119
120#define MLX4_EN_SMALL_PKT_SIZE 64
121#define MLX4_EN_MAX_TX_RING_P_UP 32
122#define MLX4_EN_NUM_UP 8
123#define MLX4_EN_DEF_TX_RING_SIZE 512
124#define MLX4_EN_DEF_RX_RING_SIZE 1024
125#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
126 MLX4_EN_NUM_UP)
127
128
129#define MLX4_EN_RX_COAL_TARGET 44
130#define MLX4_EN_RX_COAL_TIME 0x10
131
132#define MLX4_EN_TX_COAL_PKTS 16
133#define MLX4_EN_TX_COAL_TIME 0x10
134
135#define MLX4_EN_RX_RATE_LOW 400000
136#define MLX4_EN_RX_COAL_TIME_LOW 0
137#define MLX4_EN_RX_RATE_HIGH 450000
138#define MLX4_EN_RX_COAL_TIME_HIGH 128
139#define MLX4_EN_RX_SIZE_THRESH 1024
140#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
141#define MLX4_EN_SAMPLE_INTERVAL 0
142#define MLX4_EN_AVG_PKT_SMALL 256
143
144#define MLX4_EN_AUTO_CONF 0xffff
145
146#define MLX4_EN_DEF_RX_PAUSE 1
147#define MLX4_EN_DEF_TX_PAUSE 1
148
149
150
151#define MLX4_EN_TX_POLL_MODER 16
152#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
153
154#define ETH_LLC_SNAP_SIZE 8
155
156#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
157#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
158#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
159
160#define MLX4_EN_MIN_MTU 46
161#define ETH_BCAST 0xffffffffffffULL
162
163#define MLX4_EN_LOOPBACK_RETRIES 5
164#define MLX4_EN_LOOPBACK_TIMEOUT 100
165
166#ifdef MLX4_EN_PERF_STAT
167
168#define AVG_SIZE 128
169#define AVG_FACTOR 1024
170#define NUM_PERF_STATS NUM_PERF_COUNTERS
171
172#define INC_PERF_COUNTER(cnt) (++(cnt))
173#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
174#define AVG_PERF_COUNTER(cnt, sample) \
175 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
176#define GET_PERF_COUNTER(cnt) (cnt)
177#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
178
179#else
180
181#define NUM_PERF_STATS 0
182#define INC_PERF_COUNTER(cnt) do {} while (0)
183#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
184#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
185#define GET_PERF_COUNTER(cnt) (0)
186#define GET_AVG_PERF_COUNTER(cnt) (0)
187#endif
188
189
190
191
192
193enum cq_type {
194 RX = 0,
195 TX = 1,
196};
197
198
199
200
201
202#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
203#define XNOR(x, y) (!(x) == !(y))
204
205
206struct mlx4_en_tx_info {
207 struct sk_buff *skb;
208 u32 nr_txbb;
209 u32 nr_bytes;
210 u8 linear;
211 u8 data_offset;
212 u8 inl;
213 u8 ts_requested;
214};
215
216
217#define MLX4_EN_BIT_DESC_OWN 0x80000000
218#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
219#define MLX4_EN_MEMTYPE_PAD 0x100
220#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
221
222
223struct mlx4_en_tx_desc {
224 struct mlx4_wqe_ctrl_seg ctrl;
225 union {
226 struct mlx4_wqe_data_seg data;
227 struct mlx4_wqe_lso_seg lso;
228 struct mlx4_wqe_inline_seg inl;
229 };
230};
231
232#define MLX4_EN_USE_SRQ 0x01000000
233
234#define MLX4_EN_CX3_LOW_ID 0x1000
235#define MLX4_EN_CX3_HIGH_ID 0x1005
236
237struct mlx4_en_rx_alloc {
238 struct page *page;
239 dma_addr_t dma;
240 u32 offset;
241 u32 size;
242};
243
244struct mlx4_en_tx_ring {
245 struct mlx4_hwq_resources wqres;
246 u32 size ;
247 u32 size_mask;
248 u16 stride;
249 u16 cqn;
250 u32 prod;
251 u32 cons;
252 u32 buf_size;
253 u32 doorbell_qpn;
254 void *buf;
255 u16 poll_cnt;
256 struct mlx4_en_tx_info *tx_info;
257 u8 *bounce_buf;
258 u32 last_nr_txbb;
259 struct mlx4_qp qp;
260 struct mlx4_qp_context context;
261 int qpn;
262 enum mlx4_qp_state qp_state;
263 struct mlx4_srq dummy;
264 unsigned long bytes;
265 unsigned long packets;
266 unsigned long tx_csum;
267 struct mlx4_bf bf;
268 bool bf_enabled;
269 struct netdev_queue *tx_queue;
270 int hwtstamp_tx_type;
271};
272
273struct mlx4_en_rx_desc {
274
275 struct mlx4_wqe_data_seg data[0];
276};
277
278struct mlx4_en_rx_ring {
279 struct mlx4_hwq_resources wqres;
280 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
281 u32 size ;
282 u32 actual_size;
283 u32 size_mask;
284 u16 stride;
285 u16 log_stride;
286 u16 cqn;
287 u32 prod;
288 u32 cons;
289 u32 buf_size;
290 u8 fcs_del;
291 void *buf;
292 void *rx_info;
293 unsigned long bytes;
294 unsigned long packets;
295#ifdef CONFIG_NET_RX_BUSY_POLL
296 unsigned long yields;
297 unsigned long misses;
298 unsigned long cleaned;
299#endif
300 unsigned long csum_ok;
301 unsigned long csum_none;
302 int hwtstamp_rx_filter;
303};
304
305struct mlx4_en_cq {
306 struct mlx4_cq mcq;
307 struct mlx4_hwq_resources wqres;
308 int ring;
309 spinlock_t lock;
310 struct net_device *dev;
311 struct napi_struct napi;
312 int size;
313 int buf_size;
314 unsigned vector;
315 enum cq_type is_tx;
316 u16 moder_time;
317 u16 moder_cnt;
318 struct mlx4_cqe *buf;
319#define MLX4_EN_OPCODE_ERROR 0x1e
320
321#ifdef CONFIG_NET_RX_BUSY_POLL
322 unsigned int state;
323#define MLX4_EN_CQ_STATE_IDLE 0
324#define MLX4_EN_CQ_STATE_NAPI 1
325#define MLX4_EN_CQ_STATE_POLL 2
326#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
327#define MLX4_EN_CQ_STATE_NAPI_YIELD 4
328#define MLX4_EN_CQ_STATE_POLL_YIELD 8
329#define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
330#define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
331 spinlock_t poll_lock;
332#endif
333};
334
335struct mlx4_en_port_profile {
336 u32 flags;
337 u32 tx_ring_num;
338 u32 rx_ring_num;
339 u32 tx_ring_size;
340 u32 rx_ring_size;
341 u8 rx_pause;
342 u8 rx_ppp;
343 u8 tx_pause;
344 u8 tx_ppp;
345 int rss_rings;
346};
347
348struct mlx4_en_profile {
349 int rss_xor;
350 int udp_rss;
351 u8 rss_mask;
352 u32 active_ports;
353 u32 small_pkt_int;
354 u8 no_reset;
355 u8 num_tx_rings_p_up;
356 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
357};
358
359struct mlx4_en_dev {
360 struct mlx4_dev *dev;
361 struct pci_dev *pdev;
362 struct mutex state_lock;
363 struct net_device *pndev[MLX4_MAX_PORTS + 1];
364 u32 port_cnt;
365 bool device_up;
366 struct mlx4_en_profile profile;
367 u32 LSO_support;
368 struct workqueue_struct *workqueue;
369 struct device *dma_device;
370 void __iomem *uar_map;
371 struct mlx4_uar priv_uar;
372 struct mlx4_mr mr;
373 u32 priv_pdn;
374 spinlock_t uar_lock;
375 u8 mac_removed[MLX4_MAX_PORTS + 1];
376 struct cyclecounter cycles;
377 struct timecounter clock;
378 unsigned long last_overflow_check;
379 unsigned long overflow_period;
380};
381
382
383struct mlx4_en_rss_map {
384 int base_qpn;
385 struct mlx4_qp qps[MAX_RX_RINGS];
386 enum mlx4_qp_state state[MAX_RX_RINGS];
387 struct mlx4_qp indir_qp;
388 enum mlx4_qp_state indir_state;
389};
390
391struct mlx4_en_port_state {
392 int link_state;
393 int link_speed;
394 int transciver;
395};
396
397struct mlx4_en_pkt_stats {
398 unsigned long broadcast;
399 unsigned long rx_prio[8];
400 unsigned long tx_prio[8];
401#define NUM_PKT_STATS 17
402};
403
404struct mlx4_en_port_stats {
405 unsigned long tso_packets;
406 unsigned long queue_stopped;
407 unsigned long wake_queue;
408 unsigned long tx_timeout;
409 unsigned long rx_alloc_failed;
410 unsigned long rx_chksum_good;
411 unsigned long rx_chksum_none;
412 unsigned long tx_chksum_offload;
413#define NUM_PORT_STATS 8
414};
415
416struct mlx4_en_perf_stats {
417 u32 tx_poll;
418 u64 tx_pktsz_avg;
419 u32 inflight_avg;
420 u16 tx_coal_avg;
421 u16 rx_coal_avg;
422 u32 napi_quota;
423#define NUM_PERF_COUNTERS 6
424};
425
426enum mlx4_en_mclist_act {
427 MCLIST_NONE,
428 MCLIST_REM,
429 MCLIST_ADD,
430};
431
432struct mlx4_en_mc_list {
433 struct list_head list;
434 enum mlx4_en_mclist_act action;
435 u8 addr[ETH_ALEN];
436 u64 reg_id;
437};
438
439struct mlx4_en_frag_info {
440 u16 frag_size;
441 u16 frag_prefix_size;
442 u16 frag_stride;
443 u16 frag_align;
444};
445
446#ifdef CONFIG_MLX4_EN_DCB
447
448#define MLX4_EN_BW_MIN 1
449#define MLX4_EN_BW_MAX 100
450
451#define MLX4_EN_TC_ETS 7
452
453#endif
454
455struct ethtool_flow_id {
456 struct list_head list;
457 struct ethtool_rx_flow_spec flow_spec;
458 u64 id;
459};
460
461enum {
462 MLX4_EN_FLAG_PROMISC = (1 << 0),
463 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
464
465
466
467 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
468
469 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
470 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4)
471};
472
473#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
474#define MLX4_EN_MAC_HASH_IDX 5
475
476struct mlx4_en_priv {
477 struct mlx4_en_dev *mdev;
478 struct mlx4_en_port_profile *prof;
479 struct net_device *dev;
480 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
481 struct net_device_stats stats;
482 struct net_device_stats ret_stats;
483 struct mlx4_en_port_state port_state;
484 spinlock_t stats_lock;
485 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
486
487 struct list_head ethtool_list;
488
489 unsigned long last_moder_packets[MAX_RX_RINGS];
490 unsigned long last_moder_tx_packets;
491 unsigned long last_moder_bytes[MAX_RX_RINGS];
492 unsigned long last_moder_jiffies;
493 int last_moder_time[MAX_RX_RINGS];
494 u16 rx_usecs;
495 u16 rx_frames;
496 u16 tx_usecs;
497 u16 tx_frames;
498 u32 pkt_rate_low;
499 u16 rx_usecs_low;
500 u32 pkt_rate_high;
501 u16 rx_usecs_high;
502 u16 sample_interval;
503 u16 adaptive_rx_coal;
504 u32 msg_enable;
505 u32 loopback_ok;
506 u32 validate_loopback;
507
508 struct mlx4_hwq_resources res;
509 int link_state;
510 int last_link_state;
511 bool port_up;
512 int port;
513 int registered;
514 int allocated;
515 int stride;
516 unsigned char prev_mac[ETH_ALEN + 2];
517 int mac_index;
518 unsigned max_mtu;
519 int base_qpn;
520 int cqe_factor;
521
522 struct mlx4_en_rss_map rss_map;
523 __be32 ctrl_flags;
524 u32 flags;
525 u8 num_tx_rings_p_up;
526 u32 tx_ring_num;
527 u32 rx_ring_num;
528 u32 rx_skb_size;
529 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
530 u16 num_frags;
531 u16 log_rx_info;
532
533 struct mlx4_en_tx_ring *tx_ring;
534 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
535 struct mlx4_en_cq *tx_cq;
536 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
537 struct mlx4_qp drop_qp;
538 struct work_struct rx_mode_task;
539 struct work_struct watchdog_task;
540 struct work_struct linkstate_task;
541 struct delayed_work stats_task;
542 struct delayed_work service_task;
543 struct mlx4_en_perf_stats pstats;
544 struct mlx4_en_pkt_stats pkstats;
545 struct mlx4_en_port_stats port_stats;
546 u64 stats_bitmap;
547 struct list_head mc_list;
548 struct list_head curr_list;
549 u64 broadcast_id;
550 struct mlx4_en_stat_out_mbox hw_stats;
551 int vids[128];
552 bool wol;
553 struct device *ddev;
554 int base_tx_qpn;
555 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
556 struct hwtstamp_config hwtstamp_config;
557
558#ifdef CONFIG_MLX4_EN_DCB
559 struct ieee_ets ets;
560 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
561#endif
562#ifdef CONFIG_RFS_ACCEL
563 spinlock_t filters_lock;
564 int last_filter_id;
565 struct list_head filters;
566 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
567#endif
568
569};
570
571enum mlx4_en_wol {
572 MLX4_EN_WOL_MAGIC = (1ULL << 61),
573 MLX4_EN_WOL_ENABLED = (1ULL << 62),
574};
575
576struct mlx4_mac_entry {
577 struct hlist_node hlist;
578 unsigned char mac[ETH_ALEN + 2];
579 u64 reg_id;
580 struct rcu_head rcu;
581};
582
583#ifdef CONFIG_NET_RX_BUSY_POLL
584static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
585{
586 spin_lock_init(&cq->poll_lock);
587 cq->state = MLX4_EN_CQ_STATE_IDLE;
588}
589
590
591static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
592{
593 int rc = true;
594 spin_lock(&cq->poll_lock);
595 if (cq->state & MLX4_CQ_LOCKED) {
596 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
597 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
598 rc = false;
599 } else
600
601 cq->state = MLX4_EN_CQ_STATE_NAPI;
602 spin_unlock(&cq->poll_lock);
603 return rc;
604}
605
606
607static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
608{
609 int rc = false;
610 spin_lock(&cq->poll_lock);
611 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
612 MLX4_EN_CQ_STATE_NAPI_YIELD));
613
614 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
615 rc = true;
616 cq->state = MLX4_EN_CQ_STATE_IDLE;
617 spin_unlock(&cq->poll_lock);
618 return rc;
619}
620
621
622static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
623{
624 int rc = true;
625 spin_lock_bh(&cq->poll_lock);
626 if ((cq->state & MLX4_CQ_LOCKED)) {
627 struct net_device *dev = cq->dev;
628 struct mlx4_en_priv *priv = netdev_priv(dev);
629 struct mlx4_en_rx_ring *rx_ring = &priv->rx_ring[cq->ring];
630
631 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
632 rc = false;
633 rx_ring->yields++;
634 } else
635
636 cq->state |= MLX4_EN_CQ_STATE_POLL;
637 spin_unlock_bh(&cq->poll_lock);
638 return rc;
639}
640
641
642static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
643{
644 int rc = false;
645 spin_lock_bh(&cq->poll_lock);
646 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
647
648 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
649 rc = true;
650 cq->state = MLX4_EN_CQ_STATE_IDLE;
651 spin_unlock_bh(&cq->poll_lock);
652 return rc;
653}
654
655
656static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
657{
658 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
659 return cq->state & CQ_USER_PEND;
660}
661#else
662static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
663{
664}
665
666static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
667{
668 return true;
669}
670
671static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
672{
673 return false;
674}
675
676static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
677{
678 return false;
679}
680
681static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
682{
683 return false;
684}
685
686static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
687{
688 return false;
689}
690#endif
691
692#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
693
694void mlx4_en_update_loopback_state(struct net_device *dev,
695 netdev_features_t features);
696
697void mlx4_en_destroy_netdev(struct net_device *dev);
698int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
699 struct mlx4_en_port_profile *prof);
700
701int mlx4_en_start_port(struct net_device *dev);
702void mlx4_en_stop_port(struct net_device *dev, int detach);
703
704void mlx4_en_free_resources(struct mlx4_en_priv *priv);
705int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
706
707int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
708 int entries, int ring, enum cq_type mode);
709void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
710int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
711 int cq_idx);
712void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
713int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
714int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
715
716void mlx4_en_tx_irq(struct mlx4_cq *mcq);
717u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
718netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
719
720int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
721 int qpn, u32 size, u16 stride);
722void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
723int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
724 struct mlx4_en_tx_ring *ring,
725 int cq, int user_prio);
726void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
727 struct mlx4_en_tx_ring *ring);
728
729int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
730 struct mlx4_en_rx_ring *ring,
731 u32 size, u16 stride);
732void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
733 struct mlx4_en_rx_ring *ring,
734 u32 size, u16 stride);
735int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
736void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
737 struct mlx4_en_rx_ring *ring);
738int mlx4_en_process_rx_cq(struct net_device *dev,
739 struct mlx4_en_cq *cq,
740 int budget);
741int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
742void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
743 int is_tx, int rss, int qpn, int cqn, int user_prio,
744 struct mlx4_qp_context *context);
745void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
746int mlx4_en_map_buffer(struct mlx4_buf *buf);
747void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
748
749void mlx4_en_calc_rx_buf(struct net_device *dev);
750int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
751void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
752int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
753void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
754int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
755void mlx4_en_rx_irq(struct mlx4_cq *mcq);
756
757int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
758int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
759
760int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
761int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
762
763#ifdef CONFIG_MLX4_EN_DCB
764extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
765extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
766#endif
767
768int mlx4_en_setup_tc(struct net_device *dev, u8 up);
769
770#ifdef CONFIG_RFS_ACCEL
771void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
772 struct mlx4_en_rx_ring *rx_ring);
773#endif
774
775#define MLX4_EN_NUM_SELF_TEST 5
776void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
777u64 mlx4_en_mac_to_u64(u8 *addr);
778void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
779
780
781
782
783u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
784void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
785 struct skb_shared_hwtstamps *hwts,
786 u64 timestamp);
787void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
788int mlx4_en_timestamp_config(struct net_device *dev,
789 int tx_type,
790 int rx_filter);
791
792
793
794extern const struct ethtool_ops mlx4_en_ethtool_ops;
795
796
797
798
799
800
801
802__printf(3, 4)
803int en_print(const char *level, const struct mlx4_en_priv *priv,
804 const char *format, ...);
805
806#define en_dbg(mlevel, priv, format, arg...) \
807do { \
808 if (NETIF_MSG_##mlevel & priv->msg_enable) \
809 en_print(KERN_DEBUG, priv, format, ##arg); \
810} while (0)
811#define en_warn(priv, format, arg...) \
812 en_print(KERN_WARNING, priv, format, ##arg)
813#define en_err(priv, format, arg...) \
814 en_print(KERN_ERR, priv, format, ##arg)
815#define en_info(priv, format, arg...) \
816 en_print(KERN_INFO, priv, format, ## arg)
817
818#define mlx4_err(mdev, format, arg...) \
819 pr_err("%s %s: " format, DRV_NAME, \
820 dev_name(&mdev->pdev->dev), ##arg)
821#define mlx4_info(mdev, format, arg...) \
822 pr_info("%s %s: " format, DRV_NAME, \
823 dev_name(&mdev->pdev->dev), ##arg)
824#define mlx4_warn(mdev, format, arg...) \
825 pr_warning("%s %s: " format, DRV_NAME, \
826 dev_name(&mdev->pdev->dev), ##arg)
827
828#endif
829
