LXR linux/drivers/net/ethernet/qlogic/netxen/netxen_nic

   1/*
   2 * Copyright (C) 2003 - 2009 NetXen, Inc.
   3 * Copyright (C) 2009 - QLogic Corporation.
   4 * All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but
  12 * WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19 * MA  02111-1307, USA.
  20 *
  21 * The full GNU General Public License is included in this distribution
  22 * in the file called "COPYING".
  23 *
  24 */
  25
  26#ifndef __NETXEN_NIC_HW_H_
  27#define __NETXEN_NIC_HW_H_
  28
  29/* Hardware memory size of 128 meg */
  30#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
  31
  32struct netxen_adapter;
  33
  34#define NETXEN_PCI_MAPSIZE_BYTES  (NETXEN_PCI_MAPSIZE << 20)
  35
  36void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
  37
  38/* Nibble or Byte mode for phy interface (GbE mode only) */
  39
  40#define _netxen_crb_get_bit(var, bit)  ((var >> bit) & 0x1)
  41
  42/*
  43 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
  44 *
  45 *      Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
  46 *      Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
  47 *      Bit 2 : enable_rx => 1:enable frame recv, 0:disable
  48 *      Bit 3 : rx_synced => R/O: recv enable synched to recv stream
  49 *      Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
  50 *      Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
  51 *      Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
  52 *      Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
  53 *      Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
  54 *      Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
  55 *      Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
  56 *      Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
  57 */
  58
  59#define netxen_gb_tx_flowctl(config_word)       \
  60        ((config_word) |= 1 << 4)
  61#define netxen_gb_rx_flowctl(config_word)       \
  62        ((config_word) |= 1 << 5)
  63#define netxen_gb_tx_reset_pb(config_word)      \
  64        ((config_word) |= 1 << 16)
  65#define netxen_gb_rx_reset_pb(config_word)      \
  66        ((config_word) |= 1 << 17)
  67#define netxen_gb_tx_reset_mac(config_word)     \
  68        ((config_word) |= 1 << 18)
  69#define netxen_gb_rx_reset_mac(config_word)     \
  70        ((config_word) |= 1 << 19)
  71
  72#define netxen_gb_unset_tx_flowctl(config_word) \
  73        ((config_word) &= ~(1 << 4))
  74#define netxen_gb_unset_rx_flowctl(config_word) \
  75        ((config_word) &= ~(1 << 5))
  76
  77#define netxen_gb_get_tx_synced(config_word)    \
  78                _netxen_crb_get_bit((config_word), 1)
  79#define netxen_gb_get_rx_synced(config_word)    \
  80                _netxen_crb_get_bit((config_word), 3)
  81#define netxen_gb_get_tx_flowctl(config_word)   \
  82                _netxen_crb_get_bit((config_word), 4)
  83#define netxen_gb_get_rx_flowctl(config_word)   \
  84                _netxen_crb_get_bit((config_word), 5)
  85#define netxen_gb_get_soft_reset(config_word)   \
  86                _netxen_crb_get_bit((config_word), 31)
  87
  88#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
  89
  90#define netxen_gb_set_mii_mgmt_clockselect(config_word, val)    \
  91                ((config_word) |= ((val) & 0x07))
  92#define netxen_gb_mii_mgmt_reset(config_word)   \
  93                ((config_word) |= 1 << 31)
  94#define netxen_gb_mii_mgmt_unset(config_word)   \
  95                ((config_word) &= ~(1 << 31))
  96
  97/*
  98 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
  99 * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
 100 * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
 101 */
 102
 103#define netxen_gb_mii_mgmt_set_read_cycle(config_word)  \
 104                ((config_word) |= 1 << 0)
 105#define netxen_gb_mii_mgmt_reg_addr(config_word, val)   \
 106                ((config_word) |= ((val) & 0x1F))
 107#define netxen_gb_mii_mgmt_phy_addr(config_word, val)   \
 108                ((config_word) |= (((val) & 0x1F) << 8))
 109
 110/*
 111 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
 112 * Read-only register.
 113 * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
 114 * Bit 1 : scanning => 1:scan operation in progress, 0:idle
 115 * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
 116 */
 117#define netxen_get_gb_mii_mgmt_busy(config_word)        \
 118                _netxen_crb_get_bit(config_word, 0)
 119#define netxen_get_gb_mii_mgmt_scanning(config_word)    \
 120                _netxen_crb_get_bit(config_word, 1)
 121#define netxen_get_gb_mii_mgmt_notvalid(config_word)    \
 122                _netxen_crb_get_bit(config_word, 2)
 123/*
 124 * NIU XG Pause Ctl Register
 125 *
 126 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 127 *      Bit 1       : xg0_request => 1:request single pause frame
 128 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 129 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 130 *      Bit 4       : xg1_request => 1:request single pause frame
 131 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 132 */
 133
 134#define netxen_xg_set_xg0_mask(config_word)    \
 135        ((config_word) |= 1 << 0)
 136#define netxen_xg_set_xg1_mask(config_word)    \
 137        ((config_word) |= 1 << 3)
 138
 139#define netxen_xg_get_xg0_mask(config_word)    \
 140        _netxen_crb_get_bit((config_word), 0)
 141#define netxen_xg_get_xg1_mask(config_word)    \
 142        _netxen_crb_get_bit((config_word), 3)
 143
 144#define netxen_xg_unset_xg0_mask(config_word)  \
 145        ((config_word) &= ~(1 << 0))
 146#define netxen_xg_unset_xg1_mask(config_word)  \
 147        ((config_word) &= ~(1 << 3))
 148
 149/*
 150 * NIU XG Pause Ctl Register
 151 *
 152 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 153 *      Bit 1       : xg0_request => 1:request single pause frame
 154 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 155 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 156 *      Bit 4       : xg1_request => 1:request single pause frame
 157 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 158 */
 159#define netxen_gb_set_gb0_mask(config_word)    \
 160        ((config_word) |= 1 << 0)
 161#define netxen_gb_set_gb1_mask(config_word)    \
 162        ((config_word) |= 1 << 2)
 163#define netxen_gb_set_gb2_mask(config_word)    \
 164        ((config_word) |= 1 << 4)
 165#define netxen_gb_set_gb3_mask(config_word)    \
 166        ((config_word) |= 1 << 6)
 167
 168#define netxen_gb_get_gb0_mask(config_word)    \
 169        _netxen_crb_get_bit((config_word), 0)
 170#define netxen_gb_get_gb1_mask(config_word)    \
 171        _netxen_crb_get_bit((config_word), 2)
 172#define netxen_gb_get_gb2_mask(config_word)    \
 173        _netxen_crb_get_bit((config_word), 4)
 174#define netxen_gb_get_gb3_mask(config_word)    \
 175        _netxen_crb_get_bit((config_word), 6)
 176
 177#define netxen_gb_unset_gb0_mask(config_word)  \
 178        ((config_word) &= ~(1 << 0))
 179#define netxen_gb_unset_gb1_mask(config_word)  \
 180        ((config_word) &= ~(1 << 2))
 181#define netxen_gb_unset_gb2_mask(config_word)  \
 182        ((config_word) &= ~(1 << 4))
 183#define netxen_gb_unset_gb3_mask(config_word)  \
 184        ((config_word) &= ~(1 << 6))
 185
 186
 187/*
 188 * PHY-Specific MII control/status registers.
 189 */
 190#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL             0
 191#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS              1
 192#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0            2
 193#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1            3
 194#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG             4
 195#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART             5
 196#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE        6
 197#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT       7
 198#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE    8
 199#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL      9
 200#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS       10
 201#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS     15
 202#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL         16
 203#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS          17
 204#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE          18
 205#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS          19
 206#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE    20
 207#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT    21
 208#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL         24
 209#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE        25
 210#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET        26
 211#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE     27
 212
 213/*
 214 * PHY-Specific Status Register (reg 17).
 215 *
 216 * Bit 0      : jabber => 1:jabber detected, 0:not
 217 * Bit 1      : polarity => 1:polarity reversed, 0:normal
 218 * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
 219 * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
 220 * Bit 4      : energydetect => 1:sleep, 0:active
 221 * Bit 5      : downshift => 1:downshift, 0:no downshift
 222 * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
 223 * Bits 7-9   : cablelen => not valid in 10Mb/s mode
 224 *                      0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
 225 * Bit 10     : link => 1:link up, 0:link down
 226 * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
 227 * Bit 12     : pagercvd => 1:page received, 0:page not received
 228 * Bit 13     : duplex => 1:full duplex, 0:half duplex
 229 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
 230 */
 231
 232#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
 233
 234#define netxen_set_phy_speed(config_word, val)  \
 235                ((config_word) |= ((val & 0x03) << 14))
 236#define netxen_set_phy_duplex(config_word)      \
 237                ((config_word) |= 1 << 13)
 238#define netxen_clear_phy_duplex(config_word)    \
 239                ((config_word) &= ~(1 << 13))
 240
 241#define netxen_get_phy_link(config_word)        \
 242                _netxen_crb_get_bit(config_word, 10)
 243#define netxen_get_phy_duplex(config_word)      \
 244                _netxen_crb_get_bit(config_word, 13)
 245
 246/*
 247 * NIU Mode Register.
 248 * Bit 0 : enable FibreChannel
 249 * Bit 1 : enable 10/100/1000 Ethernet
 250 * Bit 2 : enable 10Gb Ethernet
 251 */
 252
 253#define netxen_get_niu_enable_ge(config_word)   \
 254                _netxen_crb_get_bit(config_word, 1)
 255
 256#define NETXEN_NIU_NON_PROMISC_MODE     0
 257#define NETXEN_NIU_PROMISC_MODE         1
 258#define NETXEN_NIU_ALLMULTI_MODE        2
 259
 260/*
 261 * NIU XG MAC Config Register
 262 *
 263 * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
 264 * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
 265 * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
 266 * Bit 27: xaui_framer_reset
 267 * Bit 28: xaui_rx_reset
 268 * Bit 29: xaui_tx_reset
 269 * Bit 30: xg_ingress_afifo_reset
 270 * Bit 31: xg_egress_afifo_reset
 271 */
 272
 273#define netxen_xg_soft_reset(config_word)       \
 274                ((config_word) |= 1 << 4)
 275
 276typedef struct {
 277        unsigned valid;
 278        unsigned start_128M;
 279        unsigned end_128M;
 280        unsigned start_2M;
 281} crb_128M_2M_sub_block_map_t;
 282
 283typedef struct {
 284        crb_128M_2M_sub_block_map_t sub_block[16];
 285} crb_128M_2M_block_map_t;
 286
 287#endif                          /* __NETXEN_NIC_HW_H_ */
 288