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92#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94#define DRV_NAME "8139too"
95#define DRV_VERSION "0.9.28"
96
97
98#include <linux/module.h>
99#include <linux/kernel.h>
100#include <linux/compiler.h>
101#include <linux/pci.h>
102#include <linux/init.h>
103#include <linux/interrupt.h>
104#include <linux/netdevice.h>
105#include <linux/etherdevice.h>
106#include <linux/rtnetlink.h>
107#include <linux/delay.h>
108#include <linux/ethtool.h>
109#include <linux/mii.h>
110#include <linux/completion.h>
111#include <linux/crc32.h>
112#include <linux/io.h>
113#include <linux/uaccess.h>
114#include <linux/gfp.h>
115#include <asm/irq.h>
116
117#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
118
119
120#define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125
126#define RTL8139_DEBUG 0
127
128
129#undef RTL8139_NDEBUG
130
131
132#ifdef RTL8139_NDEBUG
133# define assert(expr) do {} while (0)
134#else
135# define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
139 }
140#endif
141
142
143
144
145#define MAX_UNITS 8
146static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
148
149
150#ifdef CONFIG_8139TOO_PIO
151static bool use_io = true;
152#else
153static bool use_io = false;
154#endif
155
156
157
158static int multicast_filter_limit = 32;
159
160
161static int debug = -1;
162
163
164
165
166
167#if defined(CONFIG_SH_DREAMCAST)
168#define RX_BUF_IDX 0
169#else
170#define RX_BUF_IDX 2
171#endif
172#define RX_BUF_LEN (8192 << RX_BUF_IDX)
173#define RX_BUF_PAD 16
174#define RX_BUF_WRAP_PAD 2048
175
176#if RX_BUF_LEN == 65536
177#define RX_BUF_TOT_LEN RX_BUF_LEN
178#else
179#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
180#endif
181
182
183#define NUM_TX_DESC 4
184
185
186#define MAX_ETH_FRAME_SIZE 1536
187
188
189#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
190#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
191
192
193
194#define TX_FIFO_THRESH 256
195
196
197#define RX_FIFO_THRESH 7
198#define RX_DMA_BURST 7
199#define TX_DMA_BURST 6
200#define TX_RETRY 8
201
202
203
204#define TX_TIMEOUT (6*HZ)
205
206
207enum {
208 HAS_MII_XCVR = 0x010000,
209 HAS_CHIP_XCVR = 0x020000,
210 HAS_LNK_CHNG = 0x040000,
211};
212
213#define RTL_NUM_STATS 4
214#define RTL_REGS_VER 1
215#define RTL_MIN_IO_SIZE 0x80
216#define RTL8139B_IO_SIZE 256
217
218#define RTL8129_CAPS HAS_MII_XCVR
219#define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
220
221typedef enum {
222 RTL8139 = 0,
223 RTL8129,
224} board_t;
225
226
227
228static const struct {
229 const char *name;
230 u32 hw_flags;
231} board_info[] = {
232 { "RealTek RTL8139", RTL8139_CAPS },
233 { "RealTek RTL8129", RTL8129_CAPS },
234};
235
236
237static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257
258#ifdef CONFIG_SH_SECUREEDGE5410
259
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261#endif
262#ifdef CONFIG_8139TOO_8129
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
264#endif
265
266
267
268
269
270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
273
274 {0,}
275};
276MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
277
278static struct {
279 const char str[ETH_GSTRING_LEN];
280} ethtool_stats_keys[] = {
281 { "early_rx" },
282 { "tx_buf_mapped" },
283 { "tx_timeouts" },
284 { "rx_lost_in_ring" },
285};
286
287
288
289
290enum RTL8139_registers {
291 MAC0 = 0,
292 MAR0 = 8,
293 TxStatus0 = 0x10,
294 TxAddr0 = 0x20,
295 RxBuf = 0x30,
296 ChipCmd = 0x37,
297 RxBufPtr = 0x38,
298 RxBufAddr = 0x3A,
299 IntrMask = 0x3C,
300 IntrStatus = 0x3E,
301 TxConfig = 0x40,
302 RxConfig = 0x44,
303 Timer = 0x48,
304 RxMissed = 0x4C,
305 Cfg9346 = 0x50,
306 Config0 = 0x51,
307 Config1 = 0x52,
308 TimerInt = 0x54,
309 MediaStatus = 0x58,
310 Config3 = 0x59,
311 Config4 = 0x5A,
312 HltClk = 0x5B,
313 MultiIntr = 0x5C,
314 TxSummary = 0x60,
315 BasicModeCtrl = 0x62,
316 BasicModeStatus = 0x64,
317 NWayAdvert = 0x66,
318 NWayLPAR = 0x68,
319 NWayExpansion = 0x6A,
320
321 FIFOTMS = 0x70,
322 CSCR = 0x74,
323 PARA78 = 0x78,
324 FlashReg = 0xD4,
325 PARA7c = 0x7c,
326 Config5 = 0xD8,
327};
328
329enum ClearBitMasks {
330 MultiIntrClear = 0xF000,
331 ChipCmdClear = 0xE2,
332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
333};
334
335enum ChipCmdBits {
336 CmdReset = 0x10,
337 CmdRxEnb = 0x08,
338 CmdTxEnb = 0x04,
339 RxBufEmpty = 0x01,
340};
341
342
343enum IntrStatusBits {
344 PCIErr = 0x8000,
345 PCSTimeout = 0x4000,
346 RxFIFOOver = 0x40,
347 RxUnderrun = 0x20,
348 RxOverflow = 0x10,
349 TxErr = 0x08,
350 TxOK = 0x04,
351 RxErr = 0x02,
352 RxOK = 0x01,
353
354 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
355};
356
357enum TxStatusBits {
358 TxHostOwns = 0x2000,
359 TxUnderrun = 0x4000,
360 TxStatOK = 0x8000,
361 TxOutOfWindow = 0x20000000,
362 TxAborted = 0x40000000,
363 TxCarrierLost = 0x80000000,
364};
365enum RxStatusBits {
366 RxMulticast = 0x8000,
367 RxPhysical = 0x4000,
368 RxBroadcast = 0x2000,
369 RxBadSymbol = 0x0020,
370 RxRunt = 0x0010,
371 RxTooLong = 0x0008,
372 RxCRCErr = 0x0004,
373 RxBadAlign = 0x0002,
374 RxStatusOK = 0x0001,
375};
376
377
378enum rx_mode_bits {
379 AcceptErr = 0x20,
380 AcceptRunt = 0x10,
381 AcceptBroadcast = 0x08,
382 AcceptMulticast = 0x04,
383 AcceptMyPhys = 0x02,
384 AcceptAllPhys = 0x01,
385};
386
387
388enum tx_config_bits {
389
390 TxIFGShift = 24,
391 TxIFG84 = (0 << TxIFGShift),
392 TxIFG88 = (1 << TxIFGShift),
393 TxIFG92 = (2 << TxIFGShift),
394 TxIFG96 = (3 << TxIFGShift),
395
396 TxLoopBack = (1 << 18) | (1 << 17),
397 TxCRC = (1 << 16),
398 TxClearAbt = (1 << 0),
399 TxDMAShift = 8,
400 TxRetryShift = 4,
401
402 TxVersionMask = 0x7C800000,
403};
404
405
406enum Config1Bits {
407 Cfg1_PM_Enable = 0x01,
408 Cfg1_VPD_Enable = 0x02,
409 Cfg1_PIO = 0x04,
410 Cfg1_MMIO = 0x08,
411 LWAKE = 0x10,
412 Cfg1_Driver_Load = 0x20,
413 Cfg1_LED0 = 0x40,
414 Cfg1_LED1 = 0x80,
415 SLEEP = (1 << 1),
416 PWRDN = (1 << 0),
417};
418
419
420enum Config3Bits {
421 Cfg3_FBtBEn = (1 << 0),
422 Cfg3_FuncRegEn = (1 << 1),
423 Cfg3_CLKRUN_En = (1 << 2),
424 Cfg3_CardB_En = (1 << 3),
425 Cfg3_LinkUp = (1 << 4),
426 Cfg3_Magic = (1 << 5),
427 Cfg3_PARM_En = (1 << 6),
428 Cfg3_GNTSel = (1 << 7),
429};
430
431
432enum Config4Bits {
433 LWPTN = (1 << 2),
434};
435
436
437enum Config5Bits {
438 Cfg5_PME_STS = (1 << 0),
439 Cfg5_LANWake = (1 << 1),
440 Cfg5_LDPS = (1 << 2),
441 Cfg5_FIFOAddrPtr= (1 << 3),
442 Cfg5_UWF = (1 << 4),
443 Cfg5_MWF = (1 << 5),
444 Cfg5_BWF = (1 << 6),
445};
446
447enum RxConfigBits {
448
449 RxCfgFIFOShift = 13,
450 RxCfgFIFONone = (7 << RxCfgFIFOShift),
451
452
453 RxCfgDMAShift = 8,
454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
455
456
457 RxCfgRcv8K = 0,
458 RxCfgRcv16K = (1 << 11),
459 RxCfgRcv32K = (1 << 12),
460 RxCfgRcv64K = (1 << 11) | (1 << 12),
461
462
463 RxNoWrap = (1 << 7),
464};
465
466
467
468enum CSCRBits {
469 CSCR_LinkOKBit = 0x0400,
470 CSCR_LinkChangeBit = 0x0800,
471 CSCR_LinkStatusBits = 0x0f000,
472 CSCR_LinkDownOffCmd = 0x003c0,
473 CSCR_LinkDownCmd = 0x0f3c0,
474};
475
476enum Cfg9346Bits {
477 Cfg9346_Lock = 0x00,
478 Cfg9346_Unlock = 0xC0,
479};
480
481typedef enum {
482 CH_8139 = 0,
483 CH_8139_K,
484 CH_8139A,
485 CH_8139A_G,
486 CH_8139B,
487 CH_8130,
488 CH_8139C,
489 CH_8100,
490 CH_8100B_8139D,
491 CH_8101,
492} chip_t;
493
494enum chip_flags {
495 HasHltClk = (1 << 0),
496 HasLWake = (1 << 1),
497};
498
499#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
501#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
502
503
504static const struct {
505 const char *name;
506 u32 version;
507 u32 flags;
508} rtl_chip_info[] = {
509 { "RTL-8139",
510 HW_REVID(1, 0, 0, 0, 0, 0, 0),
511 HasHltClk,
512 },
513
514 { "RTL-8139 rev K",
515 HW_REVID(1, 1, 0, 0, 0, 0, 0),
516 HasHltClk,
517 },
518
519 { "RTL-8139A",
520 HW_REVID(1, 1, 1, 0, 0, 0, 0),
521 HasHltClk,
522 },
523
524 { "RTL-8139A rev G",
525 HW_REVID(1, 1, 1, 0, 0, 1, 0),
526 HasHltClk,
527 },
528
529 { "RTL-8139B",
530 HW_REVID(1, 1, 1, 1, 0, 0, 0),
531 HasLWake,
532 },
533
534 { "RTL-8130",
535 HW_REVID(1, 1, 1, 1, 1, 0, 0),
536 HasLWake,
537 },
538
539 { "RTL-8139C",
540 HW_REVID(1, 1, 1, 0, 1, 0, 0),
541 HasLWake,
542 },
543
544 { "RTL-8100",
545 HW_REVID(1, 1, 1, 1, 0, 1, 0),
546 HasLWake,
547 },
548
549 { "RTL-8100B/8139D",
550 HW_REVID(1, 1, 1, 0, 1, 0, 1),
551 HasHltClk
552 | HasLWake,
553 },
554
555 { "RTL-8101",
556 HW_REVID(1, 1, 1, 0, 1, 1, 1),
557 HasLWake,
558 },
559};
560
561struct rtl_extra_stats {
562 unsigned long early_rx;
563 unsigned long tx_buf_mapped;
564 unsigned long tx_timeouts;
565 unsigned long rx_lost_in_ring;
566};
567
568struct rtl8139_stats {
569 u64 packets;
570 u64 bytes;
571 struct u64_stats_sync syncp;
572};
573
574struct rtl8139_private {
575 void __iomem *mmio_addr;
576 int drv_flags;
577 struct pci_dev *pci_dev;
578 u32 msg_enable;
579 struct napi_struct napi;
580 struct net_device *dev;
581
582 unsigned char *rx_ring;
583 unsigned int cur_rx;
584 struct rtl8139_stats rx_stats;
585 dma_addr_t rx_ring_dma;
586
587 unsigned int tx_flag;
588 unsigned long cur_tx;
589 unsigned long dirty_tx;
590 struct rtl8139_stats tx_stats;
591 unsigned char *tx_buf[NUM_TX_DESC];
592 unsigned char *tx_bufs;
593 dma_addr_t tx_bufs_dma;
594
595 signed char phys[4];
596
597
598 char twistie, twist_row, twist_col;
599
600 unsigned int watchdog_fired : 1;
601 unsigned int default_port : 4;
602 unsigned int have_thread : 1;
603
604 spinlock_t lock;
605 spinlock_t rx_lock;
606
607 chip_t chipset;
608 u32 rx_config;
609 struct rtl_extra_stats xstats;
610
611 struct delayed_work thread;
612
613 struct mii_if_info mii;
614 unsigned int regs_len;
615 unsigned long fifo_copy_timeout;
616};
617
618MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
619MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
620MODULE_LICENSE("GPL");
621MODULE_VERSION(DRV_VERSION);
622
623module_param(use_io, bool, 0);
624MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
625module_param(multicast_filter_limit, int, 0);
626module_param_array(media, int, NULL, 0);
627module_param_array(full_duplex, int, NULL, 0);
628module_param(debug, int, 0);
629MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
630MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
631MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
632MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
633
634static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
635static int rtl8139_open (struct net_device *dev);
636static int mdio_read (struct net_device *dev, int phy_id, int location);
637static void mdio_write (struct net_device *dev, int phy_id, int location,
638 int val);
639static void rtl8139_start_thread(struct rtl8139_private *tp);
640static void rtl8139_tx_timeout (struct net_device *dev);
641static void rtl8139_init_ring (struct net_device *dev);
642static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
643 struct net_device *dev);
644#ifdef CONFIG_NET_POLL_CONTROLLER
645static void rtl8139_poll_controller(struct net_device *dev);
646#endif
647static int rtl8139_set_mac_address(struct net_device *dev, void *p);
648static int rtl8139_poll(struct napi_struct *napi, int budget);
649static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
650static int rtl8139_close (struct net_device *dev);
651static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
652static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
653 struct rtnl_link_stats64
654 *stats);
655static void rtl8139_set_rx_mode (struct net_device *dev);
656static void __set_rx_mode (struct net_device *dev);
657static void rtl8139_hw_start (struct net_device *dev);
658static void rtl8139_thread (struct work_struct *work);
659static void rtl8139_tx_timeout_task(struct work_struct *work);
660static const struct ethtool_ops rtl8139_ethtool_ops;
661
662
663
664#define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
665#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
666#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
667
668
669#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
670#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
671#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
672
673
674#define RTL_R8(reg) ioread8 (ioaddr + (reg))
675#define RTL_R16(reg) ioread16 (ioaddr + (reg))
676#define RTL_R32(reg) ioread32 (ioaddr + (reg))
677
678
679static const u16 rtl8139_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
681 TxErr | TxOK | RxErr | RxOK;
682
683static const u16 rtl8139_norx_intr_mask =
684 PCIErr | PCSTimeout | RxUnderrun |
685 TxErr | TxOK | RxErr ;
686
687#if RX_BUF_IDX == 0
688static const unsigned int rtl8139_rx_config =
689 RxCfgRcv8K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692#elif RX_BUF_IDX == 1
693static const unsigned int rtl8139_rx_config =
694 RxCfgRcv16K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697#elif RX_BUF_IDX == 2
698static const unsigned int rtl8139_rx_config =
699 RxCfgRcv32K | RxNoWrap |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702#elif RX_BUF_IDX == 3
703static const unsigned int rtl8139_rx_config =
704 RxCfgRcv64K |
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
707#else
708#error "Invalid configuration for 8139_RXBUF_IDX"
709#endif
710
711static const unsigned int rtl8139_tx_config =
712 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
713
714static void __rtl8139_cleanup_dev (struct net_device *dev)
715{
716 struct rtl8139_private *tp = netdev_priv(dev);
717 struct pci_dev *pdev;
718
719 assert (dev != NULL);
720 assert (tp->pci_dev != NULL);
721 pdev = tp->pci_dev;
722
723 if (tp->mmio_addr)
724 pci_iounmap (pdev, tp->mmio_addr);
725
726
727 pci_release_regions (pdev);
728
729 free_netdev(dev);
730 pci_set_drvdata (pdev, NULL);
731}
732
733
734static void rtl8139_chip_reset (void __iomem *ioaddr)
735{
736 int i;
737
738
739 RTL_W8 (ChipCmd, CmdReset);
740
741
742 for (i = 1000; i > 0; i--) {
743 barrier();
744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
745 break;
746 udelay (10);
747 }
748}
749
750
751static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
752{
753 struct device *d = &pdev->dev;
754 void __iomem *ioaddr;
755 struct net_device *dev;
756 struct rtl8139_private *tp;
757 u8 tmp8;
758 int rc, disable_dev_on_err = 0;
759 unsigned int i, bar;
760 unsigned long io_len;
761 u32 version;
762 static const struct {
763 unsigned long mask;
764 char *type;
765 } res[] = {
766 { IORESOURCE_IO, "PIO" },
767 { IORESOURCE_MEM, "MMIO" }
768 };
769
770 assert (pdev != NULL);
771
772
773 dev = alloc_etherdev (sizeof (*tp));
774 if (dev == NULL)
775 return ERR_PTR(-ENOMEM);
776
777 SET_NETDEV_DEV(dev, &pdev->dev);
778
779 tp = netdev_priv(dev);
780 tp->pci_dev = pdev;
781
782
783 rc = pci_enable_device (pdev);
784 if (rc)
785 goto err_out;
786
787 rc = pci_request_regions (pdev, DRV_NAME);
788 if (rc)
789 goto err_out;
790 disable_dev_on_err = 1;
791
792 pci_set_master (pdev);
793
794retry:
795
796 bar = !use_io;
797
798 io_len = pci_resource_len(pdev, bar);
799
800 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
801
802 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
803 dev_err(d, "region #%d not a %s resource, aborting\n", bar,
804 res[bar].type);
805 rc = -ENODEV;
806 goto err_out;
807 }
808 if (io_len < RTL_MIN_IO_SIZE) {
809 dev_err(d, "Invalid PCI %s region size(s), aborting\n",
810 res[bar].type);
811 rc = -ENODEV;
812 goto err_out;
813 }
814
815 ioaddr = pci_iomap(pdev, bar, 0);
816 if (!ioaddr) {
817 dev_err(d, "cannot map %s\n", res[bar].type);
818 if (!use_io) {
819 use_io = true;
820 goto retry;
821 }
822 rc = -ENODEV;
823 goto err_out;
824 }
825 tp->regs_len = io_len;
826 tp->mmio_addr = ioaddr;
827
828
829 RTL_W8 (HltClk, 'R');
830
831
832 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
833 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
834 rc = -EIO;
835 goto err_out;
836 }
837
838
839 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
840 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
841 if (version == rtl_chip_info[i].version) {
842 tp->chipset = i;
843 goto match;
844 }
845
846
847 i = 0;
848 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
849 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
850 tp->chipset = 0;
851
852match:
853 pr_debug("chipset id (%d) == index %d, '%s'\n",
854 version, i, rtl_chip_info[i].name);
855
856 if (tp->chipset >= CH_8139B) {
857 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
858 pr_debug("PCI PM wakeup\n");
859 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
860 (tmp8 & LWAKE))
861 new_tmp8 &= ~LWAKE;
862 new_tmp8 |= Cfg1_PM_Enable;
863 if (new_tmp8 != tmp8) {
864 RTL_W8 (Cfg9346, Cfg9346_Unlock);
865 RTL_W8 (Config1, tmp8);
866 RTL_W8 (Cfg9346, Cfg9346_Lock);
867 }
868 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
869 tmp8 = RTL_R8 (Config4);
870 if (tmp8 & LWPTN) {
871 RTL_W8 (Cfg9346, Cfg9346_Unlock);
872 RTL_W8 (Config4, tmp8 & ~LWPTN);
873 RTL_W8 (Cfg9346, Cfg9346_Lock);
874 }
875 }
876 } else {
877 pr_debug("Old chip wakeup\n");
878 tmp8 = RTL_R8 (Config1);
879 tmp8 &= ~(SLEEP | PWRDN);
880 RTL_W8 (Config1, tmp8);
881 }
882
883 rtl8139_chip_reset (ioaddr);
884
885 return dev;
886
887err_out:
888 __rtl8139_cleanup_dev (dev);
889 if (disable_dev_on_err)
890 pci_disable_device (pdev);
891 return ERR_PTR(rc);
892}
893
894static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
895{
896 struct rtl8139_private *tp = netdev_priv(dev);
897 unsigned long flags;
898 netdev_features_t changed = features ^ dev->features;
899 void __iomem *ioaddr = tp->mmio_addr;
900
901 if (!(changed & (NETIF_F_RXALL)))
902 return 0;
903
904 spin_lock_irqsave(&tp->lock, flags);
905
906 if (changed & NETIF_F_RXALL) {
907 int rx_mode = tp->rx_config;
908 if (features & NETIF_F_RXALL)
909 rx_mode |= (AcceptErr | AcceptRunt);
910 else
911 rx_mode &= ~(AcceptErr | AcceptRunt);
912 tp->rx_config = rtl8139_rx_config | rx_mode;
913 RTL_W32_F(RxConfig, tp->rx_config);
914 }
915
916 spin_unlock_irqrestore(&tp->lock, flags);
917
918 return 0;
919}
920
921static const struct net_device_ops rtl8139_netdev_ops = {
922 .ndo_open = rtl8139_open,
923 .ndo_stop = rtl8139_close,
924 .ndo_get_stats64 = rtl8139_get_stats64,
925 .ndo_change_mtu = eth_change_mtu,
926 .ndo_validate_addr = eth_validate_addr,
927 .ndo_set_mac_address = rtl8139_set_mac_address,
928 .ndo_start_xmit = rtl8139_start_xmit,
929 .ndo_set_rx_mode = rtl8139_set_rx_mode,
930 .ndo_do_ioctl = netdev_ioctl,
931 .ndo_tx_timeout = rtl8139_tx_timeout,
932#ifdef CONFIG_NET_POLL_CONTROLLER
933 .ndo_poll_controller = rtl8139_poll_controller,
934#endif
935 .ndo_set_features = rtl8139_set_features,
936};
937
938static int rtl8139_init_one(struct pci_dev *pdev,
939 const struct pci_device_id *ent)
940{
941 struct net_device *dev = NULL;
942 struct rtl8139_private *tp;
943 int i, addr_len, option;
944 void __iomem *ioaddr;
945 static int board_idx = -1;
946
947 assert (pdev != NULL);
948 assert (ent != NULL);
949
950 board_idx++;
951
952
953
954
955#ifndef MODULE
956 {
957 static int printed_version;
958 if (!printed_version++)
959 pr_info(RTL8139_DRIVER_NAME "\n");
960 }
961#endif
962
963 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
964 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
965 dev_info(&pdev->dev,
966 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
967 pdev->vendor, pdev->device, pdev->revision);
968 return -ENODEV;
969 }
970
971 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
972 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
973 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
974 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
975 pr_info("OQO Model 2 detected. Forcing PIO\n");
976 use_io = 1;
977 }
978
979 dev = rtl8139_init_board (pdev);
980 if (IS_ERR(dev))
981 return PTR_ERR(dev);
982
983 assert (dev != NULL);
984 tp = netdev_priv(dev);
985 tp->dev = dev;
986
987 ioaddr = tp->mmio_addr;
988 assert (ioaddr != NULL);
989
990 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
991 for (i = 0; i < 3; i++)
992 ((__le16 *) (dev->dev_addr))[i] =
993 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
994
995
996 dev->netdev_ops = &rtl8139_netdev_ops;
997 dev->ethtool_ops = &rtl8139_ethtool_ops;
998 dev->watchdog_timeo = TX_TIMEOUT;
999 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1000
1001
1002
1003
1004
1005 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1006 dev->vlan_features = dev->features;
1007
1008 dev->hw_features |= NETIF_F_RXALL;
1009 dev->hw_features |= NETIF_F_RXFCS;
1010
1011
1012 tp = netdev_priv(dev);
1013
1014
1015 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1016 tp->mmio_addr = ioaddr;
1017 tp->msg_enable =
1018 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1019 spin_lock_init (&tp->lock);
1020 spin_lock_init (&tp->rx_lock);
1021 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1022 tp->mii.dev = dev;
1023 tp->mii.mdio_read = mdio_read;
1024 tp->mii.mdio_write = mdio_write;
1025 tp->mii.phy_id_mask = 0x3f;
1026 tp->mii.reg_num_mask = 0x1f;
1027
1028
1029 pr_debug("about to register device named %s (%p)...\n",
1030 dev->name, dev);
1031 i = register_netdev (dev);
1032 if (i) goto err_out;
1033
1034 pci_set_drvdata (pdev, dev);
1035
1036 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1037 board_info[ent->driver_data].name,
1038 ioaddr, dev->dev_addr, pdev->irq);
1039
1040 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1041 rtl_chip_info[tp->chipset].name);
1042
1043
1044
1045
1046#ifdef CONFIG_8139TOO_8129
1047 if (tp->drv_flags & HAS_MII_XCVR) {
1048 int phy, phy_idx = 0;
1049 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1050 int mii_status = mdio_read(dev, phy, 1);
1051 if (mii_status != 0xffff && mii_status != 0x0000) {
1052 u16 advertising = mdio_read(dev, phy, 4);
1053 tp->phys[phy_idx++] = phy;
1054 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1055 phy, mii_status, advertising);
1056 }
1057 }
1058 if (phy_idx == 0) {
1059 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1060 tp->phys[0] = 32;
1061 }
1062 } else
1063#endif
1064 tp->phys[0] = 32;
1065 tp->mii.phy_id = tp->phys[0];
1066
1067
1068 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1069 if (option > 0) {
1070 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1071 tp->default_port = option & 0xFF;
1072 if (tp->default_port)
1073 tp->mii.force_media = 1;
1074 }
1075 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1076 tp->mii.full_duplex = full_duplex[board_idx];
1077 if (tp->mii.full_duplex) {
1078 netdev_info(dev, "Media type forced to Full Duplex\n");
1079
1080
1081 tp->mii.force_media = 1;
1082 }
1083 if (tp->default_port) {
1084 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1085 (option & 0x20 ? 100 : 10),
1086 (option & 0x10 ? "full" : "half"));
1087 mdio_write(dev, tp->phys[0], 0,
1088 ((option & 0x20) ? 0x2000 : 0) |
1089 ((option & 0x10) ? 0x0100 : 0));
1090 }
1091
1092
1093 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1094 RTL_W8 (HltClk, 'H');
1095
1096 return 0;
1097
1098err_out:
1099 __rtl8139_cleanup_dev (dev);
1100 pci_disable_device (pdev);
1101 return i;
1102}
1103
1104
1105static void rtl8139_remove_one(struct pci_dev *pdev)
1106{
1107 struct net_device *dev = pci_get_drvdata (pdev);
1108 struct rtl8139_private *tp = netdev_priv(dev);
1109
1110 assert (dev != NULL);
1111
1112 cancel_delayed_work_sync(&tp->thread);
1113
1114 unregister_netdev (dev);
1115
1116 __rtl8139_cleanup_dev (dev);
1117 pci_disable_device (pdev);
1118}
1119
1120
1121
1122
1123
1124#define EE_SHIFT_CLK 0x04
1125#define EE_CS 0x08
1126#define EE_DATA_WRITE 0x02
1127#define EE_WRITE_0 0x00
1128#define EE_WRITE_1 0x02
1129#define EE_DATA_READ 0x01
1130#define EE_ENB (0x80 | EE_CS)
1131
1132
1133
1134
1135
1136#define eeprom_delay() (void)RTL_R8(Cfg9346)
1137
1138
1139#define EE_WRITE_CMD (5)
1140#define EE_READ_CMD (6)
1141#define EE_ERASE_CMD (7)
1142
1143static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
1144{
1145 int i;
1146 unsigned retval = 0;
1147 int read_cmd = location | (EE_READ_CMD << addr_len);
1148
1149 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1150 RTL_W8 (Cfg9346, EE_ENB);
1151 eeprom_delay ();
1152
1153
1154 for (i = 4 + addr_len; i >= 0; i--) {
1155 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1156 RTL_W8 (Cfg9346, EE_ENB | dataval);
1157 eeprom_delay ();
1158 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1159 eeprom_delay ();
1160 }
1161 RTL_W8 (Cfg9346, EE_ENB);
1162 eeprom_delay ();
1163
1164 for (i = 16; i > 0; i--) {
1165 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1166 eeprom_delay ();
1167 retval =
1168 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1169 0);
1170 RTL_W8 (Cfg9346, EE_ENB);
1171 eeprom_delay ();
1172 }
1173
1174
1175 RTL_W8(Cfg9346, 0);
1176 eeprom_delay ();
1177
1178 return retval;
1179}
1180
1181
1182
1183
1184
1185
1186
1187#define MDIO_DIR 0x80
1188#define MDIO_DATA_OUT 0x04
1189#define MDIO_DATA_IN 0x02
1190#define MDIO_CLK 0x01
1191#define MDIO_WRITE0 (MDIO_DIR)
1192#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1193
1194#define mdio_delay() RTL_R8(Config4)
1195
1196
1197static const char mii_2_8139_map[8] = {
1198 BasicModeCtrl,
1199 BasicModeStatus,
1200 0,
1201 0,
1202 NWayAdvert,
1203 NWayLPAR,
1204 NWayExpansion,
1205 0
1206};
1207
1208
1209#ifdef CONFIG_8139TOO_8129
1210
1211static void mdio_sync (void __iomem *ioaddr)
1212{
1213 int i;
1214
1215 for (i = 32; i >= 0; i--) {
1216 RTL_W8 (Config4, MDIO_WRITE1);
1217 mdio_delay ();
1218 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1219 mdio_delay ();
1220 }
1221}
1222#endif
1223
1224static int mdio_read (struct net_device *dev, int phy_id, int location)
1225{
1226 struct rtl8139_private *tp = netdev_priv(dev);
1227 int retval = 0;
1228#ifdef CONFIG_8139TOO_8129
1229 void __iomem *ioaddr = tp->mmio_addr;
1230 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1231 int i;
1232#endif
1233
1234 if (phy_id > 31) {
1235 void __iomem *ioaddr = tp->mmio_addr;
1236 return location < 8 && mii_2_8139_map[location] ?
1237 RTL_R16 (mii_2_8139_map[location]) : 0;
1238 }
1239
1240#ifdef CONFIG_8139TOO_8129
1241 mdio_sync (ioaddr);
1242
1243 for (i = 15; i >= 0; i--) {
1244 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1245
1246 RTL_W8 (Config4, MDIO_DIR | dataval);
1247 mdio_delay ();
1248 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1249 mdio_delay ();
1250 }
1251
1252
1253 for (i = 19; i > 0; i--) {
1254 RTL_W8 (Config4, 0);
1255 mdio_delay ();
1256 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1257 RTL_W8 (Config4, MDIO_CLK);
1258 mdio_delay ();
1259 }
1260#endif
1261
1262 return (retval >> 1) & 0xffff;
1263}
1264
1265
1266static void mdio_write (struct net_device *dev, int phy_id, int location,
1267 int value)
1268{
1269 struct rtl8139_private *tp = netdev_priv(dev);
1270#ifdef CONFIG_8139TOO_8129
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1273 int i;
1274#endif
1275
1276 if (phy_id > 31) {
1277 void __iomem *ioaddr = tp->mmio_addr;
1278 if (location == 0) {
1279 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1280 RTL_W16 (BasicModeCtrl, value);
1281 RTL_W8 (Cfg9346, Cfg9346_Lock);
1282 } else if (location < 8 && mii_2_8139_map[location])
1283 RTL_W16 (mii_2_8139_map[location], value);
1284 return;
1285 }
1286
1287#ifdef CONFIG_8139TOO_8129
1288 mdio_sync (ioaddr);
1289
1290
1291 for (i = 31; i >= 0; i--) {
1292 int dataval =
1293 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1294 RTL_W8 (Config4, dataval);
1295 mdio_delay ();
1296 RTL_W8 (Config4, dataval | MDIO_CLK);
1297 mdio_delay ();
1298 }
1299
1300 for (i = 2; i > 0; i--) {
1301 RTL_W8 (Config4, 0);
1302 mdio_delay ();
1303 RTL_W8 (Config4, MDIO_CLK);
1304 mdio_delay ();
1305 }
1306#endif
1307}
1308
1309
1310static int rtl8139_open (struct net_device *dev)
1311{
1312 struct rtl8139_private *tp = netdev_priv(dev);
1313 void __iomem *ioaddr = tp->mmio_addr;
1314 const int irq = tp->pci_dev->irq;
1315 int retval;
1316
1317 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1318 if (retval)
1319 return retval;
1320
1321 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1322 &tp->tx_bufs_dma, GFP_KERNEL);
1323 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1324 &tp->rx_ring_dma, GFP_KERNEL);
1325 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1326 free_irq(irq, dev);
1327
1328 if (tp->tx_bufs)
1329 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1330 tp->tx_bufs, tp->tx_bufs_dma);
1331 if (tp->rx_ring)
1332 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1333 tp->rx_ring, tp->rx_ring_dma);
1334
1335 return -ENOMEM;
1336
1337 }
1338
1339 napi_enable(&tp->napi);
1340
1341 tp->mii.full_duplex = tp->mii.force_media;
1342 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1343
1344 rtl8139_init_ring (dev);
1345 rtl8139_hw_start (dev);
1346 netif_start_queue (dev);
1347
1348 netif_dbg(tp, ifup, dev,
1349 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1350 __func__,
1351 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1352 irq, RTL_R8 (MediaStatus),
1353 tp->mii.full_duplex ? "full" : "half");
1354
1355 rtl8139_start_thread(tp);
1356
1357 return 0;
1358}
1359
1360
1361static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1362{
1363 struct rtl8139_private *tp = netdev_priv(dev);
1364
1365 if (tp->phys[0] >= 0) {
1366 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1367 }
1368}
1369
1370
1371static void rtl8139_hw_start (struct net_device *dev)
1372{
1373 struct rtl8139_private *tp = netdev_priv(dev);
1374 void __iomem *ioaddr = tp->mmio_addr;
1375 u32 i;
1376 u8 tmp;
1377
1378
1379 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1380 RTL_W8 (HltClk, 'R');
1381
1382 rtl8139_chip_reset (ioaddr);
1383
1384
1385 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1386
1387 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1388 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1389
1390 tp->cur_rx = 0;
1391
1392
1393 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1394
1395
1396 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1397
1398 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1399 RTL_W32 (RxConfig, tp->rx_config);
1400 RTL_W32 (TxConfig, rtl8139_tx_config);
1401
1402 rtl_check_media (dev, 1);
1403
1404 if (tp->chipset >= CH_8139B) {
1405
1406
1407
1408 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1409 }
1410
1411 netdev_dbg(dev, "init buffer addresses\n");
1412
1413
1414 RTL_W8 (Cfg9346, Cfg9346_Lock);
1415
1416
1417 for (i = 0; i < NUM_TX_DESC; i++)
1418 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1419
1420 RTL_W32 (RxMissed, 0);
1421
1422 rtl8139_set_rx_mode (dev);
1423
1424
1425 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1426
1427
1428 tmp = RTL_R8 (ChipCmd);
1429 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1430 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1431
1432
1433 RTL_W16 (IntrMask, rtl8139_intr_mask);
1434}
1435
1436
1437
1438static void rtl8139_init_ring (struct net_device *dev)
1439{
1440 struct rtl8139_private *tp = netdev_priv(dev);
1441 int i;
1442
1443 tp->cur_rx = 0;
1444 tp->cur_tx = 0;
1445 tp->dirty_tx = 0;
1446
1447 for (i = 0; i < NUM_TX_DESC; i++)
1448 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1449}
1450
1451
1452
1453static int next_tick = 3 * HZ;
1454
1455#ifndef CONFIG_8139TOO_TUNE_TWISTER
1456static inline void rtl8139_tune_twister (struct net_device *dev,
1457 struct rtl8139_private *tp) {}
1458#else
1459enum TwisterParamVals {
1460 PARA78_default = 0x78fa8388,
1461 PARA7c_default = 0xcb38de43,
1462 PARA7c_xxx = 0xcb38de43,
1463};
1464
1465static const unsigned long param[4][4] = {
1466 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1467 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1468 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1469 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1470};
1471
1472static void rtl8139_tune_twister (struct net_device *dev,
1473 struct rtl8139_private *tp)
1474{
1475 int linkcase;
1476 void __iomem *ioaddr = tp->mmio_addr;
1477
1478
1479
1480
1481
1482 switch (tp->twistie) {
1483 case 1:
1484 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1485
1486 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1487 tp->twistie = 2;
1488 next_tick = HZ / 10;
1489 } else {
1490
1491 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1492 RTL_W32 (FIFOTMS, 0x20);
1493 RTL_W32 (PARA78, PARA78_default);
1494 RTL_W32 (PARA7c, PARA7c_default);
1495 tp->twistie = 0;
1496 }
1497 break;
1498 case 2:
1499
1500 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1501 if (linkcase == 0x7000)
1502 tp->twist_row = 3;
1503 else if (linkcase == 0x3000)
1504 tp->twist_row = 2;
1505 else if (linkcase == 0x1000)
1506 tp->twist_row = 1;
1507 else
1508 tp->twist_row = 0;
1509 tp->twist_col = 0;
1510 tp->twistie = 3;
1511 next_tick = HZ / 10;
1512 break;
1513 case 3:
1514
1515 if (tp->twist_col == 0)
1516 RTL_W16 (FIFOTMS, 0);
1517 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1518 [(int) tp->twist_col]);
1519 next_tick = HZ / 10;
1520 if (++tp->twist_col >= 4) {
1521
1522
1523 tp->twistie =
1524 (tp->twist_row == 3) ? 4 : 0;
1525 }
1526 break;
1527 case 4:
1528
1529 if ((RTL_R16 (CSCR) &
1530 CSCR_LinkStatusBits) == 0x7000) {
1531 tp->twistie = 0;
1532 break;
1533 } else {
1534 RTL_W32 (PARA7c, 0xfb38de03);
1535 tp->twistie = 5;
1536 next_tick = HZ / 10;
1537 }
1538 break;
1539 case 5:
1540
1541 RTL_W32 (FIFOTMS, 0x20);
1542 RTL_W32 (PARA78, PARA78_default);
1543 RTL_W32 (PARA7c, PARA7c_default);
1544 RTL_W32 (FIFOTMS, 0x00);
1545 tp->twist_row = 2;
1546 tp->twist_col = 0;
1547 tp->twistie = 3;
1548 next_tick = HZ / 10;
1549 break;
1550
1551 default:
1552
1553 break;
1554 }
1555}
1556#endif
1557
1558static inline void rtl8139_thread_iter (struct net_device *dev,
1559 struct rtl8139_private *tp,
1560 void __iomem *ioaddr)
1561{
1562 int mii_lpa;
1563
1564 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1565
1566 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1567 int duplex = ((mii_lpa & LPA_100FULL) ||
1568 (mii_lpa & 0x01C0) == 0x0040);
1569 if (tp->mii.full_duplex != duplex) {
1570 tp->mii.full_duplex = duplex;
1571
1572 if (mii_lpa) {
1573 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1574 tp->mii.full_duplex ? "full" : "half",
1575 tp->phys[0], mii_lpa);
1576 } else {
1577 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1578 }
1579#if 0
1580 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1581 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1582 RTL_W8 (Cfg9346, Cfg9346_Lock);
1583#endif
1584 }
1585 }
1586
1587 next_tick = HZ * 60;
1588
1589 rtl8139_tune_twister (dev, tp);
1590
1591 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1592 RTL_R16(NWayLPAR));
1593 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1594 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1595 netdev_dbg(dev, "Chip config %02x %02x\n",
1596 RTL_R8(Config0), RTL_R8(Config1));
1597}
1598
1599static void rtl8139_thread (struct work_struct *work)
1600{
1601 struct rtl8139_private *tp =
1602 container_of(work, struct rtl8139_private, thread.work);
1603 struct net_device *dev = tp->mii.dev;
1604 unsigned long thr_delay = next_tick;
1605
1606 rtnl_lock();
1607
1608 if (!netif_running(dev))
1609 goto out_unlock;
1610
1611 if (tp->watchdog_fired) {
1612 tp->watchdog_fired = 0;
1613 rtl8139_tx_timeout_task(work);
1614 } else
1615 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1616
1617 if (tp->have_thread)
1618 schedule_delayed_work(&tp->thread, thr_delay);
1619out_unlock:
1620 rtnl_unlock ();
1621}
1622
1623static void rtl8139_start_thread(struct rtl8139_private *tp)
1624{
1625 tp->twistie = 0;
1626 if (tp->chipset == CH_8139_K)
1627 tp->twistie = 1;
1628 else if (tp->drv_flags & HAS_LNK_CHNG)
1629 return;
1630
1631 tp->have_thread = 1;
1632 tp->watchdog_fired = 0;
1633
1634 schedule_delayed_work(&tp->thread, next_tick);
1635}
1636
1637static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1638{
1639 tp->cur_tx = 0;
1640 tp->dirty_tx = 0;
1641
1642
1643}
1644
1645static void rtl8139_tx_timeout_task (struct work_struct *work)
1646{
1647 struct rtl8139_private *tp =
1648 container_of(work, struct rtl8139_private, thread.work);
1649 struct net_device *dev = tp->mii.dev;
1650 void __iomem *ioaddr = tp->mmio_addr;
1651 int i;
1652 u8 tmp8;
1653
1654 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1655 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1656 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1657
1658 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1659 tp->cur_tx, tp->dirty_tx);
1660 for (i = 0; i < NUM_TX_DESC; i++)
1661 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1662 i, RTL_R32(TxStatus0 + (i * 4)),
1663 i == tp->dirty_tx % NUM_TX_DESC ?
1664 " (queue head)" : "");
1665
1666 tp->xstats.tx_timeouts++;
1667
1668
1669 tmp8 = RTL_R8 (ChipCmd);
1670 if (tmp8 & CmdTxEnb)
1671 RTL_W8 (ChipCmd, CmdRxEnb);
1672
1673 spin_lock_bh(&tp->rx_lock);
1674
1675 RTL_W16 (IntrMask, 0x0000);
1676
1677
1678 spin_lock_irq(&tp->lock);
1679 rtl8139_tx_clear (tp);
1680 spin_unlock_irq(&tp->lock);
1681
1682
1683 if (netif_running(dev)) {
1684 rtl8139_hw_start (dev);
1685 netif_wake_queue (dev);
1686 }
1687 spin_unlock_bh(&tp->rx_lock);
1688}
1689
1690static void rtl8139_tx_timeout (struct net_device *dev)
1691{
1692 struct rtl8139_private *tp = netdev_priv(dev);
1693
1694 tp->watchdog_fired = 1;
1695 if (!tp->have_thread) {
1696 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1697 schedule_delayed_work(&tp->thread, next_tick);
1698 }
1699}
1700
1701static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1702 struct net_device *dev)
1703{
1704 struct rtl8139_private *tp = netdev_priv(dev);
1705 void __iomem *ioaddr = tp->mmio_addr;
1706 unsigned int entry;
1707 unsigned int len = skb->len;
1708 unsigned long flags;
1709
1710
1711 entry = tp->cur_tx % NUM_TX_DESC;
1712
1713
1714 if (likely(len < TX_BUF_SIZE)) {
1715 if (len < ETH_ZLEN)
1716 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1717 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1718 dev_kfree_skb(skb);
1719 } else {
1720 dev_kfree_skb(skb);
1721 dev->stats.tx_dropped++;
1722 return NETDEV_TX_OK;
1723 }
1724
1725 spin_lock_irqsave(&tp->lock, flags);
1726
1727
1728
1729
1730
1731 wmb();
1732 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1733 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1734
1735 tp->cur_tx++;
1736
1737 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1738 netif_stop_queue (dev);
1739 spin_unlock_irqrestore(&tp->lock, flags);
1740
1741 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1742 len, entry);
1743
1744 return NETDEV_TX_OK;
1745}
1746
1747
1748static void rtl8139_tx_interrupt (struct net_device *dev,
1749 struct rtl8139_private *tp,
1750 void __iomem *ioaddr)
1751{
1752 unsigned long dirty_tx, tx_left;
1753
1754 assert (dev != NULL);
1755 assert (ioaddr != NULL);
1756
1757 dirty_tx = tp->dirty_tx;
1758 tx_left = tp->cur_tx - dirty_tx;
1759 while (tx_left > 0) {
1760 int entry = dirty_tx % NUM_TX_DESC;
1761 int txstatus;
1762
1763 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1764
1765 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1766 break;
1767
1768
1769 if (txstatus & (TxOutOfWindow | TxAborted)) {
1770
1771 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1772 txstatus);
1773 dev->stats.tx_errors++;
1774 if (txstatus & TxAborted) {
1775 dev->stats.tx_aborted_errors++;
1776 RTL_W32 (TxConfig, TxClearAbt);
1777 RTL_W16 (IntrStatus, TxErr);
1778 wmb();
1779 }
1780 if (txstatus & TxCarrierLost)
1781 dev->stats.tx_carrier_errors++;
1782 if (txstatus & TxOutOfWindow)
1783 dev->stats.tx_window_errors++;
1784 } else {
1785 if (txstatus & TxUnderrun) {
1786
1787 if (tp->tx_flag < 0x00300000)
1788 tp->tx_flag += 0x00020000;
1789 dev->stats.tx_fifo_errors++;
1790 }
1791 dev->stats.collisions += (txstatus >> 24) & 15;
1792 u64_stats_update_begin(&tp->tx_stats.syncp);
1793 tp->tx_stats.packets++;
1794 tp->tx_stats.bytes += txstatus & 0x7ff;
1795 u64_stats_update_end(&tp->tx_stats.syncp);
1796 }
1797
1798 dirty_tx++;
1799 tx_left--;
1800 }
1801
1802#ifndef RTL8139_NDEBUG
1803 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1804 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1805 dirty_tx, tp->cur_tx);
1806 dirty_tx += NUM_TX_DESC;
1807 }
1808#endif
1809
1810
1811 if (tp->dirty_tx != dirty_tx) {
1812 tp->dirty_tx = dirty_tx;
1813 mb();
1814 netif_wake_queue (dev);
1815 }
1816}
1817
1818
1819
1820static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1821 struct rtl8139_private *tp, void __iomem *ioaddr)
1822{
1823 u8 tmp8;
1824#ifdef CONFIG_8139_OLD_RX_RESET
1825 int tmp_work;
1826#endif
1827
1828 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1829 rx_status);
1830 dev->stats.rx_errors++;
1831 if (!(rx_status & RxStatusOK)) {
1832 if (rx_status & RxTooLong) {
1833 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1834 rx_status);
1835
1836 }
1837 if (rx_status & (RxBadSymbol | RxBadAlign))
1838 dev->stats.rx_frame_errors++;
1839 if (rx_status & (RxRunt | RxTooLong))
1840 dev->stats.rx_length_errors++;
1841 if (rx_status & RxCRCErr)
1842 dev->stats.rx_crc_errors++;
1843 } else {
1844 tp->xstats.rx_lost_in_ring++;
1845 }
1846
1847#ifndef CONFIG_8139_OLD_RX_RESET
1848 tmp8 = RTL_R8 (ChipCmd);
1849 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1850 RTL_W8 (ChipCmd, tmp8);
1851 RTL_W32 (RxConfig, tp->rx_config);
1852 tp->cur_rx = 0;
1853#else
1854
1855
1856
1857 RTL_W8_F (ChipCmd, CmdTxEnb);
1858 tmp_work = 200;
1859 while (--tmp_work > 0) {
1860 udelay(1);
1861 tmp8 = RTL_R8 (ChipCmd);
1862 if (!(tmp8 & CmdRxEnb))
1863 break;
1864 }
1865 if (tmp_work <= 0)
1866 netdev_warn(dev, "rx stop wait too long\n");
1867
1868 tmp_work = 200;
1869 while (--tmp_work > 0) {
1870 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1871 udelay(1);
1872 tmp8 = RTL_R8 (ChipCmd);
1873 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1874 break;
1875 }
1876 if (tmp_work <= 0)
1877 netdev_warn(dev, "tx/rx enable wait too long\n");
1878
1879
1880 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1881
1882 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1883
1884 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1885 RTL_W32 (RxConfig, tp->rx_config);
1886 tp->cur_rx = 0;
1887
1888 netdev_dbg(dev, "init buffer addresses\n");
1889
1890
1891 RTL_W8 (Cfg9346, Cfg9346_Lock);
1892
1893
1894 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1895
1896
1897 __set_rx_mode (dev);
1898#endif
1899}
1900
1901#if RX_BUF_IDX == 3
1902static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1903 u32 offset, unsigned int size)
1904{
1905 u32 left = RX_BUF_LEN - offset;
1906
1907 if (size > left) {
1908 skb_copy_to_linear_data(skb, ring + offset, left);
1909 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1910 } else
1911 skb_copy_to_linear_data(skb, ring + offset, size);
1912}
1913#endif
1914
1915static void rtl8139_isr_ack(struct rtl8139_private *tp)
1916{
1917 void __iomem *ioaddr = tp->mmio_addr;
1918 u16 status;
1919
1920 status = RTL_R16 (IntrStatus) & RxAckBits;
1921
1922
1923 if (likely(status != 0)) {
1924 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1925 tp->dev->stats.rx_errors++;
1926 if (status & RxFIFOOver)
1927 tp->dev->stats.rx_fifo_errors++;
1928 }
1929 RTL_W16_F (IntrStatus, RxAckBits);
1930 }
1931}
1932
1933static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1934 int budget)
1935{
1936 void __iomem *ioaddr = tp->mmio_addr;
1937 int received = 0;
1938 unsigned char *rx_ring = tp->rx_ring;
1939 unsigned int cur_rx = tp->cur_rx;
1940 unsigned int rx_size = 0;
1941
1942 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1943 __func__, (u16)cur_rx,
1944 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1945
1946 while (netif_running(dev) && received < budget &&
1947 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1948 u32 ring_offset = cur_rx % RX_BUF_LEN;
1949 u32 rx_status;
1950 unsigned int pkt_size;
1951 struct sk_buff *skb;
1952
1953 rmb();
1954
1955
1956 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1957 rx_size = rx_status >> 16;
1958 if (likely(!(dev->features & NETIF_F_RXFCS)))
1959 pkt_size = rx_size - 4;
1960 else
1961 pkt_size = rx_size;
1962
1963 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1964 __func__, rx_status, rx_size, cur_rx);
1965#if RTL8139_DEBUG > 2
1966 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1967 DUMP_PREFIX_OFFSET, 16, 1,
1968 &rx_ring[ring_offset], 70, true);
1969#endif
1970
1971
1972
1973
1974
1975 if (unlikely(rx_size == 0xfff0)) {
1976 if (!tp->fifo_copy_timeout)
1977 tp->fifo_copy_timeout = jiffies + 2;
1978 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1979 netdev_dbg(dev, "hung FIFO. Reset\n");
1980 rx_size = 0;
1981 goto no_early_rx;
1982 }
1983 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1984 tp->xstats.early_rx++;
1985 break;
1986 }
1987
1988no_early_rx:
1989 tp->fifo_copy_timeout = 0;
1990
1991
1992
1993
1994
1995
1996 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1997 (rx_size < 8) ||
1998 (!(rx_status & RxStatusOK)))) {
1999 if ((dev->features & NETIF_F_RXALL) &&
2000 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2001 (rx_size >= 8) &&
2002 (!(rx_status & RxStatusOK))) {
2003
2004
2005
2006
2007 dev->stats.rx_errors++;
2008 if (rx_status & RxCRCErr) {
2009 dev->stats.rx_crc_errors++;
2010 goto keep_pkt;
2011 }
2012 if (rx_status & RxRunt) {
2013 dev->stats.rx_length_errors++;
2014 goto keep_pkt;
2015 }
2016 }
2017 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2018 received = -1;
2019 goto out;
2020 }
2021
2022keep_pkt:
2023
2024
2025
2026 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
2027 if (likely(skb)) {
2028#if RX_BUF_IDX == 3
2029 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2030#else
2031 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2032#endif
2033 skb_put (skb, pkt_size);
2034
2035 skb->protocol = eth_type_trans (skb, dev);
2036
2037 u64_stats_update_begin(&tp->rx_stats.syncp);
2038 tp->rx_stats.packets++;
2039 tp->rx_stats.bytes += pkt_size;
2040 u64_stats_update_end(&tp->rx_stats.syncp);
2041
2042 netif_receive_skb (skb);
2043 } else {
2044 dev->stats.rx_dropped++;
2045 }
2046 received++;
2047
2048 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2049 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2050
2051 rtl8139_isr_ack(tp);
2052 }
2053
2054 if (unlikely(!received || rx_size == 0xfff0))
2055 rtl8139_isr_ack(tp);
2056
2057 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2058 __func__, cur_rx,
2059 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2060
2061 tp->cur_rx = cur_rx;
2062
2063
2064
2065
2066
2067 if (tp->fifo_copy_timeout)
2068 received = budget;
2069
2070out:
2071 return received;
2072}
2073
2074
2075static void rtl8139_weird_interrupt (struct net_device *dev,
2076 struct rtl8139_private *tp,
2077 void __iomem *ioaddr,
2078 int status, int link_changed)
2079{
2080 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2081
2082 assert (dev != NULL);
2083 assert (tp != NULL);
2084 assert (ioaddr != NULL);
2085
2086
2087 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2088 RTL_W32 (RxMissed, 0);
2089
2090 if ((status & RxUnderrun) && link_changed &&
2091 (tp->drv_flags & HAS_LNK_CHNG)) {
2092 rtl_check_media(dev, 0);
2093 status &= ~RxUnderrun;
2094 }
2095
2096 if (status & (RxUnderrun | RxErr))
2097 dev->stats.rx_errors++;
2098
2099 if (status & PCSTimeout)
2100 dev->stats.rx_length_errors++;
2101 if (status & RxUnderrun)
2102 dev->stats.rx_fifo_errors++;
2103 if (status & PCIErr) {
2104 u16 pci_cmd_status;
2105 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2106 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2107
2108 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2109 }
2110}
2111
2112static int rtl8139_poll(struct napi_struct *napi, int budget)
2113{
2114 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2115 struct net_device *dev = tp->dev;
2116 void __iomem *ioaddr = tp->mmio_addr;
2117 int work_done;
2118
2119 spin_lock(&tp->rx_lock);
2120 work_done = 0;
2121 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2122 work_done += rtl8139_rx(dev, tp, budget);
2123
2124 if (work_done < budget) {
2125 unsigned long flags;
2126
2127
2128
2129
2130 spin_lock_irqsave(&tp->lock, flags);
2131 __napi_complete(napi);
2132 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2133 spin_unlock_irqrestore(&tp->lock, flags);
2134 }
2135 spin_unlock(&tp->rx_lock);
2136
2137 return work_done;
2138}
2139
2140
2141
2142static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2143{
2144 struct net_device *dev = (struct net_device *) dev_instance;
2145 struct rtl8139_private *tp = netdev_priv(dev);
2146 void __iomem *ioaddr = tp->mmio_addr;
2147 u16 status, ackstat;
2148 int link_changed = 0;
2149 int handled = 0;
2150
2151 spin_lock (&tp->lock);
2152 status = RTL_R16 (IntrStatus);
2153
2154
2155 if (unlikely((status & rtl8139_intr_mask) == 0))
2156 goto out;
2157
2158 handled = 1;
2159
2160
2161 if (unlikely(status == 0xFFFF))
2162 goto out;
2163
2164
2165 if (unlikely(!netif_running(dev))) {
2166 RTL_W16 (IntrMask, 0);
2167 goto out;
2168 }
2169
2170
2171
2172 if (unlikely(status & RxUnderrun))
2173 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2174
2175 ackstat = status & ~(RxAckBits | TxErr);
2176 if (ackstat)
2177 RTL_W16 (IntrStatus, ackstat);
2178
2179
2180
2181 if (status & RxAckBits){
2182 if (napi_schedule_prep(&tp->napi)) {
2183 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2184 __napi_schedule(&tp->napi);
2185 }
2186 }
2187
2188
2189 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2190 rtl8139_weird_interrupt (dev, tp, ioaddr,
2191 status, link_changed);
2192
2193 if (status & (TxOK | TxErr)) {
2194 rtl8139_tx_interrupt (dev, tp, ioaddr);
2195 if (status & TxErr)
2196 RTL_W16 (IntrStatus, TxErr);
2197 }
2198 out:
2199 spin_unlock (&tp->lock);
2200
2201 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2202 RTL_R16(IntrStatus));
2203 return IRQ_RETVAL(handled);
2204}
2205
2206#ifdef CONFIG_NET_POLL_CONTROLLER
2207
2208
2209
2210
2211static void rtl8139_poll_controller(struct net_device *dev)
2212{
2213 struct rtl8139_private *tp = netdev_priv(dev);
2214 const int irq = tp->pci_dev->irq;
2215
2216 disable_irq(irq);
2217 rtl8139_interrupt(irq, dev);
2218 enable_irq(irq);
2219}
2220#endif
2221
2222static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2223{
2224 struct rtl8139_private *tp = netdev_priv(dev);
2225 void __iomem *ioaddr = tp->mmio_addr;
2226 struct sockaddr *addr = p;
2227
2228 if (!is_valid_ether_addr(addr->sa_data))
2229 return -EADDRNOTAVAIL;
2230
2231 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2232
2233 spin_lock_irq(&tp->lock);
2234
2235 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2236 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2237 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2238 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2239
2240 spin_unlock_irq(&tp->lock);
2241
2242 return 0;
2243}
2244
2245static int rtl8139_close (struct net_device *dev)
2246{
2247 struct rtl8139_private *tp = netdev_priv(dev);
2248 void __iomem *ioaddr = tp->mmio_addr;
2249 unsigned long flags;
2250
2251 netif_stop_queue(dev);
2252 napi_disable(&tp->napi);
2253
2254 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2255 RTL_R16(IntrStatus));
2256
2257 spin_lock_irqsave (&tp->lock, flags);
2258
2259
2260 RTL_W8 (ChipCmd, 0);
2261
2262
2263 RTL_W16 (IntrMask, 0);
2264
2265
2266 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2267 RTL_W32 (RxMissed, 0);
2268
2269 spin_unlock_irqrestore (&tp->lock, flags);
2270
2271 free_irq(tp->pci_dev->irq, dev);
2272
2273 rtl8139_tx_clear (tp);
2274
2275 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2276 tp->rx_ring, tp->rx_ring_dma);
2277 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2278 tp->tx_bufs, tp->tx_bufs_dma);
2279 tp->rx_ring = NULL;
2280 tp->tx_bufs = NULL;
2281
2282
2283 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2284
2285 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2286 RTL_W8 (HltClk, 'H');
2287
2288 return 0;
2289}
2290
2291
2292
2293
2294
2295static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2296{
2297 struct rtl8139_private *tp = netdev_priv(dev);
2298 void __iomem *ioaddr = tp->mmio_addr;
2299
2300 spin_lock_irq(&tp->lock);
2301 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2302 u8 cfg3 = RTL_R8 (Config3);
2303 u8 cfg5 = RTL_R8 (Config5);
2304
2305 wol->supported = WAKE_PHY | WAKE_MAGIC
2306 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2307
2308 wol->wolopts = 0;
2309 if (cfg3 & Cfg3_LinkUp)
2310 wol->wolopts |= WAKE_PHY;
2311 if (cfg3 & Cfg3_Magic)
2312 wol->wolopts |= WAKE_MAGIC;
2313
2314
2315 if (cfg5 & Cfg5_UWF)
2316 wol->wolopts |= WAKE_UCAST;
2317 if (cfg5 & Cfg5_MWF)
2318 wol->wolopts |= WAKE_MCAST;
2319 if (cfg5 & Cfg5_BWF)
2320 wol->wolopts |= WAKE_BCAST;
2321 }
2322 spin_unlock_irq(&tp->lock);
2323}
2324
2325
2326
2327
2328
2329static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2330{
2331 struct rtl8139_private *tp = netdev_priv(dev);
2332 void __iomem *ioaddr = tp->mmio_addr;
2333 u32 support;
2334 u8 cfg3, cfg5;
2335
2336 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2337 ? (WAKE_PHY | WAKE_MAGIC
2338 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2339 : 0);
2340 if (wol->wolopts & ~support)
2341 return -EINVAL;
2342
2343 spin_lock_irq(&tp->lock);
2344 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2345 if (wol->wolopts & WAKE_PHY)
2346 cfg3 |= Cfg3_LinkUp;
2347 if (wol->wolopts & WAKE_MAGIC)
2348 cfg3 |= Cfg3_Magic;
2349 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2350 RTL_W8 (Config3, cfg3);
2351 RTL_W8 (Cfg9346, Cfg9346_Lock);
2352
2353 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2354
2355
2356
2357 if (wol->wolopts & WAKE_UCAST)
2358 cfg5 |= Cfg5_UWF;
2359 if (wol->wolopts & WAKE_MCAST)
2360 cfg5 |= Cfg5_MWF;
2361 if (wol->wolopts & WAKE_BCAST)
2362 cfg5 |= Cfg5_BWF;
2363 RTL_W8 (Config5, cfg5);
2364 spin_unlock_irq(&tp->lock);
2365
2366 return 0;
2367}
2368
2369static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2370{
2371 struct rtl8139_private *tp = netdev_priv(dev);
2372 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2373 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2374 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2375 info->regdump_len = tp->regs_len;
2376}
2377
2378static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2379{
2380 struct rtl8139_private *tp = netdev_priv(dev);
2381 spin_lock_irq(&tp->lock);
2382 mii_ethtool_gset(&tp->mii, cmd);
2383 spin_unlock_irq(&tp->lock);
2384 return 0;
2385}
2386
2387static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2388{
2389 struct rtl8139_private *tp = netdev_priv(dev);
2390 int rc;
2391 spin_lock_irq(&tp->lock);
2392 rc = mii_ethtool_sset(&tp->mii, cmd);
2393 spin_unlock_irq(&tp->lock);
2394 return rc;
2395}
2396
2397static int rtl8139_nway_reset(struct net_device *dev)
2398{
2399 struct rtl8139_private *tp = netdev_priv(dev);
2400 return mii_nway_restart(&tp->mii);
2401}
2402
2403static u32 rtl8139_get_link(struct net_device *dev)
2404{
2405 struct rtl8139_private *tp = netdev_priv(dev);
2406 return mii_link_ok(&tp->mii);
2407}
2408
2409static u32 rtl8139_get_msglevel(struct net_device *dev)
2410{
2411 struct rtl8139_private *tp = netdev_priv(dev);
2412 return tp->msg_enable;
2413}
2414
2415static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2416{
2417 struct rtl8139_private *tp = netdev_priv(dev);
2418 tp->msg_enable = datum;
2419}
2420
2421static int rtl8139_get_regs_len(struct net_device *dev)
2422{
2423 struct rtl8139_private *tp;
2424
2425 if (use_io)
2426 return 0;
2427 tp = netdev_priv(dev);
2428 return tp->regs_len;
2429}
2430
2431static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2432{
2433 struct rtl8139_private *tp;
2434
2435
2436 if (use_io)
2437 return;
2438 tp = netdev_priv(dev);
2439
2440 regs->version = RTL_REGS_VER;
2441
2442 spin_lock_irq(&tp->lock);
2443 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2444 spin_unlock_irq(&tp->lock);
2445}
2446
2447static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2448{
2449 switch (sset) {
2450 case ETH_SS_STATS:
2451 return RTL_NUM_STATS;
2452 default:
2453 return -EOPNOTSUPP;
2454 }
2455}
2456
2457static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2458{
2459 struct rtl8139_private *tp = netdev_priv(dev);
2460
2461 data[0] = tp->xstats.early_rx;
2462 data[1] = tp->xstats.tx_buf_mapped;
2463 data[2] = tp->xstats.tx_timeouts;
2464 data[3] = tp->xstats.rx_lost_in_ring;
2465}
2466
2467static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2468{
2469 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2470}
2471
2472static const struct ethtool_ops rtl8139_ethtool_ops = {
2473 .get_drvinfo = rtl8139_get_drvinfo,
2474 .get_settings = rtl8139_get_settings,
2475 .set_settings = rtl8139_set_settings,
2476 .get_regs_len = rtl8139_get_regs_len,
2477 .get_regs = rtl8139_get_regs,
2478 .nway_reset = rtl8139_nway_reset,
2479 .get_link = rtl8139_get_link,
2480 .get_msglevel = rtl8139_get_msglevel,
2481 .set_msglevel = rtl8139_set_msglevel,
2482 .get_wol = rtl8139_get_wol,
2483 .set_wol = rtl8139_set_wol,
2484 .get_strings = rtl8139_get_strings,
2485 .get_sset_count = rtl8139_get_sset_count,
2486 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2487};
2488
2489static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2490{
2491 struct rtl8139_private *tp = netdev_priv(dev);
2492 int rc;
2493
2494 if (!netif_running(dev))
2495 return -EINVAL;
2496
2497 spin_lock_irq(&tp->lock);
2498 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2499 spin_unlock_irq(&tp->lock);
2500
2501 return rc;
2502}
2503
2504
2505static struct rtnl_link_stats64 *
2506rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2507{
2508 struct rtl8139_private *tp = netdev_priv(dev);
2509 void __iomem *ioaddr = tp->mmio_addr;
2510 unsigned long flags;
2511 unsigned int start;
2512
2513 if (netif_running(dev)) {
2514 spin_lock_irqsave (&tp->lock, flags);
2515 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2516 RTL_W32 (RxMissed, 0);
2517 spin_unlock_irqrestore (&tp->lock, flags);
2518 }
2519
2520 netdev_stats_to_stats64(stats, &dev->stats);
2521
2522 do {
2523 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
2524 stats->rx_packets = tp->rx_stats.packets;
2525 stats->rx_bytes = tp->rx_stats.bytes;
2526 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
2527
2528 do {
2529 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
2530 stats->tx_packets = tp->tx_stats.packets;
2531 stats->tx_bytes = tp->tx_stats.bytes;
2532 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
2533
2534 return stats;
2535}
2536
2537
2538
2539
2540static void __set_rx_mode (struct net_device *dev)
2541{
2542 struct rtl8139_private *tp = netdev_priv(dev);
2543 void __iomem *ioaddr = tp->mmio_addr;
2544 u32 mc_filter[2];
2545 int rx_mode;
2546 u32 tmp;
2547
2548 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2549 dev->flags, RTL_R32(RxConfig));
2550
2551
2552 if (dev->flags & IFF_PROMISC) {
2553 rx_mode =
2554 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2555 AcceptAllPhys;
2556 mc_filter[1] = mc_filter[0] = 0xffffffff;
2557 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2558 (dev->flags & IFF_ALLMULTI)) {
2559
2560 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2561 mc_filter[1] = mc_filter[0] = 0xffffffff;
2562 } else {
2563 struct netdev_hw_addr *ha;
2564 rx_mode = AcceptBroadcast | AcceptMyPhys;
2565 mc_filter[1] = mc_filter[0] = 0;
2566 netdev_for_each_mc_addr(ha, dev) {
2567 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2568
2569 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2570 rx_mode |= AcceptMulticast;
2571 }
2572 }
2573
2574 if (dev->features & NETIF_F_RXALL)
2575 rx_mode |= (AcceptErr | AcceptRunt);
2576
2577
2578 tmp = rtl8139_rx_config | rx_mode;
2579 if (tp->rx_config != tmp) {
2580 RTL_W32_F (RxConfig, tmp);
2581 tp->rx_config = tmp;
2582 }
2583 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2584 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2585}
2586
2587static void rtl8139_set_rx_mode (struct net_device *dev)
2588{
2589 unsigned long flags;
2590 struct rtl8139_private *tp = netdev_priv(dev);
2591
2592 spin_lock_irqsave (&tp->lock, flags);
2593 __set_rx_mode(dev);
2594 spin_unlock_irqrestore (&tp->lock, flags);
2595}
2596
2597#ifdef CONFIG_PM
2598
2599static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2600{
2601 struct net_device *dev = pci_get_drvdata (pdev);
2602 struct rtl8139_private *tp = netdev_priv(dev);
2603 void __iomem *ioaddr = tp->mmio_addr;
2604 unsigned long flags;
2605
2606 pci_save_state (pdev);
2607
2608 if (!netif_running (dev))
2609 return 0;
2610
2611 netif_device_detach (dev);
2612
2613 spin_lock_irqsave (&tp->lock, flags);
2614
2615
2616 RTL_W16 (IntrMask, 0);
2617 RTL_W8 (ChipCmd, 0);
2618
2619
2620 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2621 RTL_W32 (RxMissed, 0);
2622
2623 spin_unlock_irqrestore (&tp->lock, flags);
2624
2625 pci_set_power_state (pdev, PCI_D3hot);
2626
2627 return 0;
2628}
2629
2630
2631static int rtl8139_resume (struct pci_dev *pdev)
2632{
2633 struct net_device *dev = pci_get_drvdata (pdev);
2634
2635 pci_restore_state (pdev);
2636 if (!netif_running (dev))
2637 return 0;
2638 pci_set_power_state (pdev, PCI_D0);
2639 rtl8139_init_ring (dev);
2640 rtl8139_hw_start (dev);
2641 netif_device_attach (dev);
2642 return 0;
2643}
2644
2645#endif
2646
2647
2648static struct pci_driver rtl8139_pci_driver = {
2649 .name = DRV_NAME,
2650 .id_table = rtl8139_pci_tbl,
2651 .probe = rtl8139_init_one,
2652 .remove = rtl8139_remove_one,
2653#ifdef CONFIG_PM
2654 .suspend = rtl8139_suspend,
2655 .resume = rtl8139_resume,
2656#endif
2657};
2658
2659
2660static int __init rtl8139_init_module (void)
2661{
2662
2663
2664
2665#ifdef MODULE
2666 pr_info(RTL8139_DRIVER_NAME "\n");
2667#endif
2668
2669 return pci_register_driver(&rtl8139_pci_driver);
2670}
2671
2672
2673static void __exit rtl8139_cleanup_module (void)
2674{
2675 pci_unregister_driver (&rtl8139_pci_driver);
2676}
2677
2678
2679module_init(rtl8139_init_module);
2680module_exit(rtl8139_cleanup_module);
2681