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68
69#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
70
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/types.h>
74#include <linux/compiler.h>
75#include <linux/slab.h>
76#include <linux/delay.h>
77#include <linux/init.h>
78#include <linux/interrupt.h>
79#include <linux/vmalloc.h>
80#include <linux/ioport.h>
81#include <linux/pci.h>
82#include <linux/mm.h>
83#include <linux/highmem.h>
84#include <linux/list.h>
85#include <linux/dma-mapping.h>
86
87#include <linux/netdevice.h>
88#include <linux/etherdevice.h>
89#include <linux/skbuff.h>
90#include <linux/ethtool.h>
91#include <linux/crc32.h>
92#include <linux/random.h>
93#include <linux/mii.h>
94#include <linux/ip.h>
95#include <linux/tcp.h>
96#include <linux/mutex.h>
97#include <linux/firmware.h>
98
99#include <net/checksum.h>
100
101#include <linux/atomic.h>
102#include <asm/io.h>
103#include <asm/byteorder.h>
104#include <asm/uaccess.h>
105
106#define cas_page_map(x) kmap_atomic((x))
107#define cas_page_unmap(x) kunmap_atomic((x))
108#define CAS_NCPUS num_online_cpus()
109
110#define cas_skb_release(x) netif_rx(x)
111
112
113#define USE_HP_WORKAROUND
114#define HP_WORKAROUND_DEFAULT
115#define CAS_HP_ALT_FIRMWARE cas_prog_null
116
117#include "cassini.h"
118
119#define USE_TX_COMPWB
120#define USE_CSMA_CD_PROTO
121#define USE_RX_BLANK
122#undef USE_ENTROPY_DEV
123
124
125
126
127#undef USE_PCI_INTB
128#undef USE_PCI_INTC
129#undef USE_PCI_INTD
130#undef USE_QOS
131
132#undef USE_VPD_DEBUG
133
134
135#define USE_PAGE_ORDER
136#define RX_DONT_BATCH 0
137#define RX_COPY_ALWAYS 0
138#define RX_COPY_MIN 64
139#undef RX_COUNT_BUFFERS
140
141#define DRV_MODULE_NAME "cassini"
142#define DRV_MODULE_VERSION "1.6"
143#define DRV_MODULE_RELDATE "21 May 2008"
144
145#define CAS_DEF_MSG_ENABLE \
146 (NETIF_MSG_DRV | \
147 NETIF_MSG_PROBE | \
148 NETIF_MSG_LINK | \
149 NETIF_MSG_TIMER | \
150 NETIF_MSG_IFDOWN | \
151 NETIF_MSG_IFUP | \
152 NETIF_MSG_RX_ERR | \
153 NETIF_MSG_TX_ERR)
154
155
156
157
158#define CAS_TX_TIMEOUT (HZ)
159#define CAS_LINK_TIMEOUT (22*HZ/10)
160#define CAS_LINK_FAST_TIMEOUT (1)
161
162
163
164
165#define STOP_TRIES_PHY 1000
166#define STOP_TRIES 5000
167
168
169
170
171
172#define CAS_MIN_FRAME 97
173#define CAS_1000MB_MIN_FRAME 255
174#define CAS_MIN_MTU 60
175#define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
176
177#if 1
178
179
180
181
182#else
183#define CAS_RESET_MTU 1
184#define CAS_RESET_ALL 2
185#define CAS_RESET_SPARE 3
186#endif
187
188static char version[] =
189 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
190
191static int cassini_debug = -1;
192static int link_mode;
193
194MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
195MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
196MODULE_LICENSE("GPL");
197MODULE_FIRMWARE("sun/cassini.bin");
198module_param(cassini_debug, int, 0);
199MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
200module_param(link_mode, int, 0);
201MODULE_PARM_DESC(link_mode, "default link mode");
202
203
204
205
206
207#define DEFAULT_LINKDOWN_TIMEOUT 5
208
209
210
211static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
212module_param(linkdown_timeout, int, 0);
213MODULE_PARM_DESC(linkdown_timeout,
214"min reset interval in sec. for PCS linkdown issue; disabled if not positive");
215
216
217
218
219
220
221static int link_transition_timeout;
222
223
224
225static u16 link_modes[] = {
226 BMCR_ANENABLE,
227 0,
228 BMCR_SPEED100,
229 BMCR_FULLDPLX,
230 BMCR_SPEED100|BMCR_FULLDPLX,
231 CAS_BMCR_SPEED1000|BMCR_FULLDPLX
232};
233
234static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
235 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
237 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { 0, }
240};
241
242MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
243
244static void cas_set_link_modes(struct cas *cp);
245
246static inline void cas_lock_tx(struct cas *cp)
247{
248 int i;
249
250 for (i = 0; i < N_TX_RINGS; i++)
251 spin_lock(&cp->tx_lock[i]);
252}
253
254static inline void cas_lock_all(struct cas *cp)
255{
256 spin_lock_irq(&cp->lock);
257 cas_lock_tx(cp);
258}
259
260
261
262
263
264
265
266
267
268#define cas_lock_all_save(cp, flags) \
269do { \
270 struct cas *xxxcp = (cp); \
271 spin_lock_irqsave(&xxxcp->lock, flags); \
272 cas_lock_tx(xxxcp); \
273} while (0)
274
275static inline void cas_unlock_tx(struct cas *cp)
276{
277 int i;
278
279 for (i = N_TX_RINGS; i > 0; i--)
280 spin_unlock(&cp->tx_lock[i - 1]);
281}
282
283static inline void cas_unlock_all(struct cas *cp)
284{
285 cas_unlock_tx(cp);
286 spin_unlock_irq(&cp->lock);
287}
288
289#define cas_unlock_all_restore(cp, flags) \
290do { \
291 struct cas *xxxcp = (cp); \
292 cas_unlock_tx(xxxcp); \
293 spin_unlock_irqrestore(&xxxcp->lock, flags); \
294} while (0)
295
296static void cas_disable_irq(struct cas *cp, const int ring)
297{
298
299 if (ring == 0) {
300 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
301 return;
302 }
303
304
305 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
306 switch (ring) {
307#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
308#ifdef USE_PCI_INTB
309 case 1:
310#endif
311#ifdef USE_PCI_INTC
312 case 2:
313#endif
314#ifdef USE_PCI_INTD
315 case 3:
316#endif
317 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
318 cp->regs + REG_PLUS_INTRN_MASK(ring));
319 break;
320#endif
321 default:
322 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
323 REG_PLUS_INTRN_MASK(ring));
324 break;
325 }
326 }
327}
328
329static inline void cas_mask_intr(struct cas *cp)
330{
331 int i;
332
333 for (i = 0; i < N_RX_COMP_RINGS; i++)
334 cas_disable_irq(cp, i);
335}
336
337static void cas_enable_irq(struct cas *cp, const int ring)
338{
339 if (ring == 0) {
340 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
341 return;
342 }
343
344 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
345 switch (ring) {
346#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
347#ifdef USE_PCI_INTB
348 case 1:
349#endif
350#ifdef USE_PCI_INTC
351 case 2:
352#endif
353#ifdef USE_PCI_INTD
354 case 3:
355#endif
356 writel(INTRN_MASK_RX_EN, cp->regs +
357 REG_PLUS_INTRN_MASK(ring));
358 break;
359#endif
360 default:
361 break;
362 }
363 }
364}
365
366static inline void cas_unmask_intr(struct cas *cp)
367{
368 int i;
369
370 for (i = 0; i < N_RX_COMP_RINGS; i++)
371 cas_enable_irq(cp, i);
372}
373
374static inline void cas_entropy_gather(struct cas *cp)
375{
376#ifdef USE_ENTROPY_DEV
377 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
378 return;
379
380 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
381 readl(cp->regs + REG_ENTROPY_IV),
382 sizeof(uint64_t)*8);
383#endif
384}
385
386static inline void cas_entropy_reset(struct cas *cp)
387{
388#ifdef USE_ENTROPY_DEV
389 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
390 return;
391
392 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
393 cp->regs + REG_BIM_LOCAL_DEV_EN);
394 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
395 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
396
397
398 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
399 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
400#endif
401}
402
403
404
405
406static u16 cas_phy_read(struct cas *cp, int reg)
407{
408 u32 cmd;
409 int limit = STOP_TRIES_PHY;
410
411 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
412 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
413 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
414 cmd |= MIF_FRAME_TURN_AROUND_MSB;
415 writel(cmd, cp->regs + REG_MIF_FRAME);
416
417
418 while (limit-- > 0) {
419 udelay(10);
420 cmd = readl(cp->regs + REG_MIF_FRAME);
421 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
422 return cmd & MIF_FRAME_DATA_MASK;
423 }
424 return 0xFFFF;
425}
426
427static int cas_phy_write(struct cas *cp, int reg, u16 val)
428{
429 int limit = STOP_TRIES_PHY;
430 u32 cmd;
431
432 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
433 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
434 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
435 cmd |= MIF_FRAME_TURN_AROUND_MSB;
436 cmd |= val & MIF_FRAME_DATA_MASK;
437 writel(cmd, cp->regs + REG_MIF_FRAME);
438
439
440 while (limit-- > 0) {
441 udelay(10);
442 cmd = readl(cp->regs + REG_MIF_FRAME);
443 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
444 return 0;
445 }
446 return -1;
447}
448
449static void cas_phy_powerup(struct cas *cp)
450{
451 u16 ctl = cas_phy_read(cp, MII_BMCR);
452
453 if ((ctl & BMCR_PDOWN) == 0)
454 return;
455 ctl &= ~BMCR_PDOWN;
456 cas_phy_write(cp, MII_BMCR, ctl);
457}
458
459static void cas_phy_powerdown(struct cas *cp)
460{
461 u16 ctl = cas_phy_read(cp, MII_BMCR);
462
463 if (ctl & BMCR_PDOWN)
464 return;
465 ctl |= BMCR_PDOWN;
466 cas_phy_write(cp, MII_BMCR, ctl);
467}
468
469
470static int cas_page_free(struct cas *cp, cas_page_t *page)
471{
472 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
473 PCI_DMA_FROMDEVICE);
474 __free_pages(page->buffer, cp->page_order);
475 kfree(page);
476 return 0;
477}
478
479#ifdef RX_COUNT_BUFFERS
480#define RX_USED_ADD(x, y) ((x)->used += (y))
481#define RX_USED_SET(x, y) ((x)->used = (y))
482#else
483#define RX_USED_ADD(x, y)
484#define RX_USED_SET(x, y)
485#endif
486
487
488
489
490static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
491{
492 cas_page_t *page;
493
494 page = kmalloc(sizeof(cas_page_t), flags);
495 if (!page)
496 return NULL;
497
498 INIT_LIST_HEAD(&page->list);
499 RX_USED_SET(page, 0);
500 page->buffer = alloc_pages(flags, cp->page_order);
501 if (!page->buffer)
502 goto page_err;
503 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
504 cp->page_size, PCI_DMA_FROMDEVICE);
505 return page;
506
507page_err:
508 kfree(page);
509 return NULL;
510}
511
512
513static void cas_spare_init(struct cas *cp)
514{
515 spin_lock(&cp->rx_inuse_lock);
516 INIT_LIST_HEAD(&cp->rx_inuse_list);
517 spin_unlock(&cp->rx_inuse_lock);
518
519 spin_lock(&cp->rx_spare_lock);
520 INIT_LIST_HEAD(&cp->rx_spare_list);
521 cp->rx_spares_needed = RX_SPARE_COUNT;
522 spin_unlock(&cp->rx_spare_lock);
523}
524
525
526static void cas_spare_free(struct cas *cp)
527{
528 struct list_head list, *elem, *tmp;
529
530
531 INIT_LIST_HEAD(&list);
532 spin_lock(&cp->rx_spare_lock);
533 list_splice_init(&cp->rx_spare_list, &list);
534 spin_unlock(&cp->rx_spare_lock);
535 list_for_each_safe(elem, tmp, &list) {
536 cas_page_free(cp, list_entry(elem, cas_page_t, list));
537 }
538
539 INIT_LIST_HEAD(&list);
540#if 1
541
542
543
544
545 spin_lock(&cp->rx_inuse_lock);
546 list_splice_init(&cp->rx_inuse_list, &list);
547 spin_unlock(&cp->rx_inuse_lock);
548#else
549 spin_lock(&cp->rx_spare_lock);
550 list_splice_init(&cp->rx_inuse_list, &list);
551 spin_unlock(&cp->rx_spare_lock);
552#endif
553 list_for_each_safe(elem, tmp, &list) {
554 cas_page_free(cp, list_entry(elem, cas_page_t, list));
555 }
556}
557
558
559static void cas_spare_recover(struct cas *cp, const gfp_t flags)
560{
561 struct list_head list, *elem, *tmp;
562 int needed, i;
563
564
565
566
567
568
569 INIT_LIST_HEAD(&list);
570 spin_lock(&cp->rx_inuse_lock);
571 list_splice_init(&cp->rx_inuse_list, &list);
572 spin_unlock(&cp->rx_inuse_lock);
573
574 list_for_each_safe(elem, tmp, &list) {
575 cas_page_t *page = list_entry(elem, cas_page_t, list);
576
577
578
579
580
581
582
583
584
585
586
587
588
589 if (page_count(page->buffer) > 1)
590 continue;
591
592 list_del(elem);
593 spin_lock(&cp->rx_spare_lock);
594 if (cp->rx_spares_needed > 0) {
595 list_add(elem, &cp->rx_spare_list);
596 cp->rx_spares_needed--;
597 spin_unlock(&cp->rx_spare_lock);
598 } else {
599 spin_unlock(&cp->rx_spare_lock);
600 cas_page_free(cp, page);
601 }
602 }
603
604
605 if (!list_empty(&list)) {
606 spin_lock(&cp->rx_inuse_lock);
607 list_splice(&list, &cp->rx_inuse_list);
608 spin_unlock(&cp->rx_inuse_lock);
609 }
610
611 spin_lock(&cp->rx_spare_lock);
612 needed = cp->rx_spares_needed;
613 spin_unlock(&cp->rx_spare_lock);
614 if (!needed)
615 return;
616
617
618 INIT_LIST_HEAD(&list);
619 i = 0;
620 while (i < needed) {
621 cas_page_t *spare = cas_page_alloc(cp, flags);
622 if (!spare)
623 break;
624 list_add(&spare->list, &list);
625 i++;
626 }
627
628 spin_lock(&cp->rx_spare_lock);
629 list_splice(&list, &cp->rx_spare_list);
630 cp->rx_spares_needed -= i;
631 spin_unlock(&cp->rx_spare_lock);
632}
633
634
635static cas_page_t *cas_page_dequeue(struct cas *cp)
636{
637 struct list_head *entry;
638 int recover;
639
640 spin_lock(&cp->rx_spare_lock);
641 if (list_empty(&cp->rx_spare_list)) {
642
643 spin_unlock(&cp->rx_spare_lock);
644 cas_spare_recover(cp, GFP_ATOMIC);
645 spin_lock(&cp->rx_spare_lock);
646 if (list_empty(&cp->rx_spare_list)) {
647 netif_err(cp, rx_err, cp->dev,
648 "no spare buffers available\n");
649 spin_unlock(&cp->rx_spare_lock);
650 return NULL;
651 }
652 }
653
654 entry = cp->rx_spare_list.next;
655 list_del(entry);
656 recover = ++cp->rx_spares_needed;
657 spin_unlock(&cp->rx_spare_lock);
658
659
660 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
661#if 1
662 atomic_inc(&cp->reset_task_pending);
663 atomic_inc(&cp->reset_task_pending_spare);
664 schedule_work(&cp->reset_task);
665#else
666 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
667 schedule_work(&cp->reset_task);
668#endif
669 }
670 return list_entry(entry, cas_page_t, list);
671}
672
673
674static void cas_mif_poll(struct cas *cp, const int enable)
675{
676 u32 cfg;
677
678 cfg = readl(cp->regs + REG_MIF_CFG);
679 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
680
681 if (cp->phy_type & CAS_PHY_MII_MDIO1)
682 cfg |= MIF_CFG_PHY_SELECT;
683
684
685 if (enable) {
686 cfg |= MIF_CFG_POLL_EN;
687 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
688 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
689 }
690 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
691 cp->regs + REG_MIF_MASK);
692 writel(cfg, cp->regs + REG_MIF_CFG);
693}
694
695
696static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
697{
698 u16 ctl;
699#if 1
700 int lcntl;
701 int changed = 0;
702 int oldstate = cp->lstate;
703 int link_was_not_down = !(oldstate == link_down);
704#endif
705
706 if (!ep)
707 goto start_aneg;
708 lcntl = cp->link_cntl;
709 if (ep->autoneg == AUTONEG_ENABLE)
710 cp->link_cntl = BMCR_ANENABLE;
711 else {
712 u32 speed = ethtool_cmd_speed(ep);
713 cp->link_cntl = 0;
714 if (speed == SPEED_100)
715 cp->link_cntl |= BMCR_SPEED100;
716 else if (speed == SPEED_1000)
717 cp->link_cntl |= CAS_BMCR_SPEED1000;
718 if (ep->duplex == DUPLEX_FULL)
719 cp->link_cntl |= BMCR_FULLDPLX;
720 }
721#if 1
722 changed = (lcntl != cp->link_cntl);
723#endif
724start_aneg:
725 if (cp->lstate == link_up) {
726 netdev_info(cp->dev, "PCS link down\n");
727 } else {
728 if (changed) {
729 netdev_info(cp->dev, "link configuration changed\n");
730 }
731 }
732 cp->lstate = link_down;
733 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
734 if (!cp->hw_running)
735 return;
736#if 1
737
738
739
740
741
742 if (oldstate == link_up)
743 netif_carrier_off(cp->dev);
744 if (changed && link_was_not_down) {
745
746
747
748
749
750 atomic_inc(&cp->reset_task_pending);
751 atomic_inc(&cp->reset_task_pending_all);
752 schedule_work(&cp->reset_task);
753 cp->timer_ticks = 0;
754 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
755 return;
756 }
757#endif
758 if (cp->phy_type & CAS_PHY_SERDES) {
759 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
760
761 if (cp->link_cntl & BMCR_ANENABLE) {
762 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
763 cp->lstate = link_aneg;
764 } else {
765 if (cp->link_cntl & BMCR_FULLDPLX)
766 val |= PCS_MII_CTRL_DUPLEX;
767 val &= ~PCS_MII_AUTONEG_EN;
768 cp->lstate = link_force_ok;
769 }
770 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
771 writel(val, cp->regs + REG_PCS_MII_CTRL);
772
773 } else {
774 cas_mif_poll(cp, 0);
775 ctl = cas_phy_read(cp, MII_BMCR);
776 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
777 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
778 ctl |= cp->link_cntl;
779 if (ctl & BMCR_ANENABLE) {
780 ctl |= BMCR_ANRESTART;
781 cp->lstate = link_aneg;
782 } else {
783 cp->lstate = link_force_ok;
784 }
785 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
786 cas_phy_write(cp, MII_BMCR, ctl);
787 cas_mif_poll(cp, 1);
788 }
789
790 cp->timer_ticks = 0;
791 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
792}
793
794
795static int cas_reset_mii_phy(struct cas *cp)
796{
797 int limit = STOP_TRIES_PHY;
798 u16 val;
799
800 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
801 udelay(100);
802 while (--limit) {
803 val = cas_phy_read(cp, MII_BMCR);
804 if ((val & BMCR_RESET) == 0)
805 break;
806 udelay(10);
807 }
808 return limit <= 0;
809}
810
811static void cas_saturn_firmware_init(struct cas *cp)
812{
813 const struct firmware *fw;
814 const char fw_name[] = "sun/cassini.bin";
815 int err;
816
817 if (PHY_NS_DP83065 != cp->phy_id)
818 return;
819
820 err = request_firmware(&fw, fw_name, &cp->pdev->dev);
821 if (err) {
822 pr_err("Failed to load firmware \"%s\"\n",
823 fw_name);
824 return;
825 }
826 if (fw->size < 2) {
827 pr_err("bogus length %zu in \"%s\"\n",
828 fw->size, fw_name);
829 goto out;
830 }
831 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
832 cp->fw_size = fw->size - 2;
833 cp->fw_data = vmalloc(cp->fw_size);
834 if (!cp->fw_data)
835 goto out;
836 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
837out:
838 release_firmware(fw);
839}
840
841static void cas_saturn_firmware_load(struct cas *cp)
842{
843 int i;
844
845 if (!cp->fw_data)
846 return;
847
848 cas_phy_powerdown(cp);
849
850
851 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
852
853
854 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
855 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
856 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
857 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
858 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
859 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
860 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
861 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
862
863
864 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
865 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
866 for (i = 0; i < cp->fw_size; i++)
867 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
868
869
870 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
871 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
872}
873
874
875
876static void cas_phy_init(struct cas *cp)
877{
878 u16 val;
879
880
881 if (CAS_PHY_MII(cp->phy_type)) {
882 writel(PCS_DATAPATH_MODE_MII,
883 cp->regs + REG_PCS_DATAPATH_MODE);
884
885 cas_mif_poll(cp, 0);
886 cas_reset_mii_phy(cp);
887
888 if (PHY_LUCENT_B0 == cp->phy_id) {
889
890 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
891 cas_phy_write(cp, MII_BMCR, 0x00f1);
892 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
893
894 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
895
896 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
897 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
898 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
899 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
900 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
901 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
902 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
903 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
904 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
905 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
906 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
907
908 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
909 val = cas_phy_read(cp, BROADCOM_MII_REG4);
910 val = cas_phy_read(cp, BROADCOM_MII_REG4);
911 if (val & 0x0080) {
912
913 cas_phy_write(cp, BROADCOM_MII_REG4,
914 val & ~0x0080);
915 }
916
917 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
918 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
919 SATURN_PCFG_FSI : 0x0,
920 cp->regs + REG_SATURN_PCFG);
921
922
923
924
925
926 if (PHY_NS_DP83065 == cp->phy_id) {
927 cas_saturn_firmware_load(cp);
928 }
929 cas_phy_powerup(cp);
930 }
931
932
933 val = cas_phy_read(cp, MII_BMCR);
934 val &= ~BMCR_ANENABLE;
935 cas_phy_write(cp, MII_BMCR, val);
936 udelay(10);
937
938 cas_phy_write(cp, MII_ADVERTISE,
939 cas_phy_read(cp, MII_ADVERTISE) |
940 (ADVERTISE_10HALF | ADVERTISE_10FULL |
941 ADVERTISE_100HALF | ADVERTISE_100FULL |
942 CAS_ADVERTISE_PAUSE |
943 CAS_ADVERTISE_ASYM_PAUSE));
944
945 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
946
947
948
949 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
950 val &= ~CAS_ADVERTISE_1000HALF;
951 val |= CAS_ADVERTISE_1000FULL;
952 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
953 }
954
955 } else {
956
957 u32 val;
958 int limit;
959
960 writel(PCS_DATAPATH_MODE_SERDES,
961 cp->regs + REG_PCS_DATAPATH_MODE);
962
963
964 if (cp->cas_flags & CAS_FLAG_SATURN)
965 writel(0, cp->regs + REG_SATURN_PCFG);
966
967
968 val = readl(cp->regs + REG_PCS_MII_CTRL);
969 val |= PCS_MII_RESET;
970 writel(val, cp->regs + REG_PCS_MII_CTRL);
971
972 limit = STOP_TRIES;
973 while (--limit > 0) {
974 udelay(10);
975 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
976 PCS_MII_RESET) == 0)
977 break;
978 }
979 if (limit <= 0)
980 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
981 readl(cp->regs + REG_PCS_STATE_MACHINE));
982
983
984
985
986 writel(0x0, cp->regs + REG_PCS_CFG);
987
988
989 val = readl(cp->regs + REG_PCS_MII_ADVERT);
990 val &= ~PCS_MII_ADVERT_HD;
991 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
992 PCS_MII_ADVERT_ASYM_PAUSE);
993 writel(val, cp->regs + REG_PCS_MII_ADVERT);
994
995
996 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
997
998
999 writel(PCS_SERDES_CTRL_SYNCD_EN,
1000 cp->regs + REG_PCS_SERDES_CTRL);
1001 }
1002}
1003
1004
1005static int cas_pcs_link_check(struct cas *cp)
1006{
1007 u32 stat, state_machine;
1008 int retval = 0;
1009
1010
1011
1012
1013
1014 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1015 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1016 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1017
1018
1019
1020
1021 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1022 PCS_MII_STATUS_REMOTE_FAULT)) ==
1023 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1024 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1025
1026
1027
1028
1029 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1030 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1031 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1032 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1033 stat |= PCS_MII_STATUS_LINK_STATUS;
1034 }
1035
1036 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1037 if (cp->lstate != link_up) {
1038 if (cp->opened) {
1039 cp->lstate = link_up;
1040 cp->link_transition = LINK_TRANSITION_LINK_UP;
1041
1042 cas_set_link_modes(cp);
1043 netif_carrier_on(cp->dev);
1044 }
1045 }
1046 } else if (cp->lstate == link_up) {
1047 cp->lstate = link_down;
1048 if (link_transition_timeout != 0 &&
1049 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1050 !cp->link_transition_jiffies_valid) {
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063 retval = 1;
1064 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1065 cp->link_transition_jiffies = jiffies;
1066 cp->link_transition_jiffies_valid = 1;
1067 } else {
1068 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1069 }
1070 netif_carrier_off(cp->dev);
1071 if (cp->opened)
1072 netif_info(cp, link, cp->dev, "PCS link down\n");
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1083
1084 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1085 if (stat == 0x03)
1086 return 1;
1087 }
1088 } else if (cp->lstate == link_down) {
1089 if (link_transition_timeout != 0 &&
1090 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1091 !cp->link_transition_jiffies_valid) {
1092
1093
1094
1095
1096
1097 retval = 1;
1098 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1099 cp->link_transition_jiffies = jiffies;
1100 cp->link_transition_jiffies_valid = 1;
1101 } else {
1102 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1103 }
1104 }
1105
1106 return retval;
1107}
1108
1109static int cas_pcs_interrupt(struct net_device *dev,
1110 struct cas *cp, u32 status)
1111{
1112 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1113
1114 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1115 return 0;
1116 return cas_pcs_link_check(cp);
1117}
1118
1119static int cas_txmac_interrupt(struct net_device *dev,
1120 struct cas *cp, u32 status)
1121{
1122 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1123
1124 if (!txmac_stat)
1125 return 0;
1126
1127 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1128 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1129
1130
1131
1132
1133 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1134 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1135 return 0;
1136
1137 spin_lock(&cp->stat_lock[0]);
1138 if (txmac_stat & MAC_TX_UNDERRUN) {
1139 netdev_err(dev, "TX MAC xmit underrun\n");
1140 cp->net_stats[0].tx_fifo_errors++;
1141 }
1142
1143 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1144 netdev_err(dev, "TX MAC max packet size error\n");
1145 cp->net_stats[0].tx_errors++;
1146 }
1147
1148
1149
1150
1151 if (txmac_stat & MAC_TX_COLL_NORMAL)
1152 cp->net_stats[0].collisions += 0x10000;
1153
1154 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1155 cp->net_stats[0].tx_aborted_errors += 0x10000;
1156 cp->net_stats[0].collisions += 0x10000;
1157 }
1158
1159 if (txmac_stat & MAC_TX_COLL_LATE) {
1160 cp->net_stats[0].tx_aborted_errors += 0x10000;
1161 cp->net_stats[0].collisions += 0x10000;
1162 }
1163 spin_unlock(&cp->stat_lock[0]);
1164
1165
1166
1167
1168 return 0;
1169}
1170
1171static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1172{
1173 cas_hp_inst_t *inst;
1174 u32 val;
1175 int i;
1176
1177 i = 0;
1178 while ((inst = firmware) && inst->note) {
1179 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1180
1181 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1182 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1183 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1184
1185 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1186 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1187 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1188 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1189 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1190 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1191 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1192 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1193
1194 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1195 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1196 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1197 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1198 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1199 ++firmware;
1200 ++i;
1201 }
1202}
1203
1204static void cas_init_rx_dma(struct cas *cp)
1205{
1206 u64 desc_dma = cp->block_dvma;
1207 u32 val;
1208 int i, size;
1209
1210
1211 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1212 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1213 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1214 if ((N_RX_DESC_RINGS > 1) &&
1215 (cp->cas_flags & CAS_FLAG_REG_PLUS))
1216 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1217 writel(val, cp->regs + REG_RX_CFG);
1218
1219 val = (unsigned long) cp->init_rxds[0] -
1220 (unsigned long) cp->init_block;
1221 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1222 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1223 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1224
1225 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1226
1227
1228
1229 val = (unsigned long) cp->init_rxds[1] -
1230 (unsigned long) cp->init_block;
1231 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1232 writel((desc_dma + val) & 0xffffffff, cp->regs +
1233 REG_PLUS_RX_DB1_LOW);
1234 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1235 REG_PLUS_RX_KICK1);
1236 }
1237
1238
1239 val = (unsigned long) cp->init_rxcs[0] -
1240 (unsigned long) cp->init_block;
1241 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1242 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1243
1244 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1245
1246 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1247 val = (unsigned long) cp->init_rxcs[i] -
1248 (unsigned long) cp->init_block;
1249 writel((desc_dma + val) >> 32, cp->regs +
1250 REG_PLUS_RX_CBN_HI(i));
1251 writel((desc_dma + val) & 0xffffffff, cp->regs +
1252 REG_PLUS_RX_CBN_LOW(i));
1253 }
1254 }
1255
1256
1257
1258
1259
1260 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1261 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1262 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1263 for (i = 1; i < N_RX_COMP_RINGS; i++)
1264 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1265
1266
1267 if (N_RX_COMP_RINGS > 1)
1268 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1269 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1270
1271 for (i = 2; i < N_RX_COMP_RINGS; i++)
1272 writel(INTR_RX_DONE_ALT,
1273 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1274 }
1275
1276
1277 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1278 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1279 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1280 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1281 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1282
1283
1284 for (i = 0; i < 64; i++) {
1285 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1286 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1287 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1288 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1289 }
1290
1291
1292 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1293 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1294
1295
1296#ifdef USE_RX_BLANK
1297 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1298 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1299 writel(val, cp->regs + REG_RX_BLANK);
1300#else
1301 writel(0x0, cp->regs + REG_RX_BLANK);
1302#endif
1303
1304
1305
1306
1307
1308
1309
1310 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1311 writel(val, cp->regs + REG_RX_AE_THRESH);
1312 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1313 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1314 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1315 }
1316
1317
1318
1319
1320 writel(0x0, cp->regs + REG_RX_RED);
1321
1322
1323 val = 0;
1324 if (cp->page_size == 0x1000)
1325 val = 0x1;
1326 else if (cp->page_size == 0x2000)
1327 val = 0x2;
1328 else if (cp->page_size == 0x4000)
1329 val = 0x3;
1330
1331
1332 size = cp->dev->mtu + 64;
1333 if (size > cp->page_size)
1334 size = cp->page_size;
1335
1336 if (size <= 0x400)
1337 i = 0x0;
1338 else if (size <= 0x800)
1339 i = 0x1;
1340 else if (size <= 0x1000)
1341 i = 0x2;
1342 else
1343 i = 0x3;
1344
1345 cp->mtu_stride = 1 << (i + 10);
1346 val = CAS_BASE(RX_PAGE_SIZE, val);
1347 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1348 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1349 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1350 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1351
1352
1353 if (CAS_HP_FIRMWARE == cas_prog_null)
1354 return;
1355
1356 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1357 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1358 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1359 writel(val, cp->regs + REG_HP_CFG);
1360}
1361
1362static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1363{
1364 memset(rxc, 0, sizeof(*rxc));
1365 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1366}
1367
1368
1369
1370
1371
1372static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1373{
1374 cas_page_t *page = cp->rx_pages[1][index];
1375 cas_page_t *new;
1376
1377 if (page_count(page->buffer) == 1)
1378 return page;
1379
1380 new = cas_page_dequeue(cp);
1381 if (new) {
1382 spin_lock(&cp->rx_inuse_lock);
1383 list_add(&page->list, &cp->rx_inuse_list);
1384 spin_unlock(&cp->rx_inuse_lock);
1385 }
1386 return new;
1387}
1388
1389
1390static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1391 const int index)
1392{
1393 cas_page_t **page0 = cp->rx_pages[0];
1394 cas_page_t **page1 = cp->rx_pages[1];
1395
1396
1397 if (page_count(page0[index]->buffer) > 1) {
1398 cas_page_t *new = cas_page_spare(cp, index);
1399 if (new) {
1400 page1[index] = page0[index];
1401 page0[index] = new;
1402 }
1403 }
1404 RX_USED_SET(page0[index], 0);
1405 return page0[index];
1406}
1407
1408static void cas_clean_rxds(struct cas *cp)
1409{
1410
1411 struct cas_rx_desc *rxd = cp->init_rxds[0];
1412 int i, size;
1413
1414
1415 for (i = 0; i < N_RX_FLOWS; i++) {
1416 struct sk_buff *skb;
1417 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1418 cas_skb_release(skb);
1419 }
1420 }
1421
1422
1423 size = RX_DESC_RINGN_SIZE(0);
1424 for (i = 0; i < size; i++) {
1425 cas_page_t *page = cas_page_swap(cp, 0, i);
1426 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1427 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1428 CAS_BASE(RX_INDEX_RING, 0));
1429 }
1430
1431 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1432 cp->rx_last[0] = 0;
1433 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1434}
1435
1436static void cas_clean_rxcs(struct cas *cp)
1437{
1438 int i, j;
1439
1440
1441 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1442 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1443 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1444 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1445 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1446 cas_rxc_init(rxc + j);
1447 }
1448 }
1449}
1450
1451#if 0
1452
1453
1454
1455
1456
1457
1458static int cas_rxmac_reset(struct cas *cp)
1459{
1460 struct net_device *dev = cp->dev;
1461 int limit;
1462 u32 val;
1463
1464
1465 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1466 for (limit = 0; limit < STOP_TRIES; limit++) {
1467 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1468 break;
1469 udelay(10);
1470 }
1471 if (limit == STOP_TRIES) {
1472 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1473 return 1;
1474 }
1475
1476
1477 writel(0, cp->regs + REG_RX_CFG);
1478 for (limit = 0; limit < STOP_TRIES; limit++) {
1479 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1480 break;
1481 udelay(10);
1482 }
1483 if (limit == STOP_TRIES) {
1484 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1485 return 1;
1486 }
1487
1488 mdelay(5);
1489
1490
1491 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1492 for (limit = 0; limit < STOP_TRIES; limit++) {
1493 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1494 break;
1495 udelay(10);
1496 }
1497 if (limit == STOP_TRIES) {
1498 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1499 return 1;
1500 }
1501
1502
1503 cas_clean_rxds(cp);
1504 cas_clean_rxcs(cp);
1505
1506
1507 cas_init_rx_dma(cp);
1508
1509
1510 val = readl(cp->regs + REG_RX_CFG);
1511 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1512 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1513 val = readl(cp->regs + REG_MAC_RX_CFG);
1514 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1515 return 0;
1516}
1517#endif
1518
1519static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1520 u32 status)
1521{
1522 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1523
1524 if (!stat)
1525 return 0;
1526
1527 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1528
1529
1530 spin_lock(&cp->stat_lock[0]);
1531 if (stat & MAC_RX_ALIGN_ERR)
1532 cp->net_stats[0].rx_frame_errors += 0x10000;
1533
1534 if (stat & MAC_RX_CRC_ERR)
1535 cp->net_stats[0].rx_crc_errors += 0x10000;
1536
1537 if (stat & MAC_RX_LEN_ERR)
1538 cp->net_stats[0].rx_length_errors += 0x10000;
1539
1540 if (stat & MAC_RX_OVERFLOW) {
1541 cp->net_stats[0].rx_over_errors++;
1542 cp->net_stats[0].rx_fifo_errors++;
1543 }
1544
1545
1546
1547
1548 spin_unlock(&cp->stat_lock[0]);
1549 return 0;
1550}
1551
1552static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1553 u32 status)
1554{
1555 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1556
1557 if (!stat)
1558 return 0;
1559
1560 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1561 "mac interrupt, stat: 0x%x\n", stat);
1562
1563
1564
1565
1566
1567 if (stat & MAC_CTRL_PAUSE_STATE)
1568 cp->pause_entered++;
1569
1570 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1571 cp->pause_last_time_recvd = (stat >> 16);
1572
1573 return 0;
1574}
1575
1576
1577
1578static inline int cas_mdio_link_not_up(struct cas *cp)
1579{
1580 u16 val;
1581
1582 switch (cp->lstate) {
1583 case link_force_ret:
1584 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1585 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1586 cp->timer_ticks = 5;
1587 cp->lstate = link_force_ok;
1588 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1589 break;
1590
1591 case link_aneg:
1592 val = cas_phy_read(cp, MII_BMCR);
1593
1594
1595
1596
1597 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1598 val |= BMCR_FULLDPLX;
1599 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1600 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1601 cas_phy_write(cp, MII_BMCR, val);
1602 cp->timer_ticks = 5;
1603 cp->lstate = link_force_try;
1604 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1605 break;
1606
1607 case link_force_try:
1608
1609 val = cas_phy_read(cp, MII_BMCR);
1610 cp->timer_ticks = 5;
1611 if (val & CAS_BMCR_SPEED1000) {
1612 val &= ~CAS_BMCR_SPEED1000;
1613 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1614 cas_phy_write(cp, MII_BMCR, val);
1615 break;
1616 }
1617
1618 if (val & BMCR_SPEED100) {
1619 if (val & BMCR_FULLDPLX)
1620 val &= ~BMCR_FULLDPLX;
1621 else {
1622 val &= ~BMCR_SPEED100;
1623 }
1624 cas_phy_write(cp, MII_BMCR, val);
1625 break;
1626 }
1627 default:
1628 break;
1629 }
1630 return 0;
1631}
1632
1633
1634
1635static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1636{
1637 int restart;
1638
1639 if (bmsr & BMSR_LSTATUS) {
1640
1641
1642
1643
1644
1645 if ((cp->lstate == link_force_try) &&
1646 (cp->link_cntl & BMCR_ANENABLE)) {
1647 cp->lstate = link_force_ret;
1648 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1649 cas_mif_poll(cp, 0);
1650 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1651 cp->timer_ticks = 5;
1652 if (cp->opened)
1653 netif_info(cp, link, cp->dev,
1654 "Got link after fallback, retrying autoneg once...\n");
1655 cas_phy_write(cp, MII_BMCR,
1656 cp->link_fcntl | BMCR_ANENABLE |
1657 BMCR_ANRESTART);
1658 cas_mif_poll(cp, 1);
1659
1660 } else if (cp->lstate != link_up) {
1661 cp->lstate = link_up;
1662 cp->link_transition = LINK_TRANSITION_LINK_UP;
1663
1664 if (cp->opened) {
1665 cas_set_link_modes(cp);
1666 netif_carrier_on(cp->dev);
1667 }
1668 }
1669 return 0;
1670 }
1671
1672
1673
1674
1675 restart = 0;
1676 if (cp->lstate == link_up) {
1677 cp->lstate = link_down;
1678 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1679
1680 netif_carrier_off(cp->dev);
1681 if (cp->opened)
1682 netif_info(cp, link, cp->dev, "Link down\n");
1683 restart = 1;
1684
1685 } else if (++cp->timer_ticks > 10)
1686 cas_mdio_link_not_up(cp);
1687
1688 return restart;
1689}
1690
1691static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1692 u32 status)
1693{
1694 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1695 u16 bmsr;
1696
1697
1698 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1699 return 0;
1700
1701 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1702 return cas_mii_link_check(cp, bmsr);
1703}
1704
1705static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1706 u32 status)
1707{
1708 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1709
1710 if (!stat)
1711 return 0;
1712
1713 netdev_err(dev, "PCI error [%04x:%04x]",
1714 stat, readl(cp->regs + REG_BIM_DIAG));
1715
1716
1717 if ((stat & PCI_ERR_BADACK) &&
1718 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1719 pr_cont(" <No ACK64# during ABS64 cycle>");
1720
1721 if (stat & PCI_ERR_DTRTO)
1722 pr_cont(" <Delayed transaction timeout>");
1723 if (stat & PCI_ERR_OTHER)
1724 pr_cont(" <other>");
1725 if (stat & PCI_ERR_BIM_DMA_WRITE)
1726 pr_cont(" <BIM DMA 0 write req>");
1727 if (stat & PCI_ERR_BIM_DMA_READ)
1728 pr_cont(" <BIM DMA 0 read req>");
1729 pr_cont("\n");
1730
1731 if (stat & PCI_ERR_OTHER) {
1732 u16 cfg;
1733
1734
1735
1736
1737 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1738 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1739 if (cfg & PCI_STATUS_PARITY)
1740 netdev_err(dev, "PCI parity error detected\n");
1741 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1742 netdev_err(dev, "PCI target abort\n");
1743 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1744 netdev_err(dev, "PCI master acks target abort\n");
1745 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1746 netdev_err(dev, "PCI master abort\n");
1747 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1748 netdev_err(dev, "PCI system error SERR#\n");
1749 if (cfg & PCI_STATUS_DETECTED_PARITY)
1750 netdev_err(dev, "PCI parity error\n");
1751
1752
1753 cfg &= (PCI_STATUS_PARITY |
1754 PCI_STATUS_SIG_TARGET_ABORT |
1755 PCI_STATUS_REC_TARGET_ABORT |
1756 PCI_STATUS_REC_MASTER_ABORT |
1757 PCI_STATUS_SIG_SYSTEM_ERROR |
1758 PCI_STATUS_DETECTED_PARITY);
1759 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1760 }
1761
1762
1763 return 1;
1764}
1765
1766
1767
1768
1769
1770
1771static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1772 u32 status)
1773{
1774 if (status & INTR_RX_TAG_ERROR) {
1775
1776 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1777 "corrupt rx tag framing\n");
1778 spin_lock(&cp->stat_lock[0]);
1779 cp->net_stats[0].rx_errors++;
1780 spin_unlock(&cp->stat_lock[0]);
1781 goto do_reset;
1782 }
1783
1784 if (status & INTR_RX_LEN_MISMATCH) {
1785
1786 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1787 "length mismatch for rx frame\n");
1788 spin_lock(&cp->stat_lock[0]);
1789 cp->net_stats[0].rx_errors++;
1790 spin_unlock(&cp->stat_lock[0]);
1791 goto do_reset;
1792 }
1793
1794 if (status & INTR_PCS_STATUS) {
1795 if (cas_pcs_interrupt(dev, cp, status))
1796 goto do_reset;
1797 }
1798
1799 if (status & INTR_TX_MAC_STATUS) {
1800 if (cas_txmac_interrupt(dev, cp, status))
1801 goto do_reset;
1802 }
1803
1804 if (status & INTR_RX_MAC_STATUS) {
1805 if (cas_rxmac_interrupt(dev, cp, status))
1806 goto do_reset;
1807 }
1808
1809 if (status & INTR_MAC_CTRL_STATUS) {
1810 if (cas_mac_interrupt(dev, cp, status))
1811 goto do_reset;
1812 }
1813
1814 if (status & INTR_MIF_STATUS) {
1815 if (cas_mif_interrupt(dev, cp, status))
1816 goto do_reset;
1817 }
1818
1819 if (status & INTR_PCI_ERROR_STATUS) {
1820 if (cas_pci_interrupt(dev, cp, status))
1821 goto do_reset;
1822 }
1823 return 0;
1824
1825do_reset:
1826#if 1
1827 atomic_inc(&cp->reset_task_pending);
1828 atomic_inc(&cp->reset_task_pending_all);
1829 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1830 schedule_work(&cp->reset_task);
1831#else
1832 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1833 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1834 schedule_work(&cp->reset_task);
1835#endif
1836 return 1;
1837}
1838
1839
1840
1841
1842#define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1843#define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1844static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1845 const int len)
1846{
1847 unsigned long off = addr + len;
1848
1849 if (CAS_TABORT(cp) == 1)
1850 return 0;
1851 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1852 return 0;
1853 return TX_TARGET_ABORT_LEN;
1854}
1855
1856static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1857{
1858 struct cas_tx_desc *txds;
1859 struct sk_buff **skbs;
1860 struct net_device *dev = cp->dev;
1861 int entry, count;
1862
1863 spin_lock(&cp->tx_lock[ring]);
1864 txds = cp->init_txds[ring];
1865 skbs = cp->tx_skbs[ring];
1866 entry = cp->tx_old[ring];
1867
1868 count = TX_BUFF_COUNT(ring, entry, limit);
1869 while (entry != limit) {
1870 struct sk_buff *skb = skbs[entry];
1871 dma_addr_t daddr;
1872 u32 dlen;
1873 int frag;
1874
1875 if (!skb) {
1876
1877 entry = TX_DESC_NEXT(ring, entry);
1878 continue;
1879 }
1880
1881
1882 count -= skb_shinfo(skb)->nr_frags +
1883 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1884 if (count < 0)
1885 break;
1886
1887 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1888 "tx[%d] done, slot %d\n", ring, entry);
1889
1890 skbs[entry] = NULL;
1891 cp->tx_tiny_use[ring][entry].nbufs = 0;
1892
1893 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1894 struct cas_tx_desc *txd = txds + entry;
1895
1896 daddr = le64_to_cpu(txd->buffer);
1897 dlen = CAS_VAL(TX_DESC_BUFLEN,
1898 le64_to_cpu(txd->control));
1899 pci_unmap_page(cp->pdev, daddr, dlen,
1900 PCI_DMA_TODEVICE);
1901 entry = TX_DESC_NEXT(ring, entry);
1902
1903
1904 if (cp->tx_tiny_use[ring][entry].used) {
1905 cp->tx_tiny_use[ring][entry].used = 0;
1906 entry = TX_DESC_NEXT(ring, entry);
1907 }
1908 }
1909
1910 spin_lock(&cp->stat_lock[ring]);
1911 cp->net_stats[ring].tx_packets++;
1912 cp->net_stats[ring].tx_bytes += skb->len;
1913 spin_unlock(&cp->stat_lock[ring]);
1914 dev_kfree_skb_irq(skb);
1915 }
1916 cp->tx_old[ring] = entry;
1917
1918
1919
1920
1921
1922 if (netif_queue_stopped(dev) &&
1923 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1924 netif_wake_queue(dev);
1925 spin_unlock(&cp->tx_lock[ring]);
1926}
1927
1928static void cas_tx(struct net_device *dev, struct cas *cp,
1929 u32 status)
1930{
1931 int limit, ring;
1932#ifdef USE_TX_COMPWB
1933 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1934#endif
1935 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1936 "tx interrupt, status: 0x%x, %llx\n",
1937 status, (unsigned long long)compwb);
1938
1939 for (ring = 0; ring < N_TX_RINGS; ring++) {
1940#ifdef USE_TX_COMPWB
1941
1942 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1943 CAS_VAL(TX_COMPWB_LSB, compwb);
1944 compwb = TX_COMPWB_NEXT(compwb);
1945#else
1946 limit = readl(cp->regs + REG_TX_COMPN(ring));
1947#endif
1948 if (cp->tx_old[ring] != limit)
1949 cas_tx_ringN(cp, ring, limit);
1950 }
1951}
1952
1953
1954static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1955 int entry, const u64 *words,
1956 struct sk_buff **skbref)
1957{
1958 int dlen, hlen, len, i, alloclen;
1959 int off, swivel = RX_SWIVEL_OFF_VAL;
1960 struct cas_page *page;
1961 struct sk_buff *skb;
1962 void *addr, *crcaddr;
1963 __sum16 csum;
1964 char *p;
1965
1966 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1967 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1968 len = hlen + dlen;
1969
1970 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1971 alloclen = len;
1972 else
1973 alloclen = max(hlen, RX_COPY_MIN);
1974
1975 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1976 if (skb == NULL)
1977 return -1;
1978
1979 *skbref = skb;
1980 skb_reserve(skb, swivel);
1981
1982 p = skb->data;
1983 addr = crcaddr = NULL;
1984 if (hlen) {
1985 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1986 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1987 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1988 swivel;
1989
1990 i = hlen;
1991 if (!dlen)
1992 i += cp->crc_size;
1993 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1994 PCI_DMA_FROMDEVICE);
1995 addr = cas_page_map(page->buffer);
1996 memcpy(p, addr + off, i);
1997 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1998 PCI_DMA_FROMDEVICE);
1999 cas_page_unmap(addr);
2000 RX_USED_ADD(page, 0x100);
2001 p += hlen;
2002 swivel = 0;
2003 }
2004
2005
2006 if (alloclen < (hlen + dlen)) {
2007 skb_frag_t *frag = skb_shinfo(skb)->frags;
2008
2009
2010 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2011 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2012 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2013
2014 hlen = min(cp->page_size - off, dlen);
2015 if (hlen < 0) {
2016 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2017 "rx page overflow: %d\n", hlen);
2018 dev_kfree_skb_irq(skb);
2019 return -1;
2020 }
2021 i = hlen;
2022 if (i == dlen)
2023 i += cp->crc_size;
2024 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2025 PCI_DMA_FROMDEVICE);
2026
2027
2028 swivel = 0;
2029 if (p == (char *) skb->data) {
2030 addr = cas_page_map(page->buffer);
2031 memcpy(p, addr + off, RX_COPY_MIN);
2032 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2033 PCI_DMA_FROMDEVICE);
2034 cas_page_unmap(addr);
2035 off += RX_COPY_MIN;
2036 swivel = RX_COPY_MIN;
2037 RX_USED_ADD(page, cp->mtu_stride);
2038 } else {
2039 RX_USED_ADD(page, hlen);
2040 }
2041 skb_put(skb, alloclen);
2042
2043 skb_shinfo(skb)->nr_frags++;
2044 skb->data_len += hlen - swivel;
2045 skb->truesize += hlen - swivel;
2046 skb->len += hlen - swivel;
2047
2048 __skb_frag_set_page(frag, page->buffer);
2049 __skb_frag_ref(frag);
2050 frag->page_offset = off;
2051 skb_frag_size_set(frag, hlen - swivel);
2052
2053
2054 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2055 hlen = dlen;
2056 off = 0;
2057
2058 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2059 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2060 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2061 hlen + cp->crc_size,
2062 PCI_DMA_FROMDEVICE);
2063 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2064 hlen + cp->crc_size,
2065 PCI_DMA_FROMDEVICE);
2066
2067 skb_shinfo(skb)->nr_frags++;
2068 skb->data_len += hlen;
2069 skb->len += hlen;
2070 frag++;
2071
2072 __skb_frag_set_page(frag, page->buffer);
2073 __skb_frag_ref(frag);
2074 frag->page_offset = 0;
2075 skb_frag_size_set(frag, hlen);
2076 RX_USED_ADD(page, hlen + cp->crc_size);
2077 }
2078
2079 if (cp->crc_size) {
2080 addr = cas_page_map(page->buffer);
2081 crcaddr = addr + off + hlen;
2082 }
2083
2084 } else {
2085
2086 if (!dlen)
2087 goto end_copy_pkt;
2088
2089 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2090 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2091 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2092 hlen = min(cp->page_size - off, dlen);
2093 if (hlen < 0) {
2094 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2095 "rx page overflow: %d\n", hlen);
2096 dev_kfree_skb_irq(skb);
2097 return -1;
2098 }
2099 i = hlen;
2100 if (i == dlen)
2101 i += cp->crc_size;
2102 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2103 PCI_DMA_FROMDEVICE);
2104 addr = cas_page_map(page->buffer);
2105 memcpy(p, addr + off, i);
2106 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2107 PCI_DMA_FROMDEVICE);
2108 cas_page_unmap(addr);
2109 if (p == (char *) skb->data)
2110 RX_USED_ADD(page, cp->mtu_stride);
2111 else
2112 RX_USED_ADD(page, i);
2113
2114
2115 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2116 p += hlen;
2117 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2118 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2119 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2120 dlen + cp->crc_size,
2121 PCI_DMA_FROMDEVICE);
2122 addr = cas_page_map(page->buffer);
2123 memcpy(p, addr, dlen + cp->crc_size);
2124 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2125 dlen + cp->crc_size,
2126 PCI_DMA_FROMDEVICE);
2127 cas_page_unmap(addr);
2128 RX_USED_ADD(page, dlen + cp->crc_size);
2129 }
2130end_copy_pkt:
2131 if (cp->crc_size) {
2132 addr = NULL;
2133 crcaddr = skb->data + alloclen;
2134 }
2135 skb_put(skb, alloclen);
2136 }
2137
2138 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2139 if (cp->crc_size) {
2140
2141 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2142 csum_unfold(csum)));
2143 if (addr)
2144 cas_page_unmap(addr);
2145 }
2146 skb->protocol = eth_type_trans(skb, cp->dev);
2147 if (skb->protocol == htons(ETH_P_IP)) {
2148 skb->csum = csum_unfold(~csum);
2149 skb->ip_summed = CHECKSUM_COMPLETE;
2150 } else
2151 skb_checksum_none_assert(skb);
2152 return len;
2153}
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2171 struct sk_buff *skb)
2172{
2173 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2174 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2175
2176
2177
2178
2179
2180 __skb_queue_tail(flow, skb);
2181 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2182 while ((skb = __skb_dequeue(flow))) {
2183 cas_skb_release(skb);
2184 }
2185 }
2186}
2187
2188
2189
2190
2191static void cas_post_page(struct cas *cp, const int ring, const int index)
2192{
2193 cas_page_t *new;
2194 int entry;
2195
2196 entry = cp->rx_old[ring];
2197
2198 new = cas_page_swap(cp, ring, index);
2199 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2200 cp->init_rxds[ring][entry].index =
2201 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2202 CAS_BASE(RX_INDEX_RING, ring));
2203
2204 entry = RX_DESC_ENTRY(ring, entry + 1);
2205 cp->rx_old[ring] = entry;
2206
2207 if (entry % 4)
2208 return;
2209
2210 if (ring == 0)
2211 writel(entry, cp->regs + REG_RX_KICK);
2212 else if ((N_RX_DESC_RINGS > 1) &&
2213 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2214 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2215}
2216
2217
2218
2219static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2220{
2221 unsigned int entry, last, count, released;
2222 int cluster;
2223 cas_page_t **page = cp->rx_pages[ring];
2224
2225 entry = cp->rx_old[ring];
2226
2227 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2228 "rxd[%d] interrupt, done: %d\n", ring, entry);
2229
2230 cluster = -1;
2231 count = entry & 0x3;
2232 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2233 released = 0;
2234 while (entry != last) {
2235
2236 if (page_count(page[entry]->buffer) > 1) {
2237 cas_page_t *new = cas_page_dequeue(cp);
2238 if (!new) {
2239
2240
2241
2242 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2243 if (!timer_pending(&cp->link_timer))
2244 mod_timer(&cp->link_timer, jiffies +
2245 CAS_LINK_FAST_TIMEOUT);
2246 cp->rx_old[ring] = entry;
2247 cp->rx_last[ring] = num ? num - released : 0;
2248 return -ENOMEM;
2249 }
2250 spin_lock(&cp->rx_inuse_lock);
2251 list_add(&page[entry]->list, &cp->rx_inuse_list);
2252 spin_unlock(&cp->rx_inuse_lock);
2253 cp->init_rxds[ring][entry].buffer =
2254 cpu_to_le64(new->dma_addr);
2255 page[entry] = new;
2256
2257 }
2258
2259 if (++count == 4) {
2260 cluster = entry;
2261 count = 0;
2262 }
2263 released++;
2264 entry = RX_DESC_ENTRY(ring, entry + 1);
2265 }
2266 cp->rx_old[ring] = entry;
2267
2268 if (cluster < 0)
2269 return 0;
2270
2271 if (ring == 0)
2272 writel(cluster, cp->regs + REG_RX_KICK);
2273 else if ((N_RX_DESC_RINGS > 1) &&
2274 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2275 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2276 return 0;
2277}
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2293{
2294 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2295 int entry, drops;
2296 int npackets = 0;
2297
2298 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2299 "rx[%d] interrupt, done: %d/%d\n",
2300 ring,
2301 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2302
2303 entry = cp->rx_new[ring];
2304 drops = 0;
2305 while (1) {
2306 struct cas_rx_comp *rxc = rxcs + entry;
2307 struct sk_buff *uninitialized_var(skb);
2308 int type, len;
2309 u64 words[4];
2310 int i, dring;
2311
2312 words[0] = le64_to_cpu(rxc->word1);
2313 words[1] = le64_to_cpu(rxc->word2);
2314 words[2] = le64_to_cpu(rxc->word3);
2315 words[3] = le64_to_cpu(rxc->word4);
2316
2317
2318 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2319 if (type == 0)
2320 break;
2321
2322
2323 if (words[3] & RX_COMP4_ZERO) {
2324 break;
2325 }
2326
2327
2328 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2329 spin_lock(&cp->stat_lock[ring]);
2330 cp->net_stats[ring].rx_errors++;
2331 if (words[3] & RX_COMP4_LEN_MISMATCH)
2332 cp->net_stats[ring].rx_length_errors++;
2333 if (words[3] & RX_COMP4_BAD)
2334 cp->net_stats[ring].rx_crc_errors++;
2335 spin_unlock(&cp->stat_lock[ring]);
2336
2337
2338 drop_it:
2339 spin_lock(&cp->stat_lock[ring]);
2340 ++cp->net_stats[ring].rx_dropped;
2341 spin_unlock(&cp->stat_lock[ring]);
2342 goto next;
2343 }
2344
2345 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2346 if (len < 0) {
2347 ++drops;
2348 goto drop_it;
2349 }
2350
2351
2352
2353
2354 if (RX_DONT_BATCH || (type == 0x2)) {
2355
2356 cas_skb_release(skb);
2357 } else {
2358 cas_rx_flow_pkt(cp, words, skb);
2359 }
2360
2361 spin_lock(&cp->stat_lock[ring]);
2362 cp->net_stats[ring].rx_packets++;
2363 cp->net_stats[ring].rx_bytes += len;
2364 spin_unlock(&cp->stat_lock[ring]);
2365
2366 next:
2367 npackets++;
2368
2369
2370 if (words[0] & RX_COMP1_RELEASE_HDR) {
2371 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2372 dring = CAS_VAL(RX_INDEX_RING, i);
2373 i = CAS_VAL(RX_INDEX_NUM, i);
2374 cas_post_page(cp, dring, i);
2375 }
2376
2377 if (words[0] & RX_COMP1_RELEASE_DATA) {
2378 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2379 dring = CAS_VAL(RX_INDEX_RING, i);
2380 i = CAS_VAL(RX_INDEX_NUM, i);
2381 cas_post_page(cp, dring, i);
2382 }
2383
2384 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2385 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2386 dring = CAS_VAL(RX_INDEX_RING, i);
2387 i = CAS_VAL(RX_INDEX_NUM, i);
2388 cas_post_page(cp, dring, i);
2389 }
2390
2391
2392 entry = RX_COMP_ENTRY(ring, entry + 1 +
2393 CAS_VAL(RX_COMP1_SKIP, words[0]));
2394#ifdef USE_NAPI
2395 if (budget && (npackets >= budget))
2396 break;
2397#endif
2398 }
2399 cp->rx_new[ring] = entry;
2400
2401 if (drops)
2402 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2403 return npackets;
2404}
2405
2406
2407
2408static void cas_post_rxcs_ringN(struct net_device *dev,
2409 struct cas *cp, int ring)
2410{
2411 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2412 int last, entry;
2413
2414 last = cp->rx_cur[ring];
2415 entry = cp->rx_new[ring];
2416 netif_printk(cp, intr, KERN_DEBUG, dev,
2417 "rxc[%d] interrupt, done: %d/%d\n",
2418 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2419
2420
2421 while (last != entry) {
2422 cas_rxc_init(rxc + last);
2423 last = RX_COMP_ENTRY(ring, last + 1);
2424 }
2425 cp->rx_cur[ring] = last;
2426
2427 if (ring == 0)
2428 writel(last, cp->regs + REG_RX_COMP_TAIL);
2429 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2430 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2431}
2432
2433
2434
2435
2436
2437
2438#if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2439static inline void cas_handle_irqN(struct net_device *dev,
2440 struct cas *cp, const u32 status,
2441 const int ring)
2442{
2443 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2444 cas_post_rxcs_ringN(dev, cp, ring);
2445}
2446
2447static irqreturn_t cas_interruptN(int irq, void *dev_id)
2448{
2449 struct net_device *dev = dev_id;
2450 struct cas *cp = netdev_priv(dev);
2451 unsigned long flags;
2452 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2453 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2454
2455
2456 if (status == 0)
2457 return IRQ_NONE;
2458
2459 spin_lock_irqsave(&cp->lock, flags);
2460 if (status & INTR_RX_DONE_ALT) {
2461#ifdef USE_NAPI
2462 cas_mask_intr(cp);
2463 napi_schedule(&cp->napi);
2464#else
2465 cas_rx_ringN(cp, ring, 0);
2466#endif
2467 status &= ~INTR_RX_DONE_ALT;
2468 }
2469
2470 if (status)
2471 cas_handle_irqN(dev, cp, status, ring);
2472 spin_unlock_irqrestore(&cp->lock, flags);
2473 return IRQ_HANDLED;
2474}
2475#endif
2476
2477#ifdef USE_PCI_INTB
2478
2479static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2480{
2481 if (status & INTR_RX_BUF_UNAVAIL_1) {
2482
2483
2484 cas_post_rxds_ringN(cp, 1, 0);
2485 spin_lock(&cp->stat_lock[1]);
2486 cp->net_stats[1].rx_dropped++;
2487 spin_unlock(&cp->stat_lock[1]);
2488 }
2489
2490 if (status & INTR_RX_BUF_AE_1)
2491 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2492 RX_AE_FREEN_VAL(1));
2493
2494 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2495 cas_post_rxcs_ringN(cp, 1);
2496}
2497
2498
2499static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2500{
2501 struct net_device *dev = dev_id;
2502 struct cas *cp = netdev_priv(dev);
2503 unsigned long flags;
2504 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2505
2506
2507 if (status == 0)
2508 return IRQ_NONE;
2509
2510 spin_lock_irqsave(&cp->lock, flags);
2511 if (status & INTR_RX_DONE_ALT) {
2512#ifdef USE_NAPI
2513 cas_mask_intr(cp);
2514 napi_schedule(&cp->napi);
2515#else
2516 cas_rx_ringN(cp, 1, 0);
2517#endif
2518 status &= ~INTR_RX_DONE_ALT;
2519 }
2520 if (status)
2521 cas_handle_irq1(cp, status);
2522 spin_unlock_irqrestore(&cp->lock, flags);
2523 return IRQ_HANDLED;
2524}
2525#endif
2526
2527static inline void cas_handle_irq(struct net_device *dev,
2528 struct cas *cp, const u32 status)
2529{
2530
2531 if (status & INTR_ERROR_MASK)
2532 cas_abnormal_irq(dev, cp, status);
2533
2534 if (status & INTR_RX_BUF_UNAVAIL) {
2535
2536
2537
2538 cas_post_rxds_ringN(cp, 0, 0);
2539 spin_lock(&cp->stat_lock[0]);
2540 cp->net_stats[0].rx_dropped++;
2541 spin_unlock(&cp->stat_lock[0]);
2542 } else if (status & INTR_RX_BUF_AE) {
2543 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2544 RX_AE_FREEN_VAL(0));
2545 }
2546
2547 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2548 cas_post_rxcs_ringN(dev, cp, 0);
2549}
2550
2551static irqreturn_t cas_interrupt(int irq, void *dev_id)
2552{
2553 struct net_device *dev = dev_id;
2554 struct cas *cp = netdev_priv(dev);
2555 unsigned long flags;
2556 u32 status = readl(cp->regs + REG_INTR_STATUS);
2557
2558 if (status == 0)
2559 return IRQ_NONE;
2560
2561 spin_lock_irqsave(&cp->lock, flags);
2562 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2563 cas_tx(dev, cp, status);
2564 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2565 }
2566
2567 if (status & INTR_RX_DONE) {
2568#ifdef USE_NAPI
2569 cas_mask_intr(cp);
2570 napi_schedule(&cp->napi);
2571#else
2572 cas_rx_ringN(cp, 0, 0);
2573#endif
2574 status &= ~INTR_RX_DONE;
2575 }
2576
2577 if (status)
2578 cas_handle_irq(dev, cp, status);
2579 spin_unlock_irqrestore(&cp->lock, flags);
2580 return IRQ_HANDLED;
2581}
2582
2583
2584#ifdef USE_NAPI
2585static int cas_poll(struct napi_struct *napi, int budget)
2586{
2587 struct cas *cp = container_of(napi, struct cas, napi);
2588 struct net_device *dev = cp->dev;
2589 int i, enable_intr, credits;
2590 u32 status = readl(cp->regs + REG_INTR_STATUS);
2591 unsigned long flags;
2592
2593 spin_lock_irqsave(&cp->lock, flags);
2594 cas_tx(dev, cp, status);
2595 spin_unlock_irqrestore(&cp->lock, flags);
2596
2597
2598
2599
2600
2601
2602
2603
2604 enable_intr = 1;
2605 credits = 0;
2606 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2607 int j;
2608 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2609 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2610 if (credits >= budget) {
2611 enable_intr = 0;
2612 goto rx_comp;
2613 }
2614 }
2615 }
2616
2617rx_comp:
2618
2619 spin_lock_irqsave(&cp->lock, flags);
2620 if (status)
2621 cas_handle_irq(dev, cp, status);
2622
2623#ifdef USE_PCI_INTB
2624 if (N_RX_COMP_RINGS > 1) {
2625 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2626 if (status)
2627 cas_handle_irq1(dev, cp, status);
2628 }
2629#endif
2630
2631#ifdef USE_PCI_INTC
2632 if (N_RX_COMP_RINGS > 2) {
2633 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2634 if (status)
2635 cas_handle_irqN(dev, cp, status, 2);
2636 }
2637#endif
2638
2639#ifdef USE_PCI_INTD
2640 if (N_RX_COMP_RINGS > 3) {
2641 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2642 if (status)
2643 cas_handle_irqN(dev, cp, status, 3);
2644 }
2645#endif
2646 spin_unlock_irqrestore(&cp->lock, flags);
2647 if (enable_intr) {
2648 napi_complete(napi);
2649 cas_unmask_intr(cp);
2650 }
2651 return credits;
2652}
2653#endif
2654
2655#ifdef CONFIG_NET_POLL_CONTROLLER
2656static void cas_netpoll(struct net_device *dev)
2657{
2658 struct cas *cp = netdev_priv(dev);
2659
2660 cas_disable_irq(cp, 0);
2661 cas_interrupt(cp->pdev->irq, dev);
2662 cas_enable_irq(cp, 0);
2663
2664#ifdef USE_PCI_INTB
2665 if (N_RX_COMP_RINGS > 1) {
2666
2667 }
2668#endif
2669#ifdef USE_PCI_INTC
2670 if (N_RX_COMP_RINGS > 2) {
2671
2672 }
2673#endif
2674#ifdef USE_PCI_INTD
2675 if (N_RX_COMP_RINGS > 3) {
2676
2677 }
2678#endif
2679}
2680#endif
2681
2682static void cas_tx_timeout(struct net_device *dev)
2683{
2684 struct cas *cp = netdev_priv(dev);
2685
2686 netdev_err(dev, "transmit timed out, resetting\n");
2687 if (!cp->hw_running) {
2688 netdev_err(dev, "hrm.. hw not running!\n");
2689 return;
2690 }
2691
2692 netdev_err(dev, "MIF_STATE[%08x]\n",
2693 readl(cp->regs + REG_MIF_STATE_MACHINE));
2694
2695 netdev_err(dev, "MAC_STATE[%08x]\n",
2696 readl(cp->regs + REG_MAC_STATE_MACHINE));
2697
2698 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2699 readl(cp->regs + REG_TX_CFG),
2700 readl(cp->regs + REG_MAC_TX_STATUS),
2701 readl(cp->regs + REG_MAC_TX_CFG),
2702 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2703 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2704 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2705 readl(cp->regs + REG_TX_SM_1),
2706 readl(cp->regs + REG_TX_SM_2));
2707
2708 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2709 readl(cp->regs + REG_RX_CFG),
2710 readl(cp->regs + REG_MAC_RX_STATUS),
2711 readl(cp->regs + REG_MAC_RX_CFG));
2712
2713 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2714 readl(cp->regs + REG_HP_STATE_MACHINE),
2715 readl(cp->regs + REG_HP_STATUS0),
2716 readl(cp->regs + REG_HP_STATUS1),
2717 readl(cp->regs + REG_HP_STATUS2));
2718
2719#if 1
2720 atomic_inc(&cp->reset_task_pending);
2721 atomic_inc(&cp->reset_task_pending_all);
2722 schedule_work(&cp->reset_task);
2723#else
2724 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2725 schedule_work(&cp->reset_task);
2726#endif
2727}
2728
2729static inline int cas_intme(int ring, int entry)
2730{
2731
2732 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2733 return 1;
2734 return 0;
2735}
2736
2737
2738static void cas_write_txd(struct cas *cp, int ring, int entry,
2739 dma_addr_t mapping, int len, u64 ctrl, int last)
2740{
2741 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2742
2743 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2744 if (cas_intme(ring, entry))
2745 ctrl |= TX_DESC_INTME;
2746 if (last)
2747 ctrl |= TX_DESC_EOF;
2748 txd->control = cpu_to_le64(ctrl);
2749 txd->buffer = cpu_to_le64(mapping);
2750}
2751
2752static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2753 const int entry)
2754{
2755 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2756}
2757
2758static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2759 const int entry, const int tentry)
2760{
2761 cp->tx_tiny_use[ring][tentry].nbufs++;
2762 cp->tx_tiny_use[ring][entry].used = 1;
2763 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2764}
2765
2766static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2767 struct sk_buff *skb)
2768{
2769 struct net_device *dev = cp->dev;
2770 int entry, nr_frags, frag, tabort, tentry;
2771 dma_addr_t mapping;
2772 unsigned long flags;
2773 u64 ctrl;
2774 u32 len;
2775
2776 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2777
2778
2779 if (TX_BUFFS_AVAIL(cp, ring) <=
2780 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2781 netif_stop_queue(dev);
2782 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2783 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2784 return 1;
2785 }
2786
2787 ctrl = 0;
2788 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2789 const u64 csum_start_off = skb_checksum_start_offset(skb);
2790 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2791
2792 ctrl = TX_DESC_CSUM_EN |
2793 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2794 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2795 }
2796
2797 entry = cp->tx_new[ring];
2798 cp->tx_skbs[ring][entry] = skb;
2799
2800 nr_frags = skb_shinfo(skb)->nr_frags;
2801 len = skb_headlen(skb);
2802 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2803 offset_in_page(skb->data), len,
2804 PCI_DMA_TODEVICE);
2805
2806 tentry = entry;
2807 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2808 if (unlikely(tabort)) {
2809
2810 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2811 ctrl | TX_DESC_SOF, 0);
2812 entry = TX_DESC_NEXT(ring, entry);
2813
2814 skb_copy_from_linear_data_offset(skb, len - tabort,
2815 tx_tiny_buf(cp, ring, entry), tabort);
2816 mapping = tx_tiny_map(cp, ring, entry, tentry);
2817 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2818 (nr_frags == 0));
2819 } else {
2820 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2821 TX_DESC_SOF, (nr_frags == 0));
2822 }
2823 entry = TX_DESC_NEXT(ring, entry);
2824
2825 for (frag = 0; frag < nr_frags; frag++) {
2826 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2827
2828 len = skb_frag_size(fragp);
2829 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2830 DMA_TO_DEVICE);
2831
2832 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2833 if (unlikely(tabort)) {
2834 void *addr;
2835
2836
2837 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2838 ctrl, 0);
2839 entry = TX_DESC_NEXT(ring, entry);
2840
2841 addr = cas_page_map(skb_frag_page(fragp));
2842 memcpy(tx_tiny_buf(cp, ring, entry),
2843 addr + fragp->page_offset + len - tabort,
2844 tabort);
2845 cas_page_unmap(addr);
2846 mapping = tx_tiny_map(cp, ring, entry, tentry);
2847 len = tabort;
2848 }
2849
2850 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2851 (frag + 1 == nr_frags));
2852 entry = TX_DESC_NEXT(ring, entry);
2853 }
2854
2855 cp->tx_new[ring] = entry;
2856 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2857 netif_stop_queue(dev);
2858
2859 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2860 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2861 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2862 writel(entry, cp->regs + REG_TX_KICKN(ring));
2863 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2864 return 0;
2865}
2866
2867static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2868{
2869 struct cas *cp = netdev_priv(dev);
2870
2871
2872
2873
2874 static int ring;
2875
2876 if (skb_padto(skb, cp->min_frame_size))
2877 return NETDEV_TX_OK;
2878
2879
2880
2881
2882 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2883 return NETDEV_TX_BUSY;
2884 return NETDEV_TX_OK;
2885}
2886
2887static void cas_init_tx_dma(struct cas *cp)
2888{
2889 u64 desc_dma = cp->block_dvma;
2890 unsigned long off;
2891 u32 val;
2892 int i;
2893
2894
2895#ifdef USE_TX_COMPWB
2896 off = offsetof(struct cas_init_block, tx_compwb);
2897 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2898 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2899#endif
2900
2901
2902
2903
2904 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2905 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2906 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2907 TX_CFG_INTR_COMPWB_DIS;
2908
2909
2910 for (i = 0; i < MAX_TX_RINGS; i++) {
2911 off = (unsigned long) cp->init_txds[i] -
2912 (unsigned long) cp->init_block;
2913
2914 val |= CAS_TX_RINGN_BASE(i);
2915 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2916 writel((desc_dma + off) & 0xffffffff, cp->regs +
2917 REG_TX_DBN_LOW(i));
2918
2919
2920
2921 }
2922 writel(val, cp->regs + REG_TX_CFG);
2923
2924
2925
2926
2927#ifdef USE_QOS
2928 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2929 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2930 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2931 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2932#else
2933 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2934 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2935 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2936 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2937#endif
2938}
2939
2940
2941static inline void cas_init_dma(struct cas *cp)
2942{
2943 cas_init_tx_dma(cp);
2944 cas_init_rx_dma(cp);
2945}
2946
2947static void cas_process_mc_list(struct cas *cp)
2948{
2949 u16 hash_table[16];
2950 u32 crc;
2951 struct netdev_hw_addr *ha;
2952 int i = 1;
2953
2954 memset(hash_table, 0, sizeof(hash_table));
2955 netdev_for_each_mc_addr(ha, cp->dev) {
2956 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2957
2958
2959
2960 writel((ha->addr[4] << 8) | ha->addr[5],
2961 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2962 writel((ha->addr[2] << 8) | ha->addr[3],
2963 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2964 writel((ha->addr[0] << 8) | ha->addr[1],
2965 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2966 i++;
2967 }
2968 else {
2969
2970
2971
2972 crc = ether_crc_le(ETH_ALEN, ha->addr);
2973 crc >>= 24;
2974 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2975 }
2976 }
2977 for (i = 0; i < 16; i++)
2978 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2979}
2980
2981
2982static u32 cas_setup_multicast(struct cas *cp)
2983{
2984 u32 rxcfg = 0;
2985 int i;
2986
2987 if (cp->dev->flags & IFF_PROMISC) {
2988 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2989
2990 } else if (cp->dev->flags & IFF_ALLMULTI) {
2991 for (i=0; i < 16; i++)
2992 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2993 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2994
2995 } else {
2996 cas_process_mc_list(cp);
2997 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2998 }
2999
3000 return rxcfg;
3001}
3002
3003
3004static void cas_clear_mac_err(struct cas *cp)
3005{
3006 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3007 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3008 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3009 writel(0, cp->regs + REG_MAC_COLL_LATE);
3010 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3011 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3012 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3013 writel(0, cp->regs + REG_MAC_LEN_ERR);
3014 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3015 writel(0, cp->regs + REG_MAC_FCS_ERR);
3016 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3017}
3018
3019
3020static void cas_mac_reset(struct cas *cp)
3021{
3022 int i;
3023
3024
3025 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3026 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3027
3028
3029 i = STOP_TRIES;
3030 while (i-- > 0) {
3031 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3032 break;
3033 udelay(10);
3034 }
3035
3036
3037 i = STOP_TRIES;
3038 while (i-- > 0) {
3039 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3040 break;
3041 udelay(10);
3042 }
3043
3044 if (readl(cp->regs + REG_MAC_TX_RESET) |
3045 readl(cp->regs + REG_MAC_RX_RESET))
3046 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3047 readl(cp->regs + REG_MAC_TX_RESET),
3048 readl(cp->regs + REG_MAC_RX_RESET),
3049 readl(cp->regs + REG_MAC_STATE_MACHINE));
3050}
3051
3052
3053
3054static void cas_init_mac(struct cas *cp)
3055{
3056 unsigned char *e = &cp->dev->dev_addr[0];
3057 int i;
3058 cas_mac_reset(cp);
3059
3060
3061 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3062
3063
3064#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3065
3066
3067
3068 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3069 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3070#endif
3071
3072 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3073
3074 writel(0x00, cp->regs + REG_MAC_IPG0);
3075 writel(0x08, cp->regs + REG_MAC_IPG1);
3076 writel(0x04, cp->regs + REG_MAC_IPG2);
3077
3078
3079 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3080
3081
3082 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3083
3084
3085
3086
3087
3088 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3089 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3090 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3091 cp->regs + REG_MAC_FRAMESIZE_MAX);
3092
3093
3094
3095
3096
3097 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3098 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3099 else
3100 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3101 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3102 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3103 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3104
3105 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3106
3107 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3108 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3109 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3110 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3111 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3112
3113
3114 for (i = 0; i < 45; i++)
3115 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3116
3117 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3118 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3119 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3120
3121 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3122 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3123 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3124
3125 cp->mac_rx_cfg = cas_setup_multicast(cp);
3126
3127 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3128 cas_clear_mac_err(cp);
3129 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3130
3131
3132
3133
3134
3135 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3136 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3137
3138
3139
3140
3141 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3142}
3143
3144
3145static void cas_init_pause_thresholds(struct cas *cp)
3146{
3147
3148
3149
3150 if (cp->rx_fifo_size <= (2 * 1024)) {
3151 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3152 } else {
3153 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3154 if (max_frame * 3 > cp->rx_fifo_size) {
3155 cp->rx_pause_off = 7104;
3156 cp->rx_pause_on = 960;
3157 } else {
3158 int off = (cp->rx_fifo_size - (max_frame * 2));
3159 int on = off - max_frame;
3160 cp->rx_pause_off = off;
3161 cp->rx_pause_on = on;
3162 }
3163 }
3164}
3165
3166static int cas_vpd_match(const void __iomem *p, const char *str)
3167{
3168 int len = strlen(str) + 1;
3169 int i;
3170
3171 for (i = 0; i < len; i++) {
3172 if (readb(p + i) != str[i])
3173 return 0;
3174 }
3175 return 1;
3176}
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3191 const int offset)
3192{
3193 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3194 void __iomem *base, *kstart;
3195 int i, len;
3196 int found = 0;
3197#define VPD_FOUND_MAC 0x01
3198#define VPD_FOUND_PHY 0x02
3199
3200 int phy_type = CAS_PHY_MII_MDIO0;
3201 int mac_off = 0;
3202
3203#if defined(CONFIG_SPARC)
3204 const unsigned char *addr;
3205#endif
3206
3207
3208 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3209 cp->regs + REG_BIM_LOCAL_DEV_EN);
3210
3211
3212 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3213 goto use_random_mac_addr;
3214
3215
3216 base = NULL;
3217 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3218
3219 if ((readb(p + i + 0) == 0x50) &&
3220 (readb(p + i + 1) == 0x43) &&
3221 (readb(p + i + 2) == 0x49) &&
3222 (readb(p + i + 3) == 0x52)) {
3223 base = p + (readb(p + i + 8) |
3224 (readb(p + i + 9) << 8));
3225 break;
3226 }
3227 }
3228
3229 if (!base || (readb(base) != 0x82))
3230 goto use_random_mac_addr;
3231
3232 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3233 while (i < EXPANSION_ROM_SIZE) {
3234 if (readb(base + i) != 0x90)
3235 goto use_random_mac_addr;
3236
3237
3238 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3239
3240
3241 kstart = base + i + 3;
3242 p = kstart;
3243 while ((p - kstart) < len) {
3244 int klen = readb(p + 2);
3245 int j;
3246 char type;
3247
3248 p += 3;
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287 if (readb(p) != 'I')
3288 goto next;
3289
3290
3291 type = readb(p + 3);
3292 if (type == 'B') {
3293 if ((klen == 29) && readb(p + 4) == 6 &&
3294 cas_vpd_match(p + 5,
3295 "local-mac-address")) {
3296 if (mac_off++ > offset)
3297 goto next;
3298
3299
3300 for (j = 0; j < 6; j++)
3301 dev_addr[j] =
3302 readb(p + 23 + j);
3303 goto found_mac;
3304 }
3305 }
3306
3307 if (type != 'S')
3308 goto next;
3309
3310#ifdef USE_ENTROPY_DEV
3311 if ((klen == 24) &&
3312 cas_vpd_match(p + 5, "entropy-dev") &&
3313 cas_vpd_match(p + 17, "vms110")) {
3314 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3315 goto next;
3316 }
3317#endif
3318
3319 if (found & VPD_FOUND_PHY)
3320 goto next;
3321
3322 if ((klen == 18) && readb(p + 4) == 4 &&
3323 cas_vpd_match(p + 5, "phy-type")) {
3324 if (cas_vpd_match(p + 14, "pcs")) {
3325 phy_type = CAS_PHY_SERDES;
3326 goto found_phy;
3327 }
3328 }
3329
3330 if ((klen == 23) && readb(p + 4) == 4 &&
3331 cas_vpd_match(p + 5, "phy-interface")) {
3332 if (cas_vpd_match(p + 19, "pcs")) {
3333 phy_type = CAS_PHY_SERDES;
3334 goto found_phy;
3335 }
3336 }
3337found_mac:
3338 found |= VPD_FOUND_MAC;
3339 goto next;
3340
3341found_phy:
3342 found |= VPD_FOUND_PHY;
3343
3344next:
3345 p += klen;
3346 }
3347 i += len + 3;
3348 }
3349
3350use_random_mac_addr:
3351 if (found & VPD_FOUND_MAC)
3352 goto done;
3353
3354#if defined(CONFIG_SPARC)
3355 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3356 if (addr != NULL) {
3357 memcpy(dev_addr, addr, 6);
3358 goto done;
3359 }
3360#endif
3361
3362
3363 pr_info("MAC address not found in ROM VPD\n");
3364 dev_addr[0] = 0x08;
3365 dev_addr[1] = 0x00;
3366 dev_addr[2] = 0x20;
3367 get_random_bytes(dev_addr + 3, 3);
3368
3369done:
3370 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3371 return phy_type;
3372}
3373
3374
3375static void cas_check_pci_invariants(struct cas *cp)
3376{
3377 struct pci_dev *pdev = cp->pdev;
3378
3379 cp->cas_flags = 0;
3380 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3381 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3382 if (pdev->revision >= CAS_ID_REVPLUS)
3383 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3384 if (pdev->revision < CAS_ID_REVPLUS02u)
3385 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3386
3387
3388
3389
3390 if (pdev->revision < CAS_ID_REV2)
3391 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3392 } else {
3393
3394 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3395
3396
3397
3398
3399 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3400 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3401 cp->cas_flags |= CAS_FLAG_SATURN;
3402 }
3403}
3404
3405
3406static int cas_check_invariants(struct cas *cp)
3407{
3408 struct pci_dev *pdev = cp->pdev;
3409 u32 cfg;
3410 int i;
3411
3412
3413 cp->page_order = 0;
3414#ifdef USE_PAGE_ORDER
3415 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3416
3417 struct page *page = alloc_pages(GFP_ATOMIC,
3418 CAS_JUMBO_PAGE_SHIFT -
3419 PAGE_SHIFT);
3420 if (page) {
3421 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3422 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3423 } else {
3424 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3425 }
3426 }
3427#endif
3428 cp->page_size = (PAGE_SIZE << cp->page_order);
3429
3430
3431 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3432 cp->rx_fifo_size = RX_FIFO_SIZE;
3433
3434
3435
3436
3437 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3438 PCI_SLOT(pdev->devfn));
3439 if (cp->phy_type & CAS_PHY_SERDES) {
3440 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3441 return 0;
3442 }
3443
3444
3445 cfg = readl(cp->regs + REG_MIF_CFG);
3446 if (cfg & MIF_CFG_MDIO_1) {
3447 cp->phy_type = CAS_PHY_MII_MDIO1;
3448 } else if (cfg & MIF_CFG_MDIO_0) {
3449 cp->phy_type = CAS_PHY_MII_MDIO0;
3450 }
3451
3452 cas_mif_poll(cp, 0);
3453 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3454
3455 for (i = 0; i < 32; i++) {
3456 u32 phy_id;
3457 int j;
3458
3459 for (j = 0; j < 3; j++) {
3460 cp->phy_addr = i;
3461 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3462 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3463 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3464 cp->phy_id = phy_id;
3465 goto done;
3466 }
3467 }
3468 }
3469 pr_err("MII phy did not respond [%08x]\n",
3470 readl(cp->regs + REG_MIF_STATE_MACHINE));
3471 return -1;
3472
3473done:
3474
3475 cfg = cas_phy_read(cp, MII_BMSR);
3476 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3477 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3478 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3479 return 0;
3480}
3481
3482
3483static inline void cas_start_dma(struct cas *cp)
3484{
3485 int i;
3486 u32 val;
3487 int txfailed = 0;
3488
3489
3490 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3491 writel(val, cp->regs + REG_TX_CFG);
3492 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3493 writel(val, cp->regs + REG_RX_CFG);
3494
3495
3496 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3497 writel(val, cp->regs + REG_MAC_TX_CFG);
3498 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3499 writel(val, cp->regs + REG_MAC_RX_CFG);
3500
3501 i = STOP_TRIES;
3502 while (i-- > 0) {
3503 val = readl(cp->regs + REG_MAC_TX_CFG);
3504 if ((val & MAC_TX_CFG_EN))
3505 break;
3506 udelay(10);
3507 }
3508 if (i < 0) txfailed = 1;
3509 i = STOP_TRIES;
3510 while (i-- > 0) {
3511 val = readl(cp->regs + REG_MAC_RX_CFG);
3512 if ((val & MAC_RX_CFG_EN)) {
3513 if (txfailed) {
3514 netdev_err(cp->dev,
3515 "enabling mac failed [tx:%08x:%08x]\n",
3516 readl(cp->regs + REG_MIF_STATE_MACHINE),
3517 readl(cp->regs + REG_MAC_STATE_MACHINE));
3518 }
3519 goto enable_rx_done;
3520 }
3521 udelay(10);
3522 }
3523 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3524 (txfailed ? "tx,rx" : "rx"),
3525 readl(cp->regs + REG_MIF_STATE_MACHINE),
3526 readl(cp->regs + REG_MAC_STATE_MACHINE));
3527
3528enable_rx_done:
3529 cas_unmask_intr(cp);
3530 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3531 writel(0, cp->regs + REG_RX_COMP_TAIL);
3532
3533 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3534 if (N_RX_DESC_RINGS > 1)
3535 writel(RX_DESC_RINGN_SIZE(1) - 4,
3536 cp->regs + REG_PLUS_RX_KICK1);
3537
3538 for (i = 1; i < N_RX_COMP_RINGS; i++)
3539 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3540 }
3541}
3542
3543
3544static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3545 int *pause)
3546{
3547 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3548 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3549 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3550 if (val & PCS_MII_LPA_ASYM_PAUSE)
3551 *pause |= 0x10;
3552 *spd = 1000;
3553}
3554
3555
3556static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3557 int *pause)
3558{
3559 u32 val;
3560
3561 *fd = 0;
3562 *spd = 10;
3563 *pause = 0;
3564
3565
3566 val = cas_phy_read(cp, MII_LPA);
3567 if (val & CAS_LPA_PAUSE)
3568 *pause = 0x01;
3569
3570 if (val & CAS_LPA_ASYM_PAUSE)
3571 *pause |= 0x10;
3572
3573 if (val & LPA_DUPLEX)
3574 *fd = 1;
3575 if (val & LPA_100)
3576 *spd = 100;
3577
3578 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3579 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3580 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3581 *spd = 1000;
3582 if (val & CAS_LPA_1000FULL)
3583 *fd = 1;
3584 }
3585}
3586
3587
3588
3589
3590
3591
3592static void cas_set_link_modes(struct cas *cp)
3593{
3594 u32 val;
3595 int full_duplex, speed, pause;
3596
3597 full_duplex = 0;
3598 speed = 10;
3599 pause = 0;
3600
3601 if (CAS_PHY_MII(cp->phy_type)) {
3602 cas_mif_poll(cp, 0);
3603 val = cas_phy_read(cp, MII_BMCR);
3604 if (val & BMCR_ANENABLE) {
3605 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3606 &pause);
3607 } else {
3608 if (val & BMCR_FULLDPLX)
3609 full_duplex = 1;
3610
3611 if (val & BMCR_SPEED100)
3612 speed = 100;
3613 else if (val & CAS_BMCR_SPEED1000)
3614 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3615 1000 : 100;
3616 }
3617 cas_mif_poll(cp, 1);
3618
3619 } else {
3620 val = readl(cp->regs + REG_PCS_MII_CTRL);
3621 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3622 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3623 if (val & PCS_MII_CTRL_DUPLEX)
3624 full_duplex = 1;
3625 }
3626 }
3627
3628 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3629 speed, full_duplex ? "full" : "half");
3630
3631 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3632 if (CAS_PHY_MII(cp->phy_type)) {
3633 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3634 if (!full_duplex)
3635 val |= MAC_XIF_DISABLE_ECHO;
3636 }
3637 if (full_duplex)
3638 val |= MAC_XIF_FDPLX_LED;
3639 if (speed == 1000)
3640 val |= MAC_XIF_GMII_MODE;
3641 writel(val, cp->regs + REG_MAC_XIF_CFG);
3642
3643
3644 val = MAC_TX_CFG_IPG_EN;
3645 if (full_duplex) {
3646 val |= MAC_TX_CFG_IGNORE_CARRIER;
3647 val |= MAC_TX_CFG_IGNORE_COLL;
3648 } else {
3649#ifndef USE_CSMA_CD_PROTO
3650 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3651 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3652#endif
3653 }
3654
3655
3656
3657
3658
3659
3660
3661 if ((speed == 1000) && !full_duplex) {
3662 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3663 cp->regs + REG_MAC_TX_CFG);
3664
3665 val = readl(cp->regs + REG_MAC_RX_CFG);
3666 val &= ~MAC_RX_CFG_STRIP_FCS;
3667 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3668 cp->regs + REG_MAC_RX_CFG);
3669
3670 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3671
3672 cp->crc_size = 4;
3673
3674 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3675
3676 } else {
3677 writel(val, cp->regs + REG_MAC_TX_CFG);
3678
3679
3680
3681
3682 val = readl(cp->regs + REG_MAC_RX_CFG);
3683 if (full_duplex) {
3684 val |= MAC_RX_CFG_STRIP_FCS;
3685 cp->crc_size = 0;
3686 cp->min_frame_size = CAS_MIN_MTU;
3687 } else {
3688 val &= ~MAC_RX_CFG_STRIP_FCS;
3689 cp->crc_size = 4;
3690 cp->min_frame_size = CAS_MIN_FRAME;
3691 }
3692 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3693 cp->regs + REG_MAC_RX_CFG);
3694 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3695 }
3696
3697 if (netif_msg_link(cp)) {
3698 if (pause & 0x01) {
3699 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3700 cp->rx_fifo_size,
3701 cp->rx_pause_off,
3702 cp->rx_pause_on);
3703 } else if (pause & 0x10) {
3704 netdev_info(cp->dev, "TX pause enabled\n");
3705 } else {
3706 netdev_info(cp->dev, "Pause is disabled\n");
3707 }
3708 }
3709
3710 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3711 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3712 if (pause) {
3713 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3714 if (pause & 0x01) {
3715 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3716 }
3717 }
3718 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3719 cas_start_dma(cp);
3720}
3721
3722
3723static void cas_init_hw(struct cas *cp, int restart_link)
3724{
3725 if (restart_link)
3726 cas_phy_init(cp);
3727
3728 cas_init_pause_thresholds(cp);
3729 cas_init_mac(cp);
3730 cas_init_dma(cp);
3731
3732 if (restart_link) {
3733
3734 cp->timer_ticks = 0;
3735 cas_begin_auto_negotiation(cp, NULL);
3736 } else if (cp->lstate == link_up) {
3737 cas_set_link_modes(cp);
3738 netif_carrier_on(cp->dev);
3739 }
3740}
3741
3742
3743
3744
3745
3746static void cas_hard_reset(struct cas *cp)
3747{
3748 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3749 udelay(20);
3750 pci_restore_state(cp->pdev);
3751}
3752
3753
3754static void cas_global_reset(struct cas *cp, int blkflag)
3755{
3756 int limit;
3757
3758
3759 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3760
3761
3762
3763
3764
3765
3766 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3767 cp->regs + REG_SW_RESET);
3768 } else {
3769 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3770 }
3771
3772
3773 mdelay(3);
3774
3775 limit = STOP_TRIES;
3776 while (limit-- > 0) {
3777 u32 val = readl(cp->regs + REG_SW_RESET);
3778 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3779 goto done;
3780 udelay(10);
3781 }
3782 netdev_err(cp->dev, "sw reset failed\n");
3783
3784done:
3785
3786 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3787 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3788
3789
3790
3791
3792
3793 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3794 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3795 PCI_ERR_BIM_DMA_READ), cp->regs +
3796 REG_PCI_ERR_STATUS_MASK);
3797
3798
3799
3800
3801 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3802}
3803
3804static void cas_reset(struct cas *cp, int blkflag)
3805{
3806 u32 val;
3807
3808 cas_mask_intr(cp);
3809 cas_global_reset(cp, blkflag);
3810 cas_mac_reset(cp);
3811 cas_entropy_reset(cp);
3812
3813
3814 val = readl(cp->regs + REG_TX_CFG);
3815 val &= ~TX_CFG_DMA_EN;
3816 writel(val, cp->regs + REG_TX_CFG);
3817
3818 val = readl(cp->regs + REG_RX_CFG);
3819 val &= ~RX_CFG_DMA_EN;
3820 writel(val, cp->regs + REG_RX_CFG);
3821
3822
3823 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3824 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3825 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3826 } else {
3827 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3828 }
3829
3830
3831 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3832 cas_clear_mac_err(cp);
3833 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3834}
3835
3836
3837static void cas_shutdown(struct cas *cp)
3838{
3839 unsigned long flags;
3840
3841
3842 cp->hw_running = 0;
3843
3844 del_timer_sync(&cp->link_timer);
3845
3846
3847#if 0
3848 while (atomic_read(&cp->reset_task_pending_mtu) ||
3849 atomic_read(&cp->reset_task_pending_spare) ||
3850 atomic_read(&cp->reset_task_pending_all))
3851 schedule();
3852
3853#else
3854 while (atomic_read(&cp->reset_task_pending))
3855 schedule();
3856#endif
3857
3858 cas_lock_all_save(cp, flags);
3859 cas_reset(cp, 0);
3860 if (cp->cas_flags & CAS_FLAG_SATURN)
3861 cas_phy_powerdown(cp);
3862 cas_unlock_all_restore(cp, flags);
3863}
3864
3865static int cas_change_mtu(struct net_device *dev, int new_mtu)
3866{
3867 struct cas *cp = netdev_priv(dev);
3868
3869 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3870 return -EINVAL;
3871
3872 dev->mtu = new_mtu;
3873 if (!netif_running(dev) || !netif_device_present(dev))
3874 return 0;
3875
3876
3877#if 1
3878 atomic_inc(&cp->reset_task_pending);
3879 if ((cp->phy_type & CAS_PHY_SERDES)) {
3880 atomic_inc(&cp->reset_task_pending_all);
3881 } else {
3882 atomic_inc(&cp->reset_task_pending_mtu);
3883 }
3884 schedule_work(&cp->reset_task);
3885#else
3886 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3887 CAS_RESET_ALL : CAS_RESET_MTU);
3888 pr_err("reset called in cas_change_mtu\n");
3889 schedule_work(&cp->reset_task);
3890#endif
3891
3892 flush_work(&cp->reset_task);
3893 return 0;
3894}
3895
3896static void cas_clean_txd(struct cas *cp, int ring)
3897{
3898 struct cas_tx_desc *txd = cp->init_txds[ring];
3899 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3900 u64 daddr, dlen;
3901 int i, size;
3902
3903 size = TX_DESC_RINGN_SIZE(ring);
3904 for (i = 0; i < size; i++) {
3905 int frag;
3906
3907 if (skbs[i] == NULL)
3908 continue;
3909
3910 skb = skbs[i];
3911 skbs[i] = NULL;
3912
3913 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3914 int ent = i & (size - 1);
3915
3916
3917
3918
3919 daddr = le64_to_cpu(txd[ent].buffer);
3920 dlen = CAS_VAL(TX_DESC_BUFLEN,
3921 le64_to_cpu(txd[ent].control));
3922 pci_unmap_page(cp->pdev, daddr, dlen,
3923 PCI_DMA_TODEVICE);
3924
3925 if (frag != skb_shinfo(skb)->nr_frags) {
3926 i++;
3927
3928
3929
3930
3931 ent = i & (size - 1);
3932 if (cp->tx_tiny_use[ring][ent].used)
3933 i++;
3934 }
3935 }
3936 dev_kfree_skb_any(skb);
3937 }
3938
3939
3940 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3941}
3942
3943
3944static inline void cas_free_rx_desc(struct cas *cp, int ring)
3945{
3946 cas_page_t **page = cp->rx_pages[ring];
3947 int i, size;
3948
3949 size = RX_DESC_RINGN_SIZE(ring);
3950 for (i = 0; i < size; i++) {
3951 if (page[i]) {
3952 cas_page_free(cp, page[i]);
3953 page[i] = NULL;
3954 }
3955 }
3956}
3957
3958static void cas_free_rxds(struct cas *cp)
3959{
3960 int i;
3961
3962 for (i = 0; i < N_RX_DESC_RINGS; i++)
3963 cas_free_rx_desc(cp, i);
3964}
3965
3966
3967static void cas_clean_rings(struct cas *cp)
3968{
3969 int i;
3970
3971
3972 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3973 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3974 for (i = 0; i < N_TX_RINGS; i++)
3975 cas_clean_txd(cp, i);
3976
3977
3978 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3979 cas_clean_rxds(cp);
3980 cas_clean_rxcs(cp);
3981}
3982
3983
3984static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3985{
3986 cas_page_t **page = cp->rx_pages[ring];
3987 int size, i = 0;
3988
3989 size = RX_DESC_RINGN_SIZE(ring);
3990 for (i = 0; i < size; i++) {
3991 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3992 return -1;
3993 }
3994 return 0;
3995}
3996
3997static int cas_alloc_rxds(struct cas *cp)
3998{
3999 int i;
4000
4001 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4002 if (cas_alloc_rx_desc(cp, i) < 0) {
4003 cas_free_rxds(cp);
4004 return -1;
4005 }
4006 }
4007 return 0;
4008}
4009
4010static void cas_reset_task(struct work_struct *work)
4011{
4012 struct cas *cp = container_of(work, struct cas, reset_task);
4013#if 0
4014 int pending = atomic_read(&cp->reset_task_pending);
4015#else
4016 int pending_all = atomic_read(&cp->reset_task_pending_all);
4017 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4018 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4019
4020 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4021
4022
4023
4024 atomic_dec(&cp->reset_task_pending);
4025 return;
4026 }
4027#endif
4028
4029
4030
4031
4032 if (cp->hw_running) {
4033 unsigned long flags;
4034
4035
4036 netif_device_detach(cp->dev);
4037 cas_lock_all_save(cp, flags);
4038
4039 if (cp->opened) {
4040
4041
4042
4043
4044 cas_spare_recover(cp, GFP_ATOMIC);
4045 }
4046#if 1
4047
4048 if (!pending_all && !pending_mtu)
4049 goto done;
4050#else
4051 if (pending == CAS_RESET_SPARE)
4052 goto done;
4053#endif
4054
4055
4056
4057
4058
4059
4060
4061#if 1
4062 cas_reset(cp, !(pending_all > 0));
4063 if (cp->opened)
4064 cas_clean_rings(cp);
4065 cas_init_hw(cp, (pending_all > 0));
4066#else
4067 cas_reset(cp, !(pending == CAS_RESET_ALL));
4068 if (cp->opened)
4069 cas_clean_rings(cp);
4070 cas_init_hw(cp, pending == CAS_RESET_ALL);
4071#endif
4072
4073done:
4074 cas_unlock_all_restore(cp, flags);
4075 netif_device_attach(cp->dev);
4076 }
4077#if 1
4078 atomic_sub(pending_all, &cp->reset_task_pending_all);
4079 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4080 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4081 atomic_dec(&cp->reset_task_pending);
4082#else
4083 atomic_set(&cp->reset_task_pending, 0);
4084#endif
4085}
4086
4087static void cas_link_timer(unsigned long data)
4088{
4089 struct cas *cp = (struct cas *) data;
4090 int mask, pending = 0, reset = 0;
4091 unsigned long flags;
4092
4093 if (link_transition_timeout != 0 &&
4094 cp->link_transition_jiffies_valid &&
4095 ((jiffies - cp->link_transition_jiffies) >
4096 (link_transition_timeout))) {
4097
4098
4099
4100
4101 cp->link_transition_jiffies_valid = 0;
4102 }
4103
4104 if (!cp->hw_running)
4105 return;
4106
4107 spin_lock_irqsave(&cp->lock, flags);
4108 cas_lock_tx(cp);
4109 cas_entropy_gather(cp);
4110
4111
4112
4113
4114#if 1
4115 if (atomic_read(&cp->reset_task_pending_all) ||
4116 atomic_read(&cp->reset_task_pending_spare) ||
4117 atomic_read(&cp->reset_task_pending_mtu))
4118 goto done;
4119#else
4120 if (atomic_read(&cp->reset_task_pending))
4121 goto done;
4122#endif
4123
4124
4125 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4126 int i, rmask;
4127
4128 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4129 rmask = CAS_FLAG_RXD_POST(i);
4130 if ((mask & rmask) == 0)
4131 continue;
4132
4133
4134 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4135 pending = 1;
4136 continue;
4137 }
4138 cp->cas_flags &= ~rmask;
4139 }
4140 }
4141
4142 if (CAS_PHY_MII(cp->phy_type)) {
4143 u16 bmsr;
4144 cas_mif_poll(cp, 0);
4145 bmsr = cas_phy_read(cp, MII_BMSR);
4146
4147
4148
4149
4150
4151 bmsr = cas_phy_read(cp, MII_BMSR);
4152 cas_mif_poll(cp, 1);
4153 readl(cp->regs + REG_MIF_STATUS);
4154 reset = cas_mii_link_check(cp, bmsr);
4155 } else {
4156 reset = cas_pcs_link_check(cp);
4157 }
4158
4159 if (reset)
4160 goto done;
4161
4162
4163 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4164 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4165 u32 wptr, rptr;
4166 int tlm = CAS_VAL(MAC_SM_TLM, val);
4167
4168 if (((tlm == 0x5) || (tlm == 0x3)) &&
4169 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4170 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4171 "tx err: MAC_STATE[%08x]\n", val);
4172 reset = 1;
4173 goto done;
4174 }
4175
4176 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4177 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4178 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4179 if ((val == 0) && (wptr != rptr)) {
4180 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4181 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4182 val, wptr, rptr);
4183 reset = 1;
4184 }
4185
4186 if (reset)
4187 cas_hard_reset(cp);
4188 }
4189
4190done:
4191 if (reset) {
4192#if 1
4193 atomic_inc(&cp->reset_task_pending);
4194 atomic_inc(&cp->reset_task_pending_all);
4195 schedule_work(&cp->reset_task);
4196#else
4197 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4198 pr_err("reset called in cas_link_timer\n");
4199 schedule_work(&cp->reset_task);
4200#endif
4201 }
4202
4203 if (!pending)
4204 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4205 cas_unlock_tx(cp);
4206 spin_unlock_irqrestore(&cp->lock, flags);
4207}
4208
4209
4210
4211
4212static void cas_tx_tiny_free(struct cas *cp)
4213{
4214 struct pci_dev *pdev = cp->pdev;
4215 int i;
4216
4217 for (i = 0; i < N_TX_RINGS; i++) {
4218 if (!cp->tx_tiny_bufs[i])
4219 continue;
4220
4221 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4222 cp->tx_tiny_bufs[i],
4223 cp->tx_tiny_dvma[i]);
4224 cp->tx_tiny_bufs[i] = NULL;
4225 }
4226}
4227
4228static int cas_tx_tiny_alloc(struct cas *cp)
4229{
4230 struct pci_dev *pdev = cp->pdev;
4231 int i;
4232
4233 for (i = 0; i < N_TX_RINGS; i++) {
4234 cp->tx_tiny_bufs[i] =
4235 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4236 &cp->tx_tiny_dvma[i]);
4237 if (!cp->tx_tiny_bufs[i]) {
4238 cas_tx_tiny_free(cp);
4239 return -1;
4240 }
4241 }
4242 return 0;
4243}
4244
4245
4246static int cas_open(struct net_device *dev)
4247{
4248 struct cas *cp = netdev_priv(dev);
4249 int hw_was_up, err;
4250 unsigned long flags;
4251
4252 mutex_lock(&cp->pm_mutex);
4253
4254 hw_was_up = cp->hw_running;
4255
4256
4257
4258
4259 if (!cp->hw_running) {
4260
4261 cas_lock_all_save(cp, flags);
4262
4263
4264
4265
4266
4267 cas_reset(cp, 0);
4268 cp->hw_running = 1;
4269 cas_unlock_all_restore(cp, flags);
4270 }
4271
4272 err = -ENOMEM;
4273 if (cas_tx_tiny_alloc(cp) < 0)
4274 goto err_unlock;
4275
4276
4277 if (cas_alloc_rxds(cp) < 0)
4278 goto err_tx_tiny;
4279
4280
4281 cas_spare_init(cp);
4282 cas_spare_recover(cp, GFP_KERNEL);
4283
4284
4285
4286
4287
4288
4289 if (request_irq(cp->pdev->irq, cas_interrupt,
4290 IRQF_SHARED, dev->name, (void *) dev)) {
4291 netdev_err(cp->dev, "failed to request irq !\n");
4292 err = -EAGAIN;
4293 goto err_spare;
4294 }
4295
4296#ifdef USE_NAPI
4297 napi_enable(&cp->napi);
4298#endif
4299
4300 cas_lock_all_save(cp, flags);
4301 cas_clean_rings(cp);
4302 cas_init_hw(cp, !hw_was_up);
4303 cp->opened = 1;
4304 cas_unlock_all_restore(cp, flags);
4305
4306 netif_start_queue(dev);
4307 mutex_unlock(&cp->pm_mutex);
4308 return 0;
4309
4310err_spare:
4311 cas_spare_free(cp);
4312 cas_free_rxds(cp);
4313err_tx_tiny:
4314 cas_tx_tiny_free(cp);
4315err_unlock:
4316 mutex_unlock(&cp->pm_mutex);
4317 return err;
4318}
4319
4320static int cas_close(struct net_device *dev)
4321{
4322 unsigned long flags;
4323 struct cas *cp = netdev_priv(dev);
4324
4325#ifdef USE_NAPI
4326 napi_disable(&cp->napi);
4327#endif
4328
4329 mutex_lock(&cp->pm_mutex);
4330
4331 netif_stop_queue(dev);
4332
4333
4334 cas_lock_all_save(cp, flags);
4335 cp->opened = 0;
4336 cas_reset(cp, 0);
4337 cas_phy_init(cp);
4338 cas_begin_auto_negotiation(cp, NULL);
4339 cas_clean_rings(cp);
4340 cas_unlock_all_restore(cp, flags);
4341
4342 free_irq(cp->pdev->irq, (void *) dev);
4343 cas_spare_free(cp);
4344 cas_free_rxds(cp);
4345 cas_tx_tiny_free(cp);
4346 mutex_unlock(&cp->pm_mutex);
4347 return 0;
4348}
4349
4350static struct {
4351 const char name[ETH_GSTRING_LEN];
4352} ethtool_cassini_statnames[] = {
4353 {"collisions"},
4354 {"rx_bytes"},
4355 {"rx_crc_errors"},
4356 {"rx_dropped"},
4357 {"rx_errors"},
4358 {"rx_fifo_errors"},
4359 {"rx_frame_errors"},
4360 {"rx_length_errors"},
4361 {"rx_over_errors"},
4362 {"rx_packets"},
4363 {"tx_aborted_errors"},
4364 {"tx_bytes"},
4365 {"tx_dropped"},
4366 {"tx_errors"},
4367 {"tx_fifo_errors"},
4368 {"tx_packets"}
4369};
4370#define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4371
4372static struct {
4373 const int offsets;
4374} ethtool_register_table[] = {
4375 {-MII_BMSR},
4376 {-MII_BMCR},
4377 {REG_CAWR},
4378 {REG_INF_BURST},
4379 {REG_BIM_CFG},
4380 {REG_RX_CFG},
4381 {REG_HP_CFG},
4382 {REG_MAC_TX_CFG},
4383 {REG_MAC_RX_CFG},
4384 {REG_MAC_CTRL_CFG},
4385 {REG_MAC_XIF_CFG},
4386 {REG_MIF_CFG},
4387 {REG_PCS_CFG},
4388 {REG_SATURN_PCFG},
4389 {REG_PCS_MII_STATUS},
4390 {REG_PCS_STATE_MACHINE},
4391 {REG_MAC_COLL_EXCESS},
4392 {REG_MAC_COLL_LATE}
4393};
4394#define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4395#define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4396
4397static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4398{
4399 u8 *p;
4400 int i;
4401 unsigned long flags;
4402
4403 spin_lock_irqsave(&cp->lock, flags);
4404 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4405 u16 hval;
4406 u32 val;
4407 if (ethtool_register_table[i].offsets < 0) {
4408 hval = cas_phy_read(cp,
4409 -ethtool_register_table[i].offsets);
4410 val = hval;
4411 } else {
4412 val= readl(cp->regs+ethtool_register_table[i].offsets);
4413 }
4414 memcpy(p, (u8 *)&val, sizeof(u32));
4415 }
4416 spin_unlock_irqrestore(&cp->lock, flags);
4417}
4418
4419static struct net_device_stats *cas_get_stats(struct net_device *dev)
4420{
4421 struct cas *cp = netdev_priv(dev);
4422 struct net_device_stats *stats = cp->net_stats;
4423 unsigned long flags;
4424 int i;
4425 unsigned long tmp;
4426
4427
4428 if (!cp->hw_running)
4429 return stats + N_TX_RINGS;
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4440 stats[N_TX_RINGS].rx_crc_errors +=
4441 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4442 stats[N_TX_RINGS].rx_frame_errors +=
4443 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4444 stats[N_TX_RINGS].rx_length_errors +=
4445 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4446#if 1
4447 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4448 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4449 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4450 stats[N_TX_RINGS].collisions +=
4451 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4452#else
4453 stats[N_TX_RINGS].tx_aborted_errors +=
4454 readl(cp->regs + REG_MAC_COLL_EXCESS);
4455 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4456 readl(cp->regs + REG_MAC_COLL_LATE);
4457#endif
4458 cas_clear_mac_err(cp);
4459
4460
4461 spin_lock(&cp->stat_lock[0]);
4462 stats[N_TX_RINGS].collisions += stats[0].collisions;
4463 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4464 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4465 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4466 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4467 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4468 spin_unlock(&cp->stat_lock[0]);
4469
4470 for (i = 0; i < N_TX_RINGS; i++) {
4471 spin_lock(&cp->stat_lock[i]);
4472 stats[N_TX_RINGS].rx_length_errors +=
4473 stats[i].rx_length_errors;
4474 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4475 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4476 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4477 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4478 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4479 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4480 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4481 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4482 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4483 memset(stats + i, 0, sizeof(struct net_device_stats));
4484 spin_unlock(&cp->stat_lock[i]);
4485 }
4486 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4487 return stats + N_TX_RINGS;
4488}
4489
4490
4491static void cas_set_multicast(struct net_device *dev)
4492{
4493 struct cas *cp = netdev_priv(dev);
4494 u32 rxcfg, rxcfg_new;
4495 unsigned long flags;
4496 int limit = STOP_TRIES;
4497
4498 if (!cp->hw_running)
4499 return;
4500
4501 spin_lock_irqsave(&cp->lock, flags);
4502 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4503
4504
4505 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4506 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4507 if (!limit--)
4508 break;
4509 udelay(10);
4510 }
4511
4512
4513 limit = STOP_TRIES;
4514 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4515 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4516 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4517 if (!limit--)
4518 break;
4519 udelay(10);
4520 }
4521
4522
4523 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4524 rxcfg |= rxcfg_new;
4525 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4526 spin_unlock_irqrestore(&cp->lock, flags);
4527}
4528
4529static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4530{
4531 struct cas *cp = netdev_priv(dev);
4532 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4533 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4534 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4535 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4536 cp->casreg_len : CAS_MAX_REGS;
4537 info->n_stats = CAS_NUM_STAT_KEYS;
4538}
4539
4540static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4541{
4542 struct cas *cp = netdev_priv(dev);
4543 u16 bmcr;
4544 int full_duplex, speed, pause;
4545 unsigned long flags;
4546 enum link_state linkstate = link_up;
4547
4548 cmd->advertising = 0;
4549 cmd->supported = SUPPORTED_Autoneg;
4550 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4551 cmd->supported |= SUPPORTED_1000baseT_Full;
4552 cmd->advertising |= ADVERTISED_1000baseT_Full;
4553 }
4554
4555
4556 spin_lock_irqsave(&cp->lock, flags);
4557 bmcr = 0;
4558 linkstate = cp->lstate;
4559 if (CAS_PHY_MII(cp->phy_type)) {
4560 cmd->port = PORT_MII;
4561 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4562 XCVR_INTERNAL : XCVR_EXTERNAL;
4563 cmd->phy_address = cp->phy_addr;
4564 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4565 ADVERTISED_10baseT_Half |
4566 ADVERTISED_10baseT_Full |
4567 ADVERTISED_100baseT_Half |
4568 ADVERTISED_100baseT_Full;
4569
4570 cmd->supported |=
4571 (SUPPORTED_10baseT_Half |
4572 SUPPORTED_10baseT_Full |
4573 SUPPORTED_100baseT_Half |
4574 SUPPORTED_100baseT_Full |
4575 SUPPORTED_TP | SUPPORTED_MII);
4576
4577 if (cp->hw_running) {
4578 cas_mif_poll(cp, 0);
4579 bmcr = cas_phy_read(cp, MII_BMCR);
4580 cas_read_mii_link_mode(cp, &full_duplex,
4581 &speed, &pause);
4582 cas_mif_poll(cp, 1);
4583 }
4584
4585 } else {
4586 cmd->port = PORT_FIBRE;
4587 cmd->transceiver = XCVR_INTERNAL;
4588 cmd->phy_address = 0;
4589 cmd->supported |= SUPPORTED_FIBRE;
4590 cmd->advertising |= ADVERTISED_FIBRE;
4591
4592 if (cp->hw_running) {
4593
4594 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4595 cas_read_pcs_link_mode(cp, &full_duplex,
4596 &speed, &pause);
4597 }
4598 }
4599 spin_unlock_irqrestore(&cp->lock, flags);
4600
4601 if (bmcr & BMCR_ANENABLE) {
4602 cmd->advertising |= ADVERTISED_Autoneg;
4603 cmd->autoneg = AUTONEG_ENABLE;
4604 ethtool_cmd_speed_set(cmd, ((speed == 10) ?
4605 SPEED_10 :
4606 ((speed == 1000) ?
4607 SPEED_1000 : SPEED_100)));
4608 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4609 } else {
4610 cmd->autoneg = AUTONEG_DISABLE;
4611 ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
4612 SPEED_1000 :
4613 ((bmcr & BMCR_SPEED100) ?
4614 SPEED_100 : SPEED_10)));
4615 cmd->duplex =
4616 (bmcr & BMCR_FULLDPLX) ?
4617 DUPLEX_FULL : DUPLEX_HALF;
4618 }
4619 if (linkstate != link_up) {
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630 if (cp->link_cntl & BMCR_ANENABLE) {
4631 ethtool_cmd_speed_set(cmd, 0);
4632 cmd->duplex = 0xff;
4633 } else {
4634 ethtool_cmd_speed_set(cmd, SPEED_10);
4635 if (cp->link_cntl & BMCR_SPEED100) {
4636 ethtool_cmd_speed_set(cmd, SPEED_100);
4637 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4638 ethtool_cmd_speed_set(cmd, SPEED_1000);
4639 }
4640 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4641 DUPLEX_FULL : DUPLEX_HALF;
4642 }
4643 }
4644 return 0;
4645}
4646
4647static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4648{
4649 struct cas *cp = netdev_priv(dev);
4650 unsigned long flags;
4651 u32 speed = ethtool_cmd_speed(cmd);
4652
4653
4654 if (cmd->autoneg != AUTONEG_ENABLE &&
4655 cmd->autoneg != AUTONEG_DISABLE)
4656 return -EINVAL;
4657
4658 if (cmd->autoneg == AUTONEG_DISABLE &&
4659 ((speed != SPEED_1000 &&
4660 speed != SPEED_100 &&
4661 speed != SPEED_10) ||
4662 (cmd->duplex != DUPLEX_HALF &&
4663 cmd->duplex != DUPLEX_FULL)))
4664 return -EINVAL;
4665
4666
4667 spin_lock_irqsave(&cp->lock, flags);
4668 cas_begin_auto_negotiation(cp, cmd);
4669 spin_unlock_irqrestore(&cp->lock, flags);
4670 return 0;
4671}
4672
4673static int cas_nway_reset(struct net_device *dev)
4674{
4675 struct cas *cp = netdev_priv(dev);
4676 unsigned long flags;
4677
4678 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4679 return -EINVAL;
4680
4681
4682 spin_lock_irqsave(&cp->lock, flags);
4683 cas_begin_auto_negotiation(cp, NULL);
4684 spin_unlock_irqrestore(&cp->lock, flags);
4685
4686 return 0;
4687}
4688
4689static u32 cas_get_link(struct net_device *dev)
4690{
4691 struct cas *cp = netdev_priv(dev);
4692 return cp->lstate == link_up;
4693}
4694
4695static u32 cas_get_msglevel(struct net_device *dev)
4696{
4697 struct cas *cp = netdev_priv(dev);
4698 return cp->msg_enable;
4699}
4700
4701static void cas_set_msglevel(struct net_device *dev, u32 value)
4702{
4703 struct cas *cp = netdev_priv(dev);
4704 cp->msg_enable = value;
4705}
4706
4707static int cas_get_regs_len(struct net_device *dev)
4708{
4709 struct cas *cp = netdev_priv(dev);
4710 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4711}
4712
4713static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4714 void *p)
4715{
4716 struct cas *cp = netdev_priv(dev);
4717 regs->version = 0;
4718
4719 cas_read_regs(cp, p, regs->len / sizeof(u32));
4720}
4721
4722static int cas_get_sset_count(struct net_device *dev, int sset)
4723{
4724 switch (sset) {
4725 case ETH_SS_STATS:
4726 return CAS_NUM_STAT_KEYS;
4727 default:
4728 return -EOPNOTSUPP;
4729 }
4730}
4731
4732static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4733{
4734 memcpy(data, ðtool_cassini_statnames,
4735 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4736}
4737
4738static void cas_get_ethtool_stats(struct net_device *dev,
4739 struct ethtool_stats *estats, u64 *data)
4740{
4741 struct cas *cp = netdev_priv(dev);
4742 struct net_device_stats *stats = cas_get_stats(cp->dev);
4743 int i = 0;
4744 data[i++] = stats->collisions;
4745 data[i++] = stats->rx_bytes;
4746 data[i++] = stats->rx_crc_errors;
4747 data[i++] = stats->rx_dropped;
4748 data[i++] = stats->rx_errors;
4749 data[i++] = stats->rx_fifo_errors;
4750 data[i++] = stats->rx_frame_errors;
4751 data[i++] = stats->rx_length_errors;
4752 data[i++] = stats->rx_over_errors;
4753 data[i++] = stats->rx_packets;
4754 data[i++] = stats->tx_aborted_errors;
4755 data[i++] = stats->tx_bytes;
4756 data[i++] = stats->tx_dropped;
4757 data[i++] = stats->tx_errors;
4758 data[i++] = stats->tx_fifo_errors;
4759 data[i++] = stats->tx_packets;
4760 BUG_ON(i != CAS_NUM_STAT_KEYS);
4761}
4762
4763static const struct ethtool_ops cas_ethtool_ops = {
4764 .get_drvinfo = cas_get_drvinfo,
4765 .get_settings = cas_get_settings,
4766 .set_settings = cas_set_settings,
4767 .nway_reset = cas_nway_reset,
4768 .get_link = cas_get_link,
4769 .get_msglevel = cas_get_msglevel,
4770 .set_msglevel = cas_set_msglevel,
4771 .get_regs_len = cas_get_regs_len,
4772 .get_regs = cas_get_regs,
4773 .get_sset_count = cas_get_sset_count,
4774 .get_strings = cas_get_strings,
4775 .get_ethtool_stats = cas_get_ethtool_stats,
4776};
4777
4778static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4779{
4780 struct cas *cp = netdev_priv(dev);
4781 struct mii_ioctl_data *data = if_mii(ifr);
4782 unsigned long flags;
4783 int rc = -EOPNOTSUPP;
4784
4785
4786
4787
4788 mutex_lock(&cp->pm_mutex);
4789 switch (cmd) {
4790 case SIOCGMIIPHY:
4791 data->phy_id = cp->phy_addr;
4792
4793
4794 case SIOCGMIIREG:
4795 spin_lock_irqsave(&cp->lock, flags);
4796 cas_mif_poll(cp, 0);
4797 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4798 cas_mif_poll(cp, 1);
4799 spin_unlock_irqrestore(&cp->lock, flags);
4800 rc = 0;
4801 break;
4802
4803 case SIOCSMIIREG:
4804 spin_lock_irqsave(&cp->lock, flags);
4805 cas_mif_poll(cp, 0);
4806 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4807 cas_mif_poll(cp, 1);
4808 spin_unlock_irqrestore(&cp->lock, flags);
4809 break;
4810 default:
4811 break;
4812 }
4813
4814 mutex_unlock(&cp->pm_mutex);
4815 return rc;
4816}
4817
4818
4819
4820
4821
4822static void cas_program_bridge(struct pci_dev *cas_pdev)
4823{
4824 struct pci_dev *pdev = cas_pdev->bus->self;
4825 u32 val;
4826
4827 if (!pdev)
4828 return;
4829
4830 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4831 return;
4832
4833
4834
4835
4836
4837
4838 pci_read_config_dword(pdev, 0x40, &val);
4839 val &= ~0x00040000;
4840 pci_write_config_dword(pdev, 0x40, val);
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886 pci_write_config_word(pdev, 0x52,
4887 (0x7 << 13) |
4888 (0x7 << 10) |
4889 (0x7 << 7) |
4890 (0x7 << 4) |
4891 (0xf << 0));
4892
4893
4894 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4895
4896
4897
4898
4899 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4900}
4901
4902static const struct net_device_ops cas_netdev_ops = {
4903 .ndo_open = cas_open,
4904 .ndo_stop = cas_close,
4905 .ndo_start_xmit = cas_start_xmit,
4906 .ndo_get_stats = cas_get_stats,
4907 .ndo_set_rx_mode = cas_set_multicast,
4908 .ndo_do_ioctl = cas_ioctl,
4909 .ndo_tx_timeout = cas_tx_timeout,
4910 .ndo_change_mtu = cas_change_mtu,
4911 .ndo_set_mac_address = eth_mac_addr,
4912 .ndo_validate_addr = eth_validate_addr,
4913#ifdef CONFIG_NET_POLL_CONTROLLER
4914 .ndo_poll_controller = cas_netpoll,
4915#endif
4916};
4917
4918static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4919{
4920 static int cas_version_printed = 0;
4921 unsigned long casreg_len;
4922 struct net_device *dev;
4923 struct cas *cp;
4924 int i, err, pci_using_dac;
4925 u16 pci_cmd;
4926 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4927
4928 if (cas_version_printed++ == 0)
4929 pr_info("%s", version);
4930
4931 err = pci_enable_device(pdev);
4932 if (err) {
4933 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4934 return err;
4935 }
4936
4937 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4938 dev_err(&pdev->dev, "Cannot find proper PCI device "
4939 "base address, aborting\n");
4940 err = -ENODEV;
4941 goto err_out_disable_pdev;
4942 }
4943
4944 dev = alloc_etherdev(sizeof(*cp));
4945 if (!dev) {
4946 err = -ENOMEM;
4947 goto err_out_disable_pdev;
4948 }
4949 SET_NETDEV_DEV(dev, &pdev->dev);
4950
4951 err = pci_request_regions(pdev, dev->name);
4952 if (err) {
4953 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4954 goto err_out_free_netdev;
4955 }
4956 pci_set_master(pdev);
4957
4958
4959
4960
4961
4962 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4963 pci_cmd &= ~PCI_COMMAND_SERR;
4964 pci_cmd |= PCI_COMMAND_PARITY;
4965 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4966 if (pci_try_set_mwi(pdev))
4967 pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
4968
4969 cas_program_bridge(pdev);
4970
4971
4972
4973
4974
4975
4976
4977#if 1
4978 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4979 &orig_cacheline_size);
4980 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4981 cas_cacheline_size =
4982 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4983 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4984 if (pci_write_config_byte(pdev,
4985 PCI_CACHE_LINE_SIZE,
4986 cas_cacheline_size)) {
4987 dev_err(&pdev->dev, "Could not set PCI cache "
4988 "line size\n");
4989 goto err_write_cacheline;
4990 }
4991 }
4992#endif
4993
4994
4995
4996 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4997 pci_using_dac = 1;
4998 err = pci_set_consistent_dma_mask(pdev,
4999 DMA_BIT_MASK(64));
5000 if (err < 0) {
5001 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5002 "for consistent allocations\n");
5003 goto err_out_free_res;
5004 }
5005
5006 } else {
5007 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5008 if (err) {
5009 dev_err(&pdev->dev, "No usable DMA configuration, "
5010 "aborting\n");
5011 goto err_out_free_res;
5012 }
5013 pci_using_dac = 0;
5014 }
5015
5016 casreg_len = pci_resource_len(pdev, 0);
5017
5018 cp = netdev_priv(dev);
5019 cp->pdev = pdev;
5020#if 1
5021
5022 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5023#endif
5024 cp->dev = dev;
5025 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5026 cassini_debug;
5027
5028#if defined(CONFIG_SPARC)
5029 cp->of_node = pci_device_to_OF_node(pdev);
5030#endif
5031
5032 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5033 cp->link_transition_jiffies_valid = 0;
5034
5035 spin_lock_init(&cp->lock);
5036 spin_lock_init(&cp->rx_inuse_lock);
5037 spin_lock_init(&cp->rx_spare_lock);
5038 for (i = 0; i < N_TX_RINGS; i++) {
5039 spin_lock_init(&cp->stat_lock[i]);
5040 spin_lock_init(&cp->tx_lock[i]);
5041 }
5042 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5043 mutex_init(&cp->pm_mutex);
5044
5045 init_timer(&cp->link_timer);
5046 cp->link_timer.function = cas_link_timer;
5047 cp->link_timer.data = (unsigned long) cp;
5048
5049#if 1
5050
5051
5052
5053 atomic_set(&cp->reset_task_pending, 0);
5054 atomic_set(&cp->reset_task_pending_all, 0);
5055 atomic_set(&cp->reset_task_pending_spare, 0);
5056 atomic_set(&cp->reset_task_pending_mtu, 0);
5057#endif
5058 INIT_WORK(&cp->reset_task, cas_reset_task);
5059
5060
5061 if (link_mode >= 0 && link_mode < 6)
5062 cp->link_cntl = link_modes[link_mode];
5063 else
5064 cp->link_cntl = BMCR_ANENABLE;
5065 cp->lstate = link_down;
5066 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5067 netif_carrier_off(cp->dev);
5068 cp->timer_ticks = 0;
5069
5070
5071 cp->regs = pci_iomap(pdev, 0, casreg_len);
5072 if (!cp->regs) {
5073 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5074 goto err_out_free_res;
5075 }
5076 cp->casreg_len = casreg_len;
5077
5078 pci_save_state(pdev);
5079 cas_check_pci_invariants(cp);
5080 cas_hard_reset(cp);
5081 cas_reset(cp, 0);
5082 if (cas_check_invariants(cp))
5083 goto err_out_iounmap;
5084 if (cp->cas_flags & CAS_FLAG_SATURN)
5085 cas_saturn_firmware_init(cp);
5086
5087 cp->init_block = (struct cas_init_block *)
5088 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5089 &cp->block_dvma);
5090 if (!cp->init_block) {
5091 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5092 goto err_out_iounmap;
5093 }
5094
5095 for (i = 0; i < N_TX_RINGS; i++)
5096 cp->init_txds[i] = cp->init_block->txds[i];
5097
5098 for (i = 0; i < N_RX_DESC_RINGS; i++)
5099 cp->init_rxds[i] = cp->init_block->rxds[i];
5100
5101 for (i = 0; i < N_RX_COMP_RINGS; i++)
5102 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5103
5104 for (i = 0; i < N_RX_FLOWS; i++)
5105 skb_queue_head_init(&cp->rx_flows[i]);
5106
5107 dev->netdev_ops = &cas_netdev_ops;
5108 dev->ethtool_ops = &cas_ethtool_ops;
5109 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5110
5111#ifdef USE_NAPI
5112 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5113#endif
5114 dev->irq = pdev->irq;
5115 dev->dma = 0;
5116
5117
5118 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5119 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5120
5121 if (pci_using_dac)
5122 dev->features |= NETIF_F_HIGHDMA;
5123
5124 if (register_netdev(dev)) {
5125 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5126 goto err_out_free_consistent;
5127 }
5128
5129 i = readl(cp->regs + REG_BIM_CFG);
5130 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5131 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5132 (i & BIM_CFG_32BIT) ? "32" : "64",
5133 (i & BIM_CFG_66MHZ) ? "66" : "33",
5134 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5135 dev->dev_addr);
5136
5137 pci_set_drvdata(pdev, dev);
5138 cp->hw_running = 1;
5139 cas_entropy_reset(cp);
5140 cas_phy_init(cp);
5141 cas_begin_auto_negotiation(cp, NULL);
5142 return 0;
5143
5144err_out_free_consistent:
5145 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5146 cp->init_block, cp->block_dvma);
5147
5148err_out_iounmap:
5149 mutex_lock(&cp->pm_mutex);
5150 if (cp->hw_running)
5151 cas_shutdown(cp);
5152 mutex_unlock(&cp->pm_mutex);
5153
5154 pci_iounmap(pdev, cp->regs);
5155
5156
5157err_out_free_res:
5158 pci_release_regions(pdev);
5159
5160err_write_cacheline:
5161
5162
5163
5164 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5165
5166err_out_free_netdev:
5167 free_netdev(dev);
5168
5169err_out_disable_pdev:
5170 pci_disable_device(pdev);
5171 pci_set_drvdata(pdev, NULL);
5172 return -ENODEV;
5173}
5174
5175static void cas_remove_one(struct pci_dev *pdev)
5176{
5177 struct net_device *dev = pci_get_drvdata(pdev);
5178 struct cas *cp;
5179 if (!dev)
5180 return;
5181
5182 cp = netdev_priv(dev);
5183 unregister_netdev(dev);
5184
5185 if (cp->fw_data)
5186 vfree(cp->fw_data);
5187
5188 mutex_lock(&cp->pm_mutex);
5189 cancel_work_sync(&cp->reset_task);
5190 if (cp->hw_running)
5191 cas_shutdown(cp);
5192 mutex_unlock(&cp->pm_mutex);
5193
5194#if 1
5195 if (cp->orig_cacheline_size) {
5196
5197
5198
5199 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5200 cp->orig_cacheline_size);
5201 }
5202#endif
5203 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5204 cp->init_block, cp->block_dvma);
5205 pci_iounmap(pdev, cp->regs);
5206 free_netdev(dev);
5207 pci_release_regions(pdev);
5208 pci_disable_device(pdev);
5209 pci_set_drvdata(pdev, NULL);
5210}
5211
5212#ifdef CONFIG_PM
5213static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5214{
5215 struct net_device *dev = pci_get_drvdata(pdev);
5216 struct cas *cp = netdev_priv(dev);
5217 unsigned long flags;
5218
5219 mutex_lock(&cp->pm_mutex);
5220
5221
5222 if (cp->opened) {
5223 netif_device_detach(dev);
5224
5225 cas_lock_all_save(cp, flags);
5226
5227
5228
5229
5230
5231
5232 cas_reset(cp, 0);
5233 cas_clean_rings(cp);
5234 cas_unlock_all_restore(cp, flags);
5235 }
5236
5237 if (cp->hw_running)
5238 cas_shutdown(cp);
5239 mutex_unlock(&cp->pm_mutex);
5240
5241 return 0;
5242}
5243
5244static int cas_resume(struct pci_dev *pdev)
5245{
5246 struct net_device *dev = pci_get_drvdata(pdev);
5247 struct cas *cp = netdev_priv(dev);
5248
5249 netdev_info(dev, "resuming\n");
5250
5251 mutex_lock(&cp->pm_mutex);
5252 cas_hard_reset(cp);
5253 if (cp->opened) {
5254 unsigned long flags;
5255 cas_lock_all_save(cp, flags);
5256 cas_reset(cp, 0);
5257 cp->hw_running = 1;
5258 cas_clean_rings(cp);
5259 cas_init_hw(cp, 1);
5260 cas_unlock_all_restore(cp, flags);
5261
5262 netif_device_attach(dev);
5263 }
5264 mutex_unlock(&cp->pm_mutex);
5265 return 0;
5266}
5267#endif
5268
5269static struct pci_driver cas_driver = {
5270 .name = DRV_MODULE_NAME,
5271 .id_table = cas_pci_tbl,
5272 .probe = cas_init_one,
5273 .remove = cas_remove_one,
5274#ifdef CONFIG_PM
5275 .suspend = cas_suspend,
5276 .resume = cas_resume
5277#endif
5278};
5279
5280static int __init cas_init(void)
5281{
5282 if (linkdown_timeout > 0)
5283 link_transition_timeout = linkdown_timeout * HZ;
5284 else
5285 link_transition_timeout = 0;
5286
5287 return pci_register_driver(&cas_driver);
5288}
5289
5290static void __exit cas_cleanup(void)
5291{
5292 pci_unregister_driver(&cas_driver);
5293}
5294
5295module_init(cas_init);
5296module_exit(cas_cleanup);
5297