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16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/in.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/ethtool.h>
28#include <linux/mii.h>
29#include <linux/crc32.h>
30#include <linux/random.h>
31#include <linux/errno.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/mm.h>
36#include <linux/bitops.h>
37#include <linux/dma-mapping.h>
38
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
43#ifdef CONFIG_SPARC
44#include <linux/of.h>
45#include <linux/of_device.h>
46#include <asm/idprom.h>
47#include <asm/openprom.h>
48#include <asm/oplib.h>
49#include <asm/prom.h>
50#include <asm/auxio.h>
51#endif
52#include <asm/uaccess.h>
53
54#include <asm/pgtable.h>
55#include <asm/irq.h>
56
57#ifdef CONFIG_PCI
58#include <linux/pci.h>
59#endif
60
61#include "sunhme.h"
62
63#define DRV_NAME "sunhme"
64#define DRV_VERSION "3.10"
65#define DRV_RELDATE "August 26, 2008"
66#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
67
68static char version[] =
69 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
70
71MODULE_VERSION(DRV_VERSION);
72MODULE_AUTHOR(DRV_AUTHOR);
73MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
74MODULE_LICENSE("GPL");
75
76static int macaddr[6];
77
78
79module_param_array(macaddr, int, NULL, 0);
80MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
81
82#ifdef CONFIG_SBUS
83static struct quattro *qfe_sbus_list;
84#endif
85
86#ifdef CONFIG_PCI
87static struct quattro *qfe_pci_list;
88#endif
89
90#undef HMEDEBUG
91#undef SXDEBUG
92#undef RXDEBUG
93#undef TXDEBUG
94#undef TXLOGGING
95
96#ifdef TXLOGGING
97struct hme_tx_logent {
98 unsigned int tstamp;
99 int tx_new, tx_old;
100 unsigned int action;
101#define TXLOG_ACTION_IRQ 0x01
102#define TXLOG_ACTION_TXMIT 0x02
103#define TXLOG_ACTION_TBUSY 0x04
104#define TXLOG_ACTION_NBUFS 0x08
105 unsigned int status;
106};
107#define TX_LOG_LEN 128
108static struct hme_tx_logent tx_log[TX_LOG_LEN];
109static int txlog_cur_entry;
110static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
111{
112 struct hme_tx_logent *tlp;
113 unsigned long flags;
114
115 local_irq_save(flags);
116 tlp = &tx_log[txlog_cur_entry];
117 tlp->tstamp = (unsigned int)jiffies;
118 tlp->tx_new = hp->tx_new;
119 tlp->tx_old = hp->tx_old;
120 tlp->action = a;
121 tlp->status = s;
122 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
123 local_irq_restore(flags);
124}
125static __inline__ void tx_dump_log(void)
126{
127 int i, this;
128
129 this = txlog_cur_entry;
130 for (i = 0; i < TX_LOG_LEN; i++) {
131 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
132 tx_log[this].tstamp,
133 tx_log[this].tx_new, tx_log[this].tx_old,
134 tx_log[this].action, tx_log[this].status);
135 this = (this + 1) & (TX_LOG_LEN - 1);
136 }
137}
138static __inline__ void tx_dump_ring(struct happy_meal *hp)
139{
140 struct hmeal_init_block *hb = hp->happy_block;
141 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
142 int i;
143
144 for (i = 0; i < TX_RING_SIZE; i+=4) {
145 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
146 i, i + 4,
147 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
148 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
149 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
150 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
151 }
152}
153#else
154#define tx_add_log(hp, a, s) do { } while(0)
155#define tx_dump_log() do { } while(0)
156#define tx_dump_ring(hp) do { } while(0)
157#endif
158
159#ifdef HMEDEBUG
160#define HMD(x) printk x
161#else
162#define HMD(x)
163#endif
164
165
166
167#ifdef AUTO_SWITCH_DEBUG
168#define ASD(x) printk x
169#else
170#define ASD(x)
171#endif
172
173#define DEFAULT_IPG0 16
174#define DEFAULT_IPG1 8
175#define DEFAULT_IPG2 4
176#define DEFAULT_JAMSIZE 4
177
178
179
180
181
182
183
184
185#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
186static void sbus_hme_write32(void __iomem *reg, u32 val)
187{
188 sbus_writel(val, reg);
189}
190
191static u32 sbus_hme_read32(void __iomem *reg)
192{
193 return sbus_readl(reg);
194}
195
196static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
197{
198 rxd->rx_addr = (__force hme32)addr;
199 wmb();
200 rxd->rx_flags = (__force hme32)flags;
201}
202
203static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
204{
205 txd->tx_addr = (__force hme32)addr;
206 wmb();
207 txd->tx_flags = (__force hme32)flags;
208}
209
210static u32 sbus_hme_read_desc32(hme32 *p)
211{
212 return (__force u32)*p;
213}
214
215static void pci_hme_write32(void __iomem *reg, u32 val)
216{
217 writel(val, reg);
218}
219
220static u32 pci_hme_read32(void __iomem *reg)
221{
222 return readl(reg);
223}
224
225static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
226{
227 rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
228 wmb();
229 rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
230}
231
232static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
233{
234 txd->tx_addr = (__force hme32)cpu_to_le32(addr);
235 wmb();
236 txd->tx_flags = (__force hme32)cpu_to_le32(flags);
237}
238
239static u32 pci_hme_read_desc32(hme32 *p)
240{
241 return le32_to_cpup((__le32 *)p);
242}
243
244#define hme_write32(__hp, __reg, __val) \
245 ((__hp)->write32((__reg), (__val)))
246#define hme_read32(__hp, __reg) \
247 ((__hp)->read32(__reg))
248#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
249 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
250#define hme_write_txd(__hp, __txd, __flags, __addr) \
251 ((__hp)->write_txd((__txd), (__flags), (__addr)))
252#define hme_read_desc32(__hp, __p) \
253 ((__hp)->read_desc32(__p))
254#define hme_dma_map(__hp, __ptr, __size, __dir) \
255 ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
256#define hme_dma_unmap(__hp, __addr, __size, __dir) \
257 ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
258#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
259 ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
260#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
261 ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
262#else
263#ifdef CONFIG_SBUS
264
265#define hme_write32(__hp, __reg, __val) \
266 sbus_writel((__val), (__reg))
267#define hme_read32(__hp, __reg) \
268 sbus_readl(__reg)
269#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
270do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
271 wmb(); \
272 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
273} while(0)
274#define hme_write_txd(__hp, __txd, __flags, __addr) \
275do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
276 wmb(); \
277 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
278} while(0)
279#define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
280#define hme_dma_map(__hp, __ptr, __size, __dir) \
281 dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
282#define hme_dma_unmap(__hp, __addr, __size, __dir) \
283 dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
284#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
285 dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
286#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
287 dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
288#else
289
290#define hme_write32(__hp, __reg, __val) \
291 writel((__val), (__reg))
292#define hme_read32(__hp, __reg) \
293 readl(__reg)
294#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
295do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
296 wmb(); \
297 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
298} while(0)
299#define hme_write_txd(__hp, __txd, __flags, __addr) \
300do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
301 wmb(); \
302 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
303} while(0)
304static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
305{
306 return le32_to_cpup((__le32 *)p);
307}
308#define hme_dma_map(__hp, __ptr, __size, __dir) \
309 pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
310#define hme_dma_unmap(__hp, __addr, __size, __dir) \
311 pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
312#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
313 pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
314#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
315 pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
316#endif
317#endif
318
319
320
321static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
322{
323 hme_write32(hp, tregs + TCVR_BBDATA, bit);
324 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
326}
327
328#if 0
329static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
330{
331 u32 ret;
332
333 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
335 ret = hme_read32(hp, tregs + TCVR_CFG);
336 if (internal)
337 ret &= TCV_CFG_MDIO0;
338 else
339 ret &= TCV_CFG_MDIO1;
340
341 return ret;
342}
343#endif
344
345static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
346{
347 u32 retval;
348
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
350 udelay(1);
351 retval = hme_read32(hp, tregs + TCVR_CFG);
352 if (internal)
353 retval &= TCV_CFG_MDIO0;
354 else
355 retval &= TCV_CFG_MDIO1;
356 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
357
358 return retval;
359}
360
361#define TCVR_FAILURE 0x80000000
362
363static int happy_meal_bb_read(struct happy_meal *hp,
364 void __iomem *tregs, int reg)
365{
366 u32 tmp;
367 int retval = 0;
368 int i;
369
370 ASD(("happy_meal_bb_read: reg=%d ", reg));
371
372
373 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
374
375
376 for (i = 0; i < 32; i++)
377 BB_PUT_BIT(hp, tregs, 1);
378
379
380 BB_PUT_BIT(hp, tregs, 0);
381 BB_PUT_BIT(hp, tregs, 1);
382 BB_PUT_BIT(hp, tregs, 1);
383 BB_PUT_BIT(hp, tregs, 0);
384
385
386 tmp = hp->paddr & 0xff;
387 for (i = 4; i >= 0; i--)
388 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
389
390
391 tmp = (reg & 0xff);
392 for (i = 4; i >= 0; i--)
393 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
394
395
396 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
397
398
399 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
400 for (i = 15; i >= 0; i--)
401 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
402 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
404 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
405 ASD(("value=%x\n", retval));
406 return retval;
407}
408
409static void happy_meal_bb_write(struct happy_meal *hp,
410 void __iomem *tregs, int reg,
411 unsigned short value)
412{
413 u32 tmp;
414 int i;
415
416 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
417
418
419 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
420
421
422 for (i = 0; i < 32; i++)
423 BB_PUT_BIT(hp, tregs, 1);
424
425
426 BB_PUT_BIT(hp, tregs, 0);
427 BB_PUT_BIT(hp, tregs, 1);
428 BB_PUT_BIT(hp, tregs, 0);
429 BB_PUT_BIT(hp, tregs, 1);
430
431
432 tmp = (hp->paddr & 0xff);
433 for (i = 4; i >= 0; i--)
434 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
435
436
437 tmp = (reg & 0xff);
438 for (i = 4; i >= 0; i--)
439 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
440
441
442 BB_PUT_BIT(hp, tregs, 1);
443 BB_PUT_BIT(hp, tregs, 0);
444
445 for (i = 15; i >= 0; i--)
446 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
447
448
449 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
450}
451
452#define TCVR_READ_TRIES 16
453
454static int happy_meal_tcvr_read(struct happy_meal *hp,
455 void __iomem *tregs, int reg)
456{
457 int tries = TCVR_READ_TRIES;
458 int retval;
459
460 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
461 if (hp->tcvr_type == none) {
462 ASD(("no transceiver, value=TCVR_FAILURE\n"));
463 return TCVR_FAILURE;
464 }
465
466 if (!(hp->happy_flags & HFLAG_FENABLE)) {
467 ASD(("doing bit bang\n"));
468 return happy_meal_bb_read(hp, tregs, reg);
469 }
470
471 hme_write32(hp, tregs + TCVR_FRAME,
472 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
473 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
474 udelay(20);
475 if (!tries) {
476 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
477 return TCVR_FAILURE;
478 }
479 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
480 ASD(("value=%04x\n", retval));
481 return retval;
482}
483
484#define TCVR_WRITE_TRIES 16
485
486static void happy_meal_tcvr_write(struct happy_meal *hp,
487 void __iomem *tregs, int reg,
488 unsigned short value)
489{
490 int tries = TCVR_WRITE_TRIES;
491
492 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
493
494
495 if (!(hp->happy_flags & HFLAG_FENABLE)) {
496 happy_meal_bb_write(hp, tregs, reg, value);
497 return;
498 }
499
500
501 hme_write32(hp, tregs + TCVR_FRAME,
502 (FRAME_WRITE | (hp->paddr << 23) |
503 ((reg & 0xff) << 18) | (value & 0xffff)));
504 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
505 udelay(20);
506
507
508 if (!tries)
509 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
510
511
512}
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546static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
547{
548 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
549
550
551
552
553 if (hp->sw_bmcr & BMCR_FULLDPLX) {
554 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
555 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
556 return 0;
557 }
558
559
560 if (hp->sw_bmcr & BMCR_SPEED100) {
561 hp->sw_bmcr &= ~(BMCR_SPEED100);
562 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
563 return 0;
564 }
565
566
567 return -1;
568}
569
570static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
571{
572 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
573 if (hp->tcvr_type == external)
574 printk("external ");
575 else
576 printk("internal ");
577 printk("transceiver at ");
578 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
579 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
580 if (hp->sw_lpa & LPA_100FULL)
581 printk("100Mb/s, Full Duplex.\n");
582 else
583 printk("100Mb/s, Half Duplex.\n");
584 } else {
585 if (hp->sw_lpa & LPA_10FULL)
586 printk("10Mb/s, Full Duplex.\n");
587 else
588 printk("10Mb/s, Half Duplex.\n");
589 }
590}
591
592static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
593{
594 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
595 if (hp->tcvr_type == external)
596 printk("external ");
597 else
598 printk("internal ");
599 printk("transceiver at ");
600 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
601 if (hp->sw_bmcr & BMCR_SPEED100)
602 printk("100Mb/s, ");
603 else
604 printk("10Mb/s, ");
605 if (hp->sw_bmcr & BMCR_FULLDPLX)
606 printk("Full Duplex.\n");
607 else
608 printk("Half Duplex.\n");
609}
610
611static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
612{
613 int full;
614
615
616
617
618 if (hp->timer_state == arbwait) {
619 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
620 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
621 goto no_response;
622 if (hp->sw_lpa & LPA_100FULL)
623 full = 1;
624 else if (hp->sw_lpa & LPA_100HALF)
625 full = 0;
626 else if (hp->sw_lpa & LPA_10FULL)
627 full = 1;
628 else
629 full = 0;
630 } else {
631
632 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
633 if (hp->sw_bmcr & BMCR_FULLDPLX)
634 full = 1;
635 else
636 full = 0;
637 }
638
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644
645
646
647 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
648 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
649 ~(BIGMAC_TXCFG_ENABLE));
650 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
651 barrier();
652 if (full) {
653 hp->happy_flags |= HFLAG_FULL;
654 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
655 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
656 BIGMAC_TXCFG_FULLDPLX);
657 } else {
658 hp->happy_flags &= ~(HFLAG_FULL);
659 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
660 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
661 ~(BIGMAC_TXCFG_FULLDPLX));
662 }
663 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
664 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
665 BIGMAC_TXCFG_ENABLE);
666 return 0;
667no_response:
668 return 1;
669}
670
671static int happy_meal_init(struct happy_meal *hp);
672
673static int is_lucent_phy(struct happy_meal *hp)
674{
675 void __iomem *tregs = hp->tcvregs;
676 unsigned short mr2, mr3;
677 int ret = 0;
678
679 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
680 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
681 if ((mr2 & 0xffff) == 0x0180 &&
682 ((mr3 & 0xffff) >> 10) == 0x1d)
683 ret = 1;
684
685 return ret;
686}
687
688static void happy_meal_timer(unsigned long data)
689{
690 struct happy_meal *hp = (struct happy_meal *) data;
691 void __iomem *tregs = hp->tcvregs;
692 int restart_timer = 0;
693
694 spin_lock_irq(&hp->happy_lock);
695
696 hp->timer_ticks++;
697 switch(hp->timer_state) {
698 case arbwait:
699
700
701
702 if (hp->timer_ticks >= 10) {
703
704 do_force_mode:
705 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
706 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
707 hp->dev->name);
708 hp->sw_bmcr = BMCR_SPEED100;
709 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
710
711 if (!is_lucent_phy(hp)) {
712
713
714
715
716 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
717 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
718 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
719 }
720 hp->timer_state = ltrywait;
721 hp->timer_ticks = 0;
722 restart_timer = 1;
723 } else {
724
725 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
726 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
727 int ret;
728
729
730 ret = set_happy_link_modes(hp, tregs);
731 if (ret) {
732
733
734
735
736
737
738 goto do_force_mode;
739 }
740
741
742 hp->timer_state = lupwait;
743 restart_timer = 1;
744 } else {
745 restart_timer = 1;
746 }
747 }
748 break;
749
750 case lupwait:
751
752
753
754
755
756 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
757 if (hp->sw_bmsr & BMSR_LSTATUS) {
758
759
760
761 display_link_mode(hp, tregs);
762 hp->timer_state = asleep;
763 restart_timer = 0;
764 } else {
765 if (hp->timer_ticks >= 10) {
766 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
767 "not completely up.\n", hp->dev->name);
768 hp->timer_ticks = 0;
769 restart_timer = 1;
770 } else {
771 restart_timer = 1;
772 }
773 }
774 break;
775
776 case ltrywait:
777
778
779
780
781
782 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
783 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
784 if (hp->timer_ticks == 1) {
785 if (!is_lucent_phy(hp)) {
786
787
788
789 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
790 happy_meal_tcvr_write(hp, tregs,
791 DP83840_CSCONFIG, hp->sw_csconfig);
792 }
793 restart_timer = 1;
794 break;
795 }
796 if (hp->timer_ticks == 2) {
797 if (!is_lucent_phy(hp)) {
798 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
799 happy_meal_tcvr_write(hp, tregs,
800 DP83840_CSCONFIG, hp->sw_csconfig);
801 }
802 restart_timer = 1;
803 break;
804 }
805 if (hp->sw_bmsr & BMSR_LSTATUS) {
806
807 display_forced_link_mode(hp, tregs);
808 set_happy_link_modes(hp, tregs);
809 hp->timer_state = asleep;
810 restart_timer = 0;
811 } else {
812 if (hp->timer_ticks >= 4) {
813 int ret;
814
815 ret = try_next_permutation(hp, tregs);
816 if (ret == -1) {
817
818
819
820
821
822 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
823 hp->dev->name);
824
825 ret = happy_meal_init(hp);
826 if (ret) {
827
828 printk(KERN_ERR "%s: Error, cannot re-init the "
829 "Happy Meal.\n", hp->dev->name);
830 }
831 goto out;
832 }
833 if (!is_lucent_phy(hp)) {
834 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
835 DP83840_CSCONFIG);
836 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
837 happy_meal_tcvr_write(hp, tregs,
838 DP83840_CSCONFIG, hp->sw_csconfig);
839 }
840 hp->timer_ticks = 0;
841 restart_timer = 1;
842 } else {
843 restart_timer = 1;
844 }
845 }
846 break;
847
848 case asleep:
849 default:
850
851 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
852 hp->dev->name);
853 restart_timer = 0;
854 hp->timer_ticks = 0;
855 hp->timer_state = asleep;
856 break;
857 }
858
859 if (restart_timer) {
860 hp->happy_timer.expires = jiffies + ((12 * HZ)/10);
861 add_timer(&hp->happy_timer);
862 }
863
864out:
865 spin_unlock_irq(&hp->happy_lock);
866}
867
868#define TX_RESET_TRIES 32
869#define RX_RESET_TRIES 32
870
871
872static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
873{
874 int tries = TX_RESET_TRIES;
875
876 HMD(("happy_meal_tx_reset: reset, "));
877
878
879 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
880 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
881 udelay(20);
882
883
884 if (!tries)
885 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
886
887
888 HMD(("done\n"));
889}
890
891
892static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
893{
894 int tries = RX_RESET_TRIES;
895
896 HMD(("happy_meal_rx_reset: reset, "));
897
898
899 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
900 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
901 udelay(20);
902
903
904 if (!tries)
905 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
906
907
908 HMD(("done\n"));
909}
910
911#define STOP_TRIES 16
912
913
914static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
915{
916 int tries = STOP_TRIES;
917
918 HMD(("happy_meal_stop: reset, "));
919
920
921 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
922 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
923 udelay(20);
924
925
926 if (!tries)
927 printk(KERN_ERR "happy meal: Fry guys.");
928
929
930 HMD(("done\n"));
931}
932
933
934static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
935{
936 struct net_device_stats *stats = &hp->net_stats;
937
938 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
939 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
940
941 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
942 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
943
944 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
945 hme_write32(hp, bregs + BMAC_GLECTR, 0);
946
947 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
948
949 stats->collisions +=
950 (hme_read32(hp, bregs + BMAC_EXCTR) +
951 hme_read32(hp, bregs + BMAC_LTCTR));
952 hme_write32(hp, bregs + BMAC_EXCTR, 0);
953 hme_write32(hp, bregs + BMAC_LTCTR, 0);
954}
955
956
957static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
958{
959 ASD(("happy_meal_poll_stop: "));
960
961
962 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
963 (HFLAG_POLLENABLE | HFLAG_POLL)) {
964 HMD(("not polling, return\n"));
965 return;
966 }
967
968
969 ASD(("were polling, mif ints off, "));
970 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
971
972
973 ASD(("polling off, "));
974 hme_write32(hp, tregs + TCVR_CFG,
975 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
976
977
978 hp->happy_flags &= ~(HFLAG_POLL);
979
980
981 udelay(200);
982 ASD(("done\n"));
983}
984
985
986
987
988#define TCVR_RESET_TRIES 16
989#define TCVR_UNISOLATE_TRIES 32
990
991
992static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
993{
994 u32 tconfig;
995 int result, tries = TCVR_RESET_TRIES;
996
997 tconfig = hme_read32(hp, tregs + TCVR_CFG);
998 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
999 if (hp->tcvr_type == external) {
1000 ASD(("external<"));
1001 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1002 hp->tcvr_type = internal;
1003 hp->paddr = TCV_PADDR_ITX;
1004 ASD(("ISOLATE,"));
1005 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1006 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1007 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1008 if (result == TCVR_FAILURE) {
1009 ASD(("phyread_fail>\n"));
1010 return -1;
1011 }
1012 ASD(("phyread_ok,PSELECT>"));
1013 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1014 hp->tcvr_type = external;
1015 hp->paddr = TCV_PADDR_ETX;
1016 } else {
1017 if (tconfig & TCV_CFG_MDIO1) {
1018 ASD(("internal<PSELECT,"));
1019 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1020 ASD(("ISOLATE,"));
1021 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1022 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1023 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1024 if (result == TCVR_FAILURE) {
1025 ASD(("phyread_fail>\n"));
1026 return -1;
1027 }
1028 ASD(("phyread_ok,~PSELECT>"));
1029 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1030 hp->tcvr_type = internal;
1031 hp->paddr = TCV_PADDR_ITX;
1032 }
1033 }
1034
1035 ASD(("BMCR_RESET "));
1036 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1037
1038 while (--tries) {
1039 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1040 if (result == TCVR_FAILURE)
1041 return -1;
1042 hp->sw_bmcr = result;
1043 if (!(result & BMCR_RESET))
1044 break;
1045 udelay(20);
1046 }
1047 if (!tries) {
1048 ASD(("BMCR RESET FAILED!\n"));
1049 return -1;
1050 }
1051 ASD(("RESET_OK\n"));
1052
1053
1054 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1055 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1056 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1057 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1058
1059 ASD(("UNISOLATE"));
1060 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1061 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1062
1063 tries = TCVR_UNISOLATE_TRIES;
1064 while (--tries) {
1065 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1066 if (result == TCVR_FAILURE)
1067 return -1;
1068 if (!(result & BMCR_ISOLATE))
1069 break;
1070 udelay(20);
1071 }
1072 if (!tries) {
1073 ASD((" FAILED!\n"));
1074 return -1;
1075 }
1076 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1077 if (!is_lucent_phy(hp)) {
1078 result = happy_meal_tcvr_read(hp, tregs,
1079 DP83840_CSCONFIG);
1080 happy_meal_tcvr_write(hp, tregs,
1081 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1082 }
1083 return 0;
1084}
1085
1086
1087
1088
1089
1090static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1091{
1092 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1093
1094 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1095 if (hp->happy_flags & HFLAG_POLL) {
1096
1097 ASD(("<polling> "));
1098 if (hp->tcvr_type == internal) {
1099 if (tconfig & TCV_CFG_MDIO1) {
1100 ASD(("<internal> <poll stop> "));
1101 happy_meal_poll_stop(hp, tregs);
1102 hp->paddr = TCV_PADDR_ETX;
1103 hp->tcvr_type = external;
1104 ASD(("<external>\n"));
1105 tconfig &= ~(TCV_CFG_PENABLE);
1106 tconfig |= TCV_CFG_PSELECT;
1107 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1108 }
1109 } else {
1110 if (hp->tcvr_type == external) {
1111 ASD(("<external> "));
1112 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1113 ASD(("<poll stop> "));
1114 happy_meal_poll_stop(hp, tregs);
1115 hp->paddr = TCV_PADDR_ITX;
1116 hp->tcvr_type = internal;
1117 ASD(("<internal>\n"));
1118 hme_write32(hp, tregs + TCVR_CFG,
1119 hme_read32(hp, tregs + TCVR_CFG) &
1120 ~(TCV_CFG_PSELECT));
1121 }
1122 ASD(("\n"));
1123 } else {
1124 ASD(("<none>\n"));
1125 }
1126 }
1127 } else {
1128 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1129
1130
1131 ASD(("<not polling> "));
1132 if (reread & TCV_CFG_MDIO1) {
1133 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1134 hp->paddr = TCV_PADDR_ETX;
1135 hp->tcvr_type = external;
1136 ASD(("<external>\n"));
1137 } else {
1138 if (reread & TCV_CFG_MDIO0) {
1139 hme_write32(hp, tregs + TCVR_CFG,
1140 tconfig & ~(TCV_CFG_PSELECT));
1141 hp->paddr = TCV_PADDR_ITX;
1142 hp->tcvr_type = internal;
1143 ASD(("<internal>\n"));
1144 } else {
1145 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1146 hp->tcvr_type = none;
1147 ASD(("<none>\n"));
1148 }
1149 }
1150 }
1151}
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197static void happy_meal_clean_rings(struct happy_meal *hp)
1198{
1199 int i;
1200
1201 for (i = 0; i < RX_RING_SIZE; i++) {
1202 if (hp->rx_skbs[i] != NULL) {
1203 struct sk_buff *skb = hp->rx_skbs[i];
1204 struct happy_meal_rxd *rxd;
1205 u32 dma_addr;
1206
1207 rxd = &hp->happy_block->happy_meal_rxd[i];
1208 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1209 dma_unmap_single(hp->dma_dev, dma_addr,
1210 RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1211 dev_kfree_skb_any(skb);
1212 hp->rx_skbs[i] = NULL;
1213 }
1214 }
1215
1216 for (i = 0; i < TX_RING_SIZE; i++) {
1217 if (hp->tx_skbs[i] != NULL) {
1218 struct sk_buff *skb = hp->tx_skbs[i];
1219 struct happy_meal_txd *txd;
1220 u32 dma_addr;
1221 int frag;
1222
1223 hp->tx_skbs[i] = NULL;
1224
1225 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1226 txd = &hp->happy_block->happy_meal_txd[i];
1227 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1228 if (!frag)
1229 dma_unmap_single(hp->dma_dev, dma_addr,
1230 (hme_read_desc32(hp, &txd->tx_flags)
1231 & TXFLAG_SIZE),
1232 DMA_TO_DEVICE);
1233 else
1234 dma_unmap_page(hp->dma_dev, dma_addr,
1235 (hme_read_desc32(hp, &txd->tx_flags)
1236 & TXFLAG_SIZE),
1237 DMA_TO_DEVICE);
1238
1239 if (frag != skb_shinfo(skb)->nr_frags)
1240 i++;
1241 }
1242
1243 dev_kfree_skb_any(skb);
1244 }
1245 }
1246}
1247
1248
1249static void happy_meal_init_rings(struct happy_meal *hp)
1250{
1251 struct hmeal_init_block *hb = hp->happy_block;
1252 int i;
1253
1254 HMD(("happy_meal_init_rings: counters to zero, "));
1255 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1256
1257
1258 HMD(("clean, "));
1259 happy_meal_clean_rings(hp);
1260
1261
1262 HMD(("init rxring, "));
1263 for (i = 0; i < RX_RING_SIZE; i++) {
1264 struct sk_buff *skb;
1265
1266 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1267 if (!skb) {
1268 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1269 continue;
1270 }
1271 hp->rx_skbs[i] = skb;
1272
1273
1274 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1275 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1276 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1277 dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1278 DMA_FROM_DEVICE));
1279 skb_reserve(skb, RX_OFFSET);
1280 }
1281
1282 HMD(("init txring, "));
1283 for (i = 0; i < TX_RING_SIZE; i++)
1284 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1285
1286 HMD(("done\n"));
1287}
1288
1289
1290static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1291 void __iomem *tregs,
1292 struct ethtool_cmd *ep)
1293{
1294 int timeout;
1295
1296
1297 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1298 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1299 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1300 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1301
1302
1303
1304 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1305 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1306
1307 if (hp->sw_bmsr & BMSR_10HALF)
1308 hp->sw_advertise |= (ADVERTISE_10HALF);
1309 else
1310 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1311
1312 if (hp->sw_bmsr & BMSR_10FULL)
1313 hp->sw_advertise |= (ADVERTISE_10FULL);
1314 else
1315 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1316 if (hp->sw_bmsr & BMSR_100HALF)
1317 hp->sw_advertise |= (ADVERTISE_100HALF);
1318 else
1319 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1320 if (hp->sw_bmsr & BMSR_100FULL)
1321 hp->sw_advertise |= (ADVERTISE_100FULL);
1322 else
1323 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1324 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1325
1326
1327
1328
1329
1330
1331
1332#ifdef AUTO_SWITCH_DEBUG
1333 ASD(("%s: Advertising [ ", hp->dev->name));
1334 if (hp->sw_advertise & ADVERTISE_10HALF)
1335 ASD(("10H "));
1336 if (hp->sw_advertise & ADVERTISE_10FULL)
1337 ASD(("10F "));
1338 if (hp->sw_advertise & ADVERTISE_100HALF)
1339 ASD(("100H "));
1340 if (hp->sw_advertise & ADVERTISE_100FULL)
1341 ASD(("100F "));
1342#endif
1343
1344
1345 hp->sw_bmcr |= BMCR_ANENABLE;
1346 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1347
1348
1349 hp->sw_bmcr |= BMCR_ANRESTART;
1350 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1351
1352
1353
1354 timeout = 64;
1355 while (--timeout) {
1356 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1357 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1358 break;
1359 udelay(10);
1360 }
1361 if (!timeout) {
1362 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1363 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1364 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1365 hp->dev->name);
1366 goto force_link;
1367 } else {
1368 hp->timer_state = arbwait;
1369 }
1370 } else {
1371force_link:
1372
1373
1374
1375
1376
1377
1378
1379
1380 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1381 hp->sw_bmcr = BMCR_SPEED100;
1382 } else {
1383 if (ethtool_cmd_speed(ep) == SPEED_100)
1384 hp->sw_bmcr = BMCR_SPEED100;
1385 else
1386 hp->sw_bmcr = 0;
1387 if (ep->duplex == DUPLEX_FULL)
1388 hp->sw_bmcr |= BMCR_FULLDPLX;
1389 }
1390 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1391
1392 if (!is_lucent_phy(hp)) {
1393
1394
1395
1396
1397 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1398 DP83840_CSCONFIG);
1399 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1400 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1401 hp->sw_csconfig);
1402 }
1403 hp->timer_state = ltrywait;
1404 }
1405
1406 hp->timer_ticks = 0;
1407 hp->happy_timer.expires = jiffies + (12 * HZ)/10;
1408 hp->happy_timer.data = (unsigned long) hp;
1409 hp->happy_timer.function = happy_meal_timer;
1410 add_timer(&hp->happy_timer);
1411}
1412
1413
1414static int happy_meal_init(struct happy_meal *hp)
1415{
1416 void __iomem *gregs = hp->gregs;
1417 void __iomem *etxregs = hp->etxregs;
1418 void __iomem *erxregs = hp->erxregs;
1419 void __iomem *bregs = hp->bigmacregs;
1420 void __iomem *tregs = hp->tcvregs;
1421 u32 regtmp, rxcfg;
1422 unsigned char *e = &hp->dev->dev_addr[0];
1423
1424
1425 del_timer(&hp->happy_timer);
1426
1427 HMD(("happy_meal_init: happy_flags[%08x] ",
1428 hp->happy_flags));
1429 if (!(hp->happy_flags & HFLAG_INIT)) {
1430 HMD(("set HFLAG_INIT, "));
1431 hp->happy_flags |= HFLAG_INIT;
1432 happy_meal_get_counters(hp, bregs);
1433 }
1434
1435
1436 HMD(("to happy_meal_poll_stop\n"));
1437 happy_meal_poll_stop(hp, tregs);
1438
1439
1440 HMD(("happy_meal_init: to happy_meal_stop\n"));
1441 happy_meal_stop(hp, gregs);
1442
1443
1444 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1445 happy_meal_init_rings(hp);
1446
1447
1448 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1449 hme_read32(hp, tregs + TCVR_IMASK)));
1450 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1451
1452
1453 if (hp->happy_flags & HFLAG_FENABLE) {
1454 HMD(("use frame old[%08x], ",
1455 hme_read32(hp, tregs + TCVR_CFG)));
1456 hme_write32(hp, tregs + TCVR_CFG,
1457 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1458 } else {
1459 HMD(("use bitbang old[%08x], ",
1460 hme_read32(hp, tregs + TCVR_CFG)));
1461 hme_write32(hp, tregs + TCVR_CFG,
1462 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1463 }
1464
1465
1466 HMD(("to happy_meal_transceiver_check\n"));
1467 happy_meal_transceiver_check(hp, tregs);
1468
1469
1470 HMD(("happy_meal_init: "));
1471 switch(hp->tcvr_type) {
1472 case none:
1473
1474 HMD(("AAIEEE no transceiver type, EAGAIN"));
1475 return -EAGAIN;
1476
1477 case internal:
1478
1479 HMD(("internal, using MII, "));
1480 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1481 break;
1482
1483 case external:
1484
1485 HMD(("external, disable MII, "));
1486 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1487 break;
1488 }
1489
1490 if (happy_meal_tcvr_reset(hp, tregs))
1491 return -EAGAIN;
1492
1493
1494 HMD(("tx/rx reset, "));
1495 happy_meal_tx_reset(hp, bregs);
1496 happy_meal_rx_reset(hp, bregs);
1497
1498
1499 HMD(("jsize/ipg1/ipg2, "));
1500 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1501 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1502 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1503
1504
1505 HMD(("rseed/macaddr, "));
1506
1507
1508 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1509
1510 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1511 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1512 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1513
1514 HMD(("htable, "));
1515 if ((hp->dev->flags & IFF_ALLMULTI) ||
1516 (netdev_mc_count(hp->dev) > 64)) {
1517 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1518 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1519 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1520 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1521 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1522 u16 hash_table[4];
1523 struct netdev_hw_addr *ha;
1524 u32 crc;
1525
1526 memset(hash_table, 0, sizeof(hash_table));
1527 netdev_for_each_mc_addr(ha, hp->dev) {
1528 crc = ether_crc_le(6, ha->addr);
1529 crc >>= 26;
1530 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1531 }
1532 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1533 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1534 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1535 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1536 } else {
1537 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1538 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1539 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1540 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1541 }
1542
1543
1544 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1545 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1546 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1547 hme_write32(hp, erxregs + ERX_RING,
1548 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1549 hme_write32(hp, etxregs + ETX_RING,
1550 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1551
1552
1553
1554
1555
1556
1557 if (hme_read32(hp, erxregs + ERX_RING) !=
1558 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1559 hme_write32(hp, erxregs + ERX_RING,
1560 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1561 | 0x4);
1562
1563
1564 HMD(("happy_meal_init: old[%08x] bursts<",
1565 hme_read32(hp, gregs + GREG_CFG)));
1566
1567#ifndef CONFIG_SPARC
1568
1569 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1570#else
1571 if ((hp->happy_bursts & DMA_BURST64) &&
1572 ((hp->happy_flags & HFLAG_PCI) != 0
1573#ifdef CONFIG_SBUS
1574 || sbus_can_burst64()
1575#endif
1576 || 0)) {
1577 u32 gcfg = GREG_CFG_BURST64;
1578
1579
1580
1581
1582
1583#ifdef CONFIG_SBUS
1584 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1585 struct platform_device *op = hp->happy_dev;
1586 if (sbus_can_dma_64bit()) {
1587 sbus_set_sbus64(&op->dev,
1588 hp->happy_bursts);
1589 gcfg |= GREG_CFG_64BIT;
1590 }
1591 }
1592#endif
1593
1594 HMD(("64>"));
1595 hme_write32(hp, gregs + GREG_CFG, gcfg);
1596 } else if (hp->happy_bursts & DMA_BURST32) {
1597 HMD(("32>"));
1598 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1599 } else if (hp->happy_bursts & DMA_BURST16) {
1600 HMD(("16>"));
1601 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1602 } else {
1603 HMD(("XXX>"));
1604 hme_write32(hp, gregs + GREG_CFG, 0);
1605 }
1606#endif
1607
1608
1609 HMD((", enable global interrupts, "));
1610 hme_write32(hp, gregs + GREG_IMASK,
1611 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1612 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1613
1614
1615 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1616 hme_read32(hp, etxregs + ETX_RSIZE)));
1617 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1618
1619
1620 HMD(("tx dma enable old[%08x], ",
1621 hme_read32(hp, etxregs + ETX_CFG)));
1622 hme_write32(hp, etxregs + ETX_CFG,
1623 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1624
1625
1626
1627
1628
1629
1630 HMD(("erx regs bug old[%08x]\n",
1631 hme_read32(hp, erxregs + ERX_CFG)));
1632 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1633 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1634 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1635 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1636 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1637 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1638 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1639
1640 }
1641
1642
1643 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1644 hme_read32(hp, bregs + BMAC_RXCFG)));
1645 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1646 if (hp->dev->flags & IFF_PROMISC)
1647 rxcfg |= BIGMAC_RXCFG_PMISC;
1648 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1649
1650
1651 udelay(10);
1652
1653
1654 HMD(("BIGMAC init, "));
1655 regtmp = 0;
1656 if (hp->happy_flags & HFLAG_FULL)
1657 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1658
1659
1660
1661
1662 hme_write32(hp, bregs + BMAC_TXCFG, regtmp );
1663
1664
1665 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1666
1667
1668 regtmp = BIGMAC_XCFG_ODENABLE;
1669
1670
1671 if (hp->happy_flags & HFLAG_LANCE)
1672 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1673
1674
1675 if (hp->tcvr_type == external)
1676 regtmp |= BIGMAC_XCFG_MIIDISAB;
1677
1678 HMD(("XIF config old[%08x], ",
1679 hme_read32(hp, bregs + BMAC_XIFCFG)));
1680 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1681
1682
1683 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1684 hme_read32(hp, bregs + BMAC_TXCFG),
1685 hme_read32(hp, bregs + BMAC_RXCFG)));
1686
1687
1688 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1689 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1690
1691 hme_write32(hp, bregs + BMAC_TXCFG,
1692 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1693 hme_write32(hp, bregs + BMAC_RXCFG,
1694 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1695
1696
1697 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1698
1699
1700 return 0;
1701}
1702
1703
1704static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1705{
1706 void __iomem *tregs = hp->tcvregs;
1707 void __iomem *bregs = hp->bigmacregs;
1708 void __iomem *gregs = hp->gregs;
1709
1710 happy_meal_stop(hp, gregs);
1711 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1712 if (hp->happy_flags & HFLAG_FENABLE)
1713 hme_write32(hp, tregs + TCVR_CFG,
1714 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1715 else
1716 hme_write32(hp, tregs + TCVR_CFG,
1717 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1718 happy_meal_transceiver_check(hp, tregs);
1719 switch(hp->tcvr_type) {
1720 case none:
1721 return;
1722 case internal:
1723 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1724 break;
1725 case external:
1726 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1727 break;
1728 }
1729 if (happy_meal_tcvr_reset(hp, tregs))
1730 return;
1731
1732
1733 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1734 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1735
1736
1737 if (hp->sw_bmsr & BMSR_10HALF)
1738 hp->sw_advertise |= (ADVERTISE_10HALF);
1739 else
1740 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1741
1742 if (hp->sw_bmsr & BMSR_10FULL)
1743 hp->sw_advertise |= (ADVERTISE_10FULL);
1744 else
1745 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1746 if (hp->sw_bmsr & BMSR_100HALF)
1747 hp->sw_advertise |= (ADVERTISE_100HALF);
1748 else
1749 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1750 if (hp->sw_bmsr & BMSR_100FULL)
1751 hp->sw_advertise |= (ADVERTISE_100FULL);
1752 else
1753 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1754
1755
1756 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1757}
1758
1759
1760
1761
1762
1763
1764static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1765{
1766 int reset = 0;
1767
1768
1769 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1770 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1771 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1772 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1773 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1774 GREG_STAT_SLVPERR))
1775 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1776 hp->dev->name, status);
1777
1778 if (status & GREG_STAT_RFIFOVF) {
1779
1780
1781 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1782 }
1783
1784 if (status & GREG_STAT_STSTERR) {
1785
1786 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1787 reset = 1;
1788 }
1789
1790 if (status & GREG_STAT_TFIFO_UND) {
1791
1792 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1793 hp->dev->name);
1794 reset = 1;
1795 }
1796
1797 if (status & GREG_STAT_MAXPKTERR) {
1798
1799
1800
1801 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1802 reset = 1;
1803 }
1804
1805 if (status & GREG_STAT_NORXD) {
1806
1807
1808
1809
1810
1811 printk(KERN_INFO "%s: Happy Meal out of receive "
1812 "descriptors, packet dropped.\n",
1813 hp->dev->name);
1814 }
1815
1816 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1817
1818 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1819 if (status & GREG_STAT_RXERR)
1820 printk("GenericError ");
1821 if (status & GREG_STAT_RXPERR)
1822 printk("ParityError ");
1823 if (status & GREG_STAT_RXTERR)
1824 printk("RxTagBotch ");
1825 printk("]\n");
1826 reset = 1;
1827 }
1828
1829 if (status & GREG_STAT_EOPERR) {
1830
1831
1832
1833 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1834 hp->dev->name);
1835 reset = 1;
1836 }
1837
1838 if (status & GREG_STAT_MIFIRQ) {
1839
1840 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1841 }
1842
1843 if (status &
1844 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1845
1846 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1847 if (status & GREG_STAT_TXEACK)
1848 printk("GenericError ");
1849 if (status & GREG_STAT_TXLERR)
1850 printk("LateError ");
1851 if (status & GREG_STAT_TXPERR)
1852 printk("ParityErro ");
1853 if (status & GREG_STAT_TXTERR)
1854 printk("TagBotch ");
1855 printk("]\n");
1856 reset = 1;
1857 }
1858
1859 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1860
1861
1862
1863 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1864 hp->dev->name,
1865 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1866 reset = 1;
1867 }
1868
1869 if (reset) {
1870 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1871 happy_meal_init(hp);
1872 return 1;
1873 }
1874 return 0;
1875}
1876
1877
1878static void happy_meal_mif_interrupt(struct happy_meal *hp)
1879{
1880 void __iomem *tregs = hp->tcvregs;
1881
1882 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1883 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1884 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1885
1886
1887 if (hp->sw_lpa & LPA_100FULL) {
1888 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1889 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1890 } else if (hp->sw_lpa & LPA_100HALF) {
1891 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1892 hp->sw_bmcr |= BMCR_SPEED100;
1893 } else if (hp->sw_lpa & LPA_10FULL) {
1894 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1895 hp->sw_bmcr |= BMCR_FULLDPLX;
1896 } else {
1897 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1898 }
1899 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1900
1901
1902 happy_meal_poll_stop(hp, tregs);
1903}
1904
1905#ifdef TXDEBUG
1906#define TXD(x) printk x
1907#else
1908#define TXD(x)
1909#endif
1910
1911
1912static void happy_meal_tx(struct happy_meal *hp)
1913{
1914 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1915 struct happy_meal_txd *this;
1916 struct net_device *dev = hp->dev;
1917 int elem;
1918
1919 elem = hp->tx_old;
1920 TXD(("TX<"));
1921 while (elem != hp->tx_new) {
1922 struct sk_buff *skb;
1923 u32 flags, dma_addr, dma_len;
1924 int frag;
1925
1926 TXD(("[%d]", elem));
1927 this = &txbase[elem];
1928 flags = hme_read_desc32(hp, &this->tx_flags);
1929 if (flags & TXFLAG_OWN)
1930 break;
1931 skb = hp->tx_skbs[elem];
1932 if (skb_shinfo(skb)->nr_frags) {
1933 int last;
1934
1935 last = elem + skb_shinfo(skb)->nr_frags;
1936 last &= (TX_RING_SIZE - 1);
1937 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1938 if (flags & TXFLAG_OWN)
1939 break;
1940 }
1941 hp->tx_skbs[elem] = NULL;
1942 hp->net_stats.tx_bytes += skb->len;
1943
1944 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1945 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1946 dma_len = hme_read_desc32(hp, &this->tx_flags);
1947
1948 dma_len &= TXFLAG_SIZE;
1949 if (!frag)
1950 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1951 else
1952 dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1953
1954 elem = NEXT_TX(elem);
1955 this = &txbase[elem];
1956 }
1957
1958 dev_kfree_skb_irq(skb);
1959 hp->net_stats.tx_packets++;
1960 }
1961 hp->tx_old = elem;
1962 TXD((">"));
1963
1964 if (netif_queue_stopped(dev) &&
1965 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1966 netif_wake_queue(dev);
1967}
1968
1969#ifdef RXDEBUG
1970#define RXD(x) printk x
1971#else
1972#define RXD(x)
1973#endif
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1985{
1986 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1987 struct happy_meal_rxd *this;
1988 int elem = hp->rx_new, drops = 0;
1989 u32 flags;
1990
1991 RXD(("RX<"));
1992 this = &rxbase[elem];
1993 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1994 struct sk_buff *skb;
1995 int len = flags >> 16;
1996 u16 csum = flags & RXFLAG_CSUM;
1997 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
1998
1999 RXD(("[%d ", elem));
2000
2001
2002 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2003 RXD(("ERR(%08x)]", flags));
2004 hp->net_stats.rx_errors++;
2005 if (len < ETH_ZLEN)
2006 hp->net_stats.rx_length_errors++;
2007 if (len & (RXFLAG_OVERFLOW >> 16)) {
2008 hp->net_stats.rx_over_errors++;
2009 hp->net_stats.rx_fifo_errors++;
2010 }
2011
2012
2013 drop_it:
2014 hp->net_stats.rx_dropped++;
2015 hme_write_rxd(hp, this,
2016 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2017 dma_addr);
2018 goto next;
2019 }
2020 skb = hp->rx_skbs[elem];
2021 if (len > RX_COPY_THRESHOLD) {
2022 struct sk_buff *new_skb;
2023
2024
2025 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2026 if (new_skb == NULL) {
2027 drops++;
2028 goto drop_it;
2029 }
2030 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2031 hp->rx_skbs[elem] = new_skb;
2032 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2033 hme_write_rxd(hp, this,
2034 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2035 dma_map_single(hp->dma_dev, new_skb->data, RX_BUF_ALLOC_SIZE,
2036 DMA_FROM_DEVICE));
2037 skb_reserve(new_skb, RX_OFFSET);
2038
2039
2040 skb_trim(skb, len);
2041 } else {
2042 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
2043
2044 if (copy_skb == NULL) {
2045 drops++;
2046 goto drop_it;
2047 }
2048
2049 skb_reserve(copy_skb, 2);
2050 skb_put(copy_skb, len);
2051 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2052 skb_copy_from_linear_data(skb, copy_skb->data, len);
2053 dma_sync_single_for_device(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2054
2055 hme_write_rxd(hp, this,
2056 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2057 dma_addr);
2058
2059 skb = copy_skb;
2060 }
2061
2062
2063 skb->csum = csum_unfold(~(__force __sum16)htons(csum));
2064 skb->ip_summed = CHECKSUM_COMPLETE;
2065
2066 RXD(("len=%d csum=%4x]", len, csum));
2067 skb->protocol = eth_type_trans(skb, dev);
2068 netif_rx(skb);
2069
2070 hp->net_stats.rx_packets++;
2071 hp->net_stats.rx_bytes += len;
2072 next:
2073 elem = NEXT_RX(elem);
2074 this = &rxbase[elem];
2075 }
2076 hp->rx_new = elem;
2077 if (drops)
2078 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2079 RXD((">"));
2080}
2081
2082static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2083{
2084 struct net_device *dev = dev_id;
2085 struct happy_meal *hp = netdev_priv(dev);
2086 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2087
2088 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2089
2090 spin_lock(&hp->happy_lock);
2091
2092 if (happy_status & GREG_STAT_ERRORS) {
2093 HMD(("ERRORS "));
2094 if (happy_meal_is_not_so_happy(hp, happy_status))
2095 goto out;
2096 }
2097
2098 if (happy_status & GREG_STAT_MIFIRQ) {
2099 HMD(("MIFIRQ "));
2100 happy_meal_mif_interrupt(hp);
2101 }
2102
2103 if (happy_status & GREG_STAT_TXALL) {
2104 HMD(("TXALL "));
2105 happy_meal_tx(hp);
2106 }
2107
2108 if (happy_status & GREG_STAT_RXTOHOST) {
2109 HMD(("RXTOHOST "));
2110 happy_meal_rx(hp, dev);
2111 }
2112
2113 HMD(("done\n"));
2114out:
2115 spin_unlock(&hp->happy_lock);
2116
2117 return IRQ_HANDLED;
2118}
2119
2120#ifdef CONFIG_SBUS
2121static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2122{
2123 struct quattro *qp = (struct quattro *) cookie;
2124 int i;
2125
2126 for (i = 0; i < 4; i++) {
2127 struct net_device *dev = qp->happy_meals[i];
2128 struct happy_meal *hp = netdev_priv(dev);
2129 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2130
2131 HMD(("quattro_interrupt: status=%08x ", happy_status));
2132
2133 if (!(happy_status & (GREG_STAT_ERRORS |
2134 GREG_STAT_MIFIRQ |
2135 GREG_STAT_TXALL |
2136 GREG_STAT_RXTOHOST)))
2137 continue;
2138
2139 spin_lock(&hp->happy_lock);
2140
2141 if (happy_status & GREG_STAT_ERRORS) {
2142 HMD(("ERRORS "));
2143 if (happy_meal_is_not_so_happy(hp, happy_status))
2144 goto next;
2145 }
2146
2147 if (happy_status & GREG_STAT_MIFIRQ) {
2148 HMD(("MIFIRQ "));
2149 happy_meal_mif_interrupt(hp);
2150 }
2151
2152 if (happy_status & GREG_STAT_TXALL) {
2153 HMD(("TXALL "));
2154 happy_meal_tx(hp);
2155 }
2156
2157 if (happy_status & GREG_STAT_RXTOHOST) {
2158 HMD(("RXTOHOST "));
2159 happy_meal_rx(hp, dev);
2160 }
2161
2162 next:
2163 spin_unlock(&hp->happy_lock);
2164 }
2165 HMD(("done\n"));
2166
2167 return IRQ_HANDLED;
2168}
2169#endif
2170
2171static int happy_meal_open(struct net_device *dev)
2172{
2173 struct happy_meal *hp = netdev_priv(dev);
2174 int res;
2175
2176 HMD(("happy_meal_open: "));
2177
2178
2179
2180
2181 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2182 res = request_irq(hp->irq, happy_meal_interrupt, IRQF_SHARED,
2183 dev->name, dev);
2184 if (res) {
2185 HMD(("EAGAIN\n"));
2186 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2187 hp->irq);
2188
2189 return -EAGAIN;
2190 }
2191 }
2192
2193 HMD(("to happy_meal_init\n"));
2194
2195 spin_lock_irq(&hp->happy_lock);
2196 res = happy_meal_init(hp);
2197 spin_unlock_irq(&hp->happy_lock);
2198
2199 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2200 free_irq(hp->irq, dev);
2201 return res;
2202}
2203
2204static int happy_meal_close(struct net_device *dev)
2205{
2206 struct happy_meal *hp = netdev_priv(dev);
2207
2208 spin_lock_irq(&hp->happy_lock);
2209 happy_meal_stop(hp, hp->gregs);
2210 happy_meal_clean_rings(hp);
2211
2212
2213 del_timer(&hp->happy_timer);
2214
2215 spin_unlock_irq(&hp->happy_lock);
2216
2217
2218
2219
2220
2221 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2222 free_irq(hp->irq, dev);
2223
2224 return 0;
2225}
2226
2227#ifdef SXDEBUG
2228#define SXD(x) printk x
2229#else
2230#define SXD(x)
2231#endif
2232
2233static void happy_meal_tx_timeout(struct net_device *dev)
2234{
2235 struct happy_meal *hp = netdev_priv(dev);
2236
2237 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2238 tx_dump_log();
2239 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2240 hme_read32(hp, hp->gregs + GREG_STAT),
2241 hme_read32(hp, hp->etxregs + ETX_CFG),
2242 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2243
2244 spin_lock_irq(&hp->happy_lock);
2245 happy_meal_init(hp);
2246 spin_unlock_irq(&hp->happy_lock);
2247
2248 netif_wake_queue(dev);
2249}
2250
2251static netdev_tx_t happy_meal_start_xmit(struct sk_buff *skb,
2252 struct net_device *dev)
2253{
2254 struct happy_meal *hp = netdev_priv(dev);
2255 int entry;
2256 u32 tx_flags;
2257
2258 tx_flags = TXFLAG_OWN;
2259 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2260 const u32 csum_start_off = skb_checksum_start_offset(skb);
2261 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2262
2263 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2264 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2265 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2266 }
2267
2268 spin_lock_irq(&hp->happy_lock);
2269
2270 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2271 netif_stop_queue(dev);
2272 spin_unlock_irq(&hp->happy_lock);
2273 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2274 dev->name);
2275 return NETDEV_TX_BUSY;
2276 }
2277
2278 entry = hp->tx_new;
2279 SXD(("SX<l[%d]e[%d]>", len, entry));
2280 hp->tx_skbs[entry] = skb;
2281
2282 if (skb_shinfo(skb)->nr_frags == 0) {
2283 u32 mapping, len;
2284
2285 len = skb->len;
2286 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2287 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2288 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2289 (tx_flags | (len & TXFLAG_SIZE)),
2290 mapping);
2291 entry = NEXT_TX(entry);
2292 } else {
2293 u32 first_len, first_mapping;
2294 int frag, first_entry = entry;
2295
2296
2297
2298
2299 first_len = skb_headlen(skb);
2300 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2301 DMA_TO_DEVICE);
2302 entry = NEXT_TX(entry);
2303
2304 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2305 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2306 u32 len, mapping, this_txflags;
2307
2308 len = skb_frag_size(this_frag);
2309 mapping = skb_frag_dma_map(hp->dma_dev, this_frag,
2310 0, len, DMA_TO_DEVICE);
2311 this_txflags = tx_flags;
2312 if (frag == skb_shinfo(skb)->nr_frags - 1)
2313 this_txflags |= TXFLAG_EOP;
2314 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2315 (this_txflags | (len & TXFLAG_SIZE)),
2316 mapping);
2317 entry = NEXT_TX(entry);
2318 }
2319 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2320 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2321 first_mapping);
2322 }
2323
2324 hp->tx_new = entry;
2325
2326 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2327 netif_stop_queue(dev);
2328
2329
2330 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2331
2332 spin_unlock_irq(&hp->happy_lock);
2333
2334 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2335 return NETDEV_TX_OK;
2336}
2337
2338static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2339{
2340 struct happy_meal *hp = netdev_priv(dev);
2341
2342 spin_lock_irq(&hp->happy_lock);
2343 happy_meal_get_counters(hp, hp->bigmacregs);
2344 spin_unlock_irq(&hp->happy_lock);
2345
2346 return &hp->net_stats;
2347}
2348
2349static void happy_meal_set_multicast(struct net_device *dev)
2350{
2351 struct happy_meal *hp = netdev_priv(dev);
2352 void __iomem *bregs = hp->bigmacregs;
2353 struct netdev_hw_addr *ha;
2354 u32 crc;
2355
2356 spin_lock_irq(&hp->happy_lock);
2357
2358 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
2359 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2360 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2361 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2362 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2363 } else if (dev->flags & IFF_PROMISC) {
2364 hme_write32(hp, bregs + BMAC_RXCFG,
2365 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2366 } else {
2367 u16 hash_table[4];
2368
2369 memset(hash_table, 0, sizeof(hash_table));
2370 netdev_for_each_mc_addr(ha, dev) {
2371 crc = ether_crc_le(6, ha->addr);
2372 crc >>= 26;
2373 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2374 }
2375 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2376 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2377 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2378 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2379 }
2380
2381 spin_unlock_irq(&hp->happy_lock);
2382}
2383
2384
2385static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2386{
2387 struct happy_meal *hp = netdev_priv(dev);
2388 u32 speed;
2389
2390 cmd->supported =
2391 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2392 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2393 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2394
2395
2396 cmd->port = PORT_TP;
2397 cmd->transceiver = XCVR_INTERNAL;
2398 cmd->phy_address = 0;
2399
2400
2401 spin_lock_irq(&hp->happy_lock);
2402 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2403 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2404 spin_unlock_irq(&hp->happy_lock);
2405
2406 if (hp->sw_bmcr & BMCR_ANENABLE) {
2407 cmd->autoneg = AUTONEG_ENABLE;
2408 speed = ((hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2409 SPEED_100 : SPEED_10);
2410 if (speed == SPEED_100)
2411 cmd->duplex =
2412 (hp->sw_lpa & (LPA_100FULL)) ?
2413 DUPLEX_FULL : DUPLEX_HALF;
2414 else
2415 cmd->duplex =
2416 (hp->sw_lpa & (LPA_10FULL)) ?
2417 DUPLEX_FULL : DUPLEX_HALF;
2418 } else {
2419 cmd->autoneg = AUTONEG_DISABLE;
2420 speed = (hp->sw_bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
2421 cmd->duplex =
2422 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2423 DUPLEX_FULL : DUPLEX_HALF;
2424 }
2425 ethtool_cmd_speed_set(cmd, speed);
2426 return 0;
2427}
2428
2429static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2430{
2431 struct happy_meal *hp = netdev_priv(dev);
2432
2433
2434 if (cmd->autoneg != AUTONEG_ENABLE &&
2435 cmd->autoneg != AUTONEG_DISABLE)
2436 return -EINVAL;
2437 if (cmd->autoneg == AUTONEG_DISABLE &&
2438 ((ethtool_cmd_speed(cmd) != SPEED_100 &&
2439 ethtool_cmd_speed(cmd) != SPEED_10) ||
2440 (cmd->duplex != DUPLEX_HALF &&
2441 cmd->duplex != DUPLEX_FULL)))
2442 return -EINVAL;
2443
2444
2445 spin_lock_irq(&hp->happy_lock);
2446 del_timer(&hp->happy_timer);
2447 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2448 spin_unlock_irq(&hp->happy_lock);
2449
2450 return 0;
2451}
2452
2453static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2454{
2455 struct happy_meal *hp = netdev_priv(dev);
2456
2457 strlcpy(info->driver, "sunhme", sizeof(info->driver));
2458 strlcpy(info->version, "2.02", sizeof(info->version));
2459 if (hp->happy_flags & HFLAG_PCI) {
2460 struct pci_dev *pdev = hp->happy_dev;
2461 strlcpy(info->bus_info, pci_name(pdev), sizeof(info->bus_info));
2462 }
2463#ifdef CONFIG_SBUS
2464 else {
2465 const struct linux_prom_registers *regs;
2466 struct platform_device *op = hp->happy_dev;
2467 regs = of_get_property(op->dev.of_node, "regs", NULL);
2468 if (regs)
2469 snprintf(info->bus_info, sizeof(info->bus_info),
2470 "SBUS:%d",
2471 regs->which_io);
2472 }
2473#endif
2474}
2475
2476static u32 hme_get_link(struct net_device *dev)
2477{
2478 struct happy_meal *hp = netdev_priv(dev);
2479
2480 spin_lock_irq(&hp->happy_lock);
2481 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2482 spin_unlock_irq(&hp->happy_lock);
2483
2484 return hp->sw_bmsr & BMSR_LSTATUS;
2485}
2486
2487static const struct ethtool_ops hme_ethtool_ops = {
2488 .get_settings = hme_get_settings,
2489 .set_settings = hme_set_settings,
2490 .get_drvinfo = hme_get_drvinfo,
2491 .get_link = hme_get_link,
2492};
2493
2494static int hme_version_printed;
2495
2496#ifdef CONFIG_SBUS
2497
2498
2499
2500
2501
2502static struct quattro *quattro_sbus_find(struct platform_device *child)
2503{
2504 struct device *parent = child->dev.parent;
2505 struct platform_device *op;
2506 struct quattro *qp;
2507
2508 op = to_platform_device(parent);
2509 qp = platform_get_drvdata(op);
2510 if (qp)
2511 return qp;
2512
2513 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2514 if (qp != NULL) {
2515 int i;
2516
2517 for (i = 0; i < 4; i++)
2518 qp->happy_meals[i] = NULL;
2519
2520 qp->quattro_dev = child;
2521 qp->next = qfe_sbus_list;
2522 qfe_sbus_list = qp;
2523
2524 platform_set_drvdata(op, qp);
2525 }
2526 return qp;
2527}
2528
2529
2530
2531
2532
2533static int __init quattro_sbus_register_irqs(void)
2534{
2535 struct quattro *qp;
2536
2537 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2538 struct platform_device *op = qp->quattro_dev;
2539 int err, qfe_slot, skip = 0;
2540
2541 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2542 if (!qp->happy_meals[qfe_slot])
2543 skip = 1;
2544 }
2545 if (skip)
2546 continue;
2547
2548 err = request_irq(op->archdata.irqs[0],
2549 quattro_sbus_interrupt,
2550 IRQF_SHARED, "Quattro",
2551 qp);
2552 if (err != 0) {
2553 printk(KERN_ERR "Quattro HME: IRQ registration "
2554 "error %d.\n", err);
2555 return err;
2556 }
2557 }
2558
2559 return 0;
2560}
2561
2562static void quattro_sbus_free_irqs(void)
2563{
2564 struct quattro *qp;
2565
2566 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2567 struct platform_device *op = qp->quattro_dev;
2568 int qfe_slot, skip = 0;
2569
2570 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2571 if (!qp->happy_meals[qfe_slot])
2572 skip = 1;
2573 }
2574 if (skip)
2575 continue;
2576
2577 free_irq(op->archdata.irqs[0], qp);
2578 }
2579}
2580#endif
2581
2582#ifdef CONFIG_PCI
2583static struct quattro *quattro_pci_find(struct pci_dev *pdev)
2584{
2585 struct pci_dev *bdev = pdev->bus->self;
2586 struct quattro *qp;
2587
2588 if (!bdev) return NULL;
2589 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2590 struct pci_dev *qpdev = qp->quattro_dev;
2591
2592 if (qpdev == bdev)
2593 return qp;
2594 }
2595 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2596 if (qp != NULL) {
2597 int i;
2598
2599 for (i = 0; i < 4; i++)
2600 qp->happy_meals[i] = NULL;
2601
2602 qp->quattro_dev = bdev;
2603 qp->next = qfe_pci_list;
2604 qfe_pci_list = qp;
2605
2606
2607 qp->nranges = 0;
2608 }
2609 return qp;
2610}
2611#endif
2612
2613static const struct net_device_ops hme_netdev_ops = {
2614 .ndo_open = happy_meal_open,
2615 .ndo_stop = happy_meal_close,
2616 .ndo_start_xmit = happy_meal_start_xmit,
2617 .ndo_tx_timeout = happy_meal_tx_timeout,
2618 .ndo_get_stats = happy_meal_get_stats,
2619 .ndo_set_rx_mode = happy_meal_set_multicast,
2620 .ndo_change_mtu = eth_change_mtu,
2621 .ndo_set_mac_address = eth_mac_addr,
2622 .ndo_validate_addr = eth_validate_addr,
2623};
2624
2625#ifdef CONFIG_SBUS
2626static int happy_meal_sbus_probe_one(struct platform_device *op, int is_qfe)
2627{
2628 struct device_node *dp = op->dev.of_node, *sbus_dp;
2629 struct quattro *qp = NULL;
2630 struct happy_meal *hp;
2631 struct net_device *dev;
2632 int i, qfe_slot = -1;
2633 int err = -ENODEV;
2634
2635 sbus_dp = op->dev.parent->of_node;
2636
2637
2638 if (strcmp(sbus_dp->name, "sbus") && strcmp(sbus_dp->name, "sbi"))
2639 return err;
2640
2641 if (is_qfe) {
2642 qp = quattro_sbus_find(op);
2643 if (qp == NULL)
2644 goto err_out;
2645 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2646 if (qp->happy_meals[qfe_slot] == NULL)
2647 break;
2648 if (qfe_slot == 4)
2649 goto err_out;
2650 }
2651
2652 err = -ENOMEM;
2653 dev = alloc_etherdev(sizeof(struct happy_meal));
2654 if (!dev)
2655 goto err_out;
2656 SET_NETDEV_DEV(dev, &op->dev);
2657
2658 if (hme_version_printed++ == 0)
2659 printk(KERN_INFO "%s", version);
2660
2661
2662
2663
2664 for (i = 0; i < 6; i++) {
2665 if (macaddr[i] != 0)
2666 break;
2667 }
2668 if (i < 6) {
2669 for (i = 0; i < 6; i++)
2670 dev->dev_addr[i] = macaddr[i];
2671 macaddr[5]++;
2672 } else {
2673 const unsigned char *addr;
2674 int len;
2675
2676 addr = of_get_property(dp, "local-mac-address", &len);
2677
2678 if (qfe_slot != -1 && addr && len == 6)
2679 memcpy(dev->dev_addr, addr, 6);
2680 else
2681 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2682 }
2683
2684 hp = netdev_priv(dev);
2685
2686 hp->happy_dev = op;
2687 hp->dma_dev = &op->dev;
2688
2689 spin_lock_init(&hp->happy_lock);
2690
2691 err = -ENODEV;
2692 if (qp != NULL) {
2693 hp->qfe_parent = qp;
2694 hp->qfe_ent = qfe_slot;
2695 qp->happy_meals[qfe_slot] = dev;
2696 }
2697
2698 hp->gregs = of_ioremap(&op->resource[0], 0,
2699 GREG_REG_SIZE, "HME Global Regs");
2700 if (!hp->gregs) {
2701 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2702 goto err_out_free_netdev;
2703 }
2704
2705 hp->etxregs = of_ioremap(&op->resource[1], 0,
2706 ETX_REG_SIZE, "HME TX Regs");
2707 if (!hp->etxregs) {
2708 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2709 goto err_out_iounmap;
2710 }
2711
2712 hp->erxregs = of_ioremap(&op->resource[2], 0,
2713 ERX_REG_SIZE, "HME RX Regs");
2714 if (!hp->erxregs) {
2715 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2716 goto err_out_iounmap;
2717 }
2718
2719 hp->bigmacregs = of_ioremap(&op->resource[3], 0,
2720 BMAC_REG_SIZE, "HME BIGMAC Regs");
2721 if (!hp->bigmacregs) {
2722 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2723 goto err_out_iounmap;
2724 }
2725
2726 hp->tcvregs = of_ioremap(&op->resource[4], 0,
2727 TCVR_REG_SIZE, "HME Tranceiver Regs");
2728 if (!hp->tcvregs) {
2729 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2730 goto err_out_iounmap;
2731 }
2732
2733 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2734 if (hp->hm_revision == 0xff)
2735 hp->hm_revision = 0xa0;
2736
2737
2738 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2739 hp->happy_flags = HFLAG_20_21;
2740 else if (hp->hm_revision != 0xa0)
2741 hp->happy_flags = HFLAG_NOT_A0;
2742
2743 if (qp != NULL)
2744 hp->happy_flags |= HFLAG_QUATTRO;
2745
2746
2747 hp->happy_bursts = of_getintprop_default(sbus_dp,
2748 "burst-sizes", 0x00);
2749
2750 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2751 PAGE_SIZE,
2752 &hp->hblock_dvma,
2753 GFP_ATOMIC);
2754 err = -ENOMEM;
2755 if (!hp->happy_block)
2756 goto err_out_iounmap;
2757
2758
2759 hp->linkcheck = 0;
2760
2761
2762 hp->timer_state = asleep;
2763 hp->timer_ticks = 0;
2764
2765 init_timer(&hp->happy_timer);
2766
2767 hp->dev = dev;
2768 dev->netdev_ops = &hme_netdev_ops;
2769 dev->watchdog_timeo = 5*HZ;
2770 dev->ethtool_ops = &hme_ethtool_ops;
2771
2772
2773 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2774 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2775
2776 hp->irq = op->archdata.irqs[0];
2777
2778#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2779
2780 hp->read_desc32 = sbus_hme_read_desc32;
2781 hp->write_txd = sbus_hme_write_txd;
2782 hp->write_rxd = sbus_hme_write_rxd;
2783 hp->read32 = sbus_hme_read32;
2784 hp->write32 = sbus_hme_write32;
2785#endif
2786
2787
2788
2789
2790 spin_lock_irq(&hp->happy_lock);
2791 happy_meal_set_initial_advertisement(hp);
2792 spin_unlock_irq(&hp->happy_lock);
2793
2794 err = register_netdev(hp->dev);
2795 if (err) {
2796 printk(KERN_ERR "happymeal: Cannot register net device, "
2797 "aborting.\n");
2798 goto err_out_free_coherent;
2799 }
2800
2801 dev_set_drvdata(&op->dev, hp);
2802
2803 if (qfe_slot != -1)
2804 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2805 dev->name, qfe_slot);
2806 else
2807 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2808 dev->name);
2809
2810 printk("%pM\n", dev->dev_addr);
2811
2812 return 0;
2813
2814err_out_free_coherent:
2815 dma_free_coherent(hp->dma_dev,
2816 PAGE_SIZE,
2817 hp->happy_block,
2818 hp->hblock_dvma);
2819
2820err_out_iounmap:
2821 if (hp->gregs)
2822 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
2823 if (hp->etxregs)
2824 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
2825 if (hp->erxregs)
2826 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
2827 if (hp->bigmacregs)
2828 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
2829 if (hp->tcvregs)
2830 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
2831
2832 if (qp)
2833 qp->happy_meals[qfe_slot] = NULL;
2834
2835err_out_free_netdev:
2836 free_netdev(dev);
2837
2838err_out:
2839 return err;
2840}
2841#endif
2842
2843#ifdef CONFIG_PCI
2844#ifndef CONFIG_SPARC
2845static int is_quattro_p(struct pci_dev *pdev)
2846{
2847 struct pci_dev *busdev = pdev->bus->self;
2848 struct pci_dev *this_pdev;
2849 int n_hmes;
2850
2851 if (busdev == NULL ||
2852 busdev->vendor != PCI_VENDOR_ID_DEC ||
2853 busdev->device != PCI_DEVICE_ID_DEC_21153)
2854 return 0;
2855
2856 n_hmes = 0;
2857 list_for_each_entry(this_pdev, &pdev->bus->devices, bus_list) {
2858 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2859 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2860 n_hmes++;
2861 }
2862
2863 if (n_hmes != 4)
2864 return 0;
2865
2866 return 1;
2867}
2868
2869
2870static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2871{
2872 int this_offset;
2873
2874 for (this_offset = 0x20; this_offset < len; this_offset++) {
2875 void __iomem *p = rom_base + this_offset;
2876
2877 if (readb(p + 0) != 0x90 ||
2878 readb(p + 1) != 0x00 ||
2879 readb(p + 2) != 0x09 ||
2880 readb(p + 3) != 0x4e ||
2881 readb(p + 4) != 0x41 ||
2882 readb(p + 5) != 0x06)
2883 continue;
2884
2885 this_offset += 6;
2886 p += 6;
2887
2888 if (index == 0) {
2889 int i;
2890
2891 for (i = 0; i < 6; i++)
2892 dev_addr[i] = readb(p + i);
2893 return 1;
2894 }
2895 index--;
2896 }
2897 return 0;
2898}
2899
2900static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2901{
2902 size_t size;
2903 void __iomem *p = pci_map_rom(pdev, &size);
2904
2905 if (p) {
2906 int index = 0;
2907 int found;
2908
2909 if (is_quattro_p(pdev))
2910 index = PCI_SLOT(pdev->devfn);
2911
2912 found = readb(p) == 0x55 &&
2913 readb(p + 1) == 0xaa &&
2914 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2915 pci_unmap_rom(pdev, p);
2916 if (found)
2917 return;
2918 }
2919
2920
2921 dev_addr[0] = 0x08;
2922 dev_addr[1] = 0x00;
2923 dev_addr[2] = 0x20;
2924 get_random_bytes(&dev_addr[3], 3);
2925}
2926#endif
2927
2928static int happy_meal_pci_probe(struct pci_dev *pdev,
2929 const struct pci_device_id *ent)
2930{
2931 struct quattro *qp = NULL;
2932#ifdef CONFIG_SPARC
2933 struct device_node *dp;
2934#endif
2935 struct happy_meal *hp;
2936 struct net_device *dev;
2937 void __iomem *hpreg_base;
2938 unsigned long hpreg_res;
2939 int i, qfe_slot = -1;
2940 char prom_name[64];
2941 int err;
2942
2943
2944#ifdef CONFIG_SPARC
2945 dp = pci_device_to_OF_node(pdev);
2946 strcpy(prom_name, dp->name);
2947#else
2948 if (is_quattro_p(pdev))
2949 strcpy(prom_name, "SUNW,qfe");
2950 else
2951 strcpy(prom_name, "SUNW,hme");
2952#endif
2953
2954 err = -ENODEV;
2955
2956 if (pci_enable_device(pdev))
2957 goto err_out;
2958 pci_set_master(pdev);
2959
2960 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2961 qp = quattro_pci_find(pdev);
2962 if (qp == NULL)
2963 goto err_out;
2964 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2965 if (qp->happy_meals[qfe_slot] == NULL)
2966 break;
2967 if (qfe_slot == 4)
2968 goto err_out;
2969 }
2970
2971 dev = alloc_etherdev(sizeof(struct happy_meal));
2972 err = -ENOMEM;
2973 if (!dev)
2974 goto err_out;
2975 SET_NETDEV_DEV(dev, &pdev->dev);
2976
2977 if (hme_version_printed++ == 0)
2978 printk(KERN_INFO "%s", version);
2979
2980 hp = netdev_priv(dev);
2981
2982 hp->happy_dev = pdev;
2983 hp->dma_dev = &pdev->dev;
2984
2985 spin_lock_init(&hp->happy_lock);
2986
2987 if (qp != NULL) {
2988 hp->qfe_parent = qp;
2989 hp->qfe_ent = qfe_slot;
2990 qp->happy_meals[qfe_slot] = dev;
2991 }
2992
2993 hpreg_res = pci_resource_start(pdev, 0);
2994 err = -ENODEV;
2995 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2996 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2997 goto err_out_clear_quattro;
2998 }
2999 if (pci_request_regions(pdev, DRV_NAME)) {
3000 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3001 "aborting.\n");
3002 goto err_out_clear_quattro;
3003 }
3004
3005 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
3006 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3007 goto err_out_free_res;
3008 }
3009
3010 for (i = 0; i < 6; i++) {
3011 if (macaddr[i] != 0)
3012 break;
3013 }
3014 if (i < 6) {
3015 for (i = 0; i < 6; i++)
3016 dev->dev_addr[i] = macaddr[i];
3017 macaddr[5]++;
3018 } else {
3019#ifdef CONFIG_SPARC
3020 const unsigned char *addr;
3021 int len;
3022
3023 if (qfe_slot != -1 &&
3024 (addr = of_get_property(dp, "local-mac-address", &len))
3025 != NULL &&
3026 len == 6) {
3027 memcpy(dev->dev_addr, addr, 6);
3028 } else {
3029 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3030 }
3031#else
3032 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3033#endif
3034 }
3035
3036
3037 hp->gregs = (hpreg_base + 0x0000UL);
3038 hp->etxregs = (hpreg_base + 0x2000UL);
3039 hp->erxregs = (hpreg_base + 0x4000UL);
3040 hp->bigmacregs = (hpreg_base + 0x6000UL);
3041 hp->tcvregs = (hpreg_base + 0x7000UL);
3042
3043#ifdef CONFIG_SPARC
3044 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3045 if (hp->hm_revision == 0xff)
3046 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3047#else
3048
3049 hp->hm_revision = 0x20;
3050#endif
3051
3052
3053 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3054 hp->happy_flags = HFLAG_20_21;
3055 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3056 hp->happy_flags = HFLAG_NOT_A0;
3057
3058 if (qp != NULL)
3059 hp->happy_flags |= HFLAG_QUATTRO;
3060
3061
3062 hp->happy_flags |= HFLAG_PCI;
3063
3064#ifdef CONFIG_SPARC
3065
3066 hp->happy_bursts = DMA_BURSTBITS;
3067#endif
3068
3069 hp->happy_block = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3070 &hp->hblock_dvma, GFP_KERNEL);
3071 err = -ENODEV;
3072 if (!hp->happy_block)
3073 goto err_out_iounmap;
3074
3075 hp->linkcheck = 0;
3076 hp->timer_state = asleep;
3077 hp->timer_ticks = 0;
3078
3079 init_timer(&hp->happy_timer);
3080
3081 hp->irq = pdev->irq;
3082 hp->dev = dev;
3083 dev->netdev_ops = &hme_netdev_ops;
3084 dev->watchdog_timeo = 5*HZ;
3085 dev->ethtool_ops = &hme_ethtool_ops;
3086
3087
3088 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
3089 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
3090
3091#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3092
3093 hp->read_desc32 = pci_hme_read_desc32;
3094 hp->write_txd = pci_hme_write_txd;
3095 hp->write_rxd = pci_hme_write_rxd;
3096 hp->read32 = pci_hme_read32;
3097 hp->write32 = pci_hme_write32;
3098#endif
3099
3100
3101
3102
3103 spin_lock_irq(&hp->happy_lock);
3104 happy_meal_set_initial_advertisement(hp);
3105 spin_unlock_irq(&hp->happy_lock);
3106
3107 err = register_netdev(hp->dev);
3108 if (err) {
3109 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3110 "aborting.\n");
3111 goto err_out_iounmap;
3112 }
3113
3114 dev_set_drvdata(&pdev->dev, hp);
3115
3116 if (!qfe_slot) {
3117 struct pci_dev *qpdev = qp->quattro_dev;
3118
3119 prom_name[0] = 0;
3120 if (!strncmp(dev->name, "eth", 3)) {
3121 int i = simple_strtoul(dev->name + 3, NULL, 10);
3122 sprintf(prom_name, "-%d", i + 3);
3123 }
3124 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3125 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3126 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3127 printk("DEC 21153 PCI Bridge\n");
3128 else
3129 printk("unknown bridge %04x.%04x\n",
3130 qpdev->vendor, qpdev->device);
3131 }
3132
3133 if (qfe_slot != -1)
3134 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3135 dev->name, qfe_slot);
3136 else
3137 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3138 dev->name);
3139
3140 printk("%pM\n", dev->dev_addr);
3141
3142 return 0;
3143
3144err_out_iounmap:
3145 iounmap(hp->gregs);
3146
3147err_out_free_res:
3148 pci_release_regions(pdev);
3149
3150err_out_clear_quattro:
3151 if (qp != NULL)
3152 qp->happy_meals[qfe_slot] = NULL;
3153
3154 free_netdev(dev);
3155
3156err_out:
3157 return err;
3158}
3159
3160static void happy_meal_pci_remove(struct pci_dev *pdev)
3161{
3162 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3163 struct net_device *net_dev = hp->dev;
3164
3165 unregister_netdev(net_dev);
3166
3167 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3168 hp->happy_block, hp->hblock_dvma);
3169 iounmap(hp->gregs);
3170 pci_release_regions(hp->happy_dev);
3171
3172 free_netdev(net_dev);
3173
3174 dev_set_drvdata(&pdev->dev, NULL);
3175}
3176
3177static DEFINE_PCI_DEVICE_TABLE(happymeal_pci_ids) = {
3178 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3179 { }
3180};
3181
3182MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3183
3184static struct pci_driver hme_pci_driver = {
3185 .name = "hme",
3186 .id_table = happymeal_pci_ids,
3187 .probe = happy_meal_pci_probe,
3188 .remove = happy_meal_pci_remove,
3189};
3190
3191static int __init happy_meal_pci_init(void)
3192{
3193 return pci_register_driver(&hme_pci_driver);
3194}
3195
3196static void happy_meal_pci_exit(void)
3197{
3198 pci_unregister_driver(&hme_pci_driver);
3199
3200 while (qfe_pci_list) {
3201 struct quattro *qfe = qfe_pci_list;
3202 struct quattro *next = qfe->next;
3203
3204 kfree(qfe);
3205
3206 qfe_pci_list = next;
3207 }
3208}
3209
3210#endif
3211
3212#ifdef CONFIG_SBUS
3213static const struct of_device_id hme_sbus_match[];
3214static int hme_sbus_probe(struct platform_device *op)
3215{
3216 const struct of_device_id *match;
3217 struct device_node *dp = op->dev.of_node;
3218 const char *model = of_get_property(dp, "model", NULL);
3219 int is_qfe;
3220
3221 match = of_match_device(hme_sbus_match, &op->dev);
3222 if (!match)
3223 return -EINVAL;
3224 is_qfe = (match->data != NULL);
3225
3226 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3227 is_qfe = 1;
3228
3229 return happy_meal_sbus_probe_one(op, is_qfe);
3230}
3231
3232static int hme_sbus_remove(struct platform_device *op)
3233{
3234 struct happy_meal *hp = dev_get_drvdata(&op->dev);
3235 struct net_device *net_dev = hp->dev;
3236
3237 unregister_netdev(net_dev);
3238
3239
3240
3241 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
3242 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
3243 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
3244 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
3245 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
3246 dma_free_coherent(hp->dma_dev,
3247 PAGE_SIZE,
3248 hp->happy_block,
3249 hp->hblock_dvma);
3250
3251 free_netdev(net_dev);
3252
3253 dev_set_drvdata(&op->dev, NULL);
3254
3255 return 0;
3256}
3257
3258static const struct of_device_id hme_sbus_match[] = {
3259 {
3260 .name = "SUNW,hme",
3261 },
3262 {
3263 .name = "SUNW,qfe",
3264 .data = (void *) 1,
3265 },
3266 {
3267 .name = "qfe",
3268 .data = (void *) 1,
3269 },
3270 {},
3271};
3272
3273MODULE_DEVICE_TABLE(of, hme_sbus_match);
3274
3275static struct platform_driver hme_sbus_driver = {
3276 .driver = {
3277 .name = "hme",
3278 .owner = THIS_MODULE,
3279 .of_match_table = hme_sbus_match,
3280 },
3281 .probe = hme_sbus_probe,
3282 .remove = hme_sbus_remove,
3283};
3284
3285static int __init happy_meal_sbus_init(void)
3286{
3287 int err;
3288
3289 err = platform_driver_register(&hme_sbus_driver);
3290 if (!err)
3291 err = quattro_sbus_register_irqs();
3292
3293 return err;
3294}
3295
3296static void happy_meal_sbus_exit(void)
3297{
3298 platform_driver_unregister(&hme_sbus_driver);
3299 quattro_sbus_free_irqs();
3300
3301 while (qfe_sbus_list) {
3302 struct quattro *qfe = qfe_sbus_list;
3303 struct quattro *next = qfe->next;
3304
3305 kfree(qfe);
3306
3307 qfe_sbus_list = next;
3308 }
3309}
3310#endif
3311
3312static int __init happy_meal_probe(void)
3313{
3314 int err = 0;
3315
3316#ifdef CONFIG_SBUS
3317 err = happy_meal_sbus_init();
3318#endif
3319#ifdef CONFIG_PCI
3320 if (!err) {
3321 err = happy_meal_pci_init();
3322#ifdef CONFIG_SBUS
3323 if (err)
3324 happy_meal_sbus_exit();
3325#endif
3326 }
3327#endif
3328
3329 return err;
3330}
3331
3332
3333static void __exit happy_meal_exit(void)
3334{
3335#ifdef CONFIG_SBUS
3336 happy_meal_sbus_exit();
3337#endif
3338#ifdef CONFIG_PCI
3339 happy_meal_pci_exit();
3340#endif
3341}
3342
3343module_init(happy_meal_probe);
3344module_exit(happy_meal_exit);
3345