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32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/sched.h>
35#include <linux/string.h>
36#include <linux/timer.h>
37#include <linux/errno.h>
38#include <linux/in.h>
39#include <linux/ioport.h>
40#include <linux/slab.h>
41#include <linux/mm.h>
42#include <linux/interrupt.h>
43#include <linux/init.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <linux/skbuff.h>
47#include <linux/ethtool.h>
48#include <linux/highmem.h>
49#include <linux/proc_fs.h>
50#include <linux/ctype.h>
51#include <linux/spinlock.h>
52#include <linux/dma-mapping.h>
53#include <linux/clk.h>
54#include <linux/platform_device.h>
55#include <linux/semaphore.h>
56#include <linux/phy.h>
57#include <linux/bitops.h>
58#include <linux/io.h>
59#include <linux/uaccess.h>
60#include <linux/pm_runtime.h>
61#include <linux/davinci_emac.h>
62#include <linux/of.h>
63#include <linux/of_address.h>
64#include <linux/of_irq.h>
65#include <linux/of_net.h>
66
67#include <asm/irq.h>
68#include <asm/page.h>
69
70#include "davinci_cpdma.h"
71
72static int debug_level;
73module_param(debug_level, int, 0);
74MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
75
76
77#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR | \
85 NETIF_MSG_TX_QUEUED | \
86 NETIF_MSG_INTR | \
87 NETIF_MSG_TX_DONE | \
88 NETIF_MSG_RX_STATUS | \
89 NETIF_MSG_PKTDATA | \
90 NETIF_MSG_HW | \
91 NETIF_MSG_WOL)
92
93
94#define EMAC_MAJOR_VERSION 6
95#define EMAC_MINOR_VERSION 1
96#define EMAC_MODULE_VERSION "6.1"
97MODULE_VERSION(EMAC_MODULE_VERSION);
98static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
99
100
101#define EMAC_DEF_PASS_CRC (0)
102#define EMAC_DEF_QOS_EN (0)
103#define EMAC_DEF_NO_BUFF_CHAIN (0)
104#define EMAC_DEF_MACCTRL_FRAME_EN (0)
105#define EMAC_DEF_SHORT_FRAME_EN (0)
106#define EMAC_DEF_ERROR_FRAME_EN (0)
107#define EMAC_DEF_PROM_EN (0)
108#define EMAC_DEF_PROM_CH (0)
109#define EMAC_DEF_BCAST_EN (1)
110#define EMAC_DEF_BCAST_CH (0)
111#define EMAC_DEF_MCAST_EN (1)
112#define EMAC_DEF_MCAST_CH (0)
113
114#define EMAC_DEF_TXPRIO_FIXED (1)
115#define EMAC_DEF_TXPACING_EN (0)
116
117#define EMAC_DEF_BUFFER_OFFSET (0)
118#define EMAC_DEF_MIN_ETHPKTSIZE (60)
119#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
120#define EMAC_DEF_TX_CH (0)
121#define EMAC_DEF_RX_CH (0)
122#define EMAC_DEF_RX_NUM_DESC (128)
123#define EMAC_DEF_MAX_TX_CH (1)
124#define EMAC_DEF_MAX_RX_CH (1)
125#define EMAC_POLL_WEIGHT (64)
126
127
128#define EMAC_DEF_TX_MAX_SERVICE (32)
129#define EMAC_DEF_RX_MAX_SERVICE (64)
130
131
132#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
133#define EMAC_NUM_MULTICAST_BITS (64)
134#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
135#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
136#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
137#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
138#define EMAC_INT_MASK_CLEAR (0xFF)
139
140
141#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
142#define EMAC_RXMBP_QOSEN_MASK BIT(29)
143#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
144#define EMAC_RXMBP_CMFEN_MASK BIT(24)
145#define EMAC_RXMBP_CSFEN_MASK BIT(23)
146#define EMAC_RXMBP_CEFEN_MASK BIT(22)
147#define EMAC_RXMBP_CAFEN_MASK BIT(21)
148#define EMAC_RXMBP_PROMCH_SHIFT (16)
149#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
150#define EMAC_RXMBP_BROADEN_MASK BIT(13)
151#define EMAC_RXMBP_BROADCH_SHIFT (8)
152#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
153#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
154#define EMAC_RXMBP_MULTICH_SHIFT (0)
155#define EMAC_RXMBP_MULTICH_MASK (0x7)
156#define EMAC_RXMBP_CHMASK (0x7)
157
158
159# define EMAC_MBP_RXPROMISC (0x00200000)
160# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
161# define EMAC_MBP_RXBCAST (0x00002000)
162# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
163# define EMAC_MBP_RXMCAST (0x00000020)
164# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
165
166
167#define EMAC_MACCONTROL_TXPTYPE BIT(9)
168#define EMAC_MACCONTROL_TXPACEEN BIT(6)
169#define EMAC_MACCONTROL_GMIIEN BIT(5)
170#define EMAC_MACCONTROL_GIGABITEN BIT(7)
171#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
172#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
173
174
175#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
176#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
177
178
179#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
180#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
181#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
182#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
183#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
184#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
185#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
186#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
187
188
189#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
190#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
191
192
193#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
194#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
195#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
196#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
197
198
199#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
200#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
201#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
202#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
203
204
205#define EMAC_CPPI_SOP_BIT BIT(31)
206#define EMAC_CPPI_EOP_BIT BIT(30)
207#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
208#define EMAC_CPPI_EOQ_BIT BIT(28)
209#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
210#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
211#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
212#define EMAC_BD_LENGTH_FOR_CACHE (16)
213#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
214
215
216#define EMAC_MAX_TXRX_CHANNELS (8)
217#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64)
218
219
220#define EMAC_MACINVECTOR 0x90
221
222#define EMAC_DM646X_MACEOIVECTOR 0x94
223
224#define EMAC_MACINTSTATRAW 0xB0
225#define EMAC_MACINTSTATMASKED 0xB4
226#define EMAC_MACINTMASKSET 0xB8
227#define EMAC_MACINTMASKCLEAR 0xBC
228
229#define EMAC_RXMBPENABLE 0x100
230#define EMAC_RXUNICASTSET 0x104
231#define EMAC_RXUNICASTCLEAR 0x108
232#define EMAC_RXMAXLEN 0x10C
233#define EMAC_RXBUFFEROFFSET 0x110
234#define EMAC_RXFILTERLOWTHRESH 0x114
235
236#define EMAC_MACCONTROL 0x160
237#define EMAC_MACSTATUS 0x164
238#define EMAC_EMCONTROL 0x168
239#define EMAC_FIFOCONTROL 0x16C
240#define EMAC_MACCONFIG 0x170
241#define EMAC_SOFTRESET 0x174
242#define EMAC_MACSRCADDRLO 0x1D0
243#define EMAC_MACSRCADDRHI 0x1D4
244#define EMAC_MACHASH1 0x1D8
245#define EMAC_MACHASH2 0x1DC
246#define EMAC_MACADDRLO 0x500
247#define EMAC_MACADDRHI 0x504
248#define EMAC_MACINDEX 0x508
249
250
251#define EMAC_RXGOODFRAMES 0x200
252#define EMAC_RXBCASTFRAMES 0x204
253#define EMAC_RXMCASTFRAMES 0x208
254#define EMAC_RXPAUSEFRAMES 0x20C
255#define EMAC_RXCRCERRORS 0x210
256#define EMAC_RXALIGNCODEERRORS 0x214
257#define EMAC_RXOVERSIZED 0x218
258#define EMAC_RXJABBER 0x21C
259#define EMAC_RXUNDERSIZED 0x220
260#define EMAC_RXFRAGMENTS 0x224
261#define EMAC_RXFILTERED 0x228
262#define EMAC_RXQOSFILTERED 0x22C
263#define EMAC_RXOCTETS 0x230
264#define EMAC_TXGOODFRAMES 0x234
265#define EMAC_TXBCASTFRAMES 0x238
266#define EMAC_TXMCASTFRAMES 0x23C
267#define EMAC_TXPAUSEFRAMES 0x240
268#define EMAC_TXDEFERRED 0x244
269#define EMAC_TXCOLLISION 0x248
270#define EMAC_TXSINGLECOLL 0x24C
271#define EMAC_TXMULTICOLL 0x250
272#define EMAC_TXEXCESSIVECOLL 0x254
273#define EMAC_TXLATECOLL 0x258
274#define EMAC_TXUNDERRUN 0x25C
275#define EMAC_TXCARRIERSENSE 0x260
276#define EMAC_TXOCTETS 0x264
277#define EMAC_NETOCTETS 0x280
278#define EMAC_RXSOFOVERRUNS 0x284
279#define EMAC_RXMOFOVERRUNS 0x288
280#define EMAC_RXDMAOVERRUNS 0x28C
281
282
283#define EMAC_CTRL_EWCTL (0x4)
284#define EMAC_CTRL_EWINTTCNT (0x8)
285
286
287#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
288#define EMAC_DM644X_INTMIN_INTVL 0x1
289#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
290
291
292#define EMAC_DM646X_CMINTCTRL 0x0C
293#define EMAC_DM646X_CMRXINTEN 0x14
294#define EMAC_DM646X_CMTXINTEN 0x18
295#define EMAC_DM646X_CMRXINTMAX 0x70
296#define EMAC_DM646X_CMTXINTMAX 0x74
297
298
299#define EMAC_DM646X_INTPACEEN (0x3 << 16)
300#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
301#define EMAC_DM646X_CMINTMAX_CNT 63
302#define EMAC_DM646X_CMINTMIN_CNT 2
303#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
304#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
305
306
307
308#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
309#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
310
311
312#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
313
314
315
316
317
318struct emac_priv {
319 u32 msg_enable;
320 struct net_device *ndev;
321 struct platform_device *pdev;
322 struct napi_struct napi;
323 char mac_addr[6];
324 void __iomem *remap_addr;
325 u32 emac_base_phys;
326 void __iomem *emac_base;
327 void __iomem *ctrl_base;
328 struct cpdma_ctlr *dma;
329 struct cpdma_chan *txchan;
330 struct cpdma_chan *rxchan;
331 u32 link;
332 u32 speed;
333 u32 duplex;
334 u32 rx_buf_size;
335 u32 isr_count;
336 u32 coal_intvl;
337 u32 bus_freq_mhz;
338 u8 rmii_en;
339 u8 version;
340 u32 mac_hash1;
341 u32 mac_hash2;
342 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
343 u32 rx_addr_type;
344 const char *phy_id;
345#ifdef CONFIG_OF
346 struct device_node *phy_node;
347#endif
348 struct phy_device *phydev;
349 spinlock_t lock;
350
351 void (*int_enable) (void);
352 void (*int_disable) (void);
353};
354
355
356static char *emac_txhost_errcodes[16] = {
357 "No error", "SOP error", "Ownership bit not set in SOP buffer",
358 "Zero Next Buffer Descriptor Pointer Without EOP",
359 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
360 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
361 "Reserved", "Reserved", "Reserved", "Reserved"
362};
363
364
365static char *emac_rxhost_errcodes[16] = {
366 "No error", "Reserved", "Ownership bit not set in input buffer",
367 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
368 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
369 "Reserved", "Reserved", "Reserved", "Reserved"
370};
371
372
373#define emac_read(reg) ioread32(priv->emac_base + (reg))
374#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
375
376#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
377#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
378
379
380
381
382
383
384
385
386static void emac_dump_regs(struct emac_priv *priv)
387{
388 struct device *emac_dev = &priv->ndev->dev;
389
390
391 dev_info(emac_dev, "EMAC Basic registers\n");
392 if (priv->version == EMAC_VERSION_1) {
393 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
394 emac_ctrl_read(EMAC_CTRL_EWCTL),
395 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
396 }
397 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
398 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
399 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
400 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
401 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
402 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
403 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
404 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
405 dev_info(emac_dev, "EMAC Statistics\n");
406 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
407 emac_read(EMAC_RXGOODFRAMES));
408 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
409 emac_read(EMAC_RXBCASTFRAMES));
410 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
411 emac_read(EMAC_RXMCASTFRAMES));
412 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
413 emac_read(EMAC_RXPAUSEFRAMES));
414 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
415 emac_read(EMAC_RXCRCERRORS));
416 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
417 emac_read(EMAC_RXALIGNCODEERRORS));
418 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
419 emac_read(EMAC_RXOVERSIZED));
420 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
421 emac_read(EMAC_RXJABBER));
422 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
423 emac_read(EMAC_RXUNDERSIZED));
424 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
425 emac_read(EMAC_RXFRAGMENTS));
426 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
427 emac_read(EMAC_RXFILTERED));
428 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
429 emac_read(EMAC_RXQOSFILTERED));
430 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
431 emac_read(EMAC_RXOCTETS));
432 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
433 emac_read(EMAC_TXGOODFRAMES));
434 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
435 emac_read(EMAC_TXBCASTFRAMES));
436 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
437 emac_read(EMAC_TXMCASTFRAMES));
438 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
439 emac_read(EMAC_TXPAUSEFRAMES));
440 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
441 emac_read(EMAC_TXDEFERRED));
442 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
443 emac_read(EMAC_TXCOLLISION));
444 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
445 emac_read(EMAC_TXSINGLECOLL));
446 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
447 emac_read(EMAC_TXMULTICOLL));
448 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
449 emac_read(EMAC_TXEXCESSIVECOLL));
450 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
451 emac_read(EMAC_TXLATECOLL));
452 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
453 emac_read(EMAC_TXUNDERRUN));
454 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
455 emac_read(EMAC_TXCARRIERSENSE));
456 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
457 emac_read(EMAC_TXOCTETS));
458 dev_info(emac_dev, "EMAC: net_octets:%d\n",
459 emac_read(EMAC_NETOCTETS));
460 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
461 emac_read(EMAC_RXSOFOVERRUNS));
462 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
463 emac_read(EMAC_RXMOFOVERRUNS));
464 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
465 emac_read(EMAC_RXDMAOVERRUNS));
466
467 cpdma_ctlr_dump(priv->dma);
468}
469
470
471
472
473
474
475
476
477
478static void emac_get_drvinfo(struct net_device *ndev,
479 struct ethtool_drvinfo *info)
480{
481 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
482 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
483}
484
485
486
487
488
489
490
491
492
493static int emac_get_settings(struct net_device *ndev,
494 struct ethtool_cmd *ecmd)
495{
496 struct emac_priv *priv = netdev_priv(ndev);
497 if (priv->phydev)
498 return phy_ethtool_gset(priv->phydev, ecmd);
499 else
500 return -EOPNOTSUPP;
501
502}
503
504
505
506
507
508
509
510
511
512static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
513{
514 struct emac_priv *priv = netdev_priv(ndev);
515 if (priv->phydev)
516 return phy_ethtool_sset(priv->phydev, ecmd);
517 else
518 return -EOPNOTSUPP;
519
520}
521
522
523
524
525
526
527
528
529
530static int emac_get_coalesce(struct net_device *ndev,
531 struct ethtool_coalesce *coal)
532{
533 struct emac_priv *priv = netdev_priv(ndev);
534
535 coal->rx_coalesce_usecs = priv->coal_intvl;
536 return 0;
537
538}
539
540
541
542
543
544
545
546
547
548static int emac_set_coalesce(struct net_device *ndev,
549 struct ethtool_coalesce *coal)
550{
551 struct emac_priv *priv = netdev_priv(ndev);
552 u32 int_ctrl, num_interrupts = 0;
553 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
554
555 if (!coal->rx_coalesce_usecs)
556 return -EINVAL;
557
558 coal_intvl = coal->rx_coalesce_usecs;
559
560 switch (priv->version) {
561 case EMAC_VERSION_2:
562 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
563 prescale = priv->bus_freq_mhz * 4;
564
565 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
566 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
567
568 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
569
570
571
572
573 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
574
575 if (addnl_dvdr > 1) {
576 prescale *= addnl_dvdr;
577 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
578 * addnl_dvdr))
579 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
580 * addnl_dvdr);
581 } else {
582 addnl_dvdr = 1;
583 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
584 }
585 }
586
587 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
588
589 int_ctrl |= EMAC_DM646X_INTPACEEN;
590 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
591 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
592 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
593
594 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
595 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
596
597 break;
598 default:
599 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
600 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
601 prescale = coal_intvl * priv->bus_freq_mhz;
602 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
603 prescale = EMAC_DM644X_EWINTCNT_MASK;
604 coal_intvl = prescale / priv->bus_freq_mhz;
605 }
606 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
607
608 break;
609 }
610
611 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
612 priv->coal_intvl = coal_intvl;
613
614 return 0;
615
616}
617
618
619
620
621
622
623static const struct ethtool_ops ethtool_ops = {
624 .get_drvinfo = emac_get_drvinfo,
625 .get_settings = emac_get_settings,
626 .set_settings = emac_set_settings,
627 .get_link = ethtool_op_get_link,
628 .get_coalesce = emac_get_coalesce,
629 .set_coalesce = emac_set_coalesce,
630 .get_ts_info = ethtool_op_get_ts_info,
631};
632
633
634
635
636
637
638
639
640
641static void emac_update_phystatus(struct emac_priv *priv)
642{
643 u32 mac_control;
644 u32 new_duplex;
645 u32 cur_duplex;
646 struct net_device *ndev = priv->ndev;
647
648 mac_control = emac_read(EMAC_MACCONTROL);
649 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
650 DUPLEX_FULL : DUPLEX_HALF;
651 if (priv->phydev)
652 new_duplex = priv->phydev->duplex;
653 else
654 new_duplex = DUPLEX_FULL;
655
656
657 if ((priv->link) && (new_duplex != cur_duplex)) {
658 priv->duplex = new_duplex;
659 if (DUPLEX_FULL == priv->duplex)
660 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
661 else
662 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
663 }
664
665 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
666 mac_control = emac_read(EMAC_MACCONTROL);
667 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
668 EMAC_DM646X_MACCONTORL_GIGFORCE);
669 } else {
670
671 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
672 EMAC_DM646X_MACCONTORL_GIG);
673
674 if (priv->rmii_en && (priv->speed == SPEED_100))
675 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
676 else
677 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
678 }
679
680
681 emac_write(EMAC_MACCONTROL, mac_control);
682
683 if (priv->link) {
684
685 if (!netif_carrier_ok(ndev))
686 netif_carrier_on(ndev);
687
688 if (netif_running(ndev) && netif_queue_stopped(ndev))
689 netif_wake_queue(ndev);
690 } else {
691
692 if (netif_carrier_ok(ndev))
693 netif_carrier_off(ndev);
694 if (!netif_queue_stopped(ndev))
695 netif_stop_queue(ndev);
696 }
697}
698
699
700
701
702
703
704
705
706static u32 hash_get(u8 *addr)
707{
708 u32 hash;
709 u8 tmpval;
710 int cnt;
711 hash = 0;
712
713 for (cnt = 0; cnt < 2; cnt++) {
714 tmpval = *addr++;
715 hash ^= (tmpval >> 2) ^ (tmpval << 4);
716 tmpval = *addr++;
717 hash ^= (tmpval >> 4) ^ (tmpval << 2);
718 tmpval = *addr++;
719 hash ^= (tmpval >> 6) ^ (tmpval);
720 }
721
722 return hash & 0x3F;
723}
724
725
726
727
728
729
730
731
732
733static int hash_add(struct emac_priv *priv, u8 *mac_addr)
734{
735 struct device *emac_dev = &priv->ndev->dev;
736 u32 rc = 0;
737 u32 hash_bit;
738 u32 hash_value = hash_get(mac_addr);
739
740 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
741 if (netif_msg_drv(priv)) {
742 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
743 "Hash %08x, should not be greater than %08x",
744 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
745 }
746 return -1;
747 }
748
749
750 if (priv->multicast_hash_cnt[hash_value] == 0) {
751 rc = 1;
752 if (hash_value < 32) {
753 hash_bit = BIT(hash_value);
754 priv->mac_hash1 |= hash_bit;
755 } else {
756 hash_bit = BIT((hash_value - 32));
757 priv->mac_hash2 |= hash_bit;
758 }
759 }
760
761
762 ++priv->multicast_hash_cnt[hash_value];
763
764 return rc;
765}
766
767
768
769
770
771
772
773
774
775static int hash_del(struct emac_priv *priv, u8 *mac_addr)
776{
777 u32 hash_value;
778 u32 hash_bit;
779
780 hash_value = hash_get(mac_addr);
781 if (priv->multicast_hash_cnt[hash_value] > 0) {
782
783 --priv->multicast_hash_cnt[hash_value];
784 }
785
786
787
788 if (priv->multicast_hash_cnt[hash_value] > 0)
789 return 0;
790
791 if (hash_value < 32) {
792 hash_bit = BIT(hash_value);
793 priv->mac_hash1 &= ~hash_bit;
794 } else {
795 hash_bit = BIT((hash_value - 32));
796 priv->mac_hash2 &= ~hash_bit;
797 }
798
799
800 return 1;
801}
802
803
804#define EMAC_MULTICAST_ADD 0
805#define EMAC_MULTICAST_DEL 1
806#define EMAC_ALL_MULTI_SET 2
807#define EMAC_ALL_MULTI_CLR 3
808
809
810
811
812
813
814
815
816
817
818static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
819{
820 struct device *emac_dev = &priv->ndev->dev;
821 int update = -1;
822
823 switch (action) {
824 case EMAC_MULTICAST_ADD:
825 update = hash_add(priv, mac_addr);
826 break;
827 case EMAC_MULTICAST_DEL:
828 update = hash_del(priv, mac_addr);
829 break;
830 case EMAC_ALL_MULTI_SET:
831 update = 1;
832 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
833 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
834 break;
835 case EMAC_ALL_MULTI_CLR:
836 update = 1;
837 priv->mac_hash1 = 0;
838 priv->mac_hash2 = 0;
839 memset(&(priv->multicast_hash_cnt[0]), 0,
840 sizeof(priv->multicast_hash_cnt[0]) *
841 EMAC_NUM_MULTICAST_BITS);
842 break;
843 default:
844 if (netif_msg_drv(priv))
845 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
846 ": bad operation %d", action);
847 break;
848 }
849
850
851 if (update > 0) {
852 emac_write(EMAC_MACHASH1, priv->mac_hash1);
853 emac_write(EMAC_MACHASH2, priv->mac_hash2);
854 }
855}
856
857
858
859
860
861
862
863
864static void emac_dev_mcast_set(struct net_device *ndev)
865{
866 u32 mbp_enable;
867 struct emac_priv *priv = netdev_priv(ndev);
868
869 mbp_enable = emac_read(EMAC_RXMBPENABLE);
870 if (ndev->flags & IFF_PROMISC) {
871 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
872 mbp_enable |= (EMAC_MBP_RXPROMISC);
873 } else {
874 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
875 if ((ndev->flags & IFF_ALLMULTI) ||
876 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
877 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
878 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
879 }
880 if (!netdev_mc_empty(ndev)) {
881 struct netdev_hw_addr *ha;
882
883 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
884 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
885
886 netdev_for_each_mc_addr(ha, ndev) {
887 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
888 (u8 *) ha->addr);
889 }
890 } else {
891 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
892 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
893 }
894 }
895
896 emac_write(EMAC_RXMBPENABLE, mbp_enable);
897}
898
899
900
901
902
903
904
905
906
907
908
909
910static void emac_int_disable(struct emac_priv *priv)
911{
912 if (priv->version == EMAC_VERSION_2) {
913 unsigned long flags;
914
915 local_irq_save(flags);
916
917
918
919 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
920 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
921
922 if (priv->int_disable)
923 priv->int_disable();
924
925 local_irq_restore(flags);
926
927 } else {
928
929 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
930 }
931}
932
933
934
935
936
937
938
939
940static void emac_int_enable(struct emac_priv *priv)
941{
942 if (priv->version == EMAC_VERSION_2) {
943 if (priv->int_enable)
944 priv->int_enable();
945
946 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
947 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
948
949
950
951
952
953
954
955
956 emac_write(EMAC_DM646X_MACEOIVECTOR,
957 EMAC_DM646X_MAC_EOI_C0_RXEN);
958
959
960 emac_write(EMAC_DM646X_MACEOIVECTOR,
961 EMAC_DM646X_MAC_EOI_C0_TXEN);
962
963 } else {
964
965 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
966 }
967}
968
969
970
971
972
973
974
975
976
977
978
979static irqreturn_t emac_irq(int irq, void *dev_id)
980{
981 struct net_device *ndev = (struct net_device *)dev_id;
982 struct emac_priv *priv = netdev_priv(ndev);
983
984 ++priv->isr_count;
985 if (likely(netif_running(priv->ndev))) {
986 emac_int_disable(priv);
987 napi_schedule(&priv->napi);
988 } else {
989
990 }
991 return IRQ_HANDLED;
992}
993
994static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
995{
996 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
997 if (WARN_ON(!skb))
998 return NULL;
999 skb_reserve(skb, NET_IP_ALIGN);
1000 return skb;
1001}
1002
1003static void emac_rx_handler(void *token, int len, int status)
1004{
1005 struct sk_buff *skb = token;
1006 struct net_device *ndev = skb->dev;
1007 struct emac_priv *priv = netdev_priv(ndev);
1008 struct device *emac_dev = &ndev->dev;
1009 int ret;
1010
1011
1012 if (unlikely(!netif_running(ndev))) {
1013 dev_kfree_skb_any(skb);
1014 return;
1015 }
1016
1017
1018 if (status < 0) {
1019 ndev->stats.rx_errors++;
1020 goto recycle;
1021 }
1022
1023
1024 skb_put(skb, len);
1025 skb->protocol = eth_type_trans(skb, ndev);
1026 netif_receive_skb(skb);
1027 ndev->stats.rx_bytes += len;
1028 ndev->stats.rx_packets++;
1029
1030
1031 skb = emac_rx_alloc(priv);
1032 if (!skb) {
1033 if (netif_msg_rx_err(priv) && net_ratelimit())
1034 dev_err(emac_dev, "failed rx buffer alloc\n");
1035 return;
1036 }
1037
1038recycle:
1039 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1040 skb_tailroom(skb), 0);
1041
1042 WARN_ON(ret == -ENOMEM);
1043 if (unlikely(ret < 0))
1044 dev_kfree_skb_any(skb);
1045}
1046
1047static void emac_tx_handler(void *token, int len, int status)
1048{
1049 struct sk_buff *skb = token;
1050 struct net_device *ndev = skb->dev;
1051
1052
1053
1054
1055 if (unlikely(netif_queue_stopped(ndev)))
1056 netif_wake_queue(ndev);
1057 ndev->stats.tx_packets++;
1058 ndev->stats.tx_bytes += len;
1059 dev_kfree_skb_any(skb);
1060}
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1073{
1074 struct device *emac_dev = &ndev->dev;
1075 int ret_code;
1076 struct emac_priv *priv = netdev_priv(ndev);
1077
1078
1079 if (unlikely(!priv->link)) {
1080 if (netif_msg_tx_err(priv) && net_ratelimit())
1081 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1082 goto fail_tx;
1083 }
1084
1085 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1086 if (unlikely(ret_code < 0)) {
1087 if (netif_msg_tx_err(priv) && net_ratelimit())
1088 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1089 goto fail_tx;
1090 }
1091
1092 skb_tx_timestamp(skb);
1093
1094 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1095 0);
1096 if (unlikely(ret_code != 0)) {
1097 if (netif_msg_tx_err(priv) && net_ratelimit())
1098 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1099 goto fail_tx;
1100 }
1101
1102
1103
1104
1105 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
1106 netif_stop_queue(ndev);
1107
1108 return NETDEV_TX_OK;
1109
1110fail_tx:
1111 ndev->stats.tx_dropped++;
1112 netif_stop_queue(ndev);
1113 return NETDEV_TX_BUSY;
1114}
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126static void emac_dev_tx_timeout(struct net_device *ndev)
1127{
1128 struct emac_priv *priv = netdev_priv(ndev);
1129 struct device *emac_dev = &ndev->dev;
1130
1131 if (netif_msg_tx_err(priv))
1132 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1133
1134 emac_dump_regs(priv);
1135
1136 ndev->stats.tx_errors++;
1137 emac_int_disable(priv);
1138 cpdma_chan_stop(priv->txchan);
1139 cpdma_chan_start(priv->txchan);
1140 emac_int_enable(priv);
1141}
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1154{
1155 u32 val;
1156 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1157 emac_write(EMAC_MACSRCADDRLO, val);
1158
1159 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1160 (mac_addr[1] << 8) | (mac_addr[0]));
1161 emac_write(EMAC_MACSRCADDRHI, val);
1162 val = emac_read(EMAC_RXUNICASTSET);
1163 val |= BIT(ch);
1164 emac_write(EMAC_RXUNICASTSET, val);
1165 val = emac_read(EMAC_RXUNICASTCLEAR);
1166 val &= ~BIT(ch);
1167 emac_write(EMAC_RXUNICASTCLEAR, val);
1168}
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1181{
1182 u32 val;
1183 emac_write(EMAC_MACINDEX, ch);
1184 val = ((mac_addr[5] << 8) | mac_addr[4]);
1185 emac_write(EMAC_MACADDRLO, val);
1186 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1187 (mac_addr[1] << 8) | (mac_addr[0]));
1188 emac_write(EMAC_MACADDRHI, val);
1189 emac_set_type0addr(priv, ch, mac_addr);
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1205 char *mac_addr, int index, int match)
1206{
1207 u32 val;
1208 emac_write(EMAC_MACINDEX, index);
1209 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1210 (mac_addr[1] << 8) | (mac_addr[0]));
1211 emac_write(EMAC_MACADDRHI, val);
1212 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1213 (match << 19) | BIT(20));
1214 emac_write(EMAC_MACADDRLO, val);
1215 emac_set_type0addr(priv, ch, mac_addr);
1216}
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1229{
1230 struct device *emac_dev = &priv->ndev->dev;
1231
1232 if (priv->rx_addr_type == 0) {
1233 emac_set_type0addr(priv, ch, mac_addr);
1234 } else if (priv->rx_addr_type == 1) {
1235 u32 cnt;
1236 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1237 emac_set_type1addr(priv, ch, mac_addr);
1238 } else if (priv->rx_addr_type == 2) {
1239 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1240 emac_set_type0addr(priv, ch, mac_addr);
1241 } else {
1242 if (netif_msg_drv(priv))
1243 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1244 }
1245}
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1257{
1258 struct emac_priv *priv = netdev_priv(ndev);
1259 struct device *emac_dev = &priv->ndev->dev;
1260 struct sockaddr *sa = addr;
1261
1262 if (!is_valid_ether_addr(sa->sa_data))
1263 return -EADDRNOTAVAIL;
1264
1265
1266 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1267 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1268
1269
1270 if (netif_running(ndev)) {
1271 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1272 }
1273
1274 if (netif_msg_drv(priv))
1275 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1276 priv->mac_addr);
1277
1278 return 0;
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290static int emac_hw_enable(struct emac_priv *priv)
1291{
1292 u32 val, mbp_enable, mac_control;
1293
1294
1295 emac_write(EMAC_SOFTRESET, 1);
1296 while (emac_read(EMAC_SOFTRESET))
1297 cpu_relax();
1298
1299
1300 emac_int_disable(priv);
1301
1302
1303 mac_control =
1304 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1305 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1306 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1307 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1308 emac_write(EMAC_MACCONTROL, mac_control);
1309
1310 mbp_enable =
1311 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1312 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1313 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1314 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1315 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1316 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1317 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1318 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1319 EMAC_RXMBP_PROMCH_SHIFT) |
1320 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1321 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1322 EMAC_RXMBP_BROADCH_SHIFT) |
1323 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1324 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1325 EMAC_RXMBP_MULTICH_SHIFT));
1326 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1327 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1328 EMAC_RX_MAX_LEN_MASK));
1329 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1330 EMAC_RX_BUFFER_OFFSET_MASK));
1331 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1332 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1333 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1334
1335 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1336
1337 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1338
1339
1340 val = emac_read(EMAC_MACCONTROL);
1341 val |= (EMAC_MACCONTROL_GMIIEN);
1342 emac_write(EMAC_MACCONTROL, val);
1343
1344
1345 napi_enable(&priv->napi);
1346 emac_int_enable(priv);
1347 return 0;
1348
1349}
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364static int emac_poll(struct napi_struct *napi, int budget)
1365{
1366 unsigned int mask;
1367 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1368 struct net_device *ndev = priv->ndev;
1369 struct device *emac_dev = &ndev->dev;
1370 u32 status = 0;
1371 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1372
1373
1374 status = emac_read(EMAC_MACINVECTOR);
1375
1376 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1377
1378 if (priv->version == EMAC_VERSION_2)
1379 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1380
1381 if (status & mask) {
1382 num_tx_pkts = cpdma_chan_process(priv->txchan,
1383 EMAC_DEF_TX_MAX_SERVICE);
1384 }
1385
1386 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1387
1388 if (priv->version == EMAC_VERSION_2)
1389 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1390
1391 if (status & mask) {
1392 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1393 }
1394
1395 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1396 if (priv->version == EMAC_VERSION_2)
1397 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1398
1399 if (unlikely(status & mask)) {
1400 u32 ch, cause;
1401 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1402 netif_stop_queue(ndev);
1403 napi_disable(&priv->napi);
1404
1405 status = emac_read(EMAC_MACSTATUS);
1406 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1407 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1408 if (cause) {
1409 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1410 EMAC_MACSTATUS_TXERRCH_SHIFT);
1411 if (net_ratelimit()) {
1412 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1413 &emac_txhost_errcodes[cause][0], ch);
1414 }
1415 }
1416 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1417 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1418 if (cause) {
1419 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1420 EMAC_MACSTATUS_RXERRCH_SHIFT);
1421 if (netif_msg_hw(priv) && net_ratelimit())
1422 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1423 &emac_rxhost_errcodes[cause][0], ch);
1424 }
1425 } else if (num_rx_pkts < budget) {
1426 napi_complete(napi);
1427 emac_int_enable(priv);
1428 }
1429
1430 return num_rx_pkts;
1431}
1432
1433#ifdef CONFIG_NET_POLL_CONTROLLER
1434
1435
1436
1437
1438
1439
1440
1441static void emac_poll_controller(struct net_device *ndev)
1442{
1443 struct emac_priv *priv = netdev_priv(ndev);
1444
1445 emac_int_disable(priv);
1446 emac_irq(ndev->irq, ndev);
1447 emac_int_enable(priv);
1448}
1449#endif
1450
1451static void emac_adjust_link(struct net_device *ndev)
1452{
1453 struct emac_priv *priv = netdev_priv(ndev);
1454 struct phy_device *phydev = priv->phydev;
1455 unsigned long flags;
1456 int new_state = 0;
1457
1458 spin_lock_irqsave(&priv->lock, flags);
1459
1460 if (phydev->link) {
1461
1462 if (phydev->duplex != priv->duplex) {
1463 new_state = 1;
1464 priv->duplex = phydev->duplex;
1465 }
1466 if (phydev->speed != priv->speed) {
1467 new_state = 1;
1468 priv->speed = phydev->speed;
1469 }
1470 if (!priv->link) {
1471 new_state = 1;
1472 priv->link = 1;
1473 }
1474
1475 } else if (priv->link) {
1476 new_state = 1;
1477 priv->link = 0;
1478 priv->speed = 0;
1479 priv->duplex = ~0;
1480 }
1481 if (new_state) {
1482 emac_update_phystatus(priv);
1483 phy_print_status(priv->phydev);
1484 }
1485
1486 spin_unlock_irqrestore(&priv->lock, flags);
1487}
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1504{
1505 struct emac_priv *priv = netdev_priv(ndev);
1506
1507 if (!(netif_running(ndev)))
1508 return -EINVAL;
1509
1510
1511
1512 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1513}
1514
1515static int match_first_device(struct device *dev, void *data)
1516{
1517 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1518}
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530static int emac_dev_open(struct net_device *ndev)
1531{
1532 struct device *emac_dev = &ndev->dev;
1533 u32 cnt;
1534 struct resource *res;
1535 int ret;
1536 int i = 0;
1537 int k = 0;
1538 struct emac_priv *priv = netdev_priv(ndev);
1539
1540 pm_runtime_get(&priv->pdev->dev);
1541
1542 netif_carrier_off(ndev);
1543 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1544 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1545
1546
1547 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1548
1549 priv->mac_hash1 = 0;
1550 priv->mac_hash2 = 0;
1551 emac_write(EMAC_MACHASH1, 0);
1552 emac_write(EMAC_MACHASH2, 0);
1553
1554 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1555 struct sk_buff *skb = emac_rx_alloc(priv);
1556
1557 if (!skb)
1558 break;
1559
1560 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1561 skb_tailroom(skb), 0);
1562 if (WARN_ON(ret < 0))
1563 break;
1564 }
1565
1566
1567
1568 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1569 for (i = res->start; i <= res->end; i++) {
1570 if (devm_request_irq(&priv->pdev->dev, i, emac_irq,
1571 0, ndev->name, ndev))
1572 goto rollback;
1573 }
1574 k++;
1575 }
1576
1577
1578 emac_hw_enable(priv);
1579
1580
1581 if (priv->coal_intvl != 0) {
1582 struct ethtool_coalesce coal;
1583
1584 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1585 emac_set_coalesce(ndev, &coal);
1586 }
1587
1588 cpdma_ctlr_start(priv->dma);
1589
1590 priv->phydev = NULL;
1591
1592 if (!priv->phy_id) {
1593 struct device *phy;
1594
1595 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1596 match_first_device);
1597 if (phy)
1598 priv->phy_id = dev_name(phy);
1599 }
1600
1601 if (priv->phy_id && *priv->phy_id) {
1602 priv->phydev = phy_connect(ndev, priv->phy_id,
1603 &emac_adjust_link,
1604 PHY_INTERFACE_MODE_MII);
1605
1606 if (IS_ERR(priv->phydev)) {
1607 dev_err(emac_dev, "could not connect to phy %s\n",
1608 priv->phy_id);
1609 ret = PTR_ERR(priv->phydev);
1610 priv->phydev = NULL;
1611 goto err;
1612 }
1613
1614 priv->link = 0;
1615 priv->speed = 0;
1616 priv->duplex = ~0;
1617
1618 dev_info(emac_dev, "attached PHY driver [%s] "
1619 "(mii_bus:phy_addr=%s, id=%x)\n",
1620 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1621 priv->phydev->phy_id);
1622 } else {
1623
1624 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1625 priv->link = 1;
1626 priv->speed = SPEED_100;
1627 priv->duplex = DUPLEX_FULL;
1628 emac_update_phystatus(priv);
1629 }
1630
1631 if (!netif_running(ndev))
1632 emac_dump_regs(priv);
1633
1634 if (netif_msg_drv(priv))
1635 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1636
1637 if (priv->phydev)
1638 phy_start(priv->phydev);
1639
1640 return 0;
1641
1642rollback:
1643
1644 dev_err(emac_dev, "DaVinci EMAC: devm_request_irq() failed");
1645 ret = -EBUSY;
1646err:
1647 pm_runtime_put(&priv->pdev->dev);
1648 return ret;
1649}
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660static int emac_dev_stop(struct net_device *ndev)
1661{
1662 struct emac_priv *priv = netdev_priv(ndev);
1663 struct device *emac_dev = &ndev->dev;
1664
1665
1666 netif_stop_queue(ndev);
1667 napi_disable(&priv->napi);
1668
1669 netif_carrier_off(ndev);
1670 emac_int_disable(priv);
1671 cpdma_ctlr_stop(priv->dma);
1672 emac_write(EMAC_SOFTRESET, 1);
1673
1674 if (priv->phydev)
1675 phy_disconnect(priv->phydev);
1676
1677 if (netif_msg_drv(priv))
1678 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1679
1680 pm_runtime_put(&priv->pdev->dev);
1681 return 0;
1682}
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1693{
1694 struct emac_priv *priv = netdev_priv(ndev);
1695 u32 mac_control;
1696 u32 stats_clear_mask;
1697
1698
1699
1700 mac_control = emac_read(EMAC_MACCONTROL);
1701
1702 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1703 stats_clear_mask = EMAC_STATS_CLR_MASK;
1704 else
1705 stats_clear_mask = 0;
1706
1707 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1708 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1709
1710 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1711 emac_read(EMAC_TXSINGLECOLL) +
1712 emac_read(EMAC_TXMULTICOLL));
1713 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1714 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1715 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1716
1717 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1718 emac_read(EMAC_RXJABBER) +
1719 emac_read(EMAC_RXUNDERSIZED));
1720 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1721 emac_write(EMAC_RXJABBER, stats_clear_mask);
1722 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1723
1724 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1725 emac_read(EMAC_RXMOFOVERRUNS));
1726 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1727 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1728
1729 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1730 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1731
1732 ndev->stats.tx_carrier_errors +=
1733 emac_read(EMAC_TXCARRIERSENSE);
1734 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1735
1736 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1737 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1738
1739 return &ndev->stats;
1740}
1741
1742static const struct net_device_ops emac_netdev_ops = {
1743 .ndo_open = emac_dev_open,
1744 .ndo_stop = emac_dev_stop,
1745 .ndo_start_xmit = emac_dev_xmit,
1746 .ndo_set_rx_mode = emac_dev_mcast_set,
1747 .ndo_set_mac_address = emac_dev_setmac_addr,
1748 .ndo_do_ioctl = emac_devioctl,
1749 .ndo_tx_timeout = emac_dev_tx_timeout,
1750 .ndo_get_stats = emac_dev_getnetstats,
1751#ifdef CONFIG_NET_POLL_CONTROLLER
1752 .ndo_poll_controller = emac_poll_controller,
1753#endif
1754};
1755
1756static struct emac_platform_data *
1757davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1758{
1759 struct device_node *np;
1760 struct emac_platform_data *pdata = NULL;
1761 const u8 *mac_addr;
1762
1763 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1764 return pdev->dev.platform_data;
1765
1766 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1767 if (!pdata)
1768 return NULL;
1769
1770 np = pdev->dev.of_node;
1771 pdata->version = EMAC_VERSION_2;
1772
1773 if (!is_valid_ether_addr(pdata->mac_addr)) {
1774 mac_addr = of_get_mac_address(np);
1775 if (mac_addr)
1776 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
1777 }
1778
1779 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1780 &pdata->ctrl_reg_offset);
1781
1782 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1783 &pdata->ctrl_mod_reg_offset);
1784
1785 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1786 &pdata->ctrl_ram_offset);
1787
1788 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1789 &pdata->ctrl_ram_size);
1790
1791 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1792
1793 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1794
1795 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1796 if (!priv->phy_node)
1797 pdata->phy_id = "";
1798
1799 pdev->dev.platform_data = pdata;
1800
1801 return pdata;
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812static int davinci_emac_probe(struct platform_device *pdev)
1813{
1814 int rc = 0;
1815 struct resource *res;
1816 struct net_device *ndev;
1817 struct emac_priv *priv;
1818 unsigned long hw_ram_addr;
1819 struct emac_platform_data *pdata;
1820 struct device *emac_dev;
1821 struct cpdma_params dma_params;
1822 struct clk *emac_clk;
1823 unsigned long emac_bus_frequency;
1824
1825
1826
1827 emac_clk = devm_clk_get(&pdev->dev, NULL);
1828 if (IS_ERR(emac_clk)) {
1829 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1830 return -EBUSY;
1831 }
1832 emac_bus_frequency = clk_get_rate(emac_clk);
1833
1834
1835
1836 ndev = alloc_etherdev(sizeof(struct emac_priv));
1837 if (!ndev)
1838 return -ENOMEM;
1839
1840 platform_set_drvdata(pdev, ndev);
1841 priv = netdev_priv(ndev);
1842 priv->pdev = pdev;
1843 priv->ndev = ndev;
1844 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1845
1846 spin_lock_init(&priv->lock);
1847
1848 pdata = davinci_emac_of_get_pdata(pdev, priv);
1849 if (!pdata) {
1850 dev_err(&pdev->dev, "no platform data\n");
1851 rc = -ENODEV;
1852 goto no_pdata;
1853 }
1854
1855
1856 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1857 priv->phy_id = pdata->phy_id;
1858 priv->rmii_en = pdata->rmii_en;
1859 priv->version = pdata->version;
1860 priv->int_enable = pdata->interrupt_enable;
1861 priv->int_disable = pdata->interrupt_disable;
1862
1863 priv->coal_intvl = 0;
1864 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1865
1866 emac_dev = &ndev->dev;
1867
1868 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1869 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1870 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1871 if (IS_ERR(priv->remap_addr)) {
1872 rc = PTR_ERR(priv->remap_addr);
1873 goto no_pdata;
1874 }
1875 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1876 ndev->base_addr = (unsigned long)priv->remap_addr;
1877
1878 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1879
1880 hw_ram_addr = pdata->hw_ram_addr;
1881 if (!hw_ram_addr)
1882 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1883
1884 memset(&dma_params, 0, sizeof(dma_params));
1885 dma_params.dev = emac_dev;
1886 dma_params.dmaregs = priv->emac_base;
1887 dma_params.rxthresh = priv->emac_base + 0x120;
1888 dma_params.rxfree = priv->emac_base + 0x140;
1889 dma_params.txhdp = priv->emac_base + 0x600;
1890 dma_params.rxhdp = priv->emac_base + 0x620;
1891 dma_params.txcp = priv->emac_base + 0x640;
1892 dma_params.rxcp = priv->emac_base + 0x660;
1893 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1894 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1895 dma_params.desc_hw_addr = hw_ram_addr;
1896 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1897 dma_params.desc_align = 16;
1898
1899 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1900 (u32 __force)res->start + pdata->ctrl_ram_offset;
1901
1902 priv->dma = cpdma_ctlr_create(&dma_params);
1903 if (!priv->dma) {
1904 dev_err(&pdev->dev, "error initializing DMA\n");
1905 rc = -ENOMEM;
1906 goto no_pdata;
1907 }
1908
1909 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1910 emac_tx_handler);
1911 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1912 emac_rx_handler);
1913 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1914 rc = -ENOMEM;
1915 goto no_cpdma_chan;
1916 }
1917
1918 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1919 if (!res) {
1920 dev_err(&pdev->dev, "error getting irq res\n");
1921 rc = -ENOENT;
1922 goto no_cpdma_chan;
1923 }
1924 ndev->irq = res->start;
1925
1926 if (!is_valid_ether_addr(priv->mac_addr)) {
1927
1928 eth_hw_addr_random(ndev);
1929 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1930 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1931 priv->mac_addr);
1932 }
1933
1934 ndev->netdev_ops = &emac_netdev_ops;
1935 SET_ETHTOOL_OPS(ndev, ðtool_ops);
1936 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1937
1938
1939 SET_NETDEV_DEV(ndev, &pdev->dev);
1940 rc = register_netdev(ndev);
1941 if (rc) {
1942 dev_err(&pdev->dev, "error in register_netdev\n");
1943 rc = -ENODEV;
1944 goto no_cpdma_chan;
1945 }
1946
1947
1948 if (netif_msg_probe(priv)) {
1949 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
1950 "(regs: %p, irq: %d)\n",
1951 (void *)priv->emac_base_phys, ndev->irq);
1952 }
1953
1954 pm_runtime_enable(&pdev->dev);
1955 pm_runtime_resume(&pdev->dev);
1956
1957 return 0;
1958
1959no_cpdma_chan:
1960 if (priv->txchan)
1961 cpdma_chan_destroy(priv->txchan);
1962 if (priv->rxchan)
1963 cpdma_chan_destroy(priv->rxchan);
1964 cpdma_ctlr_destroy(priv->dma);
1965no_pdata:
1966 free_netdev(ndev);
1967 return rc;
1968}
1969
1970
1971
1972
1973
1974
1975
1976
1977static int davinci_emac_remove(struct platform_device *pdev)
1978{
1979 struct net_device *ndev = platform_get_drvdata(pdev);
1980 struct emac_priv *priv = netdev_priv(ndev);
1981
1982 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1983
1984 if (priv->txchan)
1985 cpdma_chan_destroy(priv->txchan);
1986 if (priv->rxchan)
1987 cpdma_chan_destroy(priv->rxchan);
1988 cpdma_ctlr_destroy(priv->dma);
1989
1990 unregister_netdev(ndev);
1991 free_netdev(ndev);
1992
1993 return 0;
1994}
1995
1996static int davinci_emac_suspend(struct device *dev)
1997{
1998 struct platform_device *pdev = to_platform_device(dev);
1999 struct net_device *ndev = platform_get_drvdata(pdev);
2000
2001 if (netif_running(ndev))
2002 emac_dev_stop(ndev);
2003
2004 return 0;
2005}
2006
2007static int davinci_emac_resume(struct device *dev)
2008{
2009 struct platform_device *pdev = to_platform_device(dev);
2010 struct net_device *ndev = platform_get_drvdata(pdev);
2011
2012 if (netif_running(ndev))
2013 emac_dev_open(ndev);
2014
2015 return 0;
2016}
2017
2018static const struct dev_pm_ops davinci_emac_pm_ops = {
2019 .suspend = davinci_emac_suspend,
2020 .resume = davinci_emac_resume,
2021};
2022
2023#if IS_ENABLED(CONFIG_OF)
2024static const struct of_device_id davinci_emac_of_match[] = {
2025 {.compatible = "ti,davinci-dm6467-emac", },
2026 {},
2027};
2028MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2029#endif
2030
2031
2032static struct platform_driver davinci_emac_driver = {
2033 .driver = {
2034 .name = "davinci_emac",
2035 .owner = THIS_MODULE,
2036 .pm = &davinci_emac_pm_ops,
2037 .of_match_table = of_match_ptr(davinci_emac_of_match),
2038 },
2039 .probe = davinci_emac_probe,
2040 .remove = davinci_emac_remove,
2041};
2042
2043
2044
2045
2046
2047
2048
2049static int __init davinci_emac_init(void)
2050{
2051 return platform_driver_register(&davinci_emac_driver);
2052}
2053late_initcall(davinci_emac_init);
2054
2055
2056
2057
2058
2059
2060
2061static void __exit davinci_emac_exit(void)
2062{
2063 platform_driver_unregister(&davinci_emac_driver);
2064}
2065module_exit(davinci_emac_exit);
2066
2067MODULE_LICENSE("GPL");
2068MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2069MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2070MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2071