1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/bitops.h>
48#include <linux/init.h>
49#include <linux/dma-mapping.h>
50#include <linux/mm.h>
51#include <linux/errno.h>
52#include <linux/ioport.h>
53#include <linux/pci.h>
54#include <linux/kernel.h>
55#include <linux/netdevice.h>
56#include <linux/etherdevice.h>
57#include <linux/skbuff.h>
58#include <linux/delay.h>
59#include <linux/timer.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/string.h>
63#include <linux/wait.h>
64#include <linux/io.h>
65#include <linux/if.h>
66#include <linux/uaccess.h>
67#include <linux/proc_fs.h>
68#include <linux/of_address.h>
69#include <linux/of_device.h>
70#include <linux/of_irq.h>
71#include <linux/inetdevice.h>
72#include <linux/platform_device.h>
73#include <linux/reboot.h>
74#include <linux/ethtool.h>
75#include <linux/mii.h>
76#include <linux/in.h>
77#include <linux/if_arp.h>
78#include <linux/if_vlan.h>
79#include <linux/ip.h>
80#include <linux/tcp.h>
81#include <linux/udp.h>
82#include <linux/crc-ccitt.h>
83#include <linux/crc32.h>
84
85#include "via-velocity.h"
86
87enum velocity_bus_type {
88 BUS_PCI,
89 BUS_PLATFORM,
90};
91
92static int velocity_nics;
93static int msglevel = MSG_LEVEL_INFO;
94
95static void velocity_set_power_state(struct velocity_info *vptr, char state)
96{
97 void *addr = vptr->mac_regs;
98
99 if (vptr->pdev)
100 pci_set_power_state(vptr->pdev, state);
101 else
102 writeb(state, addr + 0x154);
103}
104
105
106
107
108
109
110
111
112
113static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
114{
115 int i;
116
117
118 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
119
120 writeb(0, ®s->CAMADDR);
121
122
123 for (i = 0; i < 8; i++)
124 *mask++ = readb(&(regs->MARCAM[i]));
125
126
127 writeb(0, ®s->CAMADDR);
128
129
130 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
131}
132
133
134
135
136
137
138
139
140static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
141{
142 int i;
143
144 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
145
146 writeb(CAMADDR_CAMEN, ®s->CAMADDR);
147
148 for (i = 0; i < 8; i++)
149 writeb(*mask++, &(regs->MARCAM[i]));
150
151
152 writeb(0, ®s->CAMADDR);
153
154
155 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
156}
157
158static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
159{
160 int i;
161
162 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
163
164 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, ®s->CAMADDR);
165
166 for (i = 0; i < 8; i++)
167 writeb(*mask++, &(regs->MARCAM[i]));
168
169
170 writeb(0, ®s->CAMADDR);
171
172
173 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
174}
175
176
177
178
179
180
181
182
183
184static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
185{
186 int i;
187
188
189 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
190
191 idx &= (64 - 1);
192
193 writeb(CAMADDR_CAMEN | idx, ®s->CAMADDR);
194
195 for (i = 0; i < 6; i++)
196 writeb(*addr++, &(regs->MARCAM[i]));
197
198 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
199
200 udelay(10);
201
202 writeb(0, ®s->CAMADDR);
203
204
205 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
206}
207
208static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
209 const u8 *addr)
210{
211
212
213 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
214
215 idx &= (64 - 1);
216
217 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, ®s->CAMADDR);
218 writew(*((u16 *) addr), ®s->MARCAM[0]);
219
220 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
221
222 udelay(10);
223
224 writeb(0, ®s->CAMADDR);
225
226
227 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
228}
229
230
231
232
233
234
235
236
237
238
239static void mac_wol_reset(struct mac_regs __iomem *regs)
240{
241
242
243 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, ®s->STICKHW);
244
245 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
246
247 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, ®s->CHIPGCR);
248 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
249
250 writeb(WOLCFG_PMEOVR, ®s->WOLCFGClr);
251
252 writew(0xFFFF, ®s->WOLCRClr);
253
254 writew(0xFFFF, ®s->WOLSRClr);
255}
256
257static const struct ethtool_ops velocity_ethtool_ops;
258
259
260
261
262
263MODULE_AUTHOR("VIA Networking Technologies, Inc.");
264MODULE_LICENSE("GPL");
265MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
266
267#define VELOCITY_PARAM(N, D) \
268 static int N[MAX_UNITS] = OPTION_DEFAULT;\
269 module_param_array(N, int, NULL, 0); \
270 MODULE_PARM_DESC(N, D);
271
272#define RX_DESC_MIN 64
273#define RX_DESC_MAX 255
274#define RX_DESC_DEF 64
275VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
276
277#define TX_DESC_MIN 16
278#define TX_DESC_MAX 256
279#define TX_DESC_DEF 64
280VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
281
282#define RX_THRESH_MIN 0
283#define RX_THRESH_MAX 3
284#define RX_THRESH_DEF 0
285
286
287
288
289
290
291VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
292
293#define DMA_LENGTH_MIN 0
294#define DMA_LENGTH_MAX 7
295#define DMA_LENGTH_DEF 6
296
297
298
299
300
301
302
303
304
305
306
307VELOCITY_PARAM(DMA_length, "DMA length");
308
309#define IP_ALIG_DEF 0
310
311
312
313
314
315
316VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
317
318#define FLOW_CNTL_DEF 1
319#define FLOW_CNTL_MIN 1
320#define FLOW_CNTL_MAX 5
321
322
323
324
325
326
327
328
329VELOCITY_PARAM(flow_control, "Enable flow control ability");
330
331#define MED_LNK_DEF 0
332#define MED_LNK_MIN 0
333#define MED_LNK_MAX 5
334
335
336
337
338
339
340
341
342
343
344
345
346VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
347
348#define VAL_PKT_LEN_DEF 0
349
350
351
352
353VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
354
355#define WOL_OPT_DEF 0
356#define WOL_OPT_MIN 0
357#define WOL_OPT_MAX 7
358
359
360
361
362
363
364
365VELOCITY_PARAM(wol_opts, "Wake On Lan options");
366
367static int rx_copybreak = 200;
368module_param(rx_copybreak, int, 0644);
369MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
370
371
372
373
374static struct velocity_info_tbl chip_info_table[] = {
375 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
376 { }
377};
378
379
380
381
382
383
384static DEFINE_PCI_DEVICE_TABLE(velocity_pci_id_table) = {
385 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
386 { }
387};
388
389MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
390
391
392
393
394
395static struct of_device_id velocity_of_ids[] = {
396 { .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
397 { },
398};
399MODULE_DEVICE_TABLE(of, velocity_of_ids);
400
401
402
403
404
405
406
407
408static const char *get_chip_name(enum chip_type chip_id)
409{
410 int i;
411 for (i = 0; chip_info_table[i].name != NULL; i++)
412 if (chip_info_table[i].chip_id == chip_id)
413 break;
414 return chip_info_table[i].name;
415}
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431static void velocity_set_int_opt(int *opt, int val, int min, int max, int def,
432 char *name, const char *devname)
433{
434 if (val == -1)
435 *opt = def;
436 else if (val < min || val > max) {
437 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
438 devname, name, min, max);
439 *opt = def;
440 } else {
441 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
442 devname, name, val);
443 *opt = val;
444 }
445}
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460static void velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag,
461 char *name, const char *devname)
462{
463 (*opt) &= (~flag);
464 if (val == -1)
465 *opt |= (def ? flag : 0);
466 else if (val < 0 || val > 1) {
467 printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
468 devname, name);
469 *opt |= (def ? flag : 0);
470 } else {
471 printk(KERN_INFO "%s: set parameter %s to %s\n",
472 devname, name, val ? "TRUE" : "FALSE");
473 *opt |= (val ? flag : 0);
474 }
475}
476
477
478
479
480
481
482
483
484
485
486static void velocity_get_options(struct velocity_opt *opts, int index,
487 const char *devname)
488{
489
490 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
491 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
492 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
493 velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
494
495 velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
496 velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
497 velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
498 velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
499 velocity_set_int_opt(&opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
500 opts->numrx = (opts->numrx & ~3);
501}
502
503
504
505
506
507
508
509
510static void velocity_init_cam_filter(struct velocity_info *vptr)
511{
512 struct mac_regs __iomem *regs = vptr->mac_regs;
513 unsigned int vid, i = 0;
514
515
516 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, ®s->MCFG);
517 WORD_REG_BITS_ON(MCFG_VIDFR, ®s->MCFG);
518
519
520 memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
521 memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
522 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
523 mac_set_cam_mask(regs, vptr->mCAMmask);
524
525
526 for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
527 mac_set_vlan_cam(regs, i, (u8 *) &vid);
528 vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
529 if (++i >= VCAM_SIZE)
530 break;
531 }
532 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
533}
534
535static int velocity_vlan_rx_add_vid(struct net_device *dev,
536 __be16 proto, u16 vid)
537{
538 struct velocity_info *vptr = netdev_priv(dev);
539
540 spin_lock_irq(&vptr->lock);
541 set_bit(vid, vptr->active_vlans);
542 velocity_init_cam_filter(vptr);
543 spin_unlock_irq(&vptr->lock);
544 return 0;
545}
546
547static int velocity_vlan_rx_kill_vid(struct net_device *dev,
548 __be16 proto, u16 vid)
549{
550 struct velocity_info *vptr = netdev_priv(dev);
551
552 spin_lock_irq(&vptr->lock);
553 clear_bit(vid, vptr->active_vlans);
554 velocity_init_cam_filter(vptr);
555 spin_unlock_irq(&vptr->lock);
556 return 0;
557}
558
559static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
560{
561 vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
562}
563
564
565
566
567
568
569
570
571static void velocity_rx_reset(struct velocity_info *vptr)
572{
573
574 struct mac_regs __iomem *regs = vptr->mac_regs;
575 int i;
576
577 velocity_init_rx_ring_indexes(vptr);
578
579
580
581
582 for (i = 0; i < vptr->options.numrx; ++i)
583 vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
584
585 writew(vptr->options.numrx, ®s->RBRDU);
586 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
587 writew(0, ®s->RDIdx);
588 writew(vptr->options.numrx - 1, ®s->RDCSize);
589}
590
591
592
593
594
595
596
597
598
599static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
600{
601 u32 status = 0;
602
603 switch (vptr->options.spd_dpx) {
604 case SPD_DPX_AUTO:
605 status = VELOCITY_AUTONEG_ENABLE;
606 break;
607 case SPD_DPX_100_FULL:
608 status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
609 break;
610 case SPD_DPX_10_FULL:
611 status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
612 break;
613 case SPD_DPX_100_HALF:
614 status = VELOCITY_SPEED_100;
615 break;
616 case SPD_DPX_10_HALF:
617 status = VELOCITY_SPEED_10;
618 break;
619 case SPD_DPX_1000_FULL:
620 status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
621 break;
622 }
623 vptr->mii_status = status;
624 return status;
625}
626
627
628
629
630
631
632
633static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
634{
635 u16 ww;
636
637
638 writeb(0, ®s->MIICR);
639 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
640 udelay(1);
641 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
642 break;
643 }
644}
645
646
647
648
649
650
651
652
653static void enable_mii_autopoll(struct mac_regs __iomem *regs)
654{
655 int ii;
656
657 writeb(0, &(regs->MIICR));
658 writeb(MIIADR_SWMPL, ®s->MIIADR);
659
660 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
661 udelay(1);
662 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
663 break;
664 }
665
666 writeb(MIICR_MAUTO, ®s->MIICR);
667
668 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
669 udelay(1);
670 if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
671 break;
672 }
673
674}
675
676
677
678
679
680
681
682
683
684
685static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
686{
687 u16 ww;
688
689
690
691
692 safe_disable_mii_autopoll(regs);
693
694 writeb(index, ®s->MIIADR);
695
696 BYTE_REG_BITS_ON(MIICR_RCMD, ®s->MIICR);
697
698 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
699 if (!(readb(®s->MIICR) & MIICR_RCMD))
700 break;
701 }
702
703 *data = readw(®s->MIIDATA);
704
705 enable_mii_autopoll(regs);
706 if (ww == W_MAX_TIMEOUT)
707 return -ETIMEDOUT;
708 return 0;
709}
710
711
712
713
714
715
716
717
718static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
719{
720 u32 status = 0;
721 u16 ANAR;
722
723 if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
724 status |= VELOCITY_LINK_FAIL;
725
726 if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
727 status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
728 else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
729 status |= (VELOCITY_SPEED_1000);
730 else {
731 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
732 if (ANAR & ADVERTISE_100FULL)
733 status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
734 else if (ANAR & ADVERTISE_100HALF)
735 status |= VELOCITY_SPEED_100;
736 else if (ANAR & ADVERTISE_10FULL)
737 status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
738 else
739 status |= (VELOCITY_SPEED_10);
740 }
741
742 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
743 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
744 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
745 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
746 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
747 status |= VELOCITY_AUTONEG_ENABLE;
748 }
749 }
750
751 return status;
752}
753
754
755
756
757
758
759
760
761
762
763static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
764{
765 u16 ww;
766
767
768
769
770 safe_disable_mii_autopoll(regs);
771
772
773 writeb(mii_addr, ®s->MIIADR);
774
775 writew(data, ®s->MIIDATA);
776
777
778 BYTE_REG_BITS_ON(MIICR_WCMD, ®s->MIICR);
779
780
781 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
782 udelay(5);
783 if (!(readb(®s->MIICR) & MIICR_WCMD))
784 break;
785 }
786 enable_mii_autopoll(regs);
787
788 if (ww == W_MAX_TIMEOUT)
789 return -ETIMEDOUT;
790 return 0;
791}
792
793
794
795
796
797
798
799
800static void set_mii_flow_control(struct velocity_info *vptr)
801{
802
803 switch (vptr->options.flow_cntl) {
804 case FLOW_CNTL_TX:
805 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
806 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
807 break;
808
809 case FLOW_CNTL_RX:
810 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
811 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
812 break;
813
814 case FLOW_CNTL_TX_RX:
815 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
816 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
817 break;
818
819 case FLOW_CNTL_DISABLE:
820 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
821 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
822 break;
823 default:
824 break;
825 }
826}
827
828
829
830
831
832
833
834static void mii_set_auto_on(struct velocity_info *vptr)
835{
836 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
837 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
838 else
839 MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
840}
841
842static u32 check_connection_type(struct mac_regs __iomem *regs)
843{
844 u32 status = 0;
845 u8 PHYSR0;
846 u16 ANAR;
847 PHYSR0 = readb(®s->PHYSR0);
848
849
850
851
852
853
854 if (PHYSR0 & PHYSR0_FDPX)
855 status |= VELOCITY_DUPLEX_FULL;
856
857 if (PHYSR0 & PHYSR0_SPDG)
858 status |= VELOCITY_SPEED_1000;
859 else if (PHYSR0 & PHYSR0_SPD10)
860 status |= VELOCITY_SPEED_10;
861 else
862 status |= VELOCITY_SPEED_100;
863
864 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
865 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
866 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
867 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
868 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
869 status |= VELOCITY_AUTONEG_ENABLE;
870 }
871 }
872
873 return status;
874}
875
876
877
878
879
880
881
882
883
884static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
885{
886 u32 curr_status;
887 struct mac_regs __iomem *regs = vptr->mac_regs;
888
889 vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
890 curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
891
892
893 set_mii_flow_control(vptr);
894
895
896
897
898
899
900
901
902
903
904
905
906 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
907 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
908
909
910
911
912 if (mii_status & VELOCITY_AUTONEG_ENABLE) {
913 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
914
915 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
916
917 MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
918 MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
919 MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
920
921
922 mii_set_auto_on(vptr);
923 } else {
924 u16 CTRL1000;
925 u16 ANAR;
926 u8 CHIPGCR;
927
928
929
930
931
932
933
934
935
936 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
937
938 CHIPGCR = readb(®s->CHIPGCR);
939
940 if (mii_status & VELOCITY_SPEED_1000)
941 CHIPGCR |= CHIPGCR_FCGMII;
942 else
943 CHIPGCR &= ~CHIPGCR_FCGMII;
944
945 if (mii_status & VELOCITY_DUPLEX_FULL) {
946 CHIPGCR |= CHIPGCR_FCFDX;
947 writeb(CHIPGCR, ®s->CHIPGCR);
948 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
949 if (vptr->rev_id < REV_ID_VT3216_A0)
950 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
951 } else {
952 CHIPGCR &= ~CHIPGCR_FCFDX;
953 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
954 writeb(CHIPGCR, ®s->CHIPGCR);
955 if (vptr->rev_id < REV_ID_VT3216_A0)
956 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
957 }
958
959 velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
960 CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
961 if ((mii_status & VELOCITY_SPEED_1000) &&
962 (mii_status & VELOCITY_DUPLEX_FULL)) {
963 CTRL1000 |= ADVERTISE_1000FULL;
964 }
965 velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
966
967 if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
968 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
969 else
970 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
971
972
973 velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
974 ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
975 if (mii_status & VELOCITY_SPEED_100) {
976 if (mii_status & VELOCITY_DUPLEX_FULL)
977 ANAR |= ADVERTISE_100FULL;
978 else
979 ANAR |= ADVERTISE_100HALF;
980 } else if (mii_status & VELOCITY_SPEED_10) {
981 if (mii_status & VELOCITY_DUPLEX_FULL)
982 ANAR |= ADVERTISE_10FULL;
983 else
984 ANAR |= ADVERTISE_10HALF;
985 }
986 velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
987
988 mii_set_auto_on(vptr);
989
990 }
991
992
993 return VELOCITY_LINK_CHANGE;
994}
995
996
997
998
999
1000
1001
1002
1003
1004static void velocity_print_link_status(struct velocity_info *vptr)
1005{
1006
1007 if (vptr->mii_status & VELOCITY_LINK_FAIL) {
1008 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
1009 } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1010 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
1011
1012 if (vptr->mii_status & VELOCITY_SPEED_1000)
1013 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
1014 else if (vptr->mii_status & VELOCITY_SPEED_100)
1015 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
1016 else
1017 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
1018
1019 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1020 VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
1021 else
1022 VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
1023 } else {
1024 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
1025 switch (vptr->options.spd_dpx) {
1026 case SPD_DPX_1000_FULL:
1027 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
1028 break;
1029 case SPD_DPX_100_HALF:
1030 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
1031 break;
1032 case SPD_DPX_100_FULL:
1033 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
1034 break;
1035 case SPD_DPX_10_HALF:
1036 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
1037 break;
1038 case SPD_DPX_10_FULL:
1039 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
1040 break;
1041 default:
1042 break;
1043 }
1044 }
1045}
1046
1047
1048
1049
1050
1051
1052
1053
1054static void enable_flow_control_ability(struct velocity_info *vptr)
1055{
1056
1057 struct mac_regs __iomem *regs = vptr->mac_regs;
1058
1059 switch (vptr->options.flow_cntl) {
1060
1061 case FLOW_CNTL_DEFAULT:
1062 if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, ®s->PHYSR0))
1063 writel(CR0_FDXRFCEN, ®s->CR0Set);
1064 else
1065 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1066
1067 if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, ®s->PHYSR0))
1068 writel(CR0_FDXTFCEN, ®s->CR0Set);
1069 else
1070 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1071 break;
1072
1073 case FLOW_CNTL_TX:
1074 writel(CR0_FDXTFCEN, ®s->CR0Set);
1075 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1076 break;
1077
1078 case FLOW_CNTL_RX:
1079 writel(CR0_FDXRFCEN, ®s->CR0Set);
1080 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1081 break;
1082
1083 case FLOW_CNTL_TX_RX:
1084 writel(CR0_FDXTFCEN, ®s->CR0Set);
1085 writel(CR0_FDXRFCEN, ®s->CR0Set);
1086 break;
1087
1088 case FLOW_CNTL_DISABLE:
1089 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1090 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1091 break;
1092
1093 default:
1094 break;
1095 }
1096
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106static int velocity_soft_reset(struct velocity_info *vptr)
1107{
1108 struct mac_regs __iomem *regs = vptr->mac_regs;
1109 int i = 0;
1110
1111 writel(CR0_SFRST, ®s->CR0Set);
1112
1113 for (i = 0; i < W_MAX_TIMEOUT; i++) {
1114 udelay(5);
1115 if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, ®s->CR0Set))
1116 break;
1117 }
1118
1119 if (i == W_MAX_TIMEOUT) {
1120 writel(CR0_FORSRST, ®s->CR0Set);
1121
1122
1123 mdelay(2);
1124 }
1125 return 0;
1126}
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136static void velocity_set_multi(struct net_device *dev)
1137{
1138 struct velocity_info *vptr = netdev_priv(dev);
1139 struct mac_regs __iomem *regs = vptr->mac_regs;
1140 u8 rx_mode;
1141 int i;
1142 struct netdev_hw_addr *ha;
1143
1144 if (dev->flags & IFF_PROMISC) {
1145 writel(0xffffffff, ®s->MARCAM[0]);
1146 writel(0xffffffff, ®s->MARCAM[4]);
1147 rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
1148 } else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
1149 (dev->flags & IFF_ALLMULTI)) {
1150 writel(0xffffffff, ®s->MARCAM[0]);
1151 writel(0xffffffff, ®s->MARCAM[4]);
1152 rx_mode = (RCR_AM | RCR_AB);
1153 } else {
1154 int offset = MCAM_SIZE - vptr->multicast_limit;
1155 mac_get_cam_mask(regs, vptr->mCAMmask);
1156
1157 i = 0;
1158 netdev_for_each_mc_addr(ha, dev) {
1159 mac_set_cam(regs, i + offset, ha->addr);
1160 vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
1161 i++;
1162 }
1163
1164 mac_set_cam_mask(regs, vptr->mCAMmask);
1165 rx_mode = RCR_AM | RCR_AB | RCR_AP;
1166 }
1167 if (dev->mtu > 1500)
1168 rx_mode |= RCR_AL;
1169
1170 BYTE_REG_BITS_ON(rx_mode, ®s->RCR);
1171
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185static void mii_init(struct velocity_info *vptr, u32 mii_status)
1186{
1187 u16 BMCR;
1188
1189 switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
1190 case PHYID_ICPLUS_IP101A:
1191 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
1192 MII_ADVERTISE, vptr->mac_regs);
1193 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1194 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
1195 vptr->mac_regs);
1196 else
1197 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
1198 vptr->mac_regs);
1199 MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1200 break;
1201 case PHYID_CICADA_CS8201:
1202
1203
1204
1205 MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1206
1207
1208
1209
1210
1211 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1212 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1213 else
1214 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1215
1216
1217
1218 MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1219 break;
1220 case PHYID_VT3216_32BIT:
1221 case PHYID_VT3216_64BIT:
1222
1223
1224
1225 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1226
1227
1228
1229
1230
1231 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1232 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1233 else
1234 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1235 break;
1236
1237 case PHYID_MARVELL_1000:
1238 case PHYID_MARVELL_1000S:
1239
1240
1241
1242 MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
1243
1244
1245
1246 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1247 break;
1248 default:
1249 ;
1250 }
1251 velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
1252 if (BMCR & BMCR_ISOLATE) {
1253 BMCR &= ~BMCR_ISOLATE;
1254 velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
1255 }
1256}
1257
1258
1259
1260
1261
1262
1263
1264static void setup_queue_timers(struct velocity_info *vptr)
1265{
1266
1267 if (vptr->rev_id >= REV_ID_VT3216_A0) {
1268 u8 txqueue_timer = 0;
1269 u8 rxqueue_timer = 0;
1270
1271 if (vptr->mii_status & (VELOCITY_SPEED_1000 |
1272 VELOCITY_SPEED_100)) {
1273 txqueue_timer = vptr->options.txqueue_timer;
1274 rxqueue_timer = vptr->options.rxqueue_timer;
1275 }
1276
1277 writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
1278 writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
1279 }
1280}
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290static void setup_adaptive_interrupts(struct velocity_info *vptr)
1291{
1292 struct mac_regs __iomem *regs = vptr->mac_regs;
1293 u16 tx_intsup = vptr->options.tx_intsup;
1294 u16 rx_intsup = vptr->options.rx_intsup;
1295
1296
1297 vptr->int_mask = INT_MASK_DEF;
1298
1299
1300 writeb(CAMCR_PS0, ®s->CAMCR);
1301 if (tx_intsup != 0) {
1302 vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
1303 ISR_PTX2I | ISR_PTX3I);
1304 writew(tx_intsup, ®s->ISRCTL);
1305 } else
1306 writew(ISRCTL_TSUPDIS, ®s->ISRCTL);
1307
1308
1309 writeb(CAMCR_PS1, ®s->CAMCR);
1310 if (rx_intsup != 0) {
1311 vptr->int_mask &= ~ISR_PRXI;
1312 writew(rx_intsup, ®s->ISRCTL);
1313 } else
1314 writew(ISRCTL_RSUPDIS, ®s->ISRCTL);
1315
1316
1317 writeb(0, ®s->CAMCR);
1318}
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328static void velocity_init_registers(struct velocity_info *vptr,
1329 enum velocity_init_type type)
1330{
1331 struct mac_regs __iomem *regs = vptr->mac_regs;
1332 struct net_device *netdev = vptr->netdev;
1333 int i, mii_status;
1334
1335 mac_wol_reset(regs);
1336
1337 switch (type) {
1338 case VELOCITY_INIT_RESET:
1339 case VELOCITY_INIT_WOL:
1340
1341 netif_stop_queue(netdev);
1342
1343
1344
1345
1346 velocity_rx_reset(vptr);
1347 mac_rx_queue_run(regs);
1348 mac_rx_queue_wake(regs);
1349
1350 mii_status = velocity_get_opt_media_mode(vptr);
1351 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1352 velocity_print_link_status(vptr);
1353 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1354 netif_wake_queue(netdev);
1355 }
1356
1357 enable_flow_control_ability(vptr);
1358
1359 mac_clear_isr(regs);
1360 writel(CR0_STOP, ®s->CR0Clr);
1361 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
1362 ®s->CR0Set);
1363
1364 break;
1365
1366 case VELOCITY_INIT_COLD:
1367 default:
1368
1369
1370
1371 velocity_soft_reset(vptr);
1372 mdelay(5);
1373
1374 if (!vptr->no_eeprom) {
1375 mac_eeprom_reload(regs);
1376 for (i = 0; i < 6; i++)
1377 writeb(netdev->dev_addr[i], regs->PAR + i);
1378 }
1379
1380
1381
1382
1383 BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
1384 mac_set_rx_thresh(regs, vptr->options.rx_thresh);
1385 mac_set_dma_length(regs, vptr->options.DMA_length);
1386
1387 writeb(WOLCFG_SAM | WOLCFG_SAB, ®s->WOLCFGSet);
1388
1389
1390
1391 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), ®s->CFGB);
1392
1393
1394
1395
1396 velocity_init_cam_filter(vptr);
1397
1398
1399
1400
1401 velocity_set_multi(netdev);
1402
1403
1404
1405
1406 enable_mii_autopoll(regs);
1407
1408 setup_adaptive_interrupts(vptr);
1409
1410 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
1411 writew(vptr->options.numrx - 1, ®s->RDCSize);
1412 mac_rx_queue_run(regs);
1413 mac_rx_queue_wake(regs);
1414
1415 writew(vptr->options.numtx - 1, ®s->TDCSize);
1416
1417 for (i = 0; i < vptr->tx.numq; i++) {
1418 writel(vptr->tx.pool_dma[i], ®s->TDBaseLo[i]);
1419 mac_tx_queue_run(regs, i);
1420 }
1421
1422 init_flow_control_register(vptr);
1423
1424 writel(CR0_STOP, ®s->CR0Clr);
1425 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), ®s->CR0Set);
1426
1427 mii_status = velocity_get_opt_media_mode(vptr);
1428 netif_stop_queue(netdev);
1429
1430 mii_init(vptr, mii_status);
1431
1432 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1433 velocity_print_link_status(vptr);
1434 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1435 netif_wake_queue(netdev);
1436 }
1437
1438 enable_flow_control_ability(vptr);
1439 mac_hw_mibs_init(regs);
1440 mac_write_int_mask(vptr->int_mask, regs);
1441 mac_clear_isr(regs);
1442
1443 }
1444}
1445
1446static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1447{
1448 struct mac_regs __iomem *regs = vptr->mac_regs;
1449 int avail, dirty, unusable;
1450
1451
1452
1453
1454
1455 if (vptr->rx.filled < 4)
1456 return;
1457
1458 wmb();
1459
1460 unusable = vptr->rx.filled & 0x0003;
1461 dirty = vptr->rx.dirty - unusable;
1462 for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
1463 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1464 vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
1465 }
1466
1467 writew(vptr->rx.filled & 0xfffc, ®s->RBRDU);
1468 vptr->rx.filled = unusable;
1469}
1470
1471
1472
1473
1474
1475
1476
1477
1478static int velocity_init_dma_rings(struct velocity_info *vptr)
1479{
1480 struct velocity_opt *opt = &vptr->options;
1481 const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1482 const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1483 dma_addr_t pool_dma;
1484 void *pool;
1485 unsigned int i;
1486
1487
1488
1489
1490
1491
1492
1493 pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
1494 rx_ring_size, &pool_dma, GFP_ATOMIC);
1495 if (!pool) {
1496 dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
1497 vptr->netdev->name);
1498 return -ENOMEM;
1499 }
1500
1501 vptr->rx.ring = pool;
1502 vptr->rx.pool_dma = pool_dma;
1503
1504 pool += rx_ring_size;
1505 pool_dma += rx_ring_size;
1506
1507 for (i = 0; i < vptr->tx.numq; i++) {
1508 vptr->tx.rings[i] = pool;
1509 vptr->tx.pool_dma[i] = pool_dma;
1510 pool += tx_ring_size;
1511 pool_dma += tx_ring_size;
1512 }
1513
1514 return 0;
1515}
1516
1517static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1518{
1519 vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1533{
1534 struct rx_desc *rd = &(vptr->rx.ring[idx]);
1535 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1536
1537 rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
1538 if (rd_info->skb == NULL)
1539 return -ENOMEM;
1540
1541
1542
1543
1544
1545 skb_reserve(rd_info->skb,
1546 64 - ((unsigned long) rd_info->skb->data & 63));
1547 rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
1548 vptr->rx.buf_sz, DMA_FROM_DEVICE);
1549
1550
1551
1552
1553
1554 *((u32 *) & (rd->rdesc0)) = 0;
1555 rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
1556 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1557 rd->pa_high = 0;
1558 return 0;
1559}
1560
1561
1562static int velocity_rx_refill(struct velocity_info *vptr)
1563{
1564 int dirty = vptr->rx.dirty, done = 0;
1565
1566 do {
1567 struct rx_desc *rd = vptr->rx.ring + dirty;
1568
1569
1570 if (rd->rdesc0.len & OWNED_BY_NIC)
1571 break;
1572
1573 if (!vptr->rx.info[dirty].skb) {
1574 if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1575 break;
1576 }
1577 done++;
1578 dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1579 } while (dirty != vptr->rx.curr);
1580
1581 if (done) {
1582 vptr->rx.dirty = dirty;
1583 vptr->rx.filled += done;
1584 }
1585
1586 return done;
1587}
1588
1589
1590
1591
1592
1593
1594
1595
1596static void velocity_free_rd_ring(struct velocity_info *vptr)
1597{
1598 int i;
1599
1600 if (vptr->rx.info == NULL)
1601 return;
1602
1603 for (i = 0; i < vptr->options.numrx; i++) {
1604 struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
1605 struct rx_desc *rd = vptr->rx.ring + i;
1606
1607 memset(rd, 0, sizeof(*rd));
1608
1609 if (!rd_info->skb)
1610 continue;
1611 dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
1612 DMA_FROM_DEVICE);
1613 rd_info->skb_dma = 0;
1614
1615 dev_kfree_skb(rd_info->skb);
1616 rd_info->skb = NULL;
1617 }
1618
1619 kfree(vptr->rx.info);
1620 vptr->rx.info = NULL;
1621}
1622
1623
1624
1625
1626
1627
1628
1629
1630static int velocity_init_rd_ring(struct velocity_info *vptr)
1631{
1632 int ret = -ENOMEM;
1633
1634 vptr->rx.info = kcalloc(vptr->options.numrx,
1635 sizeof(struct velocity_rd_info), GFP_KERNEL);
1636 if (!vptr->rx.info)
1637 goto out;
1638
1639 velocity_init_rx_ring_indexes(vptr);
1640
1641 if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1642 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1643 "%s: failed to allocate RX buffer.\n", vptr->netdev->name);
1644 velocity_free_rd_ring(vptr);
1645 goto out;
1646 }
1647
1648 ret = 0;
1649out:
1650 return ret;
1651}
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661static int velocity_init_td_ring(struct velocity_info *vptr)
1662{
1663 int j;
1664
1665
1666 for (j = 0; j < vptr->tx.numq; j++) {
1667
1668 vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
1669 sizeof(struct velocity_td_info),
1670 GFP_KERNEL);
1671 if (!vptr->tx.infos[j]) {
1672 while (--j >= 0)
1673 kfree(vptr->tx.infos[j]);
1674 return -ENOMEM;
1675 }
1676
1677 vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
1678 }
1679 return 0;
1680}
1681
1682
1683
1684
1685
1686
1687
1688static void velocity_free_dma_rings(struct velocity_info *vptr)
1689{
1690 const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1691 vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
1692
1693 dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
1694}
1695
1696static int velocity_init_rings(struct velocity_info *vptr, int mtu)
1697{
1698 int ret;
1699
1700 velocity_set_rxbufsize(vptr, mtu);
1701
1702 ret = velocity_init_dma_rings(vptr);
1703 if (ret < 0)
1704 goto out;
1705
1706 ret = velocity_init_rd_ring(vptr);
1707 if (ret < 0)
1708 goto err_free_dma_rings_0;
1709
1710 ret = velocity_init_td_ring(vptr);
1711 if (ret < 0)
1712 goto err_free_rd_ring_1;
1713out:
1714 return ret;
1715
1716err_free_rd_ring_1:
1717 velocity_free_rd_ring(vptr);
1718err_free_dma_rings_0:
1719 velocity_free_dma_rings(vptr);
1720 goto out;
1721}
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731static void velocity_free_tx_buf(struct velocity_info *vptr,
1732 struct velocity_td_info *tdinfo, struct tx_desc *td)
1733{
1734 struct sk_buff *skb = tdinfo->skb;
1735
1736
1737
1738
1739 if (tdinfo->skb_dma) {
1740 int i;
1741
1742 for (i = 0; i < tdinfo->nskb_dma; i++) {
1743 size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
1744
1745
1746 if (skb_shinfo(skb)->nr_frags > 0)
1747 pktlen = max_t(size_t, pktlen,
1748 td->td_buf[i].size & ~TD_QUEUE);
1749
1750 dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
1751 le16_to_cpu(pktlen), DMA_TO_DEVICE);
1752 }
1753 }
1754 dev_kfree_skb_irq(skb);
1755 tdinfo->skb = NULL;
1756}
1757
1758
1759
1760
1761static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1762 int q, int n)
1763{
1764 struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
1765 int i;
1766
1767 if (td_info == NULL)
1768 return;
1769
1770 if (td_info->skb) {
1771 for (i = 0; i < td_info->nskb_dma; i++) {
1772 if (td_info->skb_dma[i]) {
1773 dma_unmap_single(vptr->dev, td_info->skb_dma[i],
1774 td_info->skb->len, DMA_TO_DEVICE);
1775 td_info->skb_dma[i] = 0;
1776 }
1777 }
1778 dev_kfree_skb(td_info->skb);
1779 td_info->skb = NULL;
1780 }
1781}
1782
1783
1784
1785
1786
1787
1788
1789
1790static void velocity_free_td_ring(struct velocity_info *vptr)
1791{
1792 int i, j;
1793
1794 for (j = 0; j < vptr->tx.numq; j++) {
1795 if (vptr->tx.infos[j] == NULL)
1796 continue;
1797 for (i = 0; i < vptr->options.numtx; i++)
1798 velocity_free_td_ring_entry(vptr, j, i);
1799
1800 kfree(vptr->tx.infos[j]);
1801 vptr->tx.infos[j] = NULL;
1802 }
1803}
1804
1805static void velocity_free_rings(struct velocity_info *vptr)
1806{
1807 velocity_free_td_ring(vptr);
1808 velocity_free_rd_ring(vptr);
1809 velocity_free_dma_rings(vptr);
1810}
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823static void velocity_error(struct velocity_info *vptr, int status)
1824{
1825
1826 if (status & ISR_TXSTLI) {
1827 struct mac_regs __iomem *regs = vptr->mac_regs;
1828
1829 printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(®s->TDIdx[0]));
1830 BYTE_REG_BITS_ON(TXESR_TDSTR, ®s->TXESR);
1831 writew(TRDCSR_RUN, ®s->TDCSRClr);
1832 netif_stop_queue(vptr->netdev);
1833
1834
1835
1836 }
1837
1838 if (status & ISR_SRCI) {
1839 struct mac_regs __iomem *regs = vptr->mac_regs;
1840 int linked;
1841
1842 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1843 vptr->mii_status = check_connection_type(regs);
1844
1845
1846
1847
1848
1849
1850 if (vptr->rev_id < REV_ID_VT3216_A0) {
1851 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1852 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
1853 else
1854 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
1855 }
1856
1857
1858
1859 if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
1860 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
1861 else
1862 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
1863
1864 setup_queue_timers(vptr);
1865 }
1866
1867
1868
1869 linked = readb(®s->PHYSR0) & PHYSR0_LINKGD;
1870
1871 if (linked) {
1872 vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1873 netif_carrier_on(vptr->netdev);
1874 } else {
1875 vptr->mii_status |= VELOCITY_LINK_FAIL;
1876 netif_carrier_off(vptr->netdev);
1877 }
1878
1879 velocity_print_link_status(vptr);
1880 enable_flow_control_ability(vptr);
1881
1882
1883
1884
1885
1886
1887 enable_mii_autopoll(regs);
1888
1889 if (vptr->mii_status & VELOCITY_LINK_FAIL)
1890 netif_stop_queue(vptr->netdev);
1891 else
1892 netif_wake_queue(vptr->netdev);
1893
1894 }
1895 if (status & ISR_MIBFI)
1896 velocity_update_hw_mibs(vptr);
1897 if (status & ISR_LSTEI)
1898 mac_rx_queue_wake(vptr->mac_regs);
1899}
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909static int velocity_tx_srv(struct velocity_info *vptr)
1910{
1911 struct tx_desc *td;
1912 int qnum;
1913 int full = 0;
1914 int idx;
1915 int works = 0;
1916 struct velocity_td_info *tdinfo;
1917 struct net_device_stats *stats = &vptr->netdev->stats;
1918
1919 for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
1920 for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
1921 idx = (idx + 1) % vptr->options.numtx) {
1922
1923
1924
1925
1926 td = &(vptr->tx.rings[qnum][idx]);
1927 tdinfo = &(vptr->tx.infos[qnum][idx]);
1928
1929 if (td->tdesc0.len & OWNED_BY_NIC)
1930 break;
1931
1932 if ((works++ > 15))
1933 break;
1934
1935 if (td->tdesc0.TSR & TSR0_TERR) {
1936 stats->tx_errors++;
1937 stats->tx_dropped++;
1938 if (td->tdesc0.TSR & TSR0_CDH)
1939 stats->tx_heartbeat_errors++;
1940 if (td->tdesc0.TSR & TSR0_CRS)
1941 stats->tx_carrier_errors++;
1942 if (td->tdesc0.TSR & TSR0_ABT)
1943 stats->tx_aborted_errors++;
1944 if (td->tdesc0.TSR & TSR0_OWC)
1945 stats->tx_window_errors++;
1946 } else {
1947 stats->tx_packets++;
1948 stats->tx_bytes += tdinfo->skb->len;
1949 }
1950 velocity_free_tx_buf(vptr, tdinfo, td);
1951 vptr->tx.used[qnum]--;
1952 }
1953 vptr->tx.tail[qnum] = idx;
1954
1955 if (AVAIL_TD(vptr, qnum) < 1)
1956 full = 1;
1957 }
1958
1959
1960
1961
1962 if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
1963 (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1964 netif_wake_queue(vptr->netdev);
1965 }
1966 return works;
1967}
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1978{
1979 skb_checksum_none_assert(skb);
1980
1981 if (rd->rdesc1.CSM & CSM_IPKT) {
1982 if (rd->rdesc1.CSM & CSM_IPOK) {
1983 if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1984 (rd->rdesc1.CSM & CSM_UDPKT)) {
1985 if (!(rd->rdesc1.CSM & CSM_TUPOK))
1986 return;
1987 }
1988 skb->ip_summed = CHECKSUM_UNNECESSARY;
1989 }
1990 }
1991}
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
2006 struct velocity_info *vptr)
2007{
2008 int ret = -1;
2009 if (pkt_size < rx_copybreak) {
2010 struct sk_buff *new_skb;
2011
2012 new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
2013 if (new_skb) {
2014 new_skb->ip_summed = rx_skb[0]->ip_summed;
2015 skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
2016 *rx_skb = new_skb;
2017 ret = 0;
2018 }
2019
2020 }
2021 return ret;
2022}
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033static inline void velocity_iph_realign(struct velocity_info *vptr,
2034 struct sk_buff *skb, int pkt_size)
2035{
2036 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
2037 memmove(skb->data + 2, skb->data, pkt_size);
2038 skb_reserve(skb, 2);
2039 }
2040}
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050static int velocity_receive_frame(struct velocity_info *vptr, int idx)
2051{
2052 struct net_device_stats *stats = &vptr->netdev->stats;
2053 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
2054 struct rx_desc *rd = &(vptr->rx.ring[idx]);
2055 int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
2056 struct sk_buff *skb;
2057
2058 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
2059 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->netdev->name);
2060 stats->rx_length_errors++;
2061 return -EINVAL;
2062 }
2063
2064 if (rd->rdesc0.RSR & RSR_MAR)
2065 stats->multicast++;
2066
2067 skb = rd_info->skb;
2068
2069 dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
2070 vptr->rx.buf_sz, DMA_FROM_DEVICE);
2071
2072
2073
2074
2075
2076 if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
2077 if (rd->rdesc0.RSR & RSR_RL) {
2078 stats->rx_length_errors++;
2079 return -EINVAL;
2080 }
2081 }
2082
2083 velocity_rx_csum(rd, skb);
2084
2085 if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
2086 velocity_iph_realign(vptr, skb, pkt_len);
2087 rd_info->skb = NULL;
2088 dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
2089 DMA_FROM_DEVICE);
2090 } else {
2091 dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
2092 vptr->rx.buf_sz, DMA_FROM_DEVICE);
2093 }
2094
2095 skb_put(skb, pkt_len - 4);
2096 skb->protocol = eth_type_trans(skb, vptr->netdev);
2097
2098 if (rd->rdesc0.RSR & RSR_DETAG) {
2099 u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
2100
2101 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2102 }
2103 netif_receive_skb(skb);
2104
2105 stats->rx_bytes += pkt_len;
2106 stats->rx_packets++;
2107
2108 return 0;
2109}
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
2120{
2121 struct net_device_stats *stats = &vptr->netdev->stats;
2122 int rd_curr = vptr->rx.curr;
2123 int works = 0;
2124
2125 while (works < budget_left) {
2126 struct rx_desc *rd = vptr->rx.ring + rd_curr;
2127
2128 if (!vptr->rx.info[rd_curr].skb)
2129 break;
2130
2131 if (rd->rdesc0.len & OWNED_BY_NIC)
2132 break;
2133
2134 rmb();
2135
2136
2137
2138
2139 if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
2140 if (velocity_receive_frame(vptr, rd_curr) < 0)
2141 stats->rx_dropped++;
2142 } else {
2143 if (rd->rdesc0.RSR & RSR_CRC)
2144 stats->rx_crc_errors++;
2145 if (rd->rdesc0.RSR & RSR_FAE)
2146 stats->rx_frame_errors++;
2147
2148 stats->rx_dropped++;
2149 }
2150
2151 rd->size |= RX_INTEN;
2152
2153 rd_curr++;
2154 if (rd_curr >= vptr->options.numrx)
2155 rd_curr = 0;
2156 works++;
2157 }
2158
2159 vptr->rx.curr = rd_curr;
2160
2161 if ((works > 0) && (velocity_rx_refill(vptr) > 0))
2162 velocity_give_many_rx_descs(vptr);
2163
2164 VAR_USED(stats);
2165 return works;
2166}
2167
2168static int velocity_poll(struct napi_struct *napi, int budget)
2169{
2170 struct velocity_info *vptr = container_of(napi,
2171 struct velocity_info, napi);
2172 unsigned int rx_done;
2173 unsigned long flags;
2174
2175 spin_lock_irqsave(&vptr->lock, flags);
2176
2177
2178
2179
2180 rx_done = velocity_rx_srv(vptr, budget / 2);
2181 velocity_tx_srv(vptr);
2182 rx_done += velocity_rx_srv(vptr, budget - rx_done);
2183 velocity_tx_srv(vptr);
2184
2185
2186 if (rx_done < budget) {
2187 napi_complete(napi);
2188 mac_enable_int(vptr->mac_regs);
2189 }
2190 spin_unlock_irqrestore(&vptr->lock, flags);
2191
2192 return rx_done;
2193}
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205static irqreturn_t velocity_intr(int irq, void *dev_instance)
2206{
2207 struct net_device *dev = dev_instance;
2208 struct velocity_info *vptr = netdev_priv(dev);
2209 u32 isr_status;
2210
2211 spin_lock(&vptr->lock);
2212 isr_status = mac_read_isr(vptr->mac_regs);
2213
2214
2215 if (isr_status == 0) {
2216 spin_unlock(&vptr->lock);
2217 return IRQ_NONE;
2218 }
2219
2220
2221 mac_write_isr(vptr->mac_regs, isr_status);
2222
2223 if (likely(napi_schedule_prep(&vptr->napi))) {
2224 mac_disable_int(vptr->mac_regs);
2225 __napi_schedule(&vptr->napi);
2226 }
2227
2228 if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2229 velocity_error(vptr, isr_status);
2230
2231 spin_unlock(&vptr->lock);
2232
2233 return IRQ_HANDLED;
2234}
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246static int velocity_open(struct net_device *dev)
2247{
2248 struct velocity_info *vptr = netdev_priv(dev);
2249 int ret;
2250
2251 ret = velocity_init_rings(vptr, dev->mtu);
2252 if (ret < 0)
2253 goto out;
2254
2255
2256 velocity_set_power_state(vptr, PCI_D0);
2257
2258 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2259
2260 ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
2261 dev->name, dev);
2262 if (ret < 0) {
2263
2264 velocity_set_power_state(vptr, PCI_D3hot);
2265 velocity_free_rings(vptr);
2266 goto out;
2267 }
2268
2269 velocity_give_many_rx_descs(vptr);
2270
2271 mac_enable_int(vptr->mac_regs);
2272 netif_start_queue(dev);
2273 napi_enable(&vptr->napi);
2274 vptr->flags |= VELOCITY_FLAGS_OPENED;
2275out:
2276 return ret;
2277}
2278
2279
2280
2281
2282
2283
2284
2285
2286static void velocity_shutdown(struct velocity_info *vptr)
2287{
2288 struct mac_regs __iomem *regs = vptr->mac_regs;
2289 mac_disable_int(regs);
2290 writel(CR0_STOP, ®s->CR0Set);
2291 writew(0xFFFF, ®s->TDCSRClr);
2292 writeb(0xFF, ®s->RDCSRClr);
2293 safe_disable_mii_autopoll(regs);
2294 mac_clear_isr(regs);
2295}
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2307{
2308 struct velocity_info *vptr = netdev_priv(dev);
2309 int ret = 0;
2310
2311 if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
2312 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
2313 vptr->netdev->name);
2314 ret = -EINVAL;
2315 goto out_0;
2316 }
2317
2318 if (!netif_running(dev)) {
2319 dev->mtu = new_mtu;
2320 goto out_0;
2321 }
2322
2323 if (dev->mtu != new_mtu) {
2324 struct velocity_info *tmp_vptr;
2325 unsigned long flags;
2326 struct rx_info rx;
2327 struct tx_info tx;
2328
2329 tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
2330 if (!tmp_vptr) {
2331 ret = -ENOMEM;
2332 goto out_0;
2333 }
2334
2335 tmp_vptr->netdev = dev;
2336 tmp_vptr->pdev = vptr->pdev;
2337 tmp_vptr->dev = vptr->dev;
2338 tmp_vptr->options = vptr->options;
2339 tmp_vptr->tx.numq = vptr->tx.numq;
2340
2341 ret = velocity_init_rings(tmp_vptr, new_mtu);
2342 if (ret < 0)
2343 goto out_free_tmp_vptr_1;
2344
2345 spin_lock_irqsave(&vptr->lock, flags);
2346
2347 netif_stop_queue(dev);
2348 velocity_shutdown(vptr);
2349
2350 rx = vptr->rx;
2351 tx = vptr->tx;
2352
2353 vptr->rx = tmp_vptr->rx;
2354 vptr->tx = tmp_vptr->tx;
2355
2356 tmp_vptr->rx = rx;
2357 tmp_vptr->tx = tx;
2358
2359 dev->mtu = new_mtu;
2360
2361 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2362
2363 velocity_give_many_rx_descs(vptr);
2364
2365 mac_enable_int(vptr->mac_regs);
2366 netif_start_queue(dev);
2367
2368 spin_unlock_irqrestore(&vptr->lock, flags);
2369
2370 velocity_free_rings(tmp_vptr);
2371
2372out_free_tmp_vptr_1:
2373 kfree(tmp_vptr);
2374 }
2375out_0:
2376 return ret;
2377}
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2390{
2391 struct velocity_info *vptr = netdev_priv(dev);
2392 struct mac_regs __iomem *regs = vptr->mac_regs;
2393 unsigned long flags;
2394 struct mii_ioctl_data *miidata = if_mii(ifr);
2395 int err;
2396
2397 switch (cmd) {
2398 case SIOCGMIIPHY:
2399 miidata->phy_id = readb(®s->MIIADR) & 0x1f;
2400 break;
2401 case SIOCGMIIREG:
2402 if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
2403 return -ETIMEDOUT;
2404 break;
2405 case SIOCSMIIREG:
2406 spin_lock_irqsave(&vptr->lock, flags);
2407 err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
2408 spin_unlock_irqrestore(&vptr->lock, flags);
2409 check_connection_type(vptr->mac_regs);
2410 if (err)
2411 return err;
2412 break;
2413 default:
2414 return -EOPNOTSUPP;
2415 }
2416 return 0;
2417}
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2429{
2430 struct velocity_info *vptr = netdev_priv(dev);
2431 int ret;
2432
2433
2434
2435
2436 if (!netif_running(dev))
2437 velocity_set_power_state(vptr, PCI_D0);
2438
2439 switch (cmd) {
2440 case SIOCGMIIPHY:
2441 case SIOCGMIIREG:
2442 case SIOCSMIIREG:
2443 ret = velocity_mii_ioctl(dev, rq, cmd);
2444 break;
2445
2446 default:
2447 ret = -EOPNOTSUPP;
2448 }
2449 if (!netif_running(dev))
2450 velocity_set_power_state(vptr, PCI_D3hot);
2451
2452
2453 return ret;
2454}
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2467{
2468 struct velocity_info *vptr = netdev_priv(dev);
2469
2470
2471 if (!netif_running(dev))
2472 return &dev->stats;
2473
2474 spin_lock_irq(&vptr->lock);
2475 velocity_update_hw_mibs(vptr);
2476 spin_unlock_irq(&vptr->lock);
2477
2478 dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2479 dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2480 dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2481
2482
2483 dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2484
2485
2486
2487 dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2488
2489
2490
2491
2492
2493
2494
2495 return &dev->stats;
2496}
2497
2498
2499
2500
2501
2502
2503
2504
2505static int velocity_close(struct net_device *dev)
2506{
2507 struct velocity_info *vptr = netdev_priv(dev);
2508
2509 napi_disable(&vptr->napi);
2510 netif_stop_queue(dev);
2511 velocity_shutdown(vptr);
2512
2513 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2514 velocity_get_ip(vptr);
2515
2516 free_irq(dev->irq, dev);
2517
2518 velocity_free_rings(vptr);
2519
2520 vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2521 return 0;
2522}
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532static netdev_tx_t velocity_xmit(struct sk_buff *skb,
2533 struct net_device *dev)
2534{
2535 struct velocity_info *vptr = netdev_priv(dev);
2536 int qnum = 0;
2537 struct tx_desc *td_ptr;
2538 struct velocity_td_info *tdinfo;
2539 unsigned long flags;
2540 int pktlen;
2541 int index, prev;
2542 int i = 0;
2543
2544 if (skb_padto(skb, ETH_ZLEN))
2545 goto out;
2546
2547
2548
2549 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
2550 kfree_skb(skb);
2551 return NETDEV_TX_OK;
2552 }
2553
2554 pktlen = skb_shinfo(skb)->nr_frags == 0 ?
2555 max_t(unsigned int, skb->len, ETH_ZLEN) :
2556 skb_headlen(skb);
2557
2558 spin_lock_irqsave(&vptr->lock, flags);
2559
2560 index = vptr->tx.curr[qnum];
2561 td_ptr = &(vptr->tx.rings[qnum][index]);
2562 tdinfo = &(vptr->tx.infos[qnum][index]);
2563
2564 td_ptr->tdesc1.TCR = TCR0_TIC;
2565 td_ptr->td_buf[0].size &= ~TD_QUEUE;
2566
2567
2568
2569
2570
2571 tdinfo->skb = skb;
2572 tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
2573 DMA_TO_DEVICE);
2574 td_ptr->tdesc0.len = cpu_to_le16(pktlen);
2575 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2576 td_ptr->td_buf[0].pa_high = 0;
2577 td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
2578
2579
2580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2581 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2582
2583 tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
2584 frag, 0,
2585 skb_frag_size(frag),
2586 DMA_TO_DEVICE);
2587
2588 td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
2589 td_ptr->td_buf[i + 1].pa_high = 0;
2590 td_ptr->td_buf[i + 1].size = cpu_to_le16(skb_frag_size(frag));
2591 }
2592 tdinfo->nskb_dma = i + 1;
2593
2594 td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
2595
2596 if (vlan_tx_tag_present(skb)) {
2597 td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2598 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2599 }
2600
2601
2602
2603
2604 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2605 const struct iphdr *ip = ip_hdr(skb);
2606 if (ip->protocol == IPPROTO_TCP)
2607 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2608 else if (ip->protocol == IPPROTO_UDP)
2609 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2610 td_ptr->tdesc1.TCR |= TCR0_IPCK;
2611 }
2612
2613 prev = index - 1;
2614 if (prev < 0)
2615 prev = vptr->options.numtx - 1;
2616 td_ptr->tdesc0.len |= OWNED_BY_NIC;
2617 vptr->tx.used[qnum]++;
2618 vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
2619
2620 if (AVAIL_TD(vptr, qnum) < 1)
2621 netif_stop_queue(dev);
2622
2623 td_ptr = &(vptr->tx.rings[qnum][prev]);
2624 td_ptr->td_buf[0].size |= TD_QUEUE;
2625 mac_tx_queue_wake(vptr->mac_regs, qnum);
2626
2627 spin_unlock_irqrestore(&vptr->lock, flags);
2628out:
2629 return NETDEV_TX_OK;
2630}
2631
2632static const struct net_device_ops velocity_netdev_ops = {
2633 .ndo_open = velocity_open,
2634 .ndo_stop = velocity_close,
2635 .ndo_start_xmit = velocity_xmit,
2636 .ndo_get_stats = velocity_get_stats,
2637 .ndo_validate_addr = eth_validate_addr,
2638 .ndo_set_mac_address = eth_mac_addr,
2639 .ndo_set_rx_mode = velocity_set_multi,
2640 .ndo_change_mtu = velocity_change_mtu,
2641 .ndo_do_ioctl = velocity_ioctl,
2642 .ndo_vlan_rx_add_vid = velocity_vlan_rx_add_vid,
2643 .ndo_vlan_rx_kill_vid = velocity_vlan_rx_kill_vid,
2644};
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655static void velocity_init_info(struct velocity_info *vptr,
2656 const struct velocity_info_tbl *info)
2657{
2658 vptr->chip_id = info->chip_id;
2659 vptr->tx.numq = info->txqueue;
2660 vptr->multicast_limit = MCAM_SIZE;
2661 spin_lock_init(&vptr->lock);
2662}
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672static int velocity_get_pci_info(struct velocity_info *vptr)
2673{
2674 struct pci_dev *pdev = vptr->pdev;
2675
2676 pci_set_master(pdev);
2677
2678 vptr->ioaddr = pci_resource_start(pdev, 0);
2679 vptr->memaddr = pci_resource_start(pdev, 1);
2680
2681 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2682 dev_err(&pdev->dev,
2683 "region #0 is not an I/O resource, aborting.\n");
2684 return -EINVAL;
2685 }
2686
2687 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
2688 dev_err(&pdev->dev,
2689 "region #1 is an I/O resource, aborting.\n");
2690 return -EINVAL;
2691 }
2692
2693 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
2694 dev_err(&pdev->dev, "region #1 is too small.\n");
2695 return -EINVAL;
2696 }
2697
2698 return 0;
2699}
2700
2701
2702
2703
2704
2705
2706
2707
2708static int velocity_get_platform_info(struct velocity_info *vptr)
2709{
2710 struct resource res;
2711 int ret;
2712
2713 if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
2714 vptr->no_eeprom = 1;
2715
2716 ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
2717 if (ret) {
2718 dev_err(vptr->dev, "unable to find memory address\n");
2719 return ret;
2720 }
2721
2722 vptr->memaddr = res.start;
2723
2724 if (resource_size(&res) < VELOCITY_IO_SIZE) {
2725 dev_err(vptr->dev, "memory region is too small.\n");
2726 return -EINVAL;
2727 }
2728
2729 return 0;
2730}
2731
2732
2733
2734
2735
2736
2737
2738
2739static void velocity_print_info(struct velocity_info *vptr)
2740{
2741 struct net_device *dev = vptr->netdev;
2742
2743 printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
2744 printk(KERN_INFO "%s: Ethernet Address: %pM\n",
2745 dev->name, dev->dev_addr);
2746}
2747
2748static u32 velocity_get_link(struct net_device *dev)
2749{
2750 struct velocity_info *vptr = netdev_priv(dev);
2751 struct mac_regs __iomem *regs = vptr->mac_regs;
2752 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, ®s->PHYSR0) ? 1 : 0;
2753}
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764static int velocity_probe(struct device *dev, int irq,
2765 const struct velocity_info_tbl *info,
2766 enum velocity_bus_type bustype)
2767{
2768 static int first = 1;
2769 struct net_device *netdev;
2770 int i;
2771 const char *drv_string;
2772 struct velocity_info *vptr;
2773 struct mac_regs __iomem *regs;
2774 int ret = -ENOMEM;
2775
2776
2777
2778
2779 if (velocity_nics >= MAX_UNITS) {
2780 dev_notice(dev, "already found %d NICs.\n", velocity_nics);
2781 return -ENODEV;
2782 }
2783
2784 netdev = alloc_etherdev(sizeof(struct velocity_info));
2785 if (!netdev)
2786 goto out;
2787
2788
2789
2790 SET_NETDEV_DEV(netdev, dev);
2791 vptr = netdev_priv(netdev);
2792
2793 if (first) {
2794 printk(KERN_INFO "%s Ver. %s\n",
2795 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
2796 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
2797 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
2798 first = 0;
2799 }
2800
2801 netdev->irq = irq;
2802 vptr->netdev = netdev;
2803 vptr->dev = dev;
2804
2805 velocity_init_info(vptr, info);
2806
2807 if (bustype == BUS_PCI) {
2808 vptr->pdev = to_pci_dev(dev);
2809
2810 ret = velocity_get_pci_info(vptr);
2811 if (ret < 0)
2812 goto err_free_dev;
2813 } else {
2814 vptr->pdev = NULL;
2815 ret = velocity_get_platform_info(vptr);
2816 if (ret < 0)
2817 goto err_free_dev;
2818 }
2819
2820 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
2821 if (regs == NULL) {
2822 ret = -EIO;
2823 goto err_free_dev;
2824 }
2825
2826 vptr->mac_regs = regs;
2827 vptr->rev_id = readb(®s->rev_id);
2828
2829 mac_wol_reset(regs);
2830
2831 for (i = 0; i < 6; i++)
2832 netdev->dev_addr[i] = readb(®s->PAR[i]);
2833
2834
2835 drv_string = dev_driver_string(dev);
2836
2837 velocity_get_options(&vptr->options, velocity_nics, drv_string);
2838
2839
2840
2841
2842
2843 vptr->options.flags &= info->flags;
2844
2845
2846
2847
2848
2849 vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
2850
2851 vptr->wol_opts = vptr->options.wol_opts;
2852 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
2853
2854 vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
2855
2856 netdev->netdev_ops = &velocity_netdev_ops;
2857 netdev->ethtool_ops = &velocity_ethtool_ops;
2858 netif_napi_add(netdev, &vptr->napi, velocity_poll,
2859 VELOCITY_NAPI_WEIGHT);
2860
2861 netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
2862 NETIF_F_HW_VLAN_CTAG_TX;
2863 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
2864 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
2865 NETIF_F_IP_CSUM;
2866
2867 ret = register_netdev(netdev);
2868 if (ret < 0)
2869 goto err_iounmap;
2870
2871 if (!velocity_get_link(netdev)) {
2872 netif_carrier_off(netdev);
2873 vptr->mii_status |= VELOCITY_LINK_FAIL;
2874 }
2875
2876 velocity_print_info(vptr);
2877 dev_set_drvdata(vptr->dev, netdev);
2878
2879
2880
2881 velocity_set_power_state(vptr, PCI_D3hot);
2882 velocity_nics++;
2883out:
2884 return ret;
2885
2886err_iounmap:
2887 netif_napi_del(&vptr->napi);
2888 iounmap(regs);
2889err_free_dev:
2890 free_netdev(netdev);
2891 goto out;
2892}
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902static int velocity_remove(struct device *dev)
2903{
2904 struct net_device *netdev = dev_get_drvdata(dev);
2905 struct velocity_info *vptr = netdev_priv(netdev);
2906
2907 unregister_netdev(netdev);
2908 netif_napi_del(&vptr->napi);
2909 iounmap(vptr->mac_regs);
2910 free_netdev(netdev);
2911 velocity_nics--;
2912
2913 return 0;
2914}
2915
2916static int velocity_pci_probe(struct pci_dev *pdev,
2917 const struct pci_device_id *ent)
2918{
2919 const struct velocity_info_tbl *info =
2920 &chip_info_table[ent->driver_data];
2921 int ret;
2922
2923 ret = pci_enable_device(pdev);
2924 if (ret < 0)
2925 return ret;
2926
2927 ret = pci_request_regions(pdev, VELOCITY_NAME);
2928 if (ret < 0) {
2929 dev_err(&pdev->dev, "No PCI resources.\n");
2930 goto fail1;
2931 }
2932
2933 ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
2934 if (ret == 0)
2935 return 0;
2936
2937 pci_release_regions(pdev);
2938fail1:
2939 pci_disable_device(pdev);
2940 return ret;
2941}
2942
2943static void velocity_pci_remove(struct pci_dev *pdev)
2944{
2945 velocity_remove(&pdev->dev);
2946
2947 pci_release_regions(pdev);
2948 pci_disable_device(pdev);
2949}
2950
2951static int velocity_platform_probe(struct platform_device *pdev)
2952{
2953 const struct of_device_id *of_id;
2954 const struct velocity_info_tbl *info;
2955 int irq;
2956
2957 of_id = of_match_device(velocity_of_ids, &pdev->dev);
2958 if (!of_id)
2959 return -EINVAL;
2960 info = of_id->data;
2961
2962 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
2963 if (!irq)
2964 return -EINVAL;
2965
2966 return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
2967}
2968
2969static int velocity_platform_remove(struct platform_device *pdev)
2970{
2971 velocity_remove(&pdev->dev);
2972
2973 return 0;
2974}
2975
2976#ifdef CONFIG_PM_SLEEP
2977
2978
2979
2980
2981
2982
2983
2984
2985static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
2986{
2987 u16 crc = 0xFFFF;
2988 u8 mask;
2989 int i, j;
2990
2991 for (i = 0; i < size; i++) {
2992 mask = mask_pattern[i];
2993
2994
2995 if (mask == 0x00)
2996 continue;
2997
2998 for (j = 0; j < 8; j++) {
2999 if ((mask & 0x01) == 0) {
3000 mask >>= 1;
3001 continue;
3002 }
3003 mask >>= 1;
3004 crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
3005 }
3006 }
3007
3008 crc = ~crc;
3009 return bitrev32(crc) >> 16;
3010}
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021static int velocity_set_wol(struct velocity_info *vptr)
3022{
3023 struct mac_regs __iomem *regs = vptr->mac_regs;
3024 enum speed_opt spd_dpx = vptr->options.spd_dpx;
3025 static u8 buf[256];
3026 int i;
3027
3028 static u32 mask_pattern[2][4] = {
3029 {0x00203000, 0x000003C0, 0x00000000, 0x0000000},
3030 {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}
3031 };
3032
3033 writew(0xFFFF, ®s->WOLCRClr);
3034 writeb(WOLCFG_SAB | WOLCFG_SAM, ®s->WOLCFGSet);
3035 writew(WOLCR_MAGIC_EN, ®s->WOLCRSet);
3036
3037
3038
3039
3040
3041
3042 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3043 writew(WOLCR_UNICAST_EN, ®s->WOLCRSet);
3044
3045 if (vptr->wol_opts & VELOCITY_WOL_ARP) {
3046 struct arp_packet *arp = (struct arp_packet *) buf;
3047 u16 crc;
3048 memset(buf, 0, sizeof(struct arp_packet) + 7);
3049
3050 for (i = 0; i < 4; i++)
3051 writel(mask_pattern[0][i], ®s->ByteMask[0][i]);
3052
3053 arp->type = htons(ETH_P_ARP);
3054 arp->ar_op = htons(1);
3055
3056 memcpy(arp->ar_tip, vptr->ip_addr, 4);
3057
3058 crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
3059 (u8 *) & mask_pattern[0][0]);
3060
3061 writew(crc, ®s->PatternCRC[0]);
3062 writew(WOLCR_ARP_EN, ®s->WOLCRSet);
3063 }
3064
3065 BYTE_REG_BITS_ON(PWCFG_WOLTYPE, ®s->PWCFGSet);
3066 BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, ®s->PWCFGSet);
3067
3068 writew(0x0FFF, ®s->WOLSRClr);
3069
3070 if (spd_dpx == SPD_DPX_1000_FULL)
3071 goto mac_done;
3072
3073 if (spd_dpx != SPD_DPX_AUTO)
3074 goto advertise_done;
3075
3076 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
3077 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
3078 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
3079
3080 MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
3081 }
3082
3083 if (vptr->mii_status & VELOCITY_SPEED_1000)
3084 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
3085
3086advertise_done:
3087 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
3088
3089 {
3090 u8 GCR;
3091 GCR = readb(®s->CHIPGCR);
3092 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
3093 writeb(GCR, ®s->CHIPGCR);
3094 }
3095
3096mac_done:
3097 BYTE_REG_BITS_OFF(ISR_PWEI, ®s->ISR);
3098
3099 BYTE_REG_BITS_ON(STICKHW_SWPTAG, ®s->STICKHW);
3100
3101 BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
3102
3103 return 0;
3104}
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
3117{
3118 struct mac_regs __iomem *regs = vptr->mac_regs;
3119 u16 i;
3120 u8 __iomem *ptr = (u8 __iomem *)regs;
3121
3122 for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
3123 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3124
3125 for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
3126 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3127
3128 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3129 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3130
3131}
3132
3133static int velocity_suspend(struct device *dev)
3134{
3135 struct net_device *netdev = dev_get_drvdata(dev);
3136 struct velocity_info *vptr = netdev_priv(netdev);
3137 unsigned long flags;
3138
3139 if (!netif_running(vptr->netdev))
3140 return 0;
3141
3142 netif_device_detach(vptr->netdev);
3143
3144 spin_lock_irqsave(&vptr->lock, flags);
3145 if (vptr->pdev)
3146 pci_save_state(vptr->pdev);
3147
3148 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
3149 velocity_get_ip(vptr);
3150 velocity_save_context(vptr, &vptr->context);
3151 velocity_shutdown(vptr);
3152 velocity_set_wol(vptr);
3153 if (vptr->pdev)
3154 pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
3155 velocity_set_power_state(vptr, PCI_D3hot);
3156 } else {
3157 velocity_save_context(vptr, &vptr->context);
3158 velocity_shutdown(vptr);
3159 if (vptr->pdev)
3160 pci_disable_device(vptr->pdev);
3161 velocity_set_power_state(vptr, PCI_D3hot);
3162 }
3163
3164 spin_unlock_irqrestore(&vptr->lock, flags);
3165 return 0;
3166}
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
3177{
3178 struct mac_regs __iomem *regs = vptr->mac_regs;
3179 int i;
3180 u8 __iomem *ptr = (u8 __iomem *)regs;
3181
3182 for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
3183 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3184
3185
3186 for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3187
3188 writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3189
3190 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3191 }
3192
3193 for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
3194 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3195
3196 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3197 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3198
3199 for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
3200 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3201}
3202
3203static int velocity_resume(struct device *dev)
3204{
3205 struct net_device *netdev = dev_get_drvdata(dev);
3206 struct velocity_info *vptr = netdev_priv(netdev);
3207 unsigned long flags;
3208 int i;
3209
3210 if (!netif_running(vptr->netdev))
3211 return 0;
3212
3213 velocity_set_power_state(vptr, PCI_D0);
3214
3215 if (vptr->pdev) {
3216 pci_enable_wake(vptr->pdev, PCI_D0, 0);
3217 pci_restore_state(vptr->pdev);
3218 }
3219
3220 mac_wol_reset(vptr->mac_regs);
3221
3222 spin_lock_irqsave(&vptr->lock, flags);
3223 velocity_restore_context(vptr, &vptr->context);
3224 velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3225 mac_disable_int(vptr->mac_regs);
3226
3227 velocity_tx_srv(vptr);
3228
3229 for (i = 0; i < vptr->tx.numq; i++) {
3230 if (vptr->tx.used[i])
3231 mac_tx_queue_wake(vptr->mac_regs, i);
3232 }
3233
3234 mac_enable_int(vptr->mac_regs);
3235 spin_unlock_irqrestore(&vptr->lock, flags);
3236 netif_device_attach(vptr->netdev);
3237
3238 return 0;
3239}
3240#endif
3241
3242static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
3243
3244
3245
3246
3247
3248static struct pci_driver velocity_pci_driver = {
3249 .name = VELOCITY_NAME,
3250 .id_table = velocity_pci_id_table,
3251 .probe = velocity_pci_probe,
3252 .remove = velocity_pci_remove,
3253 .driver = {
3254 .pm = &velocity_pm_ops,
3255 },
3256};
3257
3258static struct platform_driver velocity_platform_driver = {
3259 .probe = velocity_platform_probe,
3260 .remove = velocity_platform_remove,
3261 .driver = {
3262 .name = "via-velocity",
3263 .owner = THIS_MODULE,
3264 .of_match_table = velocity_of_ids,
3265 .pm = &velocity_pm_ops,
3266 },
3267};
3268
3269
3270
3271
3272
3273
3274
3275
3276static int velocity_ethtool_up(struct net_device *dev)
3277{
3278 struct velocity_info *vptr = netdev_priv(dev);
3279 if (!netif_running(dev))
3280 velocity_set_power_state(vptr, PCI_D0);
3281 return 0;
3282}
3283
3284
3285
3286
3287
3288
3289
3290
3291static void velocity_ethtool_down(struct net_device *dev)
3292{
3293 struct velocity_info *vptr = netdev_priv(dev);
3294 if (!netif_running(dev))
3295 velocity_set_power_state(vptr, PCI_D3hot);
3296}
3297
3298static int velocity_get_settings(struct net_device *dev,
3299 struct ethtool_cmd *cmd)
3300{
3301 struct velocity_info *vptr = netdev_priv(dev);
3302 struct mac_regs __iomem *regs = vptr->mac_regs;
3303 u32 status;
3304 status = check_connection_type(vptr->mac_regs);
3305
3306 cmd->supported = SUPPORTED_TP |
3307 SUPPORTED_Autoneg |
3308 SUPPORTED_10baseT_Half |
3309 SUPPORTED_10baseT_Full |
3310 SUPPORTED_100baseT_Half |
3311 SUPPORTED_100baseT_Full |
3312 SUPPORTED_1000baseT_Half |
3313 SUPPORTED_1000baseT_Full;
3314
3315 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
3316 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
3317 cmd->advertising |=
3318 ADVERTISED_10baseT_Half |
3319 ADVERTISED_10baseT_Full |
3320 ADVERTISED_100baseT_Half |
3321 ADVERTISED_100baseT_Full |
3322 ADVERTISED_1000baseT_Half |
3323 ADVERTISED_1000baseT_Full;
3324 } else {
3325 switch (vptr->options.spd_dpx) {
3326 case SPD_DPX_1000_FULL:
3327 cmd->advertising |= ADVERTISED_1000baseT_Full;
3328 break;
3329 case SPD_DPX_100_HALF:
3330 cmd->advertising |= ADVERTISED_100baseT_Half;
3331 break;
3332 case SPD_DPX_100_FULL:
3333 cmd->advertising |= ADVERTISED_100baseT_Full;
3334 break;
3335 case SPD_DPX_10_HALF:
3336 cmd->advertising |= ADVERTISED_10baseT_Half;
3337 break;
3338 case SPD_DPX_10_FULL:
3339 cmd->advertising |= ADVERTISED_10baseT_Full;
3340 break;
3341 default:
3342 break;
3343 }
3344 }
3345
3346 if (status & VELOCITY_SPEED_1000)
3347 ethtool_cmd_speed_set(cmd, SPEED_1000);
3348 else if (status & VELOCITY_SPEED_100)
3349 ethtool_cmd_speed_set(cmd, SPEED_100);
3350 else
3351 ethtool_cmd_speed_set(cmd, SPEED_10);
3352
3353 cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3354 cmd->port = PORT_TP;
3355 cmd->transceiver = XCVR_INTERNAL;
3356 cmd->phy_address = readb(®s->MIIADR) & 0x1F;
3357
3358 if (status & VELOCITY_DUPLEX_FULL)
3359 cmd->duplex = DUPLEX_FULL;
3360 else
3361 cmd->duplex = DUPLEX_HALF;
3362
3363 return 0;
3364}
3365
3366static int velocity_set_settings(struct net_device *dev,
3367 struct ethtool_cmd *cmd)
3368{
3369 struct velocity_info *vptr = netdev_priv(dev);
3370 u32 speed = ethtool_cmd_speed(cmd);
3371 u32 curr_status;
3372 u32 new_status = 0;
3373 int ret = 0;
3374
3375 curr_status = check_connection_type(vptr->mac_regs);
3376 curr_status &= (~VELOCITY_LINK_FAIL);
3377
3378 new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3379 new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
3380 new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3381 new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3382 new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
3383
3384 if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
3385 (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
3386 ret = -EINVAL;
3387 } else {
3388 enum speed_opt spd_dpx;
3389
3390 if (new_status & VELOCITY_AUTONEG_ENABLE)
3391 spd_dpx = SPD_DPX_AUTO;
3392 else if ((new_status & VELOCITY_SPEED_1000) &&
3393 (new_status & VELOCITY_DUPLEX_FULL)) {
3394 spd_dpx = SPD_DPX_1000_FULL;
3395 } else if (new_status & VELOCITY_SPEED_100)
3396 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3397 SPD_DPX_100_FULL : SPD_DPX_100_HALF;
3398 else if (new_status & VELOCITY_SPEED_10)
3399 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3400 SPD_DPX_10_FULL : SPD_DPX_10_HALF;
3401 else
3402 return -EOPNOTSUPP;
3403
3404 vptr->options.spd_dpx = spd_dpx;
3405
3406 velocity_set_media_mode(vptr, new_status);
3407 }
3408
3409 return ret;
3410}
3411
3412static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3413{
3414 struct velocity_info *vptr = netdev_priv(dev);
3415
3416 strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
3417 strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
3418 if (vptr->pdev)
3419 strlcpy(info->bus_info, pci_name(vptr->pdev),
3420 sizeof(info->bus_info));
3421 else
3422 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
3423}
3424
3425static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3426{
3427 struct velocity_info *vptr = netdev_priv(dev);
3428 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3429 wol->wolopts |= WAKE_MAGIC;
3430
3431
3432
3433
3434 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3435 wol->wolopts |= WAKE_UCAST;
3436 if (vptr->wol_opts & VELOCITY_WOL_ARP)
3437 wol->wolopts |= WAKE_ARP;
3438 memcpy(&wol->sopass, vptr->wol_passwd, 6);
3439}
3440
3441static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3442{
3443 struct velocity_info *vptr = netdev_priv(dev);
3444
3445 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3446 return -EFAULT;
3447 vptr->wol_opts = VELOCITY_WOL_MAGIC;
3448
3449
3450
3451
3452
3453
3454
3455
3456 if (wol->wolopts & WAKE_MAGIC) {
3457 vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3458 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3459 }
3460 if (wol->wolopts & WAKE_UCAST) {
3461 vptr->wol_opts |= VELOCITY_WOL_UCAST;
3462 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3463 }
3464 if (wol->wolopts & WAKE_ARP) {
3465 vptr->wol_opts |= VELOCITY_WOL_ARP;
3466 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3467 }
3468 memcpy(vptr->wol_passwd, wol->sopass, 6);
3469 return 0;
3470}
3471
3472static u32 velocity_get_msglevel(struct net_device *dev)
3473{
3474 return msglevel;
3475}
3476
3477static void velocity_set_msglevel(struct net_device *dev, u32 value)
3478{
3479 msglevel = value;
3480}
3481
3482static int get_pending_timer_val(int val)
3483{
3484 int mult_bits = val >> 6;
3485 int mult = 1;
3486
3487 switch (mult_bits)
3488 {
3489 case 1:
3490 mult = 4; break;
3491 case 2:
3492 mult = 16; break;
3493 case 3:
3494 mult = 64; break;
3495 case 0:
3496 default:
3497 break;
3498 }
3499
3500 return (val & 0x3f) * mult;
3501}
3502
3503static void set_pending_timer_val(int *val, u32 us)
3504{
3505 u8 mult = 0;
3506 u8 shift = 0;
3507
3508 if (us >= 0x3f) {
3509 mult = 1;
3510 shift = 2;
3511 }
3512 if (us >= 0x3f * 4) {
3513 mult = 2;
3514 shift = 4;
3515 }
3516 if (us >= 0x3f * 16) {
3517 mult = 3;
3518 shift = 6;
3519 }
3520
3521 *val = (mult << 6) | ((us >> shift) & 0x3f);
3522}
3523
3524
3525static int velocity_get_coalesce(struct net_device *dev,
3526 struct ethtool_coalesce *ecmd)
3527{
3528 struct velocity_info *vptr = netdev_priv(dev);
3529
3530 ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
3531 ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
3532
3533 ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
3534 ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
3535
3536 return 0;
3537}
3538
3539static int velocity_set_coalesce(struct net_device *dev,
3540 struct ethtool_coalesce *ecmd)
3541{
3542 struct velocity_info *vptr = netdev_priv(dev);
3543 int max_us = 0x3f * 64;
3544 unsigned long flags;
3545
3546
3547 if (ecmd->tx_coalesce_usecs > max_us)
3548 return -EINVAL;
3549 if (ecmd->rx_coalesce_usecs > max_us)
3550 return -EINVAL;
3551
3552 if (ecmd->tx_max_coalesced_frames > 0xff)
3553 return -EINVAL;
3554 if (ecmd->rx_max_coalesced_frames > 0xff)
3555 return -EINVAL;
3556
3557 vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
3558 vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
3559
3560 set_pending_timer_val(&vptr->options.rxqueue_timer,
3561 ecmd->rx_coalesce_usecs);
3562 set_pending_timer_val(&vptr->options.txqueue_timer,
3563 ecmd->tx_coalesce_usecs);
3564
3565
3566 spin_lock_irqsave(&vptr->lock, flags);
3567 mac_disable_int(vptr->mac_regs);
3568 setup_adaptive_interrupts(vptr);
3569 setup_queue_timers(vptr);
3570
3571 mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
3572 mac_clear_isr(vptr->mac_regs);
3573 mac_enable_int(vptr->mac_regs);
3574 spin_unlock_irqrestore(&vptr->lock, flags);
3575
3576 return 0;
3577}
3578
3579static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
3580 "rx_all",
3581 "rx_ok",
3582 "tx_ok",
3583 "rx_error",
3584 "rx_runt_ok",
3585 "rx_runt_err",
3586 "rx_64",
3587 "tx_64",
3588 "rx_65_to_127",
3589 "tx_65_to_127",
3590 "rx_128_to_255",
3591 "tx_128_to_255",
3592 "rx_256_to_511",
3593 "tx_256_to_511",
3594 "rx_512_to_1023",
3595 "tx_512_to_1023",
3596 "rx_1024_to_1518",
3597 "tx_1024_to_1518",
3598 "tx_ether_collisions",
3599 "rx_crc_errors",
3600 "rx_jumbo",
3601 "tx_jumbo",
3602 "rx_mac_control_frames",
3603 "tx_mac_control_frames",
3604 "rx_frame_alignement_errors",
3605 "rx_long_ok",
3606 "rx_long_err",
3607 "tx_sqe_errors",
3608 "rx_no_buf",
3609 "rx_symbol_errors",
3610 "in_range_length_errors",
3611 "late_collisions"
3612};
3613
3614static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
3615{
3616 switch (sset) {
3617 case ETH_SS_STATS:
3618 memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
3619 break;
3620 }
3621}
3622
3623static int velocity_get_sset_count(struct net_device *dev, int sset)
3624{
3625 switch (sset) {
3626 case ETH_SS_STATS:
3627 return ARRAY_SIZE(velocity_gstrings);
3628 default:
3629 return -EOPNOTSUPP;
3630 }
3631}
3632
3633static void velocity_get_ethtool_stats(struct net_device *dev,
3634 struct ethtool_stats *stats, u64 *data)
3635{
3636 if (netif_running(dev)) {
3637 struct velocity_info *vptr = netdev_priv(dev);
3638 u32 *p = vptr->mib_counter;
3639 int i;
3640
3641 spin_lock_irq(&vptr->lock);
3642 velocity_update_hw_mibs(vptr);
3643 spin_unlock_irq(&vptr->lock);
3644
3645 for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
3646 *data++ = *p++;
3647 }
3648}
3649
3650static const struct ethtool_ops velocity_ethtool_ops = {
3651 .get_settings = velocity_get_settings,
3652 .set_settings = velocity_set_settings,
3653 .get_drvinfo = velocity_get_drvinfo,
3654 .get_wol = velocity_ethtool_get_wol,
3655 .set_wol = velocity_ethtool_set_wol,
3656 .get_msglevel = velocity_get_msglevel,
3657 .set_msglevel = velocity_set_msglevel,
3658 .get_link = velocity_get_link,
3659 .get_strings = velocity_get_strings,
3660 .get_sset_count = velocity_get_sset_count,
3661 .get_ethtool_stats = velocity_get_ethtool_stats,
3662 .get_coalesce = velocity_get_coalesce,
3663 .set_coalesce = velocity_set_coalesce,
3664 .begin = velocity_ethtool_up,
3665 .complete = velocity_ethtool_down
3666};
3667
3668#if defined(CONFIG_PM) && defined(CONFIG_INET)
3669static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3670{
3671 struct in_ifaddr *ifa = ptr;
3672 struct net_device *dev = ifa->ifa_dev->dev;
3673
3674 if (dev_net(dev) == &init_net &&
3675 dev->netdev_ops == &velocity_netdev_ops)
3676 velocity_get_ip(netdev_priv(dev));
3677
3678 return NOTIFY_DONE;
3679}
3680
3681static struct notifier_block velocity_inetaddr_notifier = {
3682 .notifier_call = velocity_netdev_event,
3683};
3684
3685static void velocity_register_notifier(void)
3686{
3687 register_inetaddr_notifier(&velocity_inetaddr_notifier);
3688}
3689
3690static void velocity_unregister_notifier(void)
3691{
3692 unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
3693}
3694
3695#else
3696
3697#define velocity_register_notifier() do {} while (0)
3698#define velocity_unregister_notifier() do {} while (0)
3699
3700#endif
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710static int __init velocity_init_module(void)
3711{
3712 int ret_pci, ret_platform;
3713
3714 velocity_register_notifier();
3715
3716 ret_pci = pci_register_driver(&velocity_pci_driver);
3717 ret_platform = platform_driver_register(&velocity_platform_driver);
3718
3719
3720 if ((ret_pci < 0) && (ret_platform < 0)) {
3721 velocity_unregister_notifier();
3722 return ret_pci;
3723 }
3724
3725 return 0;
3726}
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736static void __exit velocity_cleanup_module(void)
3737{
3738 velocity_unregister_notifier();
3739
3740 pci_unregister_driver(&velocity_pci_driver);
3741 platform_driver_unregister(&velocity_platform_driver);
3742}
3743
3744module_init(velocity_init_module);
3745module_exit(velocity_cleanup_module);
3746