LXR linux/drivers/net/ethernet/xilinx/ll

   1
   2#ifndef XILINX_LL_TEMAC_H
   3#define XILINX_LL_TEMAC_H
   4
   5#include <linux/netdevice.h>
   6#include <linux/of.h>
   7#include <linux/spinlock.h>
   8
   9#ifdef CONFIG_PPC_DCR
  10#include <asm/dcr.h>
  11#include <asm/dcr-regs.h>
  12#endif
  13
  14/* packet size info */
  15#define XTE_HDR_SIZE                    14      /* size of Ethernet header */
  16#define XTE_TRL_SIZE                    4       /* size of Ethernet trailer (FCS) */
  17#define XTE_JUMBO_MTU                   9000
  18#define XTE_MAX_JUMBO_FRAME_SIZE        (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
  19
  20/*  Configuration options */
  21
  22/*  Accept all incoming packets.
  23 *  This option defaults to disabled (cleared) */
  24#define XTE_OPTION_PROMISC                      (1 << 0)
  25/*  Jumbo frame support for Tx & Rx.
  26 *  This option defaults to disabled (cleared) */
  27#define XTE_OPTION_JUMBO                        (1 << 1)
  28/*  VLAN Rx & Tx frame support.
  29 *  This option defaults to disabled (cleared) */
  30#define XTE_OPTION_VLAN                         (1 << 2)
  31/*  Enable recognition of flow control frames on Rx
  32 *  This option defaults to enabled (set) */
  33#define XTE_OPTION_FLOW_CONTROL                 (1 << 4)
  34/*  Strip FCS and PAD from incoming frames.
  35 *  Note: PAD from VLAN frames is not stripped.
  36 *  This option defaults to disabled (set) */
  37#define XTE_OPTION_FCS_STRIP                    (1 << 5)
  38/*  Generate FCS field and add PAD automatically for outgoing frames.
  39 *  This option defaults to enabled (set) */
  40#define XTE_OPTION_FCS_INSERT                   (1 << 6)
  41/*  Enable Length/Type error checking for incoming frames. When this option is
  42set, the MAC will filter frames that have a mismatched type/length field
  43and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
  44types of frames are encountered. When this option is cleared, the MAC will
  45allow these types of frames to be received.
  46This option defaults to enabled (set) */
  47#define XTE_OPTION_LENTYPE_ERR                  (1 << 7)
  48/*  Enable the transmitter.
  49 *  This option defaults to enabled (set) */
  50#define XTE_OPTION_TXEN                         (1 << 11)
  51/*  Enable the receiver
  52*   This option defaults to enabled (set) */
  53#define XTE_OPTION_RXEN                         (1 << 12)
  54
  55/*  Default options set when device is initialized or reset */
  56#define XTE_OPTION_DEFAULTS                     \
  57        (XTE_OPTION_TXEN |                          \
  58         XTE_OPTION_FLOW_CONTROL |                  \
  59         XTE_OPTION_RXEN)
  60
  61/* XPS_LL_TEMAC SDMA registers definition */
  62
  63#define TX_NXTDESC_PTR      0x00            /* r */
  64#define TX_CURBUF_ADDR      0x01            /* r */
  65#define TX_CURBUF_LENGTH    0x02            /* r */
  66#define TX_CURDESC_PTR      0x03            /* rw */
  67#define TX_TAILDESC_PTR     0x04            /* rw */
  68#define TX_CHNL_CTRL        0x05            /* rw */
  69/*
  70 0:7      24:31       IRQTimeout
  71 8:15     16:23       IRQCount
  72 16:20    11:15       Reserved
  73 21       10          0
  74 22       9           UseIntOnEnd
  75 23       8           LdIRQCnt
  76 24       7           IRQEn
  77 25:28    3:6         Reserved
  78 29       2           IrqErrEn
  79 30       1           IrqDlyEn
  80 31       0           IrqCoalEn
  81*/
  82#define CHNL_CTRL_IRQ_IOE       (1 << 9)
  83#define CHNL_CTRL_IRQ_EN        (1 << 7)
  84#define CHNL_CTRL_IRQ_ERR_EN    (1 << 2)
  85#define CHNL_CTRL_IRQ_DLY_EN    (1 << 1)
  86#define CHNL_CTRL_IRQ_COAL_EN   (1 << 0)
  87#define TX_IRQ_REG          0x06            /* rw */
  88/*
  89  0:7      24:31       DltTmrValue
  90 8:15     16:23       ClscCntrValue
  91 16:17    14:15       Reserved
  92 18:21    10:13       ClscCnt
  93 22:23    8:9         DlyCnt
  94 24:28    3::7        Reserved
  95 29       2           ErrIrq
  96 30       1           DlyIrq
  97 31       0           CoalIrq
  98 */
  99#define TX_CHNL_STS         0x07            /* r */
 100/*
 101   0:9      22:31   Reserved
 102 10       21      TailPErr
 103 11       20      CmpErr
 104 12       19      AddrErr
 105 13       18      NxtPErr
 106 14       17      CurPErr
 107 15       16      BsyWr
 108 16:23    8:15    Reserved
 109 24       7       Error
 110 25       6       IOE
 111 26       5       SOE
 112 27       4       Cmplt
 113 28       3       SOP
 114 29       2       EOP
 115 30       1       EngBusy
 116 31       0       Reserved
 117*/
 118
 119#define RX_NXTDESC_PTR      0x08            /* r */
 120#define RX_CURBUF_ADDR      0x09            /* r */
 121#define RX_CURBUF_LENGTH    0x0a            /* r */
 122#define RX_CURDESC_PTR      0x0b            /* rw */
 123#define RX_TAILDESC_PTR     0x0c            /* rw */
 124#define RX_CHNL_CTRL        0x0d            /* rw */
 125/*
 126 0:7      24:31       IRQTimeout
 127 8:15     16:23       IRQCount
 128 16:20    11:15       Reserved
 129 21       10          0
 130 22       9           UseIntOnEnd
 131 23       8           LdIRQCnt
 132 24       7           IRQEn
 133 25:28    3:6         Reserved
 134 29       2           IrqErrEn
 135 30       1           IrqDlyEn
 136 31       0           IrqCoalEn
 137 */
 138#define RX_IRQ_REG          0x0e            /* rw */
 139#define IRQ_COAL        (1 << 0)
 140#define IRQ_DLY         (1 << 1)
 141#define IRQ_ERR         (1 << 2)
 142#define IRQ_DMAERR      (1 << 7)            /* this is not documented ??? */
 143/*
 144 0:7      24:31       DltTmrValue
 145 8:15     16:23       ClscCntrValue
 146 16:17    14:15       Reserved
 147 18:21    10:13       ClscCnt
 148 22:23    8:9         DlyCnt
 149 24:28    3::7        Reserved
 150*/
 151#define RX_CHNL_STS         0x0f        /* r */
 152#define CHNL_STS_ENGBUSY    (1 << 1)
 153#define CHNL_STS_EOP        (1 << 2)
 154#define CHNL_STS_SOP        (1 << 3)
 155#define CHNL_STS_CMPLT      (1 << 4)
 156#define CHNL_STS_SOE        (1 << 5)
 157#define CHNL_STS_IOE        (1 << 6)
 158#define CHNL_STS_ERR        (1 << 7)
 159
 160#define CHNL_STS_BSYWR      (1 << 16)
 161#define CHNL_STS_CURPERR    (1 << 17)
 162#define CHNL_STS_NXTPERR    (1 << 18)
 163#define CHNL_STS_ADDRERR    (1 << 19)
 164#define CHNL_STS_CMPERR     (1 << 20)
 165#define CHNL_STS_TAILERR    (1 << 21)
 166/*
 167 0:9      22:31   Reserved
 168 10       21      TailPErr
 169 11       20      CmpErr
 170 12       19      AddrErr
 171 13       18      NxtPErr
 172 14       17      CurPErr
 173 15       16      BsyWr
 174 16:23    8:15    Reserved
 175 24       7       Error
 176 25       6       IOE
 177 26       5       SOE
 178 27       4       Cmplt
 179 28       3       SOP
 180 29       2       EOP
 181 30       1       EngBusy
 182 31       0       Reserved
 183*/
 184
 185#define DMA_CONTROL_REG             0x10            /* rw */
 186#define DMA_CONTROL_RST                 (1 << 0)
 187#define DMA_TAIL_ENABLE                 (1 << 2)
 188
 189/* XPS_LL_TEMAC direct registers definition */
 190
 191#define XTE_RAF0_OFFSET              0x00
 192#define RAF0_RST                        (1 << 0)
 193#define RAF0_MCSTREJ                    (1 << 1)
 194#define RAF0_BCSTREJ                    (1 << 2)
 195#define XTE_TPF0_OFFSET              0x04
 196#define XTE_IFGP0_OFFSET             0x08
 197#define XTE_ISR0_OFFSET              0x0c
 198#define ISR0_HARDACSCMPLT               (1 << 0)
 199#define ISR0_AUTONEG                    (1 << 1)
 200#define ISR0_RXCMPLT                    (1 << 2)
 201#define ISR0_RXREJ                      (1 << 3)
 202#define ISR0_RXFIFOOVR                  (1 << 4)
 203#define ISR0_TXCMPLT                    (1 << 5)
 204#define ISR0_RXDCMLCK                   (1 << 6)
 205
 206#define XTE_IPR0_OFFSET              0x10
 207#define XTE_IER0_OFFSET              0x14
 208
 209#define XTE_MSW0_OFFSET              0x20
 210#define XTE_LSW0_OFFSET              0x24
 211#define XTE_CTL0_OFFSET              0x28
 212#define XTE_RDY0_OFFSET              0x2c
 213
 214#define XTE_RSE_MIIM_RR_MASK      0x0002
 215#define XTE_RSE_MIIM_WR_MASK      0x0004
 216#define XTE_RSE_CFG_RR_MASK       0x0020
 217#define XTE_RSE_CFG_WR_MASK       0x0040
 218#define XTE_RDY0_HARD_ACS_RDY_MASK  (0x10000)
 219
 220/* XPS_LL_TEMAC indirect registers offset definition */
 221
 222#define XTE_RXC0_OFFSET                 0x00000200 /* Rx configuration word 0 */
 223#define XTE_RXC1_OFFSET                 0x00000240 /* Rx configuration word 1 */
 224#define XTE_RXC1_RXRST_MASK             (1 << 31)  /* Receiver reset */
 225#define XTE_RXC1_RXJMBO_MASK            (1 << 30)  /* Jumbo frame enable */
 226#define XTE_RXC1_RXFCS_MASK             (1 << 29)  /* FCS not stripped */
 227#define XTE_RXC1_RXEN_MASK              (1 << 28)  /* Receiver enable */
 228#define XTE_RXC1_RXVLAN_MASK            (1 << 27)  /* VLAN enable */
 229#define XTE_RXC1_RXHD_MASK              (1 << 26)  /* Half duplex */
 230#define XTE_RXC1_RXLT_MASK              (1 << 25)  /* Length/type check disable */
 231
 232#define XTE_TXC_OFFSET                  0x00000280 /*  Tx configuration */
 233#define XTE_TXC_TXRST_MASK              (1 << 31)  /* Transmitter reset */
 234#define XTE_TXC_TXJMBO_MASK             (1 << 30)  /* Jumbo frame enable */
 235#define XTE_TXC_TXFCS_MASK              (1 << 29)  /* Generate FCS */
 236#define XTE_TXC_TXEN_MASK               (1 << 28)  /* Transmitter enable */
 237#define XTE_TXC_TXVLAN_MASK             (1 << 27)  /* VLAN enable */
 238#define XTE_TXC_TXHD_MASK               (1 << 26)  /* Half duplex */
 239
 240#define XTE_FCC_OFFSET                  0x000002C0 /* Flow control config */
 241#define XTE_FCC_RXFLO_MASK              (1 << 29)  /* Rx flow control enable */
 242#define XTE_FCC_TXFLO_MASK              (1 << 30)  /* Tx flow control enable */
 243
 244#define XTE_EMCFG_OFFSET                0x00000300 /* EMAC configuration */
 245#define XTE_EMCFG_LINKSPD_MASK          0xC0000000 /* Link speed */
 246#define XTE_EMCFG_HOSTEN_MASK           (1 << 26)  /* Host interface enable */
 247#define XTE_EMCFG_LINKSPD_10            0x00000000 /* 10 Mbit LINKSPD_MASK */
 248#define XTE_EMCFG_LINKSPD_100           (1 << 30)  /* 100 Mbit LINKSPD_MASK */
 249#define XTE_EMCFG_LINKSPD_1000          (1 << 31)  /* 1000 Mbit LINKSPD_MASK */
 250
 251#define XTE_GMIC_OFFSET                 0x00000320 /* RGMII/SGMII config */
 252#define XTE_MC_OFFSET                   0x00000340 /* MDIO configuration */
 253#define XTE_UAW0_OFFSET                 0x00000380 /* Unicast address word 0 */
 254#define XTE_UAW1_OFFSET                 0x00000384 /* Unicast address word 1 */
 255
 256#define XTE_MAW0_OFFSET                 0x00000388 /* Multicast addr word 0 */
 257#define XTE_MAW1_OFFSET                 0x0000038C /* Multicast addr word 1 */
 258#define XTE_AFM_OFFSET                  0x00000390 /* Promiscuous mode */
 259#define XTE_AFM_EPPRM_MASK              (1 << 31)  /* Promiscuous mode enable */
 260
 261/* Interrupt Request status */
 262#define XTE_TIS_OFFSET                  0x000003A0
 263#define TIS_FRIS                        (1 << 0)
 264#define TIS_MRIS                        (1 << 1)
 265#define TIS_MWIS                        (1 << 2)
 266#define TIS_ARIS                        (1 << 3)
 267#define TIS_AWIS                        (1 << 4)
 268#define TIS_CRIS                        (1 << 5)
 269#define TIS_CWIS                        (1 << 6)
 270
 271#define XTE_TIE_OFFSET                  0x000003A4 /* Interrupt enable */
 272
 273/**  MII Mamagement Control register (MGTCR) */
 274#define XTE_MGTDR_OFFSET                0x000003B0 /* MII data */
 275#define XTE_MIIMAI_OFFSET               0x000003B4 /* MII control */
 276
 277#define CNTLREG_WRITE_ENABLE_MASK   0x8000
 278#define CNTLREG_EMAC1SEL_MASK       0x0400
 279#define CNTLREG_ADDRESSCODE_MASK    0x03ff
 280
 281/* CDMAC descriptor status bit definitions */
 282
 283#define STS_CTRL_APP0_ERR         (1 << 31)
 284#define STS_CTRL_APP0_IRQONEND    (1 << 30)
 285/* undoccumented */
 286#define STS_CTRL_APP0_STOPONEND   (1 << 29)
 287#define STS_CTRL_APP0_CMPLT       (1 << 28)
 288#define STS_CTRL_APP0_SOP         (1 << 27)
 289#define STS_CTRL_APP0_EOP         (1 << 26)
 290#define STS_CTRL_APP0_ENGBUSY     (1 << 25)
 291/* undocumented */
 292#define STS_CTRL_APP0_ENGRST      (1 << 24)
 293
 294#define TX_CONTROL_CALC_CSUM_MASK   1
 295
 296#define MULTICAST_CAM_TABLE_NUM 4
 297
 298/* TEMAC Synthesis features */
 299#define TEMAC_FEATURE_RX_CSUM  (1 << 0)
 300#define TEMAC_FEATURE_TX_CSUM  (1 << 1)
 301
 302/* TX/RX CURDESC_PTR points to first descriptor */
 303/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
 304
 305/**
 306 * struct cdmac_bd - LocalLink buffer descriptor format
 307 *
 308 * app0 bits:
 309 *      0    Error
 310 *      1    IrqOnEnd    generate an interrupt at completion of DMA  op
 311 *      2    reserved
 312 *      3    completed   Current descriptor completed
 313 *      4    SOP         TX - marks first desc/ RX marks first desct
 314 *      5    EOP         TX marks last desc/RX marks last desc
 315 *      6    EngBusy     DMA is processing
 316 *      7    reserved
 317 *      8:31 application specific
 318 */
 319struct cdmac_bd {
 320        u32 next;       /* Physical address of next buffer descriptor */
 321        u32 phys;
 322        u32 len;
 323        u32 app0;
 324        u32 app1;       /* TX start << 16 | insert */
 325        u32 app2;       /* TX csum */
 326        u32 app3;
 327        u32 app4;       /* skb for TX length for RX */
 328};
 329
 330struct temac_local {
 331        struct net_device *ndev;
 332        struct device *dev;
 333
 334        /* Connection to PHY device */
 335        struct phy_device *phy_dev;     /* Pointer to PHY device */
 336        struct device_node *phy_node;
 337
 338        /* MDIO bus data */
 339        struct mii_bus *mii_bus;        /* MII bus reference */
 340        int mdio_irqs[PHY_MAX_ADDR];    /* IRQs table for MDIO bus */
 341
 342        /* IO registers, dma functions and IRQs */
 343        void __iomem *regs;
 344        void __iomem *sdma_regs;
 345#ifdef CONFIG_PPC_DCR
 346        dcr_host_t sdma_dcrs;
 347#endif
 348        u32 (*dma_in)(struct temac_local *, int);
 349        void (*dma_out)(struct temac_local *, int, u32);
 350
 351        int tx_irq;
 352        int rx_irq;
 353        int emac_num;
 354
 355        struct sk_buff **rx_skb;
 356        spinlock_t rx_lock;
 357        struct mutex indirect_mutex;
 358        u32 options;                    /* Current options word */
 359        int last_link;
 360        unsigned int temac_features;
 361
 362        /* Buffer descriptors */
 363        struct cdmac_bd *tx_bd_v;
 364        dma_addr_t tx_bd_p;
 365        struct cdmac_bd *rx_bd_v;
 366        dma_addr_t rx_bd_p;
 367        int tx_bd_ci;
 368        int tx_bd_next;
 369        int tx_bd_tail;
 370        int rx_bd_ci;
 371};
 372
 373/* xilinx_temac.c */
 374u32 temac_ior(struct temac_local *lp, int offset);
 375void temac_iow(struct temac_local *lp, int offset, u32 value);
 376int temac_indirect_busywait(struct temac_local *lp);
 377u32 temac_indirect_in32(struct temac_local *lp, int reg);
 378void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
 379
 380
 381/* xilinx_temac_mdio.c */
 382int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
 383void temac_mdio_teardown(struct temac_local *lp);
 384
 385#endif /* XILINX_LL_TEMAC_H */
 386