linux/drivers/net/irda/au1k_ir.c
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   1/*
   2 * Alchemy Semi Au1000 IrDA driver
   3 *
   4 * Copyright 2001 MontaVista Software Inc.
   5 * Author: MontaVista Software, Inc.
   6 *              ppopov@mvista.com or source@mvista.com
   7 *
   8 *  This program is free software; you can distribute it and/or modify it
   9 *  under the terms of the GNU General Public License (Version 2) as
  10 *  published by the Free Software Foundation.
  11 *
  12 *  This program is distributed in the hope it will be useful, but WITHOUT
  13 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 *  for more details.
  16 *
  17 *  You should have received a copy of the GNU General Public License along
  18 *  with this program; if not, write to the Free Software Foundation, Inc.,
  19 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  20 */
  21
  22#include <linux/init.h>
  23#include <linux/module.h>
  24#include <linux/netdevice.h>
  25#include <linux/interrupt.h>
  26#include <linux/platform_device.h>
  27#include <linux/slab.h>
  28#include <linux/time.h>
  29#include <linux/types.h>
  30#include <linux/ioport.h>
  31
  32#include <net/irda/irda.h>
  33#include <net/irda/irmod.h>
  34#include <net/irda/wrapper.h>
  35#include <net/irda/irda_device.h>
  36#include <asm/mach-au1x00/au1000.h>
  37
  38/* registers */
  39#define IR_RING_PTR_STATUS      0x00
  40#define IR_RING_BASE_ADDR_H     0x04
  41#define IR_RING_BASE_ADDR_L     0x08
  42#define IR_RING_SIZE            0x0C
  43#define IR_RING_PROMPT          0x10
  44#define IR_RING_ADDR_CMPR       0x14
  45#define IR_INT_CLEAR            0x18
  46#define IR_CONFIG_1             0x20
  47#define IR_SIR_FLAGS            0x24
  48#define IR_STATUS               0x28
  49#define IR_READ_PHY_CONFIG      0x2C
  50#define IR_WRITE_PHY_CONFIG     0x30
  51#define IR_MAX_PKT_LEN          0x34
  52#define IR_RX_BYTE_CNT          0x38
  53#define IR_CONFIG_2             0x3C
  54#define IR_ENABLE               0x40
  55
  56/* Config1 */
  57#define IR_RX_INVERT_LED        (1 << 0)
  58#define IR_TX_INVERT_LED        (1 << 1)
  59#define IR_ST                   (1 << 2)
  60#define IR_SF                   (1 << 3)
  61#define IR_SIR                  (1 << 4)
  62#define IR_MIR                  (1 << 5)
  63#define IR_FIR                  (1 << 6)
  64#define IR_16CRC                (1 << 7)
  65#define IR_TD                   (1 << 8)
  66#define IR_RX_ALL               (1 << 9)
  67#define IR_DMA_ENABLE           (1 << 10)
  68#define IR_RX_ENABLE            (1 << 11)
  69#define IR_TX_ENABLE            (1 << 12)
  70#define IR_LOOPBACK             (1 << 14)
  71#define IR_SIR_MODE             (IR_SIR | IR_DMA_ENABLE | \
  72                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | \
  73                                 IR_16CRC)
  74
  75/* ir_status */
  76#define IR_RX_STATUS            (1 << 9)
  77#define IR_TX_STATUS            (1 << 10)
  78#define IR_PHYEN                (1 << 15)
  79
  80/* ir_write_phy_config */
  81#define IR_BR(x)                (((x) & 0x3f) << 10)    /* baud rate */
  82#define IR_PW(x)                (((x) & 0x1f) << 5)     /* pulse width */
  83#define IR_P(x)                 ((x) & 0x1f)            /* preamble bits */
  84
  85/* Config2 */
  86#define IR_MODE_INV             (1 << 0)
  87#define IR_ONE_PIN              (1 << 1)
  88#define IR_PHYCLK_40MHZ         (0 << 2)
  89#define IR_PHYCLK_48MHZ         (1 << 2)
  90#define IR_PHYCLK_56MHZ         (2 << 2)
  91#define IR_PHYCLK_64MHZ         (3 << 2)
  92#define IR_DP                   (1 << 4)
  93#define IR_DA                   (1 << 5)
  94#define IR_FLT_HIGH             (0 << 6)
  95#define IR_FLT_MEDHI            (1 << 6)
  96#define IR_FLT_MEDLO            (2 << 6)
  97#define IR_FLT_LO               (3 << 6)
  98#define IR_IEN                  (1 << 8)
  99
 100/* ir_enable */
 101#define IR_HC                   (1 << 3)        /* divide SBUS clock by 2 */
 102#define IR_CE                   (1 << 2)        /* clock enable */
 103#define IR_C                    (1 << 1)        /* coherency bit */
 104#define IR_BE                   (1 << 0)        /* set in big endian mode */
 105
 106#define NUM_IR_DESC     64
 107#define RING_SIZE_4     0x0
 108#define RING_SIZE_16    0x3
 109#define RING_SIZE_64    0xF
 110#define MAX_NUM_IR_DESC 64
 111#define MAX_BUF_SIZE    2048
 112
 113/* Ring descriptor flags */
 114#define AU_OWN          (1 << 7) /* tx,rx */
 115#define IR_DIS_CRC      (1 << 6) /* tx */
 116#define IR_BAD_CRC      (1 << 5) /* tx */
 117#define IR_NEED_PULSE   (1 << 4) /* tx */
 118#define IR_FORCE_UNDER  (1 << 3) /* tx */
 119#define IR_DISABLE_TX   (1 << 2) /* tx */
 120#define IR_HW_UNDER     (1 << 0) /* tx */
 121#define IR_TX_ERROR     (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER)
 122
 123#define IR_PHY_ERROR    (1 << 6) /* rx */
 124#define IR_CRC_ERROR    (1 << 5) /* rx */
 125#define IR_MAX_LEN      (1 << 4) /* rx */
 126#define IR_FIFO_OVER    (1 << 3) /* rx */
 127#define IR_SIR_ERROR    (1 << 2) /* rx */
 128#define IR_RX_ERROR     (IR_PHY_ERROR | IR_CRC_ERROR | \
 129                         IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR)
 130
 131struct db_dest {
 132        struct db_dest *pnext;
 133        volatile u32 *vaddr;
 134        dma_addr_t dma_addr;
 135};
 136
 137struct ring_dest {
 138        u8 count_0;     /* 7:0  */
 139        u8 count_1;     /* 12:8 */
 140        u8 reserved;
 141        u8 flags;
 142        u8 addr_0;      /* 7:0   */
 143        u8 addr_1;      /* 15:8  */
 144        u8 addr_2;      /* 23:16 */
 145        u8 addr_3;      /* 31:24 */
 146};
 147
 148/* Private data for each instance */
 149struct au1k_private {
 150        void __iomem *iobase;
 151        int irq_rx, irq_tx;
 152
 153        struct db_dest *pDBfree;
 154        struct db_dest db[2 * NUM_IR_DESC];
 155        volatile struct ring_dest *rx_ring[NUM_IR_DESC];
 156        volatile struct ring_dest *tx_ring[NUM_IR_DESC];
 157        struct db_dest *rx_db_inuse[NUM_IR_DESC];
 158        struct db_dest *tx_db_inuse[NUM_IR_DESC];
 159        u32 rx_head;
 160        u32 tx_head;
 161        u32 tx_tail;
 162        u32 tx_full;
 163
 164        iobuff_t rx_buff;
 165
 166        struct net_device *netdev;
 167        struct timeval stamp;
 168        struct timeval now;
 169        struct qos_info qos;
 170        struct irlap_cb *irlap;
 171
 172        u8 open;
 173        u32 speed;
 174        u32 newspeed;
 175
 176        struct timer_list timer;
 177
 178        struct resource *ioarea;
 179        struct au1k_irda_platform_data *platdata;
 180};
 181
 182static int qos_mtt_bits = 0x07;  /* 1 ms or more */
 183
 184#define RUN_AT(x) (jiffies + (x))
 185
 186static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode)
 187{
 188        if (p->platdata && p->platdata->set_phy_mode)
 189                p->platdata->set_phy_mode(mode);
 190}
 191
 192static inline unsigned long irda_read(struct au1k_private *p,
 193                                      unsigned long ofs)
 194{
 195        /*
 196        * IrDA peripheral bug. You have to read the register
 197        * twice to get the right value.
 198        */
 199        (void)__raw_readl(p->iobase + ofs);
 200        return __raw_readl(p->iobase + ofs);
 201}
 202
 203static inline void irda_write(struct au1k_private *p, unsigned long ofs,
 204                              unsigned long val)
 205{
 206        __raw_writel(val, p->iobase + ofs);
 207        wmb();
 208}
 209
 210/*
 211 * Buffer allocation/deallocation routines. The buffer descriptor returned
 212 * has the virtual and dma address of a buffer suitable for
 213 * both, receive and transmit operations.
 214 */
 215static struct db_dest *GetFreeDB(struct au1k_private *aup)
 216{
 217        struct db_dest *db;
 218        db = aup->pDBfree;
 219
 220        if (db)
 221                aup->pDBfree = db->pnext;
 222        return db;
 223}
 224
 225/*
 226  DMA memory allocation, derived from pci_alloc_consistent.
 227  However, the Au1000 data cache is coherent (when programmed
 228  so), therefore we return KSEG0 address, not KSEG1.
 229*/
 230static void *dma_alloc(size_t size, dma_addr_t *dma_handle)
 231{
 232        void *ret;
 233        int gfp = GFP_ATOMIC | GFP_DMA;
 234
 235        ret = (void *)__get_free_pages(gfp, get_order(size));
 236
 237        if (ret != NULL) {
 238                memset(ret, 0, size);
 239                *dma_handle = virt_to_bus(ret);
 240                ret = (void *)KSEG0ADDR(ret);
 241        }
 242        return ret;
 243}
 244
 245static void dma_free(void *vaddr, size_t size)
 246{
 247        vaddr = (void *)KSEG0ADDR(vaddr);
 248        free_pages((unsigned long) vaddr, get_order(size));
 249}
 250
 251
 252static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
 253{
 254        int i;
 255        for (i = 0; i < NUM_IR_DESC; i++) {
 256                aup->rx_ring[i] = (volatile struct ring_dest *)
 257                        (rx_base + sizeof(struct ring_dest) * i);
 258        }
 259        for (i = 0; i < NUM_IR_DESC; i++) {
 260                aup->tx_ring[i] = (volatile struct ring_dest *)
 261                        (tx_base + sizeof(struct ring_dest) * i);
 262        }
 263}
 264
 265static int au1k_irda_init_iobuf(iobuff_t *io, int size)
 266{
 267        io->head = kmalloc(size, GFP_KERNEL);
 268        if (io->head != NULL) {
 269                io->truesize    = size;
 270                io->in_frame    = FALSE;
 271                io->state       = OUTSIDE_FRAME;
 272                io->data        = io->head;
 273        }
 274        return io->head ? 0 : -ENOMEM;
 275}
 276
 277/*
 278 * Set the IrDA communications speed.
 279 */
 280static int au1k_irda_set_speed(struct net_device *dev, int speed)
 281{
 282        struct au1k_private *aup = netdev_priv(dev);
 283        volatile struct ring_dest *ptxd;
 284        unsigned long control;
 285        int ret = 0, timeout = 10, i;
 286
 287        if (speed == aup->speed)
 288                return ret;
 289
 290        /* disable PHY first */
 291        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 292        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
 293
 294        /* disable RX/TX */
 295        irda_write(aup, IR_CONFIG_1,
 296            irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE));
 297        msleep(20);
 298        while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) {
 299                msleep(20);
 300                if (!timeout--) {
 301                        printk(KERN_ERR "%s: rx/tx disable timeout\n",
 302                                        dev->name);
 303                        break;
 304                }
 305        }
 306
 307        /* disable DMA */
 308        irda_write(aup, IR_CONFIG_1,
 309                   irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE);
 310        msleep(20);
 311
 312        /* After we disable tx/rx. the index pointers go back to zero. */
 313        aup->tx_head = aup->tx_tail = aup->rx_head = 0;
 314        for (i = 0; i < NUM_IR_DESC; i++) {
 315                ptxd = aup->tx_ring[i];
 316                ptxd->flags = 0;
 317                ptxd->count_0 = 0;
 318                ptxd->count_1 = 0;
 319        }
 320
 321        for (i = 0; i < NUM_IR_DESC; i++) {
 322                ptxd = aup->rx_ring[i];
 323                ptxd->count_0 = 0;
 324                ptxd->count_1 = 0;
 325                ptxd->flags = AU_OWN;
 326        }
 327
 328        if (speed == 4000000)
 329                au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR);
 330        else
 331                au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 332
 333        switch (speed) {
 334        case 9600:
 335                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12));
 336                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 337                break;
 338        case 19200:
 339                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12));
 340                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 341                break;
 342        case 38400:
 343                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12));
 344                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 345                break;
 346        case 57600:
 347                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12));
 348                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 349                break;
 350        case 115200:
 351                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12));
 352                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 353                break;
 354        case 4000000:
 355                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15));
 356                irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE |
 357                                IR_RX_ENABLE);
 358                break;
 359        default:
 360                printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
 361                ret = -EINVAL;
 362                break;
 363        }
 364
 365        aup->speed = speed;
 366        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN);
 367
 368        control = irda_read(aup, IR_STATUS);
 369        irda_write(aup, IR_RING_PROMPT, 0);
 370
 371        if (control & (1 << 14)) {
 372                printk(KERN_ERR "%s: configuration error\n", dev->name);
 373        } else {
 374                if (control & (1 << 11))
 375                        printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
 376                if (control & (1 << 12))
 377                        printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
 378                if (control & (1 << 13))
 379                        printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
 380                if (control & (1 << 10))
 381                        printk(KERN_DEBUG "%s TX enabled\n", dev->name);
 382                if (control & (1 << 9))
 383                        printk(KERN_DEBUG "%s RX enabled\n", dev->name);
 384        }
 385
 386        return ret;
 387}
 388
 389static void update_rx_stats(struct net_device *dev, u32 status, u32 count)
 390{
 391        struct net_device_stats *ps = &dev->stats;
 392
 393        ps->rx_packets++;
 394
 395        if (status & IR_RX_ERROR) {
 396                ps->rx_errors++;
 397                if (status & (IR_PHY_ERROR | IR_FIFO_OVER))
 398                        ps->rx_missed_errors++;
 399                if (status & IR_MAX_LEN)
 400                        ps->rx_length_errors++;
 401                if (status & IR_CRC_ERROR)
 402                        ps->rx_crc_errors++;
 403        } else
 404                ps->rx_bytes += count;
 405}
 406
 407static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
 408{
 409        struct net_device_stats *ps = &dev->stats;
 410
 411        ps->tx_packets++;
 412        ps->tx_bytes += pkt_len;
 413
 414        if (status & IR_TX_ERROR) {
 415                ps->tx_errors++;
 416                ps->tx_aborted_errors++;
 417        }
 418}
 419
 420static void au1k_tx_ack(struct net_device *dev)
 421{
 422        struct au1k_private *aup = netdev_priv(dev);
 423        volatile struct ring_dest *ptxd;
 424
 425        ptxd = aup->tx_ring[aup->tx_tail];
 426        while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
 427                update_tx_stats(dev, ptxd->flags,
 428                                (ptxd->count_1 << 8) | ptxd->count_0);
 429                ptxd->count_0 = 0;
 430                ptxd->count_1 = 0;
 431                wmb();
 432                aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
 433                ptxd = aup->tx_ring[aup->tx_tail];
 434
 435                if (aup->tx_full) {
 436                        aup->tx_full = 0;
 437                        netif_wake_queue(dev);
 438                }
 439        }
 440
 441        if (aup->tx_tail == aup->tx_head) {
 442                if (aup->newspeed) {
 443                        au1k_irda_set_speed(dev, aup->newspeed);
 444                        aup->newspeed = 0;
 445                } else {
 446                        irda_write(aup, IR_CONFIG_1,
 447                            irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE);
 448                        irda_write(aup, IR_CONFIG_1,
 449                            irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE);
 450                        irda_write(aup, IR_RING_PROMPT, 0);
 451                }
 452        }
 453}
 454
 455static int au1k_irda_rx(struct net_device *dev)
 456{
 457        struct au1k_private *aup = netdev_priv(dev);
 458        volatile struct ring_dest *prxd;
 459        struct sk_buff *skb;
 460        struct db_dest *pDB;
 461        u32 flags, count;
 462
 463        prxd = aup->rx_ring[aup->rx_head];
 464        flags = prxd->flags;
 465
 466        while (!(flags & AU_OWN))  {
 467                pDB = aup->rx_db_inuse[aup->rx_head];
 468                count = (prxd->count_1 << 8) | prxd->count_0;
 469                if (!(flags & IR_RX_ERROR)) {
 470                        /* good frame */
 471                        update_rx_stats(dev, flags, count);
 472                        skb = alloc_skb(count + 1, GFP_ATOMIC);
 473                        if (skb == NULL) {
 474                                dev->stats.rx_dropped++;
 475                                continue;
 476                        }
 477                        skb_reserve(skb, 1);
 478                        if (aup->speed == 4000000)
 479                                skb_put(skb, count);
 480                        else
 481                                skb_put(skb, count - 2);
 482                        skb_copy_to_linear_data(skb, (void *)pDB->vaddr,
 483                                                count - 2);
 484                        skb->dev = dev;
 485                        skb_reset_mac_header(skb);
 486                        skb->protocol = htons(ETH_P_IRDA);
 487                        netif_rx(skb);
 488                        prxd->count_0 = 0;
 489                        prxd->count_1 = 0;
 490                }
 491                prxd->flags |= AU_OWN;
 492                aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
 493                irda_write(aup, IR_RING_PROMPT, 0);
 494
 495                /* next descriptor */
 496                prxd = aup->rx_ring[aup->rx_head];
 497                flags = prxd->flags;
 498
 499        }
 500        return 0;
 501}
 502
 503static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
 504{
 505        struct net_device *dev = dev_id;
 506        struct au1k_private *aup = netdev_priv(dev);
 507
 508        irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */
 509
 510        au1k_irda_rx(dev);
 511        au1k_tx_ack(dev);
 512
 513        return IRQ_HANDLED;
 514}
 515
 516static int au1k_init(struct net_device *dev)
 517{
 518        struct au1k_private *aup = netdev_priv(dev);
 519        u32 enable, ring_address;
 520        int i;
 521
 522        enable = IR_HC | IR_CE | IR_C;
 523#ifndef CONFIG_CPU_LITTLE_ENDIAN
 524        enable |= IR_BE;
 525#endif
 526        aup->tx_head = 0;
 527        aup->tx_tail = 0;
 528        aup->rx_head = 0;
 529
 530        for (i = 0; i < NUM_IR_DESC; i++)
 531                aup->rx_ring[i]->flags = AU_OWN;
 532
 533        irda_write(aup, IR_ENABLE, enable);
 534        msleep(20);
 535
 536        /* disable PHY */
 537        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 538        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
 539        msleep(20);
 540
 541        irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE);
 542
 543        ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]);
 544        irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26);
 545        irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff);
 546
 547        irda_write(aup, IR_RING_SIZE,
 548                                (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12));
 549
 550        irda_write(aup, IR_CONFIG_2, IR_PHYCLK_48MHZ | IR_ONE_PIN);
 551        irda_write(aup, IR_RING_ADDR_CMPR, 0);
 552
 553        au1k_irda_set_speed(dev, 9600);
 554        return 0;
 555}
 556
 557static int au1k_irda_start(struct net_device *dev)
 558{
 559        struct au1k_private *aup = netdev_priv(dev);
 560        char hwname[32];
 561        int retval;
 562
 563        retval = au1k_init(dev);
 564        if (retval) {
 565                printk(KERN_ERR "%s: error in au1k_init\n", dev->name);
 566                return retval;
 567        }
 568
 569        retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0,
 570                             dev->name, dev);
 571        if (retval) {
 572                printk(KERN_ERR "%s: unable to get IRQ %d\n",
 573                                dev->name, dev->irq);
 574                return retval;
 575        }
 576        retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0,
 577                             dev->name, dev);
 578        if (retval) {
 579                free_irq(aup->irq_tx, dev);
 580                printk(KERN_ERR "%s: unable to get IRQ %d\n",
 581                                dev->name, dev->irq);
 582                return retval;
 583        }
 584
 585        /* Give self a hardware name */
 586        sprintf(hwname, "Au1000 SIR/FIR");
 587        aup->irlap = irlap_open(dev, &aup->qos, hwname);
 588        netif_start_queue(dev);
 589
 590        /* int enable */
 591        irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN);
 592
 593        /* power up */
 594        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 595
 596        aup->timer.expires = RUN_AT((3 * HZ));
 597        aup->timer.data = (unsigned long)dev;
 598        return 0;
 599}
 600
 601static int au1k_irda_stop(struct net_device *dev)
 602{
 603        struct au1k_private *aup = netdev_priv(dev);
 604
 605        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 606
 607        /* disable interrupts */
 608        irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN);
 609        irda_write(aup, IR_CONFIG_1, 0);
 610        irda_write(aup, IR_ENABLE, 0); /* disable clock */
 611
 612        if (aup->irlap) {
 613                irlap_close(aup->irlap);
 614                aup->irlap = NULL;
 615        }
 616
 617        netif_stop_queue(dev);
 618        del_timer(&aup->timer);
 619
 620        /* disable the interrupt */
 621        free_irq(aup->irq_tx, dev);
 622        free_irq(aup->irq_rx, dev);
 623
 624        return 0;
 625}
 626
 627/*
 628 * Au1000 transmit routine.
 629 */
 630static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
 631{
 632        struct au1k_private *aup = netdev_priv(dev);
 633        int speed = irda_get_next_speed(skb);
 634        volatile struct ring_dest *ptxd;
 635        struct db_dest *pDB;
 636        u32 len, flags;
 637
 638        if (speed != aup->speed && speed != -1)
 639                aup->newspeed = speed;
 640
 641        if ((skb->len == 0) && (aup->newspeed)) {
 642                if (aup->tx_tail == aup->tx_head) {
 643                        au1k_irda_set_speed(dev, speed);
 644                        aup->newspeed = 0;
 645                }
 646                dev_kfree_skb(skb);
 647                return NETDEV_TX_OK;
 648        }
 649
 650        ptxd = aup->tx_ring[aup->tx_head];
 651        flags = ptxd->flags;
 652
 653        if (flags & AU_OWN) {
 654                printk(KERN_DEBUG "%s: tx_full\n", dev->name);
 655                netif_stop_queue(dev);
 656                aup->tx_full = 1;
 657                return 1;
 658        } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
 659                printk(KERN_DEBUG "%s: tx_full\n", dev->name);
 660                netif_stop_queue(dev);
 661                aup->tx_full = 1;
 662                return 1;
 663        }
 664
 665        pDB = aup->tx_db_inuse[aup->tx_head];
 666
 667#if 0
 668        if (irda_read(aup, IR_RX_BYTE_CNT) != 0) {
 669                printk(KERN_DEBUG "tx warning: rx byte cnt %x\n",
 670                                irda_read(aup, IR_RX_BYTE_CNT));
 671        }
 672#endif
 673
 674        if (aup->speed == 4000000) {
 675                /* FIR */
 676                skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
 677                ptxd->count_0 = skb->len & 0xff;
 678                ptxd->count_1 = (skb->len >> 8) & 0xff;
 679        } else {
 680                /* SIR */
 681                len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE);
 682                ptxd->count_0 = len & 0xff;
 683                ptxd->count_1 = (len >> 8) & 0xff;
 684                ptxd->flags |= IR_DIS_CRC;
 685        }
 686        ptxd->flags |= AU_OWN;
 687        wmb();
 688
 689        irda_write(aup, IR_CONFIG_1,
 690                   irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE);
 691        irda_write(aup, IR_RING_PROMPT, 0);
 692
 693        dev_kfree_skb(skb);
 694        aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1);
 695        return NETDEV_TX_OK;
 696}
 697
 698/*
 699 * The Tx ring has been full longer than the watchdog timeout
 700 * value. The transmitter must be hung?
 701 */
 702static void au1k_tx_timeout(struct net_device *dev)
 703{
 704        u32 speed;
 705        struct au1k_private *aup = netdev_priv(dev);
 706
 707        printk(KERN_ERR "%s: tx timeout\n", dev->name);
 708        speed = aup->speed;
 709        aup->speed = 0;
 710        au1k_irda_set_speed(dev, speed);
 711        aup->tx_full = 0;
 712        netif_wake_queue(dev);
 713}
 714
 715static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
 716{
 717        struct if_irda_req *rq = (struct if_irda_req *)ifreq;
 718        struct au1k_private *aup = netdev_priv(dev);
 719        int ret = -EOPNOTSUPP;
 720
 721        switch (cmd) {
 722        case SIOCSBANDWIDTH:
 723                if (capable(CAP_NET_ADMIN)) {
 724                        /*
 725                         * We are unable to set the speed if the
 726                         * device is not running.
 727                         */
 728                        if (aup->open)
 729                                ret = au1k_irda_set_speed(dev,
 730                                                rq->ifr_baudrate);
 731                        else {
 732                                printk(KERN_ERR "%s ioctl: !netif_running\n",
 733                                                dev->name);
 734                                ret = 0;
 735                        }
 736                }
 737                break;
 738
 739        case SIOCSMEDIABUSY:
 740                ret = -EPERM;
 741                if (capable(CAP_NET_ADMIN)) {
 742                        irda_device_set_media_busy(dev, TRUE);
 743                        ret = 0;
 744                }
 745                break;
 746
 747        case SIOCGRECEIVING:
 748                rq->ifr_receiving = 0;
 749                break;
 750        default:
 751                break;
 752        }
 753        return ret;
 754}
 755
 756static const struct net_device_ops au1k_irda_netdev_ops = {
 757        .ndo_open               = au1k_irda_start,
 758        .ndo_stop               = au1k_irda_stop,
 759        .ndo_start_xmit         = au1k_irda_hard_xmit,
 760        .ndo_tx_timeout         = au1k_tx_timeout,
 761        .ndo_do_ioctl           = au1k_irda_ioctl,
 762};
 763
 764static int au1k_irda_net_init(struct net_device *dev)
 765{
 766        struct au1k_private *aup = netdev_priv(dev);
 767        struct db_dest *pDB, *pDBfree;
 768        int i, err, retval = 0;
 769        dma_addr_t temp;
 770
 771        err = au1k_irda_init_iobuf(&aup->rx_buff, 14384);
 772        if (err)
 773                goto out1;
 774
 775        dev->netdev_ops = &au1k_irda_netdev_ops;
 776
 777        irda_init_max_qos_capabilies(&aup->qos);
 778
 779        /* The only value we must override it the baudrate */
 780        aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 |
 781                IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8);
 782
 783        aup->qos.min_turn_time.bits = qos_mtt_bits;
 784        irda_qos_bits_to_value(&aup->qos);
 785
 786        retval = -ENOMEM;
 787
 788        /* Tx ring follows rx ring + 512 bytes */
 789        /* we need a 1k aligned buffer */
 790        aup->rx_ring[0] = (struct ring_dest *)
 791                dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)),
 792                          &temp);
 793        if (!aup->rx_ring[0])
 794                goto out2;
 795
 796        /* allocate the data buffers */
 797        aup->db[0].vaddr =
 798                dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp);
 799        if (!aup->db[0].vaddr)
 800                goto out3;
 801
 802        setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512);
 803
 804        pDBfree = NULL;
 805        pDB = aup->db;
 806        for (i = 0; i < (2 * NUM_IR_DESC); i++) {
 807                pDB->pnext = pDBfree;
 808                pDBfree = pDB;
 809                pDB->vaddr =
 810                       (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i));
 811                pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
 812                pDB++;
 813        }
 814        aup->pDBfree = pDBfree;
 815
 816        /* attach a data buffer to each descriptor */
 817        for (i = 0; i < NUM_IR_DESC; i++) {
 818                pDB = GetFreeDB(aup);
 819                if (!pDB)
 820                        goto out3;
 821                aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
 822                aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
 823                aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
 824                aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
 825                aup->rx_db_inuse[i] = pDB;
 826        }
 827        for (i = 0; i < NUM_IR_DESC; i++) {
 828                pDB = GetFreeDB(aup);
 829                if (!pDB)
 830                        goto out3;
 831                aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
 832                aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
 833                aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
 834                aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
 835                aup->tx_ring[i]->count_0 = 0;
 836                aup->tx_ring[i]->count_1 = 0;
 837                aup->tx_ring[i]->flags = 0;
 838                aup->tx_db_inuse[i] = pDB;
 839        }
 840
 841        return 0;
 842
 843out3:
 844        dma_free((void *)aup->rx_ring[0],
 845                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 846out2:
 847        kfree(aup->rx_buff.head);
 848out1:
 849        printk(KERN_ERR "au1k_irda_net_init() failed.  Returns %d\n", retval);
 850        return retval;
 851}
 852
 853static int au1k_irda_probe(struct platform_device *pdev)
 854{
 855        struct au1k_private *aup;
 856        struct net_device *dev;
 857        struct resource *r;
 858        int err;
 859
 860        dev = alloc_irdadev(sizeof(struct au1k_private));
 861        if (!dev)
 862                return -ENOMEM;
 863
 864        aup = netdev_priv(dev);
 865
 866        aup->platdata = pdev->dev.platform_data;
 867
 868        err = -EINVAL;
 869        r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 870        if (!r)
 871                goto out;
 872
 873        aup->irq_tx = r->start;
 874
 875        r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 876        if (!r)
 877                goto out;
 878
 879        aup->irq_rx = r->start;
 880
 881        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 882        if (!r)
 883                goto out;
 884
 885        err = -EBUSY;
 886        aup->ioarea = request_mem_region(r->start, resource_size(r),
 887                                         pdev->name);
 888        if (!aup->ioarea)
 889                goto out;
 890
 891        aup->iobase = ioremap_nocache(r->start, resource_size(r));
 892        if (!aup->iobase)
 893                goto out2;
 894
 895        dev->irq = aup->irq_rx;
 896
 897        err = au1k_irda_net_init(dev);
 898        if (err)
 899                goto out3;
 900        err = register_netdev(dev);
 901        if (err)
 902                goto out4;
 903
 904        platform_set_drvdata(pdev, dev);
 905
 906        printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
 907        return 0;
 908
 909out4:
 910        dma_free((void *)aup->db[0].vaddr,
 911                MAX_BUF_SIZE * 2 * NUM_IR_DESC);
 912        dma_free((void *)aup->rx_ring[0],
 913                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 914        kfree(aup->rx_buff.head);
 915out3:
 916        iounmap(aup->iobase);
 917out2:
 918        release_resource(aup->ioarea);
 919        kfree(aup->ioarea);
 920out:
 921        free_netdev(dev);
 922        return err;
 923}
 924
 925static int au1k_irda_remove(struct platform_device *pdev)
 926{
 927        struct net_device *dev = platform_get_drvdata(pdev);
 928        struct au1k_private *aup = netdev_priv(dev);
 929
 930        unregister_netdev(dev);
 931
 932        dma_free((void *)aup->db[0].vaddr,
 933                MAX_BUF_SIZE * 2 * NUM_IR_DESC);
 934        dma_free((void *)aup->rx_ring[0],
 935                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 936        kfree(aup->rx_buff.head);
 937
 938        iounmap(aup->iobase);
 939        release_resource(aup->ioarea);
 940        kfree(aup->ioarea);
 941
 942        free_netdev(dev);
 943
 944        return 0;
 945}
 946
 947static struct platform_driver au1k_irda_driver = {
 948        .driver = {
 949                .name   = "au1000-irda",
 950                .owner  = THIS_MODULE,
 951        },
 952        .probe          = au1k_irda_probe,
 953        .remove         = au1k_irda_remove,
 954};
 955
 956module_platform_driver(au1k_irda_driver);
 957
 958MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>");
 959MODULE_DESCRIPTION("Au1000 IrDA Device Driver");
 960