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15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/net.h>
21#include <linux/skbuff.h>
22#include <linux/netdevice.h>
23#include <linux/if_arp.h>
24#include <linux/delay.h>
25#include <linux/hdlc.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/slab.h>
29#include <net/arp.h>
30
31#include <asm/irq.h>
32#include <asm/io.h>
33#include <asm/dma.h>
34#include <asm/byteorder.h>
35#include "z85230.h"
36
37
38struct slvl_device
39{
40 struct z8530_channel *chan;
41 int channel;
42};
43
44
45struct slvl_board
46{
47 struct slvl_device dev[2];
48 struct z8530_dev board;
49 int iobase;
50};
51
52
53
54
55
56static inline struct slvl_device* dev_to_chan(struct net_device *dev)
57{
58 return (struct slvl_device *)dev_to_hdlc(dev)->priv;
59}
60
61
62
63
64
65
66static void sealevel_input(struct z8530_channel *c, struct sk_buff *skb)
67{
68
69 skb_trim(skb, skb->len - 2);
70 skb->protocol = hdlc_type_trans(skb, c->netdevice);
71 skb_reset_mac_header(skb);
72 skb->dev = c->netdevice;
73 netif_rx(skb);
74}
75
76
77
78
79
80static int sealevel_open(struct net_device *d)
81{
82 struct slvl_device *slvl = dev_to_chan(d);
83 int err = -1;
84 int unit = slvl->channel;
85
86
87
88
89
90 switch (unit) {
91 case 0:
92 err = z8530_sync_dma_open(d, slvl->chan);
93 break;
94 case 1:
95 err = z8530_sync_open(d, slvl->chan);
96 break;
97 }
98
99 if (err)
100 return err;
101
102 err = hdlc_open(d);
103 if (err) {
104 switch (unit) {
105 case 0:
106 z8530_sync_dma_close(d, slvl->chan);
107 break;
108 case 1:
109 z8530_sync_close(d, slvl->chan);
110 break;
111 }
112 return err;
113 }
114
115 slvl->chan->rx_function = sealevel_input;
116
117
118
119
120 netif_start_queue(d);
121 return 0;
122}
123
124static int sealevel_close(struct net_device *d)
125{
126 struct slvl_device *slvl = dev_to_chan(d);
127 int unit = slvl->channel;
128
129
130
131
132
133 slvl->chan->rx_function = z8530_null_rx;
134
135 hdlc_close(d);
136 netif_stop_queue(d);
137
138 switch (unit) {
139 case 0:
140 z8530_sync_dma_close(d, slvl->chan);
141 break;
142 case 1:
143 z8530_sync_close(d, slvl->chan);
144 break;
145 }
146 return 0;
147}
148
149static int sealevel_ioctl(struct net_device *d, struct ifreq *ifr, int cmd)
150{
151
152
153 return hdlc_ioctl(d, ifr, cmd);
154}
155
156
157
158
159
160static netdev_tx_t sealevel_queue_xmit(struct sk_buff *skb,
161 struct net_device *d)
162{
163 return z8530_queue_xmit(dev_to_chan(d)->chan, skb);
164}
165
166static int sealevel_attach(struct net_device *dev, unsigned short encoding,
167 unsigned short parity)
168{
169 if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
170 return 0;
171 return -EINVAL;
172}
173
174static const struct net_device_ops sealevel_ops = {
175 .ndo_open = sealevel_open,
176 .ndo_stop = sealevel_close,
177 .ndo_change_mtu = hdlc_change_mtu,
178 .ndo_start_xmit = hdlc_start_xmit,
179 .ndo_do_ioctl = sealevel_ioctl,
180};
181
182static int slvl_setup(struct slvl_device *sv, int iobase, int irq)
183{
184 struct net_device *dev = alloc_hdlcdev(sv);
185 if (!dev)
186 return -1;
187
188 dev_to_hdlc(dev)->attach = sealevel_attach;
189 dev_to_hdlc(dev)->xmit = sealevel_queue_xmit;
190 dev->netdev_ops = &sealevel_ops;
191 dev->base_addr = iobase;
192 dev->irq = irq;
193
194 if (register_hdlc_device(dev)) {
195 pr_err("unable to register HDLC device\n");
196 free_netdev(dev);
197 return -1;
198 }
199
200 sv->chan->netdevice = dev;
201 return 0;
202}
203
204
205
206
207
208
209static __init struct slvl_board *slvl_init(int iobase, int irq,
210 int txdma, int rxdma, int slow)
211{
212 struct z8530_dev *dev;
213 struct slvl_board *b;
214
215
216
217
218
219 if (!request_region(iobase, 8, "Sealevel 4021")) {
220 pr_warn("I/O 0x%X already in use\n", iobase);
221 return NULL;
222 }
223
224 b = kzalloc(sizeof(struct slvl_board), GFP_KERNEL);
225 if (!b)
226 goto err_kzalloc;
227
228 b->dev[0].chan = &b->board.chanA;
229 b->dev[0].channel = 0;
230
231 b->dev[1].chan = &b->board.chanB;
232 b->dev[1].channel = 1;
233
234 dev = &b->board;
235
236
237
238
239
240 dev->active = 0;
241
242 b->iobase = iobase;
243
244
245
246
247
248 if (slow)
249 iobase |= Z8530_PORT_SLEEP;
250
251 dev->chanA.ctrlio = iobase + 1;
252 dev->chanA.dataio = iobase;
253 dev->chanB.ctrlio = iobase + 3;
254 dev->chanB.dataio = iobase + 2;
255
256 dev->chanA.irqs = &z8530_nop;
257 dev->chanB.irqs = &z8530_nop;
258
259
260
261
262
263 outb(3 | (1 << 7), b->iobase + 4);
264
265
266
267
268
269 if (request_irq(irq, z8530_interrupt, IRQF_DISABLED,
270 "SeaLevel", dev) < 0) {
271 pr_warn("IRQ %d already in use\n", irq);
272 goto err_request_irq;
273 }
274
275 dev->irq = irq;
276 dev->chanA.private = &b->dev[0];
277 dev->chanB.private = &b->dev[1];
278 dev->chanA.dev = dev;
279 dev->chanB.dev = dev;
280
281 dev->chanA.txdma = 3;
282 dev->chanA.rxdma = 1;
283 if (request_dma(dev->chanA.txdma, "SeaLevel (TX)"))
284 goto err_dma_tx;
285
286 if (request_dma(dev->chanA.rxdma, "SeaLevel (RX)"))
287 goto err_dma_rx;
288
289 disable_irq(irq);
290
291
292
293
294
295 if (z8530_init(dev) != 0) {
296 pr_err("Z8530 series device not found\n");
297 enable_irq(irq);
298 goto free_hw;
299 }
300 if (dev->type == Z85C30) {
301 z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream);
302 z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream);
303 } else {
304 z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream_85230);
305 z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream_85230);
306 }
307
308
309
310
311
312 enable_irq(irq);
313
314 if (slvl_setup(&b->dev[0], iobase, irq))
315 goto free_hw;
316 if (slvl_setup(&b->dev[1], iobase, irq))
317 goto free_netdev0;
318
319 z8530_describe(dev, "I/O", iobase);
320 dev->active = 1;
321 return b;
322
323free_netdev0:
324 unregister_hdlc_device(b->dev[0].chan->netdevice);
325 free_netdev(b->dev[0].chan->netdevice);
326free_hw:
327 free_dma(dev->chanA.rxdma);
328err_dma_rx:
329 free_dma(dev->chanA.txdma);
330err_dma_tx:
331 free_irq(irq, dev);
332err_request_irq:
333 kfree(b);
334err_kzalloc:
335 release_region(iobase, 8);
336 return NULL;
337}
338
339static void __exit slvl_shutdown(struct slvl_board *b)
340{
341 int u;
342
343 z8530_shutdown(&b->board);
344
345 for (u = 0; u < 2; u++) {
346 struct net_device *d = b->dev[u].chan->netdevice;
347 unregister_hdlc_device(d);
348 free_netdev(d);
349 }
350
351 free_irq(b->board.irq, &b->board);
352 free_dma(b->board.chanA.rxdma);
353 free_dma(b->board.chanA.txdma);
354
355 outb(0, b->iobase);
356 release_region(b->iobase, 8);
357 kfree(b);
358}
359
360
361static int io=0x238;
362static int txdma=1;
363static int rxdma=3;
364static int irq=5;
365static bool slow=false;
366
367module_param(io, int, 0);
368MODULE_PARM_DESC(io, "The I/O base of the Sealevel card");
369module_param(txdma, int, 0);
370MODULE_PARM_DESC(txdma, "Transmit DMA channel");
371module_param(rxdma, int, 0);
372MODULE_PARM_DESC(rxdma, "Receive DMA channel");
373module_param(irq, int, 0);
374MODULE_PARM_DESC(irq, "The interrupt line setting for the SeaLevel card");
375module_param(slow, bool, 0);
376MODULE_PARM_DESC(slow, "Set this for an older Sealevel card such as the 4012");
377
378MODULE_AUTHOR("Alan Cox");
379MODULE_LICENSE("GPL");
380MODULE_DESCRIPTION("Modular driver for the SeaLevel 4021");
381
382static struct slvl_board *slvl_unit;
383
384static int __init slvl_init_module(void)
385{
386 slvl_unit = slvl_init(io, irq, txdma, rxdma, slow);
387
388 return slvl_unit ? 0 : -ENODEV;
389}
390
391static void __exit slvl_cleanup_module(void)
392{
393 if (slvl_unit)
394 slvl_shutdown(slvl_unit);
395}
396
397module_init(slvl_init_module);
398module_exit(slvl_cleanup_module);
399
