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17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/firmware.h>
24
25#include "mac.h"
26#include "ani.h"
27#include "eeprom.h"
28#include "calib.h"
29#include "reg.h"
30#include "phy.h"
31#include "btcoex.h"
32
33#include "../regd.h"
34
35#define ATHEROS_VENDOR_ID 0x168c
36
37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
43#define AR2427_DEVID_PCIE 0x002c
44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
47#define AR9300_DEVID_AR9340 0x0031
48#define AR9300_DEVID_AR9485_PCIE 0x0032
49#define AR9300_DEVID_AR9580 0x0033
50#define AR9300_DEVID_AR9462 0x0034
51#define AR9300_DEVID_AR9330 0x0035
52#define AR9300_DEVID_QCA955X 0x0038
53#define AR9485_DEVID_AR1111 0x0037
54#define AR9300_DEVID_AR9565 0x0036
55
56#define AR5416_AR9100_DEVID 0x000b
57
58#define AR_SUBVENDOR_ID_NOG 0x0e11
59#define AR_SUBVENDOR_ID_NEW_A 0x7065
60#define AR5416_MAGIC 0x19641014
61
62#define AR9280_COEX2WIRE_SUBSYSID 0x309b
63#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
64#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
65
66#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
67
68#define ATH_DEFAULT_NOISE_FLOOR -95
69
70#define ATH9K_RSSI_BAD -128
71
72#define ATH9K_NUM_CHANNELS 38
73
74
75#define REG_WRITE(_ah, _reg, _val) \
76 (_ah)->reg_ops.write((_ah), (_val), (_reg))
77
78#define REG_READ(_ah, _reg) \
79 (_ah)->reg_ops.read((_ah), (_reg))
80
81#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
83
84#define REG_RMW(_ah, _reg, _set, _clr) \
85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
86
87#define ENABLE_REGWRITE_BUFFER(_ah) \
88 do { \
89 if ((_ah)->reg_ops.enable_write_buffer) \
90 (_ah)->reg_ops.enable_write_buffer((_ah)); \
91 } while (0)
92
93#define REGWRITE_BUFFER_FLUSH(_ah) \
94 do { \
95 if ((_ah)->reg_ops.write_flush) \
96 (_ah)->reg_ops.write_flush((_ah)); \
97 } while (0)
98
99#define PR_EEP(_s, _val) \
100 do { \
101 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
102 _s, (_val)); \
103 } while (0)
104
105#define SM(_v, _f) (((_v) << _f##_S) & _f)
106#define MS(_v, _f) (((_v) & _f) >> _f##_S)
107#define REG_RMW_FIELD(_a, _r, _f, _v) \
108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
109#define REG_READ_FIELD(_a, _r, _f) \
110 (((REG_READ(_a, _r) & _f) >> _f##_S))
111#define REG_SET_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, (_f), 0)
113#define REG_CLR_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, 0, (_f))
115
116#define DO_DELAY(x) do { \
117 if (((++(x) % 64) == 0) && \
118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
119 != ATH_USB)) \
120 udelay(1); \
121 } while (0)
122
123#define REG_WRITE_ARRAY(iniarray, column, regWr) \
124 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
125
126#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
127#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
128#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
129#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
130#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
131#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
132#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
134#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
135#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
136#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
137#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
138#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
139#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
140#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
141#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
142#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
143
144#define AR_GPIOD_MASK 0x00001FFF
145#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
146
147#define BASE_ACTIVATE_DELAY 100
148#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
149#define COEF_SCALE_S 24
150#define HT40_CHANNEL_CENTER_SHIFT 10
151
152#define ATH9K_ANTENNA0_CHAINMASK 0x1
153#define ATH9K_ANTENNA1_CHAINMASK 0x2
154
155#define ATH9K_NUM_DMA_DEBUG_REGS 8
156#define ATH9K_NUM_QUEUES 10
157
158#define MAX_RATE_POWER 63
159#define AH_WAIT_TIMEOUT 100000
160#define AH_TSF_WRITE_TIMEOUT 100
161#define AH_TIME_QUANTUM 10
162#define AR_KEYTABLE_SIZE 128
163#define POWER_UP_TIME 10000
164#define SPUR_RSSI_THRESH 40
165#define UPPER_5G_SUB_BAND_START 5700
166#define MID_5G_SUB_BAND_START 5400
167
168#define CAB_TIMEOUT_VAL 10
169#define BEACON_TIMEOUT_VAL 10
170#define MIN_BEACON_TIMEOUT_VAL 1
171#define SLEEP_SLOP 3
172
173#define INIT_CONFIG_STATUS 0x00000000
174#define INIT_RSSI_THR 0x00000700
175#define INIT_BCON_CNTRL_REG 0x00000000
176
177#define TU_TO_USEC(_tu) ((_tu) << 10)
178
179#define ATH9K_HW_RX_HP_QDEPTH 16
180#define ATH9K_HW_RX_LP_QDEPTH 128
181
182#define PAPRD_GAIN_TABLE_ENTRIES 32
183#define PAPRD_TABLE_SZ 24
184#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
185
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190
191#define KAL_FRAME_LEN 28
192#define KAL_FRAME_TYPE 0x2
193#define KAL_FRAME_SUB_TYPE 0x4
194#define KAL_DURATION_ID 0x3d
195#define KAL_NUM_DATA_WORDS 6
196#define KAL_NUM_DESC_WORDS 12
197#define KAL_ANTENNA_MODE 1
198#define KAL_TO_DS 1
199#define KAL_DELAY 4
200#define KAL_TIMEOUT 900
201
202#define MAX_PATTERN_SIZE 256
203#define MAX_PATTERN_MASK_SIZE 32
204#define MAX_NUM_PATTERN 8
205#define MAX_NUM_USER_PATTERN 6
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211
212#define AH_WOW_USER_PATTERN_EN BIT(0)
213#define AH_WOW_MAGIC_PATTERN_EN BIT(1)
214#define AH_WOW_LINK_CHANGE BIT(2)
215#define AH_WOW_BEACON_MISS BIT(3)
216
217enum ath_hw_txq_subtype {
218 ATH_TXQ_AC_BE = 0,
219 ATH_TXQ_AC_BK = 1,
220 ATH_TXQ_AC_VI = 2,
221 ATH_TXQ_AC_VO = 3,
222};
223
224enum ath_ini_subsys {
225 ATH_INI_PRE = 0,
226 ATH_INI_CORE,
227 ATH_INI_POST,
228 ATH_INI_NUM_SPLIT,
229};
230
231enum ath9k_hw_caps {
232 ATH9K_HW_CAP_HT = BIT(0),
233 ATH9K_HW_CAP_RFSILENT = BIT(1),
234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
236 ATH9K_HW_CAP_EDMA = BIT(4),
237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
238 ATH9K_HW_CAP_LDPC = BIT(6),
239 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
240 ATH9K_HW_CAP_SGI_20 = BIT(8),
241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
242 ATH9K_HW_CAP_2GHZ = BIT(11),
243 ATH9K_HW_CAP_5GHZ = BIT(12),
244 ATH9K_HW_CAP_APM = BIT(13),
245 ATH9K_HW_CAP_RTT = BIT(14),
246 ATH9K_HW_CAP_MCI = BIT(15),
247 ATH9K_HW_CAP_DFS = BIT(16),
248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
249 ATH9K_HW_CAP_PAPRD = BIT(18),
250};
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263struct ath9k_hw_capabilities {
264 u32 hw_caps;
265 u16 rts_aggr_limit;
266 u8 tx_chainmask;
267 u8 rx_chainmask;
268 u8 max_txchains;
269 u8 max_rxchains;
270 u8 num_gpio_pins;
271 u8 rx_hp_qdepth;
272 u8 rx_lp_qdepth;
273 u8 rx_status_len;
274 u8 tx_desc_len;
275 u8 txs_len;
276};
277
278struct ath9k_ops_config {
279 int dma_beacon_response_time;
280 int sw_beacon_response_time;
281 int additional_swba_backoff;
282 int ack_6mb;
283 u32 cwm_ignore_extcca;
284 bool pcieSerDesWrite;
285 u8 pcie_clock_req;
286 u32 pcie_waen;
287 u8 analog_shiftreg;
288 u32 ofdm_trig_low;
289 u32 ofdm_trig_high;
290 u32 cck_trig_high;
291 u32 cck_trig_low;
292 u32 enable_paprd;
293 int serialize_regmode;
294 bool rx_intr_mitigation;
295 bool tx_intr_mitigation;
296#define SPUR_DISABLE 0
297#define SPUR_ENABLE_IOCTL 1
298#define SPUR_ENABLE_EEPROM 2
299#define AR_SPUR_5413_1 1640
300#define AR_SPUR_5413_2 1200
301#define AR_NO_SPUR 0x8000
302#define AR_BASE_FREQ_2GHZ 2300
303#define AR_BASE_FREQ_5GHZ 4900
304#define AR_SPUR_FEEQ_BOUND_HT40 19
305#define AR_SPUR_FEEQ_BOUND_HT20 10
306 int spurmode;
307 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
308 u8 max_txtrig_level;
309 u16 ani_poll_interval;
310
311
312 u32 xlna_gpio;
313 bool xatten_margin_cfg;
314};
315
316enum ath9k_int {
317 ATH9K_INT_RX = 0x00000001,
318 ATH9K_INT_RXDESC = 0x00000002,
319 ATH9K_INT_RXHP = 0x00000001,
320 ATH9K_INT_RXLP = 0x00000002,
321 ATH9K_INT_RXNOFRM = 0x00000008,
322 ATH9K_INT_RXEOL = 0x00000010,
323 ATH9K_INT_RXORN = 0x00000020,
324 ATH9K_INT_TX = 0x00000040,
325 ATH9K_INT_TXDESC = 0x00000080,
326 ATH9K_INT_TIM_TIMER = 0x00000100,
327 ATH9K_INT_MCI = 0x00000200,
328 ATH9K_INT_BB_WATCHDOG = 0x00000400,
329 ATH9K_INT_TXURN = 0x00000800,
330 ATH9K_INT_MIB = 0x00001000,
331 ATH9K_INT_RXPHY = 0x00004000,
332 ATH9K_INT_RXKCM = 0x00008000,
333 ATH9K_INT_SWBA = 0x00010000,
334 ATH9K_INT_BMISS = 0x00040000,
335 ATH9K_INT_BNR = 0x00100000,
336 ATH9K_INT_TIM = 0x00200000,
337 ATH9K_INT_DTIM = 0x00400000,
338 ATH9K_INT_DTIMSYNC = 0x00800000,
339 ATH9K_INT_GPIO = 0x01000000,
340 ATH9K_INT_CABEND = 0x02000000,
341 ATH9K_INT_TSFOOR = 0x04000000,
342 ATH9K_INT_GENTIMER = 0x08000000,
343 ATH9K_INT_CST = 0x10000000,
344 ATH9K_INT_GTT = 0x20000000,
345 ATH9K_INT_FATAL = 0x40000000,
346 ATH9K_INT_GLOBAL = 0x80000000,
347 ATH9K_INT_BMISC = ATH9K_INT_TIM |
348 ATH9K_INT_DTIM |
349 ATH9K_INT_DTIMSYNC |
350 ATH9K_INT_TSFOOR |
351 ATH9K_INT_CABEND,
352 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
353 ATH9K_INT_RXDESC |
354 ATH9K_INT_RXEOL |
355 ATH9K_INT_RXORN |
356 ATH9K_INT_TXURN |
357 ATH9K_INT_TXDESC |
358 ATH9K_INT_MIB |
359 ATH9K_INT_RXPHY |
360 ATH9K_INT_RXKCM |
361 ATH9K_INT_SWBA |
362 ATH9K_INT_BMISS |
363 ATH9K_INT_GPIO,
364 ATH9K_INT_NOCARD = 0xffffffff
365};
366
367#define CHANNEL_CCK 0x00020
368#define CHANNEL_OFDM 0x00040
369#define CHANNEL_2GHZ 0x00080
370#define CHANNEL_5GHZ 0x00100
371#define CHANNEL_PASSIVE 0x00200
372#define CHANNEL_DYN 0x00400
373#define CHANNEL_HALF 0x04000
374#define CHANNEL_QUARTER 0x08000
375#define CHANNEL_HT20 0x10000
376#define CHANNEL_HT40PLUS 0x20000
377#define CHANNEL_HT40MINUS 0x40000
378
379#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
380#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
381#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
382#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
383#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
384#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
385#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
386#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
387#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
388#define CHANNEL_ALL \
389 (CHANNEL_OFDM| \
390 CHANNEL_CCK| \
391 CHANNEL_2GHZ | \
392 CHANNEL_5GHZ | \
393 CHANNEL_HT20 | \
394 CHANNEL_HT40PLUS | \
395 CHANNEL_HT40MINUS)
396
397#define MAX_RTT_TABLE_ENTRY 6
398#define MAX_IQCAL_MEASUREMENT 8
399#define MAX_CL_TAB_ENTRY 16
400#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
401
402struct ath9k_hw_cal_data {
403 u16 channel;
404 u32 channelFlags;
405 u32 chanmode;
406 int32_t CalValid;
407 int8_t iCoff;
408 int8_t qCoff;
409 bool rtt_done;
410 bool paprd_packet_sent;
411 bool paprd_done;
412 bool nfcal_pending;
413 bool nfcal_interference;
414 bool done_txiqcal_once;
415 bool done_txclcal_once;
416 u16 small_signal_gain[AR9300_MAX_CHAINS];
417 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
418 u32 num_measures[AR9300_MAX_CHAINS];
419 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
420 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
421 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
422 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
423};
424
425struct ath9k_channel {
426 struct ieee80211_channel *chan;
427 u16 channel;
428 u32 channelFlags;
429 u32 chanmode;
430 s16 noisefloor;
431};
432
433#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
434 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
435 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
436 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
437#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
438#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
439#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
440#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
441#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
442#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
443 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
444 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
445
446
447#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
448#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
449 ((_c)->chanmode == CHANNEL_G_HT20))
450#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
451 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
452 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
453 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
454#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
455
456enum ath9k_power_mode {
457 ATH9K_PM_AWAKE = 0,
458 ATH9K_PM_FULL_SLEEP,
459 ATH9K_PM_NETWORK_SLEEP,
460 ATH9K_PM_UNDEFINED
461};
462
463enum ser_reg_mode {
464 SER_REG_MODE_OFF = 0,
465 SER_REG_MODE_ON = 1,
466 SER_REG_MODE_AUTO = 2,
467};
468
469enum ath9k_rx_qtype {
470 ATH9K_RX_QUEUE_HP,
471 ATH9K_RX_QUEUE_LP,
472 ATH9K_RX_QUEUE_MAX,
473};
474
475struct ath9k_beacon_state {
476 u32 bs_nexttbtt;
477 u32 bs_nextdtim;
478 u32 bs_intval;
479#define ATH9K_TSFOOR_THRESHOLD 0x00004240
480 u32 bs_dtimperiod;
481 u16 bs_cfpperiod;
482 u16 bs_cfpmaxduration;
483 u32 bs_cfpnext;
484 u16 bs_timoffset;
485 u16 bs_bmissthreshold;
486 u32 bs_sleepduration;
487 u32 bs_tsfoor_threshold;
488};
489
490struct chan_centers {
491 u16 synth_center;
492 u16 ctl_center;
493 u16 ext_center;
494};
495
496enum {
497 ATH9K_RESET_POWER_ON,
498 ATH9K_RESET_WARM,
499 ATH9K_RESET_COLD,
500};
501
502struct ath9k_hw_version {
503 u32 magic;
504 u16 devid;
505 u16 subvendorid;
506 u32 macVersion;
507 u16 macRev;
508 u16 phyRev;
509 u16 analog5GhzRev;
510 u16 analog2GhzRev;
511 enum ath_usb_dev usbdev;
512};
513
514
515
516#define ATH_MAX_GEN_TIMER 16
517
518#define AR_GENTMR_BIT(_index) (1 << (_index))
519
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522
523
524#define debruijn32 0x077CB531U
525
526struct ath_gen_timer_configuration {
527 u32 next_addr;
528 u32 period_addr;
529 u32 mode_addr;
530 u32 mode_mask;
531};
532
533struct ath_gen_timer {
534 void (*trigger)(void *arg);
535 void (*overflow)(void *arg);
536 void *arg;
537 u8 index;
538};
539
540struct ath_gen_timer_table {
541 u32 gen_timer_index[32];
542 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
543 union {
544 unsigned long timer_bits;
545 u16 val;
546 } timer_mask;
547};
548
549struct ath_hw_antcomb_conf {
550 u8 main_lna_conf;
551 u8 alt_lna_conf;
552 u8 fast_div_bias;
553 u8 main_gaintb;
554 u8 alt_gaintb;
555 int lna1_lna2_delta;
556 u8 div_group;
557};
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579struct ath_hw_radar_conf {
580 unsigned int pulse_inband;
581 unsigned int pulse_inband_step;
582 unsigned int pulse_height;
583 unsigned int pulse_rssi;
584 unsigned int pulse_maxlen;
585
586 unsigned int radar_rssi;
587 unsigned int radar_inband;
588 int fir_power;
589
590 bool ext_channel;
591};
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615struct ath_hw_private_ops {
616
617 void (*init_cal_settings)(struct ath_hw *ah);
618 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
619
620 void (*init_mode_gain_regs)(struct ath_hw *ah);
621 void (*setup_calibration)(struct ath_hw *ah,
622 struct ath9k_cal_list *currCal);
623
624
625 int (*rf_set_freq)(struct ath_hw *ah,
626 struct ath9k_channel *chan);
627 void (*spur_mitigate_freq)(struct ath_hw *ah,
628 struct ath9k_channel *chan);
629 bool (*set_rf_regs)(struct ath_hw *ah,
630 struct ath9k_channel *chan,
631 u16 modesIndex);
632 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
633 void (*init_bb)(struct ath_hw *ah,
634 struct ath9k_channel *chan);
635 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
636 void (*olc_init)(struct ath_hw *ah);
637 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
638 void (*mark_phy_inactive)(struct ath_hw *ah);
639 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
640 bool (*rfbus_req)(struct ath_hw *ah);
641 void (*rfbus_done)(struct ath_hw *ah);
642 void (*restore_chainmask)(struct ath_hw *ah);
643 u32 (*compute_pll_control)(struct ath_hw *ah,
644 struct ath9k_channel *chan);
645 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
646 int param);
647 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
648 void (*set_radar_params)(struct ath_hw *ah,
649 struct ath_hw_radar_conf *conf);
650 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
651 u8 *ini_reloaded);
652
653
654 void (*ani_cache_ini_regs)(struct ath_hw *ah);
655};
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679struct ath_spec_scan {
680 bool enabled;
681 bool short_repeat;
682 bool endless;
683 u8 count;
684 u8 period;
685 u8 fft_period;
686};
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701struct ath_hw_ops {
702 void (*config_pci_powersave)(struct ath_hw *ah,
703 bool power_off);
704 void (*rx_enable)(struct ath_hw *ah);
705 void (*set_desc_link)(void *ds, u32 link);
706 bool (*calibrate)(struct ath_hw *ah,
707 struct ath9k_channel *chan,
708 u8 rxchainmask,
709 bool longcal);
710 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
711 void (*set_txdesc)(struct ath_hw *ah, void *ds,
712 struct ath_tx_info *i);
713 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
714 struct ath_tx_status *ts);
715 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
716 struct ath_hw_antcomb_conf *antconf);
717 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
718 struct ath_hw_antcomb_conf *antconf);
719 void (*antctrl_shared_chain_lnadiv)(struct ath_hw *hw, bool enable);
720 void (*spectral_scan_config)(struct ath_hw *ah,
721 struct ath_spec_scan *param);
722 void (*spectral_scan_trigger)(struct ath_hw *ah);
723 void (*spectral_scan_wait)(struct ath_hw *ah);
724};
725
726struct ath_nf_limits {
727 s16 max;
728 s16 min;
729 s16 nominal;
730};
731
732enum ath_cal_list {
733 TX_IQ_CAL = BIT(0),
734 TX_IQ_ON_AGC_CAL = BIT(1),
735 TX_CL_CAL = BIT(2),
736};
737
738
739#define AH_USE_EEPROM 0x1
740#define AH_UNPLUGGED 0x2
741#define AH_FASTCC 0x4
742
743struct ath_hw {
744 struct ath_ops reg_ops;
745
746 struct device *dev;
747 struct ieee80211_hw *hw;
748 struct ath_common common;
749 struct ath9k_hw_version hw_version;
750 struct ath9k_ops_config config;
751 struct ath9k_hw_capabilities caps;
752 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
753 struct ath9k_channel *curchan;
754
755 union {
756 struct ar5416_eeprom_def def;
757 struct ar5416_eeprom_4k map4k;
758 struct ar9287_eeprom map9287;
759 struct ar9300_eeprom ar9300_eep;
760 } eeprom;
761 const struct eeprom_ops *eep_ops;
762
763 bool sw_mgmt_crypto;
764 bool is_pciexpress;
765 bool aspm_enabled;
766 bool is_monitoring;
767 bool need_an_top2_fixup;
768 bool shared_chain_lnadiv;
769 u16 tx_trig_level;
770
771 u32 nf_regs[6];
772 struct ath_nf_limits nf_2g;
773 struct ath_nf_limits nf_5g;
774 u16 rfsilent;
775 u32 rfkill_gpio;
776 u32 rfkill_polarity;
777 u32 ah_flags;
778
779 bool reset_power_on;
780 bool htc_reset_init;
781
782 enum nl80211_iftype opmode;
783 enum ath9k_power_mode power_mode;
784
785 s8 noise;
786 struct ath9k_hw_cal_data *caldata;
787 struct ath9k_pacal_info pacal_info;
788 struct ar5416Stats stats;
789 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
790
791 enum ath9k_int imask;
792 u32 imrs2_reg;
793 u32 txok_interrupt_mask;
794 u32 txerr_interrupt_mask;
795 u32 txdesc_interrupt_mask;
796 u32 txeol_interrupt_mask;
797 u32 txurn_interrupt_mask;
798 atomic_t intr_ref_cnt;
799 bool chip_fullsleep;
800 u32 atim_window;
801 u32 modes_index;
802
803
804 u32 supp_cals;
805 struct ath9k_cal_list iq_caldata;
806 struct ath9k_cal_list adcgain_caldata;
807 struct ath9k_cal_list adcdc_caldata;
808 struct ath9k_cal_list *cal_list;
809 struct ath9k_cal_list *cal_list_last;
810 struct ath9k_cal_list *cal_list_curr;
811#define totalPowerMeasI meas0.unsign
812#define totalPowerMeasQ meas1.unsign
813#define totalIqCorrMeas meas2.sign
814#define totalAdcIOddPhase meas0.unsign
815#define totalAdcIEvenPhase meas1.unsign
816#define totalAdcQOddPhase meas2.unsign
817#define totalAdcQEvenPhase meas3.unsign
818#define totalAdcDcOffsetIOddPhase meas0.sign
819#define totalAdcDcOffsetIEvenPhase meas1.sign
820#define totalAdcDcOffsetQOddPhase meas2.sign
821#define totalAdcDcOffsetQEvenPhase meas3.sign
822 union {
823 u32 unsign[AR5416_MAX_CHAINS];
824 int32_t sign[AR5416_MAX_CHAINS];
825 } meas0;
826 union {
827 u32 unsign[AR5416_MAX_CHAINS];
828 int32_t sign[AR5416_MAX_CHAINS];
829 } meas1;
830 union {
831 u32 unsign[AR5416_MAX_CHAINS];
832 int32_t sign[AR5416_MAX_CHAINS];
833 } meas2;
834 union {
835 u32 unsign[AR5416_MAX_CHAINS];
836 int32_t sign[AR5416_MAX_CHAINS];
837 } meas3;
838 u16 cal_samples;
839 u8 enabled_cals;
840
841 u32 sta_id1_defaults;
842 u32 misc_mode;
843
844
845 struct ath_hw_private_ops private_ops;
846
847 struct ath_hw_ops ops;
848
849
850 u32 *analogBank6Data;
851
852 int coverage_class;
853 u32 slottime;
854 u32 globaltxtimeout;
855
856
857 u32 aniperiod;
858 enum ath9k_ani_cmd ani_function;
859 u32 ani_skip_count;
860 struct ar5416AniState ani;
861
862#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
863 struct ath_btcoex_hw btcoex_hw;
864#endif
865
866 u32 intr_txqs;
867 u8 txchainmask;
868 u8 rxchainmask;
869
870 struct ath_hw_radar_conf radar_conf;
871
872 u32 originalGain[22];
873 int initPDADC;
874 int PDADCdelta;
875 int led_pin;
876 u32 gpio_mask;
877 u32 gpio_val;
878
879 struct ar5416IniArray iniModes;
880 struct ar5416IniArray iniCommon;
881 struct ar5416IniArray iniBB_RfGain;
882 struct ar5416IniArray iniBank6;
883 struct ar5416IniArray iniAddac;
884 struct ar5416IniArray iniPcieSerdes;
885 struct ar5416IniArray iniPcieSerdesLowPower;
886 struct ar5416IniArray iniModesFastClock;
887 struct ar5416IniArray iniAdditional;
888 struct ar5416IniArray iniModesRxGain;
889 struct ar5416IniArray ini_modes_rx_gain_bounds;
890 struct ar5416IniArray iniModesTxGain;
891 struct ar5416IniArray iniCckfirNormal;
892 struct ar5416IniArray iniCckfirJapan2484;
893 struct ar5416IniArray iniModes_9271_ANI_reg;
894 struct ar5416IniArray ini_radio_post_sys2ant;
895 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
896 struct ar5416IniArray ini_modes_rxgain_bb_core;
897 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
898
899 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
900 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
901 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
902 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
903
904 u32 intr_gen_timer_trigger;
905 u32 intr_gen_timer_thresh;
906 struct ath_gen_timer_table hw_gen_timers;
907
908 struct ar9003_txs *ts_ring;
909 u32 ts_paddr_start;
910 u32 ts_paddr_end;
911 u16 ts_tail;
912 u16 ts_size;
913
914 u32 bb_watchdog_last_status;
915 u32 bb_watchdog_timeout_ms;
916 u8 bb_hang_rx_ofdm;
917
918 unsigned int paprd_target_power;
919 unsigned int paprd_training_power;
920 unsigned int paprd_ratemask;
921 unsigned int paprd_ratemask_ht40;
922 bool paprd_table_write_done;
923 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
924 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
925
926
927
928
929
930 u32 WARegVal;
931
932
933 u32 ent_mode;
934
935#ifdef CONFIG_PM_SLEEP
936 u32 wow_event_mask;
937#endif
938 bool is_clk_25mhz;
939 int (*get_mac_revision)(void);
940 int (*external_reset)(void);
941
942 const struct firmware *eeprom_blob;
943};
944
945struct ath_bus_ops {
946 enum ath_bus_type ath_bus_type;
947 void (*read_cachesize)(struct ath_common *common, int *csz);
948 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
949 void (*bt_coex_prep)(struct ath_common *common);
950 void (*aspm_init)(struct ath_common *common);
951};
952
953static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
954{
955 return &ah->common;
956}
957
958static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
959{
960 return &(ath9k_hw_common(ah)->regulatory);
961}
962
963static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
964{
965 return &ah->private_ops;
966}
967
968static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
969{
970 return &ah->ops;
971}
972
973static inline u8 get_streams(int mask)
974{
975 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
976}
977
978
979void ath9k_hw_deinit(struct ath_hw *ah);
980int ath9k_hw_init(struct ath_hw *ah);
981int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
982 struct ath9k_hw_cal_data *caldata, bool fastcc);
983int ath9k_hw_fill_cap_info(struct ath_hw *ah);
984u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
985
986
987void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
988u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
989void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
990 u32 ah_signal_type);
991void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
992void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
993
994
995void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
996 int hw_delay);
997bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
998void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
999 int column, unsigned int *writecnt);
1000u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1001u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1002 u8 phy, int kbps,
1003 u32 frameLen, u16 rateix, bool shortPreamble);
1004void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1005 struct ath9k_channel *chan,
1006 struct chan_centers *centers);
1007u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1008void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1009bool ath9k_hw_phy_disable(struct ath_hw *ah);
1010bool ath9k_hw_disable(struct ath_hw *ah);
1011void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1012void ath9k_hw_setopmode(struct ath_hw *ah);
1013void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1014void ath9k_hw_write_associd(struct ath_hw *ah);
1015u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1016u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1017void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1018void ath9k_hw_reset_tsf(struct ath_hw *ah);
1019void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1020void ath9k_hw_init_global_settings(struct ath_hw *ah);
1021u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1022void ath9k_hw_set11nmac2040(struct ath_hw *ah);
1023void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1024void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1025 const struct ath9k_beacon_state *bs);
1026bool ath9k_hw_check_alive(struct ath_hw *ah);
1027
1028bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1029
1030#ifdef CONFIG_ATH9K_DEBUGFS
1031void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
1032#else
1033static inline void ath9k_debug_sync_cause(struct ath_common *common,
1034 u32 sync_cause) {}
1035#endif
1036
1037
1038struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1039 void (*trigger)(void *),
1040 void (*overflow)(void *),
1041 void *arg,
1042 u8 timer_index);
1043void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1044 struct ath_gen_timer *timer,
1045 u32 timer_next,
1046 u32 timer_period);
1047void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1048
1049void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1050void ath_gen_timer_isr(struct ath_hw *hw);
1051
1052void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1053
1054
1055void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1056 u32 *coef_mantissa, u32 *coef_exponent);
1057void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1058 bool test);
1059
1060
1061
1062
1063
1064int ar9002_hw_rf_claim(struct ath_hw *ah);
1065void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1066
1067
1068
1069
1070
1071void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1072void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1073void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1074void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1075void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1076void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1077 struct ath9k_hw_cal_data *caldata,
1078 int chain);
1079int ar9003_paprd_create_curve(struct ath_hw *ah,
1080 struct ath9k_hw_cal_data *caldata, int chain);
1081void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1082int ar9003_paprd_init_table(struct ath_hw *ah);
1083bool ar9003_paprd_is_done(struct ath_hw *ah);
1084bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1085void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1086
1087
1088int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1089void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1090void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1091
1092void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1093void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1094
1095int ar9002_hw_attach_ops(struct ath_hw *ah);
1096void ar9003_hw_attach_ops(struct ath_hw *ah);
1097
1098void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1099
1100void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1101void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1102
1103#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1104static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1105{
1106 return ah->btcoex_hw.enabled;
1107}
1108static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1109{
1110 return ah->common.btcoex_enabled &&
1111 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1112
1113}
1114void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1115static inline enum ath_btcoex_scheme
1116ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1117{
1118 return ah->btcoex_hw.scheme;
1119}
1120#else
1121static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1122{
1123 return false;
1124}
1125static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1126{
1127 return false;
1128}
1129static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1130{
1131}
1132static inline enum ath_btcoex_scheme
1133ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1134{
1135 return ATH_BTCOEX_CFG_NONE;
1136}
1137#endif
1138
1139
1140#ifdef CONFIG_PM_SLEEP
1141const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1142void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1143 u8 *user_mask, int pattern_count,
1144 int pattern_len);
1145u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1146void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1147#else
1148static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1149{
1150 return NULL;
1151}
1152static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1153 u8 *user_pattern,
1154 u8 *user_mask,
1155 int pattern_count,
1156 int pattern_len)
1157{
1158}
1159static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1160{
1161 return 0;
1162}
1163static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1164{
1165}
1166#endif
1167
1168#define ATH9K_CLOCK_RATE_CCK 22
1169#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1170#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1171#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1172
1173#endif
1174