1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/types.h>
29
30#include "b43.h"
31#include "phy_n.h"
32#include "tables_nphy.h"
33#include "radio_2055.h"
34#include "radio_2056.h"
35#include "radio_2057.h"
36#include "main.h"
37
38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
62
63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
88};
89
90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
93};
94
95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
102
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
109
110
111
112
113
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
116{
117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
127
128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
129
130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
142
143
144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
167 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
168
169 if (off) {
170 b43_phy_mask(dev, en_addr, ~en_mask);
171 if (e)
172 b43_phy_mask(dev, val_addr, ~e->val_mask);
173 } else {
174 if (!core || (core & (1 << i))) {
175 b43_phy_set(dev, en_addr, en_mask);
176 if (e)
177 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
178 }
179 }
180 }
181}
182
183
184static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
185 u16 value, u8 core, bool off)
186{
187 int i;
188 u8 index = fls(field);
189 u8 addr, en_addr, val_addr;
190
191 B43_WARN_ON(field & (~(1 << (index - 1))));
192
193 if (dev->phy.rev >= 3) {
194 const struct nphy_rf_control_override_rev3 *rf_ctrl;
195 for (i = 0; i < 2; i++) {
196 if (index == 0 || index == 16) {
197 b43err(dev->wl,
198 "Unsupported RF Ctrl Override call\n");
199 return;
200 }
201
202 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
203 en_addr = B43_PHY_N((i == 0) ?
204 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
205 val_addr = B43_PHY_N((i == 0) ?
206 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
207
208 if (off) {
209 b43_phy_mask(dev, en_addr, ~(field));
210 b43_phy_mask(dev, val_addr,
211 ~(rf_ctrl->val_mask));
212 } else {
213 if (core == 0 || ((1 << i) & core)) {
214 b43_phy_set(dev, en_addr, field);
215 b43_phy_maskset(dev, val_addr,
216 ~(rf_ctrl->val_mask),
217 (value << rf_ctrl->val_shift));
218 }
219 }
220 }
221 } else {
222 const struct nphy_rf_control_override_rev2 *rf_ctrl;
223 if (off) {
224 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
225 value = 0;
226 } else {
227 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
228 }
229
230 for (i = 0; i < 2; i++) {
231 if (index <= 1 || index == 16) {
232 b43err(dev->wl,
233 "Unsupported RF Ctrl Override call\n");
234 return;
235 }
236
237 if (index == 2 || index == 10 ||
238 (index >= 13 && index <= 15)) {
239 core = 1;
240 }
241
242 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
243 addr = B43_PHY_N((i == 0) ?
244 rf_ctrl->addr0 : rf_ctrl->addr1);
245
246 if ((1 << i) & core)
247 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
248 (value << rf_ctrl->shift));
249
250 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
251 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
252 B43_NPHY_RFCTL_CMD_START);
253 udelay(1);
254 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
255 }
256 }
257}
258
259
260static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core)
263{
264 u8 i, j;
265 u16 reg, tmp, val;
266
267 B43_WARN_ON(dev->phy.rev < 3);
268
269 for (i = 0; i < 2; i++) {
270 if ((core == 1 && i == 1) || (core == 2 && !i))
271 continue;
272
273 reg = (i == 0) ?
274 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
275 b43_phy_set(dev, reg, 0x400);
276
277 switch (intc_override) {
278 case N_INTC_OVERRIDE_OFF:
279 b43_phy_write(dev, reg, 0);
280 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
281 break;
282 case N_INTC_OVERRIDE_TRSW:
283 if (!i) {
284 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
285 0xFC3F, (value << 6));
286 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
287 0xFFFE, 1);
288 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
289 B43_NPHY_RFCTL_CMD_START);
290 for (j = 0; j < 100; j++) {
291 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
292 j = 0;
293 break;
294 }
295 udelay(10);
296 }
297 if (j)
298 b43err(dev->wl,
299 "intc override timeout\n");
300 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
301 0xFFFE);
302 } else {
303 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
304 0xFC3F, (value << 6));
305 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
306 0xFFFE, 1);
307 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
308 B43_NPHY_RFCTL_CMD_RXTX);
309 for (j = 0; j < 100; j++) {
310 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
311 j = 0;
312 break;
313 }
314 udelay(10);
315 }
316 if (j)
317 b43err(dev->wl,
318 "intc override timeout\n");
319 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
320 0xFFFE);
321 }
322 break;
323 case N_INTC_OVERRIDE_PA:
324 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
325 tmp = 0x0020;
326 val = value << 5;
327 } else {
328 tmp = 0x0010;
329 val = value << 4;
330 }
331 b43_phy_maskset(dev, reg, ~tmp, val);
332 break;
333 case N_INTC_OVERRIDE_EXT_LNA_PU:
334 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
335 tmp = 0x0001;
336 val = value;
337 } else {
338 tmp = 0x0004;
339 val = value << 2;
340 }
341 b43_phy_maskset(dev, reg, ~tmp, val);
342 break;
343 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
344 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
345 tmp = 0x0002;
346 val = value << 1;
347 } else {
348 tmp = 0x0008;
349 val = value << 3;
350 }
351 b43_phy_maskset(dev, reg, ~tmp, val);
352 break;
353 }
354 }
355}
356
357
358
359
360
361
362static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
363 const u16 *clip_st)
364{
365 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
366 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
367}
368
369
370static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
371{
372 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
373 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
374}
375
376
377static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
378{
379 u16 tmp;
380
381 if (dev->dev->core_rev == 16)
382 b43_mac_suspend(dev);
383
384 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
385 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
386 B43_NPHY_CLASSCTL_WAITEDEN);
387 tmp &= ~mask;
388 tmp |= (val & mask);
389 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
390
391 if (dev->dev->core_rev == 16)
392 b43_mac_enable(dev);
393
394 return tmp;
395}
396
397
398static void b43_nphy_reset_cca(struct b43_wldev *dev)
399{
400 u16 bbcfg;
401
402 b43_phy_force_clock(dev, 1);
403 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
404 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
405 udelay(1);
406 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
407 b43_phy_force_clock(dev, 0);
408 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
409}
410
411
412static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
413{
414 struct b43_phy *phy = &dev->phy;
415 struct b43_phy_n *nphy = phy->n;
416
417 if (enable) {
418 static const u16 clip[] = { 0xFFFF, 0xFFFF };
419 if (nphy->deaf_count++ == 0) {
420 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
421 b43_nphy_classifier(dev, 0x7, 0);
422 b43_nphy_read_clip_detection(dev, nphy->clip_state);
423 b43_nphy_write_clip_detection(dev, clip);
424 }
425 b43_nphy_reset_cca(dev);
426 } else {
427 if (--nphy->deaf_count == 0) {
428 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
429 b43_nphy_write_clip_detection(dev, nphy->clip_state);
430 }
431 }
432}
433
434
435static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
436{
437 struct b43_phy_n *nphy = dev->phy.n;
438
439 u8 i;
440 s16 tmp;
441 u16 data[4];
442 s16 gain[2];
443 u16 minmax[2];
444 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
445
446 if (nphy->hang_avoid)
447 b43_nphy_stay_in_carrier_search(dev, 1);
448
449 if (nphy->gain_boost) {
450 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
451 gain[0] = 6;
452 gain[1] = 6;
453 } else {
454 tmp = 40370 - 315 * dev->phy.channel;
455 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
456 tmp = 23242 - 224 * dev->phy.channel;
457 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
458 }
459 } else {
460 gain[0] = 0;
461 gain[1] = 0;
462 }
463
464 for (i = 0; i < 2; i++) {
465 if (nphy->elna_gain_config) {
466 data[0] = 19 + gain[i];
467 data[1] = 25 + gain[i];
468 data[2] = 25 + gain[i];
469 data[3] = 25 + gain[i];
470 } else {
471 data[0] = lna_gain[0] + gain[i];
472 data[1] = lna_gain[1] + gain[i];
473 data[2] = lna_gain[2] + gain[i];
474 data[3] = lna_gain[3] + gain[i];
475 }
476 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
477
478 minmax[i] = 23 + gain[i];
479 }
480
481 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
482 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
483 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
484 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
485
486 if (nphy->hang_avoid)
487 b43_nphy_stay_in_carrier_search(dev, 0);
488}
489
490
491static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
492 u8 *events, u8 *delays, u8 length)
493{
494 struct b43_phy_n *nphy = dev->phy.n;
495 u8 i;
496 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
497 u16 offset1 = cmd << 4;
498 u16 offset2 = offset1 + 0x80;
499
500 if (nphy->hang_avoid)
501 b43_nphy_stay_in_carrier_search(dev, true);
502
503 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
504 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
505
506 for (i = length; i < 16; i++) {
507 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
508 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
509 }
510
511 if (nphy->hang_avoid)
512 b43_nphy_stay_in_carrier_search(dev, false);
513}
514
515
516
517
518
519
520static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
521{
522 struct b43_phy *phy = &dev->phy;
523 u16 tmp;
524
525 if (phy->radio_rev == 5) {
526 b43_phy_mask(dev, 0x342, ~0x2);
527 udelay(10);
528 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
529 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
530 }
531
532 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
533 udelay(10);
534 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
535 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
536 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
537 return 0;
538 }
539 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
540 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
541 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
542
543 if (phy->radio_rev == 5) {
544 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
545 b43_radio_mask(dev, 0x1ca, ~0x2);
546 }
547 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
548 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
549 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
550 tmp << 2);
551 }
552
553 return tmp & 0x3e;
554}
555
556
557static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
558{
559 struct b43_phy *phy = &dev->phy;
560 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
561 phy->radio_rev == 6);
562 u16 tmp;
563
564 if (special) {
565 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
566 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
567 } else {
568 b43_radio_write(dev, 0x1AE, 0x61);
569 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
570 }
571 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
572 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
573 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
574 5000000))
575 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
576 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
577 if (special) {
578 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
579 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
580 } else {
581 b43_radio_write(dev, 0x1AE, 0x69);
582 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
583 }
584 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
585 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
586 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
587 5000000))
588 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
589 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
590 if (special) {
591 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
592 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
593 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
594 } else {
595 b43_radio_write(dev, 0x1AE, 0x73);
596 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
597 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
598 }
599 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
600 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
601 5000000)) {
602 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
603 return 0;
604 }
605 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
606 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
607 return tmp;
608}
609
610static void b43_radio_2057_init_pre(struct b43_wldev *dev)
611{
612 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
613
614 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
615 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
616 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
617}
618
619static void b43_radio_2057_init_post(struct b43_wldev *dev)
620{
621 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
622
623 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
624 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
625 mdelay(2);
626 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
627 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
628
629 if (dev->phy.n->init_por) {
630 b43_radio_2057_rcal(dev);
631 b43_radio_2057_rccal(dev);
632 }
633 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
634
635 dev->phy.n->init_por = false;
636}
637
638
639static void b43_radio_2057_init(struct b43_wldev *dev)
640{
641 b43_radio_2057_init_pre(dev);
642 r2057_upload_inittabs(dev);
643 b43_radio_2057_init_post(dev);
644}
645
646
647
648
649
650static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
651 const struct b43_nphy_channeltab_entry_rev3 *e)
652{
653 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
654 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
655 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
656 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
657 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
658 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
659 e->radio_syn_pll_loopfilter1);
660 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
661 e->radio_syn_pll_loopfilter2);
662 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
663 e->radio_syn_pll_loopfilter3);
664 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
665 e->radio_syn_pll_loopfilter4);
666 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
667 e->radio_syn_pll_loopfilter5);
668 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
669 e->radio_syn_reserved_addr27);
670 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
671 e->radio_syn_reserved_addr28);
672 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
673 e->radio_syn_reserved_addr29);
674 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
675 e->radio_syn_logen_vcobuf1);
676 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
677 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
678 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
679
680 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
681 e->radio_rx0_lnaa_tune);
682 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
683 e->radio_rx0_lnag_tune);
684
685 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
686 e->radio_tx0_intpaa_boost_tune);
687 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
688 e->radio_tx0_intpag_boost_tune);
689 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
690 e->radio_tx0_pada_boost_tune);
691 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
692 e->radio_tx0_padg_boost_tune);
693 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
694 e->radio_tx0_pgaa_boost_tune);
695 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
696 e->radio_tx0_pgag_boost_tune);
697 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
698 e->radio_tx0_mixa_boost_tune);
699 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
700 e->radio_tx0_mixg_boost_tune);
701
702 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
703 e->radio_rx1_lnaa_tune);
704 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
705 e->radio_rx1_lnag_tune);
706
707 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
708 e->radio_tx1_intpaa_boost_tune);
709 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
710 e->radio_tx1_intpag_boost_tune);
711 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
712 e->radio_tx1_pada_boost_tune);
713 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
714 e->radio_tx1_padg_boost_tune);
715 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
716 e->radio_tx1_pgaa_boost_tune);
717 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
718 e->radio_tx1_pgag_boost_tune);
719 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
720 e->radio_tx1_mixa_boost_tune);
721 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
722 e->radio_tx1_mixg_boost_tune);
723}
724
725
726static void b43_radio_2056_setup(struct b43_wldev *dev,
727 const struct b43_nphy_channeltab_entry_rev3 *e)
728{
729 struct ssb_sprom *sprom = dev->dev->bus_sprom;
730 enum ieee80211_band band = b43_current_band(dev->wl);
731 u16 offset;
732 u8 i;
733 u16 bias, cbias;
734 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
735 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
736
737 B43_WARN_ON(dev->phy.rev < 3);
738
739 b43_chantab_radio_2056_upload(dev, e);
740 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
741
742 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
743 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
744 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
745 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
746 if (dev->dev->chip_id == 0x4716) {
747 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
748 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
749 } else {
750 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
751 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
752 }
753 }
754 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
755 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
756 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
757 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
758 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
759 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
760 }
761
762 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
763 for (i = 0; i < 2; i++) {
764 offset = i ? B2056_TX1 : B2056_TX0;
765 if (dev->phy.rev >= 5) {
766 b43_radio_write(dev,
767 offset | B2056_TX_PADG_IDAC, 0xcc);
768
769 if (dev->dev->chip_id == 0x4716) {
770 bias = 0x40;
771 cbias = 0x45;
772 pag_boost = 0x5;
773 pgag_boost = 0x33;
774 mixg_boost = 0x55;
775 } else {
776 bias = 0x25;
777 cbias = 0x20;
778 pag_boost = 0x4;
779 pgag_boost = 0x03;
780 mixg_boost = 0x65;
781 }
782 padg_boost = 0x77;
783
784 b43_radio_write(dev,
785 offset | B2056_TX_INTPAG_IMAIN_STAT,
786 bias);
787 b43_radio_write(dev,
788 offset | B2056_TX_INTPAG_IAUX_STAT,
789 bias);
790 b43_radio_write(dev,
791 offset | B2056_TX_INTPAG_CASCBIAS,
792 cbias);
793 b43_radio_write(dev,
794 offset | B2056_TX_INTPAG_BOOST_TUNE,
795 pag_boost);
796 b43_radio_write(dev,
797 offset | B2056_TX_PGAG_BOOST_TUNE,
798 pgag_boost);
799 b43_radio_write(dev,
800 offset | B2056_TX_PADG_BOOST_TUNE,
801 padg_boost);
802 b43_radio_write(dev,
803 offset | B2056_TX_MIXG_BOOST_TUNE,
804 mixg_boost);
805 } else {
806 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
807 b43_radio_write(dev,
808 offset | B2056_TX_INTPAG_IMAIN_STAT,
809 bias);
810 b43_radio_write(dev,
811 offset | B2056_TX_INTPAG_IAUX_STAT,
812 bias);
813 b43_radio_write(dev,
814 offset | B2056_TX_INTPAG_CASCBIAS,
815 0x30);
816 }
817 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
818 }
819 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
820 u16 freq = dev->phy.channel_freq;
821 if (freq < 5100) {
822 paa_boost = 0xA;
823 pada_boost = 0x77;
824 pgaa_boost = 0xF;
825 mixa_boost = 0xF;
826 } else if (freq < 5340) {
827 paa_boost = 0x8;
828 pada_boost = 0x77;
829 pgaa_boost = 0xFB;
830 mixa_boost = 0xF;
831 } else if (freq < 5650) {
832 paa_boost = 0x0;
833 pada_boost = 0x77;
834 pgaa_boost = 0xB;
835 mixa_boost = 0xF;
836 } else {
837 paa_boost = 0x0;
838 pada_boost = 0x77;
839 if (freq != 5825)
840 pgaa_boost = -(freq - 18) / 36 + 168;
841 else
842 pgaa_boost = 6;
843 mixa_boost = 0xF;
844 }
845
846 for (i = 0; i < 2; i++) {
847 offset = i ? B2056_TX1 : B2056_TX0;
848
849 b43_radio_write(dev,
850 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
851 b43_radio_write(dev,
852 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
853 b43_radio_write(dev,
854 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
855 b43_radio_write(dev,
856 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
857 b43_radio_write(dev,
858 offset | B2056_TX_TXSPARE1, 0x30);
859 b43_radio_write(dev,
860 offset | B2056_TX_PA_SPARE2, 0xee);
861 b43_radio_write(dev,
862 offset | B2056_TX_PADA_CASCBIAS, 0x03);
863 b43_radio_write(dev,
864 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
865 b43_radio_write(dev,
866 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
867 b43_radio_write(dev,
868 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
869 }
870 }
871
872 udelay(50);
873
874 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
875 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
876 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
877 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
878 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
879 udelay(300);
880}
881
882static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
883{
884 struct b43_phy *phy = &dev->phy;
885 u16 mast2, tmp;
886
887 if (phy->rev != 3)
888 return 0;
889
890 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
891 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
892
893 udelay(10);
894 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
895 udelay(10);
896 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
897
898 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
899 1000000)) {
900 b43err(dev->wl, "Radio recalibration timeout\n");
901 return 0;
902 }
903
904 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
905 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
906 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
907
908 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
909
910 return tmp & 0x1f;
911}
912
913static void b43_radio_init2056_pre(struct b43_wldev *dev)
914{
915 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
916 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
917
918 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
919 B43_NPHY_RFCTL_CMD_OEPORFORCE);
920 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
921 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
922 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
923 B43_NPHY_RFCTL_CMD_CHIP0PU);
924}
925
926static void b43_radio_init2056_post(struct b43_wldev *dev)
927{
928 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
929 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
930 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
931 msleep(1);
932 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
933 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
934 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
935 if (dev->phy.n->init_por)
936 b43_radio_2056_rcal(dev);
937}
938
939
940
941
942
943static void b43_radio_init2056(struct b43_wldev *dev)
944{
945 b43_radio_init2056_pre(dev);
946 b2056_upload_inittabs(dev, 0, 0);
947 b43_radio_init2056_post(dev);
948
949 dev->phy.n->init_por = false;
950}
951
952
953
954
955
956static void b43_chantab_radio_upload(struct b43_wldev *dev,
957 const struct b43_nphy_channeltab_entry_rev2 *e)
958{
959 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
960 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
961 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
962 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
963 b43_read32(dev, B43_MMIO_MACCTL);
964
965 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
966 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
967 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
968 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
969 b43_read32(dev, B43_MMIO_MACCTL);
970
971 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
972 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
973 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
974 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
975 b43_read32(dev, B43_MMIO_MACCTL);
976
977 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
978 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
979 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
980 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
981 b43_read32(dev, B43_MMIO_MACCTL);
982
983 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
984 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
985 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
986 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
987 b43_read32(dev, B43_MMIO_MACCTL);
988
989 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
990 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
991}
992
993
994static void b43_radio_2055_setup(struct b43_wldev *dev,
995 const struct b43_nphy_channeltab_entry_rev2 *e)
996{
997 B43_WARN_ON(dev->phy.rev >= 3);
998
999 b43_chantab_radio_upload(dev, e);
1000 udelay(50);
1001 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1002 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1003 b43_read32(dev, B43_MMIO_MACCTL);
1004 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1005 udelay(300);
1006}
1007
1008static void b43_radio_init2055_pre(struct b43_wldev *dev)
1009{
1010 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1011 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1012 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1013 B43_NPHY_RFCTL_CMD_CHIP0PU |
1014 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1015 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1016 B43_NPHY_RFCTL_CMD_PORFORCE);
1017}
1018
1019static void b43_radio_init2055_post(struct b43_wldev *dev)
1020{
1021 struct b43_phy_n *nphy = dev->phy.n;
1022 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1023 bool workaround = false;
1024
1025 if (sprom->revision < 4)
1026 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1027 && dev->dev->board_type == SSB_BOARD_CB2_4321
1028 && dev->dev->board_rev >= 0x41);
1029 else
1030 workaround =
1031 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1032
1033 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1034 if (workaround) {
1035 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1036 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1037 }
1038 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1039 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1040 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1041 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1042 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1043 msleep(1);
1044 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1045 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1046 b43err(dev->wl, "radio post init timeout\n");
1047 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1048 b43_switch_channel(dev, dev->phy.channel);
1049 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1050 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1051 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1052 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1053 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1054 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1055 if (!nphy->gain_boost) {
1056 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1057 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1058 } else {
1059 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1060 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1061 }
1062 udelay(2);
1063}
1064
1065
1066
1067
1068
1069static void b43_radio_init2055(struct b43_wldev *dev)
1070{
1071 b43_radio_init2055_pre(dev);
1072 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1073
1074 b2055_upload_inittab(dev, 0, 0);
1075 } else {
1076 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1077 b2055_upload_inittab(dev, ghz5, 0);
1078 }
1079 b43_radio_init2055_post(dev);
1080}
1081
1082
1083
1084
1085
1086
1087static int b43_nphy_load_samples(struct b43_wldev *dev,
1088 struct b43_c32 *samples, u16 len) {
1089 struct b43_phy_n *nphy = dev->phy.n;
1090 u16 i;
1091 u32 *data;
1092
1093 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1094 if (!data) {
1095 b43err(dev->wl, "allocation for samples loading failed\n");
1096 return -ENOMEM;
1097 }
1098 if (nphy->hang_avoid)
1099 b43_nphy_stay_in_carrier_search(dev, 1);
1100
1101 for (i = 0; i < len; i++) {
1102 data[i] = (samples[i].i & 0x3FF << 10);
1103 data[i] |= samples[i].q & 0x3FF;
1104 }
1105 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1106
1107 kfree(data);
1108 if (nphy->hang_avoid)
1109 b43_nphy_stay_in_carrier_search(dev, 0);
1110 return 0;
1111}
1112
1113
1114static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1115 bool test)
1116{
1117 int i;
1118 u16 bw, len, rot, angle;
1119 struct b43_c32 *samples;
1120
1121
1122 bw = (dev->phy.is_40mhz) ? 40 : 20;
1123 len = bw << 3;
1124
1125 if (test) {
1126 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1127 bw = 82;
1128 else
1129 bw = 80;
1130
1131 if (dev->phy.is_40mhz)
1132 bw <<= 1;
1133
1134 len = bw << 1;
1135 }
1136
1137 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1138 if (!samples) {
1139 b43err(dev->wl, "allocation for samples generation failed\n");
1140 return 0;
1141 }
1142 rot = (((freq * 36) / bw) << 16) / 100;
1143 angle = 0;
1144
1145 for (i = 0; i < len; i++) {
1146 samples[i] = b43_cordic(angle);
1147 angle += rot;
1148 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1149 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1150 }
1151
1152 i = b43_nphy_load_samples(dev, samples, len);
1153 kfree(samples);
1154 return (i < 0) ? 0 : len;
1155}
1156
1157
1158static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1159 u16 wait, bool iqmode, bool dac_test)
1160{
1161 struct b43_phy_n *nphy = dev->phy.n;
1162 int i;
1163 u16 seq_mode;
1164 u32 tmp;
1165
1166 if (nphy->hang_avoid)
1167 b43_nphy_stay_in_carrier_search(dev, true);
1168
1169 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1170 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1171 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1172 }
1173
1174 if (!dev->phy.is_40mhz)
1175 tmp = 0x6464;
1176 else
1177 tmp = 0x4747;
1178 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1179
1180 if (nphy->hang_avoid)
1181 b43_nphy_stay_in_carrier_search(dev, false);
1182
1183 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1184
1185 if (loops != 0xFFFF)
1186 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1187 else
1188 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1189
1190 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1191
1192 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1193
1194 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1195 if (iqmode) {
1196 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1197 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1198 } else {
1199 if (dac_test)
1200 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1201 else
1202 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1203 }
1204 for (i = 0; i < 100; i++) {
1205 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1206 i = 0;
1207 break;
1208 }
1209 udelay(10);
1210 }
1211 if (i)
1212 b43err(dev->wl, "run samples timeout\n");
1213
1214 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1215}
1216
1217
1218
1219
1220
1221
1222static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1223 s8 offset, u8 core,
1224 enum n_rail_type rail,
1225 enum n_rssi_type rssi_type)
1226{
1227 u16 tmp;
1228 bool core1or5 = (core == 1) || (core == 5);
1229 bool core2or5 = (core == 2) || (core == 5);
1230
1231 offset = clamp_val(offset, -32, 31);
1232 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1233
1234 switch (rssi_type) {
1235 case N_RSSI_NB:
1236 if (core1or5 && rail == N_RAIL_I)
1237 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1238 if (core1or5 && rail == N_RAIL_Q)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1240 if (core2or5 && rail == N_RAIL_I)
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1242 if (core2or5 && rail == N_RAIL_Q)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1244 break;
1245 case N_RSSI_W1:
1246 if (core1or5 && rail == N_RAIL_I)
1247 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1248 if (core1or5 && rail == N_RAIL_Q)
1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1250 if (core2or5 && rail == N_RAIL_I)
1251 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1252 if (core2or5 && rail == N_RAIL_Q)
1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1254 break;
1255 case N_RSSI_W2:
1256 if (core1or5 && rail == N_RAIL_I)
1257 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1258 if (core1or5 && rail == N_RAIL_Q)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1260 if (core2or5 && rail == N_RAIL_I)
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1262 if (core2or5 && rail == N_RAIL_Q)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1264 break;
1265 case N_RSSI_TBD:
1266 if (core1or5 && rail == N_RAIL_I)
1267 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1268 if (core1or5 && rail == N_RAIL_Q)
1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1270 if (core2or5 && rail == N_RAIL_I)
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1272 if (core2or5 && rail == N_RAIL_Q)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1274 break;
1275 case N_RSSI_IQ:
1276 if (core1or5 && rail == N_RAIL_I)
1277 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1278 if (core1or5 && rail == N_RAIL_Q)
1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1280 if (core2or5 && rail == N_RAIL_I)
1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1282 if (core2or5 && rail == N_RAIL_Q)
1283 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1284 break;
1285 case N_RSSI_TSSI_2G:
1286 if (core1or5)
1287 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1288 if (core2or5)
1289 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1290 break;
1291 case N_RSSI_TSSI_5G:
1292 if (core1or5)
1293 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1294 if (core2or5)
1295 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1296 break;
1297 }
1298}
1299
1300static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1301 enum n_rssi_type rssi_type)
1302{
1303 u8 i;
1304 u16 reg, val;
1305
1306 if (code == 0) {
1307 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1308 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1309 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1310 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1311 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1312 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1313 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1314 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1315 } else {
1316 for (i = 0; i < 2; i++) {
1317 if ((code == 1 && i == 1) || (code == 2 && !i))
1318 continue;
1319
1320 reg = (i == 0) ?
1321 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1322 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1323
1324 if (rssi_type == N_RSSI_W1 ||
1325 rssi_type == N_RSSI_W2 ||
1326 rssi_type == N_RSSI_NB) {
1327 reg = (i == 0) ?
1328 B43_NPHY_AFECTL_C1 :
1329 B43_NPHY_AFECTL_C2;
1330 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1331
1332 reg = (i == 0) ?
1333 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1334 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1335 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1336
1337 if (rssi_type == N_RSSI_W1)
1338 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1339 else if (rssi_type == N_RSSI_W2)
1340 val = 16;
1341 else
1342 val = 32;
1343 b43_phy_set(dev, reg, val);
1344
1345 reg = (i == 0) ?
1346 B43_NPHY_TXF_40CO_B1S0 :
1347 B43_NPHY_TXF_40CO_B32S1;
1348 b43_phy_set(dev, reg, 0x0020);
1349 } else {
1350 if (rssi_type == N_RSSI_TBD)
1351 val = 0x0100;
1352 else if (rssi_type == N_RSSI_IQ)
1353 val = 0x0200;
1354 else
1355 val = 0x0300;
1356
1357 reg = (i == 0) ?
1358 B43_NPHY_AFECTL_C1 :
1359 B43_NPHY_AFECTL_C2;
1360
1361 b43_phy_maskset(dev, reg, 0xFCFF, val);
1362 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1363
1364 if (rssi_type != N_RSSI_IQ &&
1365 rssi_type != N_RSSI_TBD) {
1366 enum ieee80211_band band =
1367 b43_current_band(dev->wl);
1368
1369 if (b43_nphy_ipa(dev))
1370 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1371 else
1372 val = 0x11;
1373 reg = (i == 0) ? 0x2000 : 0x3000;
1374 reg |= B2055_PADDRV;
1375 b43_radio_write(dev, reg, val);
1376
1377 reg = (i == 0) ?
1378 B43_NPHY_AFECTL_OVER1 :
1379 B43_NPHY_AFECTL_OVER;
1380 b43_phy_set(dev, reg, 0x0200);
1381 }
1382 }
1383 }
1384 }
1385}
1386
1387static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1388 enum n_rssi_type rssi_type)
1389{
1390 u16 val;
1391 bool rssi_w1_w2_nb = false;
1392
1393 switch (rssi_type) {
1394 case N_RSSI_W1:
1395 case N_RSSI_W2:
1396 case N_RSSI_NB:
1397 val = 0;
1398 rssi_w1_w2_nb = true;
1399 break;
1400 case N_RSSI_TBD:
1401 val = 1;
1402 break;
1403 case N_RSSI_IQ:
1404 val = 2;
1405 break;
1406 default:
1407 val = 3;
1408 }
1409
1410 val = (val << 12) | (val << 14);
1411 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1412 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1413
1414 if (rssi_w1_w2_nb) {
1415 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1416 (rssi_type + 1) << 4);
1417 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1418 (rssi_type + 1) << 4);
1419 }
1420
1421 if (code == 0) {
1422 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1423 if (rssi_w1_w2_nb) {
1424 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1425 ~(B43_NPHY_RFCTL_CMD_RXEN |
1426 B43_NPHY_RFCTL_CMD_CORESEL));
1427 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1428 ~(0x1 << 12 |
1429 0x1 << 5 |
1430 0x1 << 1 |
1431 0x1));
1432 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1433 ~B43_NPHY_RFCTL_CMD_START);
1434 udelay(20);
1435 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1436 }
1437 } else {
1438 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1439 if (rssi_w1_w2_nb) {
1440 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1441 ~(B43_NPHY_RFCTL_CMD_RXEN |
1442 B43_NPHY_RFCTL_CMD_CORESEL),
1443 (B43_NPHY_RFCTL_CMD_RXEN |
1444 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1445 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1446 (0x1 << 12 |
1447 0x1 << 5 |
1448 0x1 << 1 |
1449 0x1));
1450 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1451 B43_NPHY_RFCTL_CMD_START);
1452 udelay(20);
1453 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1454 }
1455 }
1456}
1457
1458
1459static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1460 enum n_rssi_type type)
1461{
1462 if (dev->phy.rev >= 3)
1463 b43_nphy_rev3_rssi_select(dev, code, type);
1464 else
1465 b43_nphy_rev2_rssi_select(dev, code, type);
1466}
1467
1468
1469static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1470 enum n_rssi_type rssi_type, u8 *buf)
1471{
1472 int i;
1473 for (i = 0; i < 2; i++) {
1474 if (rssi_type == N_RSSI_NB) {
1475 if (i == 0) {
1476 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1477 0xFC, buf[0]);
1478 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1479 0xFC, buf[1]);
1480 } else {
1481 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1482 0xFC, buf[2 * i]);
1483 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1484 0xFC, buf[2 * i + 1]);
1485 }
1486 } else {
1487 if (i == 0)
1488 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1489 0xF3, buf[0] << 2);
1490 else
1491 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1492 0xF3, buf[2 * i + 1] << 2);
1493 }
1494 }
1495}
1496
1497
1498static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1499 s32 *buf, u8 nsamp)
1500{
1501 int i;
1502 int out;
1503 u16 save_regs_phy[9];
1504 u16 s[2];
1505
1506 if (dev->phy.rev >= 3) {
1507 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1508 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1509 save_regs_phy[2] = b43_phy_read(dev,
1510 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1511 save_regs_phy[3] = b43_phy_read(dev,
1512 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1513 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1514 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1515 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1516 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1517 save_regs_phy[8] = 0;
1518 } else {
1519 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1520 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1521 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1522 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1523 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1524 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1525 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1526 save_regs_phy[7] = 0;
1527 save_regs_phy[8] = 0;
1528 }
1529
1530 b43_nphy_rssi_select(dev, 5, rssi_type);
1531
1532 if (dev->phy.rev < 2) {
1533 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1534 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1535 }
1536
1537 for (i = 0; i < 4; i++)
1538 buf[i] = 0;
1539
1540 for (i = 0; i < nsamp; i++) {
1541 if (dev->phy.rev < 2) {
1542 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1543 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1544 } else {
1545 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1546 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1547 }
1548
1549 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1550 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1551 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1552 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1553 }
1554 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1555 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1556
1557 if (dev->phy.rev < 2)
1558 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1559
1560 if (dev->phy.rev >= 3) {
1561 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1562 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1563 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1564 save_regs_phy[2]);
1565 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1566 save_regs_phy[3]);
1567 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1568 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1569 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1570 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1571 } else {
1572 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1573 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1574 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1575 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1576 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1577 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1578 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1579 }
1580
1581 return out;
1582}
1583
1584
1585static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1586{
1587 struct b43_phy_n *nphy = dev->phy.n;
1588
1589 u16 saved_regs_phy_rfctl[2];
1590 u16 saved_regs_phy[13];
1591 u16 regs_to_store[] = {
1592 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1593 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1594 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1595 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1596 B43_NPHY_RFCTL_CMD,
1597 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1598 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1599 };
1600
1601 u16 class;
1602
1603 u16 clip_state[2];
1604 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1605
1606 u8 vcm_final = 0;
1607 s32 offset[4];
1608 s32 results[8][4] = { };
1609 s32 results_min[4] = { };
1610 s32 poll_results[4] = { };
1611
1612 u16 *rssical_radio_regs = NULL;
1613 u16 *rssical_phy_regs = NULL;
1614
1615 u16 r;
1616 u8 rx_core_state;
1617 int core, i, j, vcm;
1618
1619 class = b43_nphy_classifier(dev, 0, 0);
1620 b43_nphy_classifier(dev, 7, 4);
1621 b43_nphy_read_clip_detection(dev, clip_state);
1622 b43_nphy_write_clip_detection(dev, clip_off);
1623
1624 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1625 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1626 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1627 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1628
1629 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1630 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
1631 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1632 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1633 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1634 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1635
1636 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1637 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1638 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1639 } else {
1640 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1641 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1642 }
1643
1644 rx_core_state = b43_nphy_get_rx_core_state(dev);
1645 for (core = 0; core < 2; core++) {
1646 if (!(rx_core_state & (1 << core)))
1647 continue;
1648 r = core ? B2056_RX1 : B2056_RX0;
1649 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1650 N_RSSI_NB);
1651 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1652 N_RSSI_NB);
1653
1654
1655 for (vcm = 0; vcm < 8; vcm++) {
1656 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1657 vcm << 2);
1658 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1659 }
1660
1661
1662 for (i = 0; i < 4; i += 2) {
1663 s32 currd;
1664 s32 mind = 0x100000;
1665 s32 minpoll = 249;
1666 u8 minvcm = 0;
1667 if (2 * core != i)
1668 continue;
1669 for (vcm = 0; vcm < 8; vcm++) {
1670 currd = results[vcm][i] * results[vcm][i] +
1671 results[vcm][i + 1] * results[vcm][i];
1672 if (currd < mind) {
1673 mind = currd;
1674 minvcm = vcm;
1675 }
1676 if (results[vcm][i] < minpoll)
1677 minpoll = results[vcm][i];
1678 }
1679 vcm_final = minvcm;
1680 results_min[i] = minpoll;
1681 }
1682
1683
1684 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1685 vcm_final << 2);
1686
1687 for (i = 0; i < 4; i++) {
1688 if (core != i / 2)
1689 continue;
1690 offset[i] = -results[vcm_final][i];
1691 if (offset[i] < 0)
1692 offset[i] = -((abs(offset[i]) + 4) / 8);
1693 else
1694 offset[i] = (offset[i] + 4) / 8;
1695 if (results_min[i] == 248)
1696 offset[i] = -32;
1697 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1698 (i / 2 == 0) ? 1 : 2,
1699 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1700 N_RSSI_NB);
1701 }
1702 }
1703
1704 for (core = 0; core < 2; core++) {
1705 if (!(rx_core_state & (1 << core)))
1706 continue;
1707 for (i = 0; i < 2; i++) {
1708 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1709 N_RAIL_I, i);
1710 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1711 N_RAIL_Q, i);
1712 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1713 for (j = 0; j < 4; j++) {
1714 if (j / 2 == core) {
1715 offset[j] = 232 - poll_results[j];
1716 if (offset[j] < 0)
1717 offset[j] = -(abs(offset[j] + 4) / 8);
1718 else
1719 offset[j] = (offset[j] + 4) / 8;
1720 b43_nphy_scale_offset_rssi(dev, 0,
1721 offset[2 * core], core + 1, j % 2, i);
1722 }
1723 }
1724 }
1725 }
1726
1727 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1728 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1729
1730 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1731
1732 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1733 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1734 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1735
1736 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1737 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1738 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1739
1740 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1741 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1742
1743
1744 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1745 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1746 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1747 } else {
1748 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1749 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1750 }
1751 if (dev->phy.rev >= 7) {
1752 } else {
1753 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1754 B2056_RX_RSSI_MISC);
1755 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1756 B2056_RX_RSSI_MISC);
1757 }
1758 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1759 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1760 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1761 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1762 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1763 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1764 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1765 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1766 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1767 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1768 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1769 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1770
1771
1772 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1773 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1774 else
1775 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1776
1777
1778 b43_nphy_classifier(dev, 7, class);
1779 b43_nphy_write_clip_detection(dev, clip_state);
1780}
1781
1782
1783static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1784{
1785 int i, j, vcm;
1786 u8 state[4];
1787 u8 code, val;
1788 u16 class, override;
1789 u8 regs_save_radio[2];
1790 u16 regs_save_phy[2];
1791
1792 s32 offset[4];
1793 u8 core;
1794 u8 rail;
1795
1796 u16 clip_state[2];
1797 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1798 s32 results_min[4] = { };
1799 u8 vcm_final[4] = { };
1800 s32 results[4][4] = { };
1801 s32 miniq[4][2] = { };
1802
1803 if (type == N_RSSI_NB) {
1804 code = 0;
1805 val = 6;
1806 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1807 code = 25;
1808 val = 4;
1809 } else {
1810 B43_WARN_ON(1);
1811 return;
1812 }
1813
1814 class = b43_nphy_classifier(dev, 0, 0);
1815 b43_nphy_classifier(dev, 7, 4);
1816 b43_nphy_read_clip_detection(dev, clip_state);
1817 b43_nphy_write_clip_detection(dev, clip_off);
1818
1819 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1820 override = 0x140;
1821 else
1822 override = 0x110;
1823
1824 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1825 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1827 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1828
1829 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1830 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1831 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1832 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1833
1834 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1835 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1836 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1837 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1838 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1839 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1840
1841 b43_nphy_rssi_select(dev, 5, type);
1842 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1843 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1844
1845 for (vcm = 0; vcm < 4; vcm++) {
1846 u8 tmp[4];
1847 for (j = 0; j < 4; j++)
1848 tmp[j] = vcm;
1849 if (type != N_RSSI_W2)
1850 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1851 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1852 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1853 for (j = 0; j < 2; j++)
1854 miniq[vcm][j] = min(results[vcm][2 * j],
1855 results[vcm][2 * j + 1]);
1856 }
1857
1858 for (i = 0; i < 4; i++) {
1859 s32 mind = 0x100000;
1860 u8 minvcm = 0;
1861 s32 minpoll = 249;
1862 s32 currd;
1863 for (vcm = 0; vcm < 4; vcm++) {
1864 if (type == N_RSSI_NB)
1865 currd = abs(results[vcm][i] - code * 8);
1866 else
1867 currd = abs(miniq[vcm][i / 2] - code * 8);
1868
1869 if (currd < mind) {
1870 mind = currd;
1871 minvcm = vcm;
1872 }
1873
1874 if (results[vcm][i] < minpoll)
1875 minpoll = results[vcm][i];
1876 }
1877 results_min[i] = minpoll;
1878 vcm_final[i] = minvcm;
1879 }
1880
1881 if (type != N_RSSI_W2)
1882 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1883
1884 for (i = 0; i < 4; i++) {
1885 offset[i] = (code * 8) - results[vcm_final[i]][i];
1886
1887 if (offset[i] < 0)
1888 offset[i] = -((abs(offset[i]) + 4) / 8);
1889 else
1890 offset[i] = (offset[i] + 4) / 8;
1891
1892 if (results_min[i] == 248)
1893 offset[i] = code - 32;
1894
1895 core = (i / 2) ? 2 : 1;
1896 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1897
1898 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1899 type);
1900 }
1901
1902 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1903 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1904
1905 switch (state[2]) {
1906 case 1:
1907 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
1908 break;
1909 case 4:
1910 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
1911 break;
1912 case 2:
1913 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1914 break;
1915 default:
1916 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1917 break;
1918 }
1919
1920 switch (state[3]) {
1921 case 1:
1922 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
1923 break;
1924 case 4:
1925 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
1926 break;
1927 default:
1928 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
1929 break;
1930 }
1931
1932 b43_nphy_rssi_select(dev, 0, type);
1933
1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1935 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1937 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1938
1939 b43_nphy_classifier(dev, 7, class);
1940 b43_nphy_write_clip_detection(dev, clip_state);
1941
1942
1943 b43_nphy_reset_cca(dev);
1944}
1945
1946
1947
1948
1949
1950static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1951{
1952 if (dev->phy.rev >= 3) {
1953 b43_nphy_rev3_rssi_cal(dev);
1954 } else {
1955 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1956 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1957 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
1958 }
1959}
1960
1961
1962
1963
1964
1965static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1966{
1967 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1968
1969 bool ghz5;
1970 bool ext_lna;
1971 u16 rssi_gain;
1972 struct nphy_gain_ctl_workaround_entry *e;
1973 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1974 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1975
1976
1977 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1978 & B43_NPHY_BANDCTL_5GHZ;
1979 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1980 sprom->boardflags_lo & B43_BFL_EXTLNA;
1981 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1982 if (ghz5 && dev->phy.rev >= 5)
1983 rssi_gain = 0x90;
1984 else
1985 rssi_gain = 0x50;
1986
1987 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1988
1989
1990 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1991 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1992
1993 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1994 0x17);
1995 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1996 0x17);
1997 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1998 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1999 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2000 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2001 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2002 rssi_gain);
2003 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2004 rssi_gain);
2005 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2006 0x17);
2007 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2008 0x17);
2009 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2010 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2011
2012 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2013 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2014 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2015 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2016 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2017 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2018 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2019 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2020 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2021 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2022 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2023 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2024
2025 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2026 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2027
2028 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2029 e->rfseq_init);
2030
2031 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2032 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2033 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2034 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2035 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2036 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2037
2038 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2039 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2040 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2041 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2042 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2043 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2044 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2045 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2046 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2047 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2048}
2049
2050static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2051{
2052 struct b43_phy_n *nphy = dev->phy.n;
2053
2054 u8 i, j;
2055 u8 code;
2056 u16 tmp;
2057 u8 rfseq_events[3] = { 6, 8, 7 };
2058 u8 rfseq_delays[3] = { 10, 30, 1 };
2059
2060
2061 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2062 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2063
2064
2065 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2066 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2067
2068 if (!dev->phy.is_40mhz) {
2069
2070 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2071 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2072 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2073 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2074 }
2075
2076
2077 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2078 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2079 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2080 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2081
2082 if (!dev->phy.is_40mhz) {
2083 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2084 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2085 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2086 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2087 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2088 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2089 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2090 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2091 }
2092
2093 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2094
2095 if (nphy->gain_boost) {
2096 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2097 dev->phy.is_40mhz)
2098 code = 4;
2099 else
2100 code = 5;
2101 } else {
2102 code = dev->phy.is_40mhz ? 6 : 7;
2103 }
2104
2105
2106 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2107 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2108 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2109 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2110
2111 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2112
2113 for (i = 0; i < 4; i++)
2114 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2115
2116 b43_nphy_adjust_lna_gain_table(dev);
2117
2118 if (nphy->elna_gain_config) {
2119 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2120 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2121 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2122 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2123 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2124
2125 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2126 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2127 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2128 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2129 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2130
2131 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2132
2133 for (i = 0; i < 4; i++)
2134 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2135 (code << 8 | 0x74));
2136 }
2137
2138 if (dev->phy.rev == 2) {
2139 for (i = 0; i < 4; i++) {
2140 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2141 (0x0400 * i) + 0x0020);
2142 for (j = 0; j < 21; j++) {
2143 tmp = j * (i < 2 ? 3 : 1);
2144 b43_phy_write(dev,
2145 B43_NPHY_TABLE_DATALO, tmp);
2146 }
2147 }
2148 }
2149
2150 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2151 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2152 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2153 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2154
2155 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2156 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2157}
2158
2159
2160static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2161{
2162 if (dev->phy.rev >= 7)
2163 ;
2164 else if (dev->phy.rev >= 3)
2165 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2166 else
2167 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2168}
2169
2170
2171static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2172{
2173 if (!offset)
2174 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2175 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2176}
2177
2178static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2179{
2180 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2181 struct b43_phy *phy = &dev->phy;
2182
2183 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2184 0x1F };
2185 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2186
2187 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2188 u8 ntab7_138_146[] = { 0x11, 0x11 };
2189 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2190
2191 u16 lpf_20, lpf_40, lpf_11b;
2192 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2193 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2194 bool rccal_ovrd = false;
2195
2196 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2197 u16 bias, conv, filt;
2198
2199 u32 tmp32;
2200 u8 core;
2201
2202 if (phy->rev == 7) {
2203 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2204 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2205 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2206 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2207 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2208 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2209 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2210 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2211 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2212 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2213 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2214 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2215 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2216 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2217 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2218 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2219 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2220 }
2221 if (phy->rev <= 8) {
2222 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2223 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2224 }
2225 if (phy->rev >= 8)
2226 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2227
2228 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2229 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2230 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2231 tmp32 &= 0xffffff;
2232 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2233 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2234 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2235
2236 if (b43_nphy_ipa(dev))
2237 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2238 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2239
2240 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2241 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2242
2243 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2244 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2245 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2246 if (b43_nphy_ipa(dev)) {
2247 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2248 phy->radio_rev == 7 || phy->radio_rev == 8) {
2249 bcap_val = b43_radio_read(dev, 0x16b);
2250 scap_val = b43_radio_read(dev, 0x16a);
2251 scap_val_11b = scap_val;
2252 bcap_val_11b = bcap_val;
2253 if (phy->radio_rev == 5 && phy->is_40mhz) {
2254 scap_val_11n_20 = scap_val;
2255 bcap_val_11n_20 = bcap_val;
2256 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2257 rccal_ovrd = true;
2258 } else {
2259 lpf_20 = 4;
2260 lpf_11b = 1;
2261 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2262 scap_val_11n_20 = 0xc;
2263 bcap_val_11n_20 = 0xc;
2264 scap_val_11n_40 = 0xa;
2265 bcap_val_11n_40 = 0xa;
2266 } else {
2267 scap_val_11n_20 = 0x14;
2268 bcap_val_11n_20 = 0x14;
2269 scap_val_11n_40 = 0xf;
2270 bcap_val_11n_40 = 0xf;
2271 }
2272 rccal_ovrd = true;
2273 }
2274 }
2275 } else {
2276 if (phy->radio_rev == 5) {
2277 lpf_20 = 1;
2278 lpf_40 = 3;
2279 bcap_val = b43_radio_read(dev, 0x16b);
2280 scap_val = b43_radio_read(dev, 0x16a);
2281 scap_val_11b = scap_val;
2282 bcap_val_11b = bcap_val;
2283 scap_val_11n_20 = 0x11;
2284 scap_val_11n_40 = 0x11;
2285 bcap_val_11n_20 = 0x13;
2286 bcap_val_11n_40 = 0x13;
2287 rccal_ovrd = true;
2288 }
2289 }
2290 if (rccal_ovrd) {
2291 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2292 (scap_val_11b << 3) |
2293 lpf_11b;
2294 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2295 (scap_val_11n_20 << 3) |
2296 lpf_20;
2297 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2298 (scap_val_11n_40 << 3) |
2299 lpf_40;
2300 for (core = 0; core < 2; core++) {
2301 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2302 rx2tx_lut_20_11b);
2303 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2304 rx2tx_lut_20_11n);
2305 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2306 rx2tx_lut_20_11n);
2307 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2308 rx2tx_lut_40_11n);
2309 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2310 rx2tx_lut_40_11n);
2311 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2312 rx2tx_lut_40_11n);
2313 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2314 rx2tx_lut_40_11n);
2315 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2316 rx2tx_lut_40_11n);
2317 }
2318 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2319 }
2320 b43_phy_write(dev, 0x32F, 0x3);
2321 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2322 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2323
2324 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2325 if (sprom->revision &&
2326 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2327 b43_radio_write(dev, 0x5, 0x05);
2328 b43_radio_write(dev, 0x6, 0x30);
2329 b43_radio_write(dev, 0x7, 0x00);
2330 b43_radio_set(dev, 0x4f, 0x1);
2331 b43_radio_set(dev, 0xd4, 0x1);
2332 bias = 0x1f;
2333 conv = 0x6f;
2334 filt = 0xaa;
2335 } else {
2336 bias = 0x2b;
2337 conv = 0x7f;
2338 filt = 0xee;
2339 }
2340 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2341 for (core = 0; core < 2; core++) {
2342 if (core == 0) {
2343 b43_radio_write(dev, 0x5F, bias);
2344 b43_radio_write(dev, 0x64, conv);
2345 b43_radio_write(dev, 0x66, filt);
2346 } else {
2347 b43_radio_write(dev, 0xE8, bias);
2348 b43_radio_write(dev, 0xE9, conv);
2349 b43_radio_write(dev, 0xEB, filt);
2350 }
2351 }
2352 }
2353 }
2354
2355 if (b43_nphy_ipa(dev)) {
2356 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2357 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2358 phy->radio_rev == 6) {
2359 for (core = 0; core < 2; core++) {
2360 if (core == 0)
2361 b43_radio_write(dev, 0x51,
2362 0x7f);
2363 else
2364 b43_radio_write(dev, 0xd6,
2365 0x7f);
2366 }
2367 }
2368 if (phy->radio_rev == 3) {
2369 for (core = 0; core < 2; core++) {
2370 if (core == 0) {
2371 b43_radio_write(dev, 0x64,
2372 0x13);
2373 b43_radio_write(dev, 0x5F,
2374 0x1F);
2375 b43_radio_write(dev, 0x66,
2376 0xEE);
2377 b43_radio_write(dev, 0x59,
2378 0x8A);
2379 b43_radio_write(dev, 0x80,
2380 0x3E);
2381 } else {
2382 b43_radio_write(dev, 0x69,
2383 0x13);
2384 b43_radio_write(dev, 0xE8,
2385 0x1F);
2386 b43_radio_write(dev, 0xEB,
2387 0xEE);
2388 b43_radio_write(dev, 0xDE,
2389 0x8A);
2390 b43_radio_write(dev, 0x105,
2391 0x3E);
2392 }
2393 }
2394 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2395 if (!phy->is_40mhz) {
2396 b43_radio_write(dev, 0x5F, 0x14);
2397 b43_radio_write(dev, 0xE8, 0x12);
2398 } else {
2399 b43_radio_write(dev, 0x5F, 0x16);
2400 b43_radio_write(dev, 0xE8, 0x16);
2401 }
2402 }
2403 } else {
2404 u16 freq = phy->channel_freq;
2405 if ((freq >= 5180 && freq <= 5230) ||
2406 (freq >= 5745 && freq <= 5805)) {
2407 b43_radio_write(dev, 0x7D, 0xFF);
2408 b43_radio_write(dev, 0xFE, 0xFF);
2409 }
2410 }
2411 } else {
2412 if (phy->radio_rev != 5) {
2413 for (core = 0; core < 2; core++) {
2414 if (core == 0) {
2415 b43_radio_write(dev, 0x5c, 0x61);
2416 b43_radio_write(dev, 0x51, 0x70);
2417 } else {
2418 b43_radio_write(dev, 0xe1, 0x61);
2419 b43_radio_write(dev, 0xd6, 0x70);
2420 }
2421 }
2422 }
2423 }
2424
2425 if (phy->radio_rev == 4) {
2426 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2427 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2428 for (core = 0; core < 2; core++) {
2429 if (core == 0) {
2430 b43_radio_write(dev, 0x1a1, 0x00);
2431 b43_radio_write(dev, 0x1a2, 0x3f);
2432 b43_radio_write(dev, 0x1a6, 0x3f);
2433 } else {
2434 b43_radio_write(dev, 0x1a7, 0x00);
2435 b43_radio_write(dev, 0x1ab, 0x3f);
2436 b43_radio_write(dev, 0x1ac, 0x3f);
2437 }
2438 }
2439 } else {
2440 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2441 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2442 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2443 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2444
2445 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2446 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2447 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2448 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2449 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2450 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2451
2452 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2453 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2454 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2455 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2456 }
2457
2458 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2459
2460 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2461 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2462 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2463 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2464 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2465 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2466 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2467
2468 if (!phy->is_40mhz) {
2469 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2470 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2471 } else {
2472 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2473 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2474 }
2475
2476 b43_nphy_gain_ctl_workarounds(dev);
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488}
2489
2490static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2491{
2492 struct b43_phy_n *nphy = dev->phy.n;
2493 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2494
2495
2496 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2497 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2498
2499 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2500 0x1F };
2501 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2502 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2503 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2504
2505 u16 tmp16;
2506 u32 tmp32;
2507
2508 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2509 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2510
2511 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2512 tmp32 &= 0xffffff;
2513 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2514
2515 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2516 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2517 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2518 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2519 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2520 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2521
2522 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2523 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2524
2525
2526 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2527 ARRAY_SIZE(tx2rx_events));
2528
2529
2530 if (b43_nphy_ipa(dev))
2531 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2532 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2533 if (nphy->hw_phyrxchain != 3 &&
2534 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2535 if (b43_nphy_ipa(dev)) {
2536 rx2tx_delays[5] = 59;
2537 rx2tx_delays[6] = 1;
2538 rx2tx_events[7] = 0x1F;
2539 }
2540 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2541 ARRAY_SIZE(rx2tx_events));
2542 }
2543
2544 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2545 0x2 : 0x9C40;
2546 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2547
2548 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2549
2550 if (!dev->phy.is_40mhz) {
2551 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2552 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2553 } else {
2554 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2555 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2556 }
2557
2558 b43_nphy_gain_ctl_workarounds(dev);
2559
2560 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2561 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2562
2563
2564
2565 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2566 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2567 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2568 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2569 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2570 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2571 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2572 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2573 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2574 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2575 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2576 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2577
2578
2579
2580 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2581 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2582 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2583 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2584 tmp32 = 0x00088888;
2585 else
2586 tmp32 = 0x88888888;
2587 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2588 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2589 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2590
2591 if (dev->phy.rev == 4 &&
2592 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2593 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2594 0x70);
2595 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2596 0x70);
2597 }
2598
2599
2600 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2601 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2602 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2603 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2604 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2605 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2606 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2607 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2608 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2609 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2610 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2611 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2612
2613 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2614 ;
2615}
2616
2617static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2618{
2619 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2620 struct b43_phy *phy = &dev->phy;
2621 struct b43_phy_n *nphy = phy->n;
2622
2623 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2624 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2625
2626 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2627 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2628
2629 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2630 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2631 delays1[0] = 0x1;
2632 delays1[5] = 0x14;
2633 }
2634
2635 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2636 nphy->band5g_pwrgain) {
2637 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2638 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2639 } else {
2640 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2641 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2642 }
2643
2644 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2645 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2646 if (dev->phy.rev < 3) {
2647 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2648 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2649 }
2650
2651 if (dev->phy.rev < 2) {
2652 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2653 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2654 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2655 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2656 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2657 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2658 }
2659
2660 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2661 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2662 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2663 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2664
2665 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2666 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2667
2668 b43_nphy_gain_ctl_workarounds(dev);
2669
2670 if (dev->phy.rev < 2) {
2671 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2672 b43_hf_write(dev, b43_hf_read(dev) |
2673 B43_HF_MLADVW);
2674 } else if (dev->phy.rev == 2) {
2675 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2676 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2677 }
2678
2679 if (dev->phy.rev < 2)
2680 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2681 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2682
2683
2684 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2685 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2686 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2687 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2688 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2689 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2690
2691 if (dev->phy.rev < 3) {
2692 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2693 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2694 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2695 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2696 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2697 }
2698
2699 if (dev->phy.rev == 2)
2700 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2701 B43_NPHY_FINERX2_CGC_DECGC);
2702}
2703
2704
2705static void b43_nphy_workarounds(struct b43_wldev *dev)
2706{
2707 struct b43_phy *phy = &dev->phy;
2708 struct b43_phy_n *nphy = phy->n;
2709
2710 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2711 b43_nphy_classifier(dev, 1, 0);
2712 else
2713 b43_nphy_classifier(dev, 1, 1);
2714
2715 if (nphy->hang_avoid)
2716 b43_nphy_stay_in_carrier_search(dev, 1);
2717
2718 b43_phy_set(dev, B43_NPHY_IQFLIP,
2719 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2720
2721 if (dev->phy.rev >= 7)
2722 b43_nphy_workarounds_rev7plus(dev);
2723 else if (dev->phy.rev >= 3)
2724 b43_nphy_workarounds_rev3plus(dev);
2725 else
2726 b43_nphy_workarounds_rev1_2(dev);
2727
2728 if (nphy->hang_avoid)
2729 b43_nphy_stay_in_carrier_search(dev, 0);
2730}
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2741 bool iqmode, bool dac_test)
2742{
2743 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2744 if (samp == 0)
2745 return -1;
2746 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2747 return 0;
2748}
2749
2750
2751static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2752{
2753 struct b43_phy_n *nphy = dev->phy.n;
2754
2755 bool override = false;
2756 u16 chain = 0x33;
2757
2758 if (nphy->txrx_chain == 0) {
2759 chain = 0x11;
2760 override = true;
2761 } else if (nphy->txrx_chain == 1) {
2762 chain = 0x22;
2763 override = true;
2764 }
2765
2766 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2767 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2768 chain);
2769
2770 if (override)
2771 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2772 B43_NPHY_RFSEQMODE_CAOVER);
2773 else
2774 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2775 ~B43_NPHY_RFSEQMODE_CAOVER);
2776}
2777
2778
2779static void b43_nphy_stop_playback(struct b43_wldev *dev)
2780{
2781 struct b43_phy_n *nphy = dev->phy.n;
2782 u16 tmp;
2783
2784 if (nphy->hang_avoid)
2785 b43_nphy_stay_in_carrier_search(dev, 1);
2786
2787 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2788 if (tmp & 0x1)
2789 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2790 else if (tmp & 0x2)
2791 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2792
2793 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2794
2795 if (nphy->bb_mult_save & 0x80000000) {
2796 tmp = nphy->bb_mult_save & 0xFFFF;
2797 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2798 nphy->bb_mult_save = 0;
2799 }
2800
2801 if (nphy->hang_avoid)
2802 b43_nphy_stay_in_carrier_search(dev, 0);
2803}
2804
2805
2806static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2807 struct nphy_txgains target,
2808 struct nphy_iqcal_params *params)
2809{
2810 int i, j, indx;
2811 u16 gain;
2812
2813 if (dev->phy.rev >= 3) {
2814 params->txgm = target.txgm[core];
2815 params->pga = target.pga[core];
2816 params->pad = target.pad[core];
2817 params->ipa = target.ipa[core];
2818 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2819 (params->pad << 4) | (params->ipa);
2820 for (j = 0; j < 5; j++)
2821 params->ncorr[j] = 0x79;
2822 } else {
2823 gain = (target.pad[core]) | (target.pga[core] << 4) |
2824 (target.txgm[core] << 8);
2825
2826 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2827 1 : 0;
2828 for (i = 0; i < 9; i++)
2829 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2830 break;
2831 i = min(i, 8);
2832
2833 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2834 params->pga = tbl_iqcal_gainparams[indx][i][2];
2835 params->pad = tbl_iqcal_gainparams[indx][i][3];
2836 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2837 (params->pad << 2);
2838 for (j = 0; j < 4; j++)
2839 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2840 }
2841}
2842
2843
2844
2845
2846
2847static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2848{
2849}
2850
2851static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2852 bool ignore_tssi)
2853{
2854 return B43_TXPWR_RES_DONE;
2855}
2856
2857
2858static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2859{
2860 struct b43_phy_n *nphy = dev->phy.n;
2861 u8 i;
2862 u16 bmask, val, tmp;
2863 enum ieee80211_band band = b43_current_band(dev->wl);
2864
2865 if (nphy->hang_avoid)
2866 b43_nphy_stay_in_carrier_search(dev, 1);
2867
2868 nphy->txpwrctrl = enable;
2869 if (!enable) {
2870 if (dev->phy.rev >= 3 &&
2871 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2872 (B43_NPHY_TXPCTL_CMD_COEFF |
2873 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2874 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2875
2876 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2877 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2878 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2879 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2880 }
2881
2882 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2883 for (i = 0; i < 84; i++)
2884 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2885
2886 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2887 for (i = 0; i < 84; i++)
2888 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2889
2890 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2891 if (dev->phy.rev >= 3)
2892 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2893 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2894
2895 if (dev->phy.rev >= 3) {
2896 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2897 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2898 } else {
2899 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2900 }
2901
2902 if (dev->phy.rev == 2)
2903 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2904 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2905 else if (dev->phy.rev < 2)
2906 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2907 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2908
2909 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2910 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2911 } else {
2912 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2913 nphy->adj_pwr_tbl);
2914 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2915 nphy->adj_pwr_tbl);
2916
2917 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2918 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2919
2920 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2921 if (dev->phy.rev >= 3) {
2922 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2923 if (val)
2924 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2925 }
2926 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2927
2928 if (band == IEEE80211_BAND_5GHZ) {
2929 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2930 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2931 if (dev->phy.rev > 1)
2932 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2933 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2934 0x64);
2935 }
2936
2937 if (dev->phy.rev >= 3) {
2938 if (nphy->tx_pwr_idx[0] != 128 &&
2939 nphy->tx_pwr_idx[1] != 128) {
2940
2941 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2942 ~B43_NPHY_TXPCTL_CMD_INIT,
2943 nphy->tx_pwr_idx[0]);
2944 if (dev->phy.rev > 1)
2945 b43_phy_maskset(dev,
2946 B43_NPHY_TXPCTL_INIT,
2947 ~0xff, nphy->tx_pwr_idx[1]);
2948 }
2949 }
2950
2951 if (dev->phy.rev >= 3) {
2952 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2953 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2954 } else {
2955 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2956 }
2957
2958 if (dev->phy.rev == 2)
2959 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2960 else if (dev->phy.rev < 2)
2961 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2962
2963 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2964 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2965
2966 if (b43_nphy_ipa(dev)) {
2967 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2968 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2969 }
2970 }
2971
2972 if (nphy->hang_avoid)
2973 b43_nphy_stay_in_carrier_search(dev, 0);
2974}
2975
2976
2977static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2978{
2979 struct b43_phy_n *nphy = dev->phy.n;
2980 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2981
2982 u8 txpi[2], bbmult, i;
2983 u16 tmp, radio_gain, dac_gain;
2984 u16 freq = dev->phy.channel_freq;
2985 u32 txgain;
2986
2987
2988 if (nphy->hang_avoid)
2989 b43_nphy_stay_in_carrier_search(dev, 1);
2990
2991 if (dev->phy.rev >= 7) {
2992 txpi[0] = txpi[1] = 30;
2993 } else if (dev->phy.rev >= 3) {
2994 txpi[0] = 40;
2995 txpi[1] = 40;
2996 } else if (sprom->revision < 4) {
2997 txpi[0] = 72;
2998 txpi[1] = 72;
2999 } else {
3000 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3001 txpi[0] = sprom->txpid2g[0];
3002 txpi[1] = sprom->txpid2g[1];
3003 } else if (freq >= 4900 && freq < 5100) {
3004 txpi[0] = sprom->txpid5gl[0];
3005 txpi[1] = sprom->txpid5gl[1];
3006 } else if (freq >= 5100 && freq < 5500) {
3007 txpi[0] = sprom->txpid5g[0];
3008 txpi[1] = sprom->txpid5g[1];
3009 } else if (freq >= 5500) {
3010 txpi[0] = sprom->txpid5gh[0];
3011 txpi[1] = sprom->txpid5gh[1];
3012 } else {
3013 txpi[0] = 91;
3014 txpi[1] = 91;
3015 }
3016 }
3017 if (dev->phy.rev < 7 &&
3018 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3019 txpi[0] = txpi[1] = 91;
3020
3021
3022
3023
3024
3025
3026
3027
3028 for (i = 0; i < 2; i++) {
3029 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3030
3031 if (dev->phy.rev >= 3)
3032 radio_gain = (txgain >> 16) & 0x1FFFF;
3033 else
3034 radio_gain = (txgain >> 16) & 0x1FFF;
3035
3036 if (dev->phy.rev >= 7)
3037 dac_gain = (txgain >> 8) & 0x7;
3038 else
3039 dac_gain = (txgain >> 8) & 0x3F;
3040 bbmult = txgain & 0xFF;
3041
3042 if (dev->phy.rev >= 3) {
3043 if (i == 0)
3044 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3045 else
3046 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3047 } else {
3048 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3049 }
3050
3051 if (i == 0)
3052 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3053 else
3054 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3055
3056 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3057
3058 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3059 if (i == 0)
3060 tmp = (tmp & 0x00FF) | (bbmult << 8);
3061 else
3062 tmp = (tmp & 0xFF00) | bbmult;
3063 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3064
3065 if (b43_nphy_ipa(dev)) {
3066 u32 tmp32;
3067 u16 reg = (i == 0) ?
3068 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3069 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3070 576 + txpi[i]));
3071 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3072 b43_phy_set(dev, reg, 0x4);
3073 }
3074 }
3075
3076 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3077
3078 if (nphy->hang_avoid)
3079 b43_nphy_stay_in_carrier_search(dev, 0);
3080}
3081
3082static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3083{
3084 struct b43_phy *phy = &dev->phy;
3085
3086 u8 core;
3087 u16 r;
3088
3089 if (phy->rev >= 7) {
3090 for (core = 0; core < 2; core++) {
3091 r = core ? 0x190 : 0x170;
3092 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3093 b43_radio_write(dev, r + 0x5, 0x5);
3094 b43_radio_write(dev, r + 0x9, 0xE);
3095 if (phy->rev != 5)
3096 b43_radio_write(dev, r + 0xA, 0);
3097 if (phy->rev != 7)
3098 b43_radio_write(dev, r + 0xB, 1);
3099 else
3100 b43_radio_write(dev, r + 0xB, 0x31);
3101 } else {
3102 b43_radio_write(dev, r + 0x5, 0x9);
3103 b43_radio_write(dev, r + 0x9, 0xC);
3104 b43_radio_write(dev, r + 0xB, 0x0);
3105 if (phy->rev != 5)
3106 b43_radio_write(dev, r + 0xA, 1);
3107 else
3108 b43_radio_write(dev, r + 0xA, 0x31);
3109 }
3110 b43_radio_write(dev, r + 0x6, 0);
3111 b43_radio_write(dev, r + 0x7, 0);
3112 b43_radio_write(dev, r + 0x8, 3);
3113 b43_radio_write(dev, r + 0xC, 0);
3114 }
3115 } else {
3116 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3117 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3118 else
3119 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3120 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3121 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3122
3123 for (core = 0; core < 2; core++) {
3124 r = core ? B2056_TX1 : B2056_TX0;
3125
3126 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3127 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3128 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3129 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3130 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3131 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3132 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3133 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3134 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3135 0x5);
3136 if (phy->rev != 5)
3137 b43_radio_write(dev, r | B2056_TX_TSSIA,
3138 0x00);
3139 if (phy->rev >= 5)
3140 b43_radio_write(dev, r | B2056_TX_TSSIG,
3141 0x31);
3142 else
3143 b43_radio_write(dev, r | B2056_TX_TSSIG,
3144 0x11);
3145 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3146 0xE);
3147 } else {
3148 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3149 0x9);
3150 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3151 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3152 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3153 0xC);
3154 }
3155 }
3156 }
3157}
3158
3159
3160
3161
3162
3163
3164static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3165{
3166 struct b43_phy *phy = &dev->phy;
3167 struct b43_phy_n *nphy = dev->phy.n;
3168
3169 u32 tmp;
3170 s32 rssi[4] = { };
3171
3172
3173
3174 if (b43_nphy_ipa(dev))
3175 b43_nphy_ipa_internal_tssi_setup(dev);
3176
3177 if (phy->rev >= 7)
3178 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3179 else if (phy->rev >= 3)
3180 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3181
3182 b43_nphy_stop_playback(dev);
3183 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3184 udelay(20);
3185 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3186 b43_nphy_stop_playback(dev);
3187 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3188
3189 if (phy->rev >= 7)
3190 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3191 else if (phy->rev >= 3)
3192 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3193
3194 if (phy->rev >= 3) {
3195 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3196 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3197 } else {
3198 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3199 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3200 }
3201 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3202 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3203}
3204
3205
3206static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3207{
3208 struct b43_phy_n *nphy = dev->phy.n;
3209
3210 u8 idx, delta;
3211 u8 i, stf_mode;
3212
3213 for (i = 0; i < 4; i++)
3214 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3215
3216 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3217 delta = 0;
3218 switch (stf_mode) {
3219 case 0:
3220 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3221 idx = 68;
3222 } else {
3223 delta = 1;
3224 idx = dev->phy.is_40mhz ? 52 : 4;
3225 }
3226 break;
3227 case 1:
3228 idx = dev->phy.is_40mhz ? 76 : 28;
3229 break;
3230 case 2:
3231 idx = dev->phy.is_40mhz ? 84 : 36;
3232 break;
3233 case 3:
3234 idx = dev->phy.is_40mhz ? 92 : 44;
3235 break;
3236 }
3237
3238 for (i = 0; i < 20; i++) {
3239 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3240 nphy->tx_power_offset[idx];
3241 if (i == 0)
3242 idx += delta;
3243 if (i == 14)
3244 idx += 1 - delta;
3245 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3246 i == 13)
3247 idx += 1;
3248 }
3249 }
3250}
3251
3252
3253static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3254{
3255 struct b43_phy_n *nphy = dev->phy.n;
3256 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3257
3258 s16 a1[2], b0[2], b1[2];
3259 u8 idle[2];
3260 s8 target[2];
3261 s32 num, den, pwr;
3262 u32 regval[64];
3263
3264 u16 freq = dev->phy.channel_freq;
3265 u16 tmp;
3266 u16 r;
3267 u8 i, c;
3268
3269 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3270 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3271 b43_read32(dev, B43_MMIO_MACCTL);
3272 udelay(1);
3273 }
3274
3275 if (nphy->hang_avoid)
3276 b43_nphy_stay_in_carrier_search(dev, true);
3277
3278 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3279 if (dev->phy.rev >= 3)
3280 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3281 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3282 else
3283 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3284 B43_NPHY_TXPCTL_CMD_PCTLEN);
3285
3286 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3287 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3288
3289 if (sprom->revision < 4) {
3290 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3291 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3292 target[0] = target[1] = 52;
3293 a1[0] = a1[1] = -424;
3294 b0[0] = b0[1] = 5612;
3295 b1[0] = b1[1] = -1393;
3296 } else {
3297 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3298 for (c = 0; c < 2; c++) {
3299 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3300 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3301 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3302 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3303 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3304 }
3305 } else if (freq >= 4900 && freq < 5100) {
3306 for (c = 0; c < 2; c++) {
3307 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3308 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3309 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3310 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3311 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3312 }
3313 } else if (freq >= 5100 && freq < 5500) {
3314 for (c = 0; c < 2; c++) {
3315 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3316 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3317 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3318 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3319 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3320 }
3321 } else if (freq >= 5500) {
3322 for (c = 0; c < 2; c++) {
3323 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3324 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3325 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3326 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3327 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3328 }
3329 } else {
3330 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3331 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3332 target[0] = target[1] = 52;
3333 a1[0] = a1[1] = -424;
3334 b0[0] = b0[1] = 5612;
3335 b1[0] = b1[1] = -1393;
3336 }
3337 }
3338
3339
3340 if (dev->phy.rev >= 3) {
3341 if (sprom->fem.ghz2.tssipos)
3342 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3343 if (dev->phy.rev >= 7) {
3344 for (c = 0; c < 2; c++) {
3345 r = c ? 0x190 : 0x170;
3346 if (b43_nphy_ipa(dev))
3347 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3348 }
3349 } else {
3350 if (b43_nphy_ipa(dev)) {
3351 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3352 b43_radio_write(dev,
3353 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3354 b43_radio_write(dev,
3355 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3356 } else {
3357 b43_radio_write(dev,
3358 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3359 b43_radio_write(dev,
3360 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3361 }
3362 }
3363 }
3364
3365 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3366 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3367 b43_read32(dev, B43_MMIO_MACCTL);
3368 udelay(1);
3369 }
3370
3371 if (dev->phy.rev >= 7) {
3372 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3373 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3374 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3375 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3376 } else {
3377 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3378 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3379 if (dev->phy.rev > 1)
3380 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3381 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3382 }
3383
3384 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3385 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3386
3387 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3388 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3389 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3390 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3391 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3392 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3393 B43_NPHY_TXPCTL_ITSSI_BINF);
3394 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3395 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3396 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3397
3398 for (c = 0; c < 2; c++) {
3399 for (i = 0; i < 64; i++) {
3400 num = 8 * (16 * b0[c] + b1[c] * i);
3401 den = 32768 + a1[c] * i;
3402 pwr = max((4 * num + den / 2) / den, -8);
3403 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3404 pwr = max(pwr, target[c] + 1);
3405 regval[i] = pwr;
3406 }
3407 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3408 }
3409
3410 b43_nphy_tx_prepare_adjusted_power_table(dev);
3411
3412
3413
3414
3415
3416 if (nphy->hang_avoid)
3417 b43_nphy_stay_in_carrier_search(dev, false);
3418}
3419
3420static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3421{
3422 struct b43_phy *phy = &dev->phy;
3423
3424 const u32 *table = NULL;
3425 u32 rfpwr_offset;
3426 u8 pga_gain;
3427 int i;
3428
3429 table = b43_nphy_get_tx_gain_table(dev);
3430 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3431 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3432
3433 if (phy->rev >= 3) {
3434#if 0
3435 nphy->gmval = (table[0] >> 16) & 0x7000;
3436#endif
3437
3438 for (i = 0; i < 128; i++) {
3439 pga_gain = (table[i] >> 24) & 0xF;
3440 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3441 rfpwr_offset =
3442 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3443 else
3444 rfpwr_offset =
3445 0;
3446 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3447 rfpwr_offset);
3448 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3449 rfpwr_offset);
3450 }
3451 }
3452}
3453
3454
3455static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3456{
3457 struct b43_phy_n *nphy = dev->phy.n;
3458 enum ieee80211_band band;
3459 u16 tmp;
3460
3461 if (!enable) {
3462 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3463 B43_NPHY_RFCTL_INTC1);
3464 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3465 B43_NPHY_RFCTL_INTC2);
3466 band = b43_current_band(dev->wl);
3467 if (dev->phy.rev >= 3) {
3468 if (band == IEEE80211_BAND_5GHZ)
3469 tmp = 0x600;
3470 else
3471 tmp = 0x480;
3472 } else {
3473 if (band == IEEE80211_BAND_5GHZ)
3474 tmp = 0x180;
3475 else
3476 tmp = 0x120;
3477 }
3478 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3479 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3480 } else {
3481 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3482 nphy->rfctrl_intc1_save);
3483 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3484 nphy->rfctrl_intc2_save);
3485 }
3486}
3487
3488
3489static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3490{
3491 u16 tmp;
3492
3493 if (dev->phy.rev >= 3) {
3494 if (b43_nphy_ipa(dev)) {
3495 tmp = 4;
3496 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3497 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3498 }
3499
3500 tmp = 1;
3501 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3502 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3503 }
3504}
3505
3506
3507static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3508 u16 samps, u8 time, bool wait)
3509{
3510 int i;
3511 u16 tmp;
3512
3513 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3514 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3515 if (wait)
3516 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3517 else
3518 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3519
3520 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3521
3522 for (i = 1000; i; i--) {
3523 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3524 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3525 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3526 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3527 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3528 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3529 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3530 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3531
3532 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3533 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3534 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3535 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3536 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3537 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3538 return;
3539 }
3540 udelay(10);
3541 }
3542 memset(est, 0, sizeof(*est));
3543}
3544
3545
3546static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3547 struct b43_phy_n_iq_comp *pcomp)
3548{
3549 if (write) {
3550 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3551 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3552 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3553 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3554 } else {
3555 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3556 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3557 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3558 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3559 }
3560}
3561
3562#if 0
3563
3564
3565static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3566{
3567 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3568
3569 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3570 if (core == 0) {
3571 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3572 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3573 } else {
3574 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3575 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3576 }
3577 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3578 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3579 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3580 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3581 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3582 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3583 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3584 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3585}
3586
3587
3588static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3589{
3590 u8 rxval, txval;
3591 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3592
3593 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3594 if (core == 0) {
3595 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3596 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3597 } else {
3598 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3599 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3600 }
3601 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3602 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3603 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3604 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3605 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3606 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3607 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3608 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3609
3610 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3611 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3612
3613 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3614 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3615 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3616 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3617 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3618 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3619 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3620 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3621 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3622
3623 if (core == 0) {
3624 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3625 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3626 } else {
3627 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3628 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3629 }
3630
3631 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
3632 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
3633 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3634
3635 if (core == 0) {
3636 rxval = 1;
3637 txval = 8;
3638 } else {
3639 rxval = 4;
3640 txval = 2;
3641 }
3642 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3643 core + 1);
3644 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3645 2 - core);
3646}
3647#endif
3648
3649
3650static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3651{
3652 int i;
3653 s32 iq;
3654 u32 ii;
3655 u32 qq;
3656 int iq_nbits, qq_nbits;
3657 int arsh, brsh;
3658 u16 tmp, a, b;
3659
3660 struct nphy_iq_est est;
3661 struct b43_phy_n_iq_comp old;
3662 struct b43_phy_n_iq_comp new = { };
3663 bool error = false;
3664
3665 if (mask == 0)
3666 return;
3667
3668 b43_nphy_rx_iq_coeffs(dev, false, &old);
3669 b43_nphy_rx_iq_coeffs(dev, true, &new);
3670 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3671 new = old;
3672
3673 for (i = 0; i < 2; i++) {
3674 if (i == 0 && (mask & 1)) {
3675 iq = est.iq0_prod;
3676 ii = est.i0_pwr;
3677 qq = est.q0_pwr;
3678 } else if (i == 1 && (mask & 2)) {
3679 iq = est.iq1_prod;
3680 ii = est.i1_pwr;
3681 qq = est.q1_pwr;
3682 } else {
3683 continue;
3684 }
3685
3686 if (ii + qq < 2) {
3687 error = true;
3688 break;
3689 }
3690
3691 iq_nbits = fls(abs(iq));
3692 qq_nbits = fls(qq);
3693
3694 arsh = iq_nbits - 20;
3695 if (arsh >= 0) {
3696 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3697 tmp = ii >> arsh;
3698 } else {
3699 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3700 tmp = ii << -arsh;
3701 }
3702 if (tmp == 0) {
3703 error = true;
3704 break;
3705 }
3706 a /= tmp;
3707
3708 brsh = qq_nbits - 11;
3709 if (brsh >= 0) {
3710 b = (qq << (31 - qq_nbits));
3711 tmp = ii >> brsh;
3712 } else {
3713 b = (qq << (31 - qq_nbits));
3714 tmp = ii << -brsh;
3715 }
3716 if (tmp == 0) {
3717 error = true;
3718 break;
3719 }
3720 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3721
3722 if (i == 0 && (mask & 0x1)) {
3723 if (dev->phy.rev >= 3) {
3724 new.a0 = a & 0x3FF;
3725 new.b0 = b & 0x3FF;
3726 } else {
3727 new.a0 = b & 0x3FF;
3728 new.b0 = a & 0x3FF;
3729 }
3730 } else if (i == 1 && (mask & 0x2)) {
3731 if (dev->phy.rev >= 3) {
3732 new.a1 = a & 0x3FF;
3733 new.b1 = b & 0x3FF;
3734 } else {
3735 new.a1 = b & 0x3FF;
3736 new.b1 = a & 0x3FF;
3737 }
3738 }
3739 }
3740
3741 if (error)
3742 new = old;
3743
3744 b43_nphy_rx_iq_coeffs(dev, true, &new);
3745}
3746
3747
3748static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3749{
3750 u16 array[4];
3751 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3752
3753 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3754 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3755 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3756 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3757}
3758
3759
3760static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3761{
3762 struct b43_phy_n *nphy = dev->phy.n;
3763
3764 u8 channel = dev->phy.channel;
3765 int tone[2] = { 57, 58 };
3766 u32 noise[2] = { 0x3FF, 0x3FF };
3767
3768 B43_WARN_ON(dev->phy.rev < 3);
3769
3770 if (nphy->hang_avoid)
3771 b43_nphy_stay_in_carrier_search(dev, 1);
3772
3773 if (nphy->gband_spurwar_en) {
3774
3775 if (channel == 11 && dev->phy.is_40mhz)
3776 ;
3777 else
3778 ;
3779
3780 }
3781
3782 if (nphy->aband_spurwar_en) {
3783 if (channel == 54) {
3784 tone[0] = 0x20;
3785 noise[0] = 0x25F;
3786 } else if (channel == 38 || channel == 102 || channel == 118) {
3787 if (0 ) {
3788 tone[0] = 0x20;
3789 noise[0] = 0x21F;
3790 } else {
3791 tone[0] = 0;
3792 noise[0] = 0;
3793 }
3794 } else if (channel == 134) {
3795 tone[0] = 0x20;
3796 noise[0] = 0x21F;
3797 } else if (channel == 151) {
3798 tone[0] = 0x10;
3799 noise[0] = 0x23F;
3800 } else if (channel == 153 || channel == 161) {
3801 tone[0] = 0x30;
3802 noise[0] = 0x23F;
3803 } else {
3804 tone[0] = 0;
3805 noise[0] = 0;
3806 }
3807
3808 if (!tone[0] && !noise[0])
3809 ;
3810 else
3811 ;
3812 }
3813
3814 if (nphy->hang_avoid)
3815 b43_nphy_stay_in_carrier_search(dev, 0);
3816}
3817
3818
3819static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3820{
3821 struct b43_phy_n *nphy = dev->phy.n;
3822 int i, j;
3823 u32 tmp;
3824 u32 cur_real, cur_imag, real_part, imag_part;
3825
3826 u16 buffer[7];
3827
3828 if (nphy->hang_avoid)
3829 b43_nphy_stay_in_carrier_search(dev, true);
3830
3831 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3832
3833 for (i = 0; i < 2; i++) {
3834 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3835 (buffer[i * 2 + 1] & 0x3FF);
3836 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3837 (((i + 26) << 10) | 320));
3838 for (j = 0; j < 128; j++) {
3839 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3840 ((tmp >> 16) & 0xFFFF));
3841 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3842 (tmp & 0xFFFF));
3843 }
3844 }
3845
3846 for (i = 0; i < 2; i++) {
3847 tmp = buffer[5 + i];
3848 real_part = (tmp >> 8) & 0xFF;
3849 imag_part = (tmp & 0xFF);
3850 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3851 (((i + 26) << 10) | 448));
3852
3853 if (dev->phy.rev >= 3) {
3854 cur_real = real_part;
3855 cur_imag = imag_part;
3856 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3857 }
3858
3859 for (j = 0; j < 128; j++) {
3860 if (dev->phy.rev < 3) {
3861 cur_real = (real_part * loscale[j] + 128) >> 8;
3862 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3863 tmp = ((cur_real & 0xFF) << 8) |
3864 (cur_imag & 0xFF);
3865 }
3866 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3867 ((tmp >> 16) & 0xFFFF));
3868 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3869 (tmp & 0xFFFF));
3870 }
3871 }
3872
3873 if (dev->phy.rev >= 3) {
3874 b43_shm_write16(dev, B43_SHM_SHARED,
3875 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3876 b43_shm_write16(dev, B43_SHM_SHARED,
3877 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3878 }
3879
3880 if (nphy->hang_avoid)
3881 b43_nphy_stay_in_carrier_search(dev, false);
3882}
3883
3884
3885
3886
3887
3888static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3889{
3890 struct b43_phy_n *nphy = dev->phy.n;
3891
3892 u16 *rssical_radio_regs = NULL;
3893 u16 *rssical_phy_regs = NULL;
3894
3895 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3896 if (!nphy->rssical_chanspec_2G.center_freq)
3897 return;
3898 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3899 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3900 } else {
3901 if (!nphy->rssical_chanspec_5G.center_freq)
3902 return;
3903 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3904 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3905 }
3906
3907 if (dev->phy.rev >= 7) {
3908 } else {
3909 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
3910 rssical_radio_regs[0]);
3911 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
3912 rssical_radio_regs[1]);
3913 }
3914
3915 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3916 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3917 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3918 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3919
3920 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3921 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3922 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3923 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3924
3925 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3926 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3927 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3928 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3929}
3930
3931
3932static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3933{
3934 struct b43_phy_n *nphy = dev->phy.n;
3935 u16 *save = nphy->tx_rx_cal_radio_saveregs;
3936 u16 tmp;
3937 u8 offset, i;
3938
3939 if (dev->phy.rev >= 3) {
3940 for (i = 0; i < 2; i++) {
3941 tmp = (i == 0) ? 0x2000 : 0x3000;
3942 offset = i * 11;
3943
3944 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
3945 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
3946 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
3947 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
3948 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
3949 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
3950 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
3951 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
3952 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
3953 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
3954 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
3955
3956 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3957 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3958 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3959 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3960 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3961 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3962 if (nphy->ipa5g_on) {
3963 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
3964 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
3965 } else {
3966 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3967 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
3968 }
3969 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3970 } else {
3971 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3972 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3973 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3974 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3975 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3976 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
3977 if (nphy->ipa2g_on) {
3978 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
3979 b43_radio_write(dev, tmp | B2055_XOCTL2,
3980 (dev->phy.rev < 5) ? 0x11 : 0x01);
3981 } else {
3982 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3983 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3984 }
3985 }
3986 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
3987 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
3988 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
3989 }
3990 } else {
3991 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
3992 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3993
3994 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
3995 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3996
3997 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
3998 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3999
4000 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4001 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4002
4003 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4004 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4005
4006 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4007 B43_NPHY_BANDCTL_5GHZ)) {
4008 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4009 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4010 } else {
4011 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4012 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4013 }
4014
4015 if (dev->phy.rev < 2) {
4016 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4017 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4018 } else {
4019 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4020 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4021 }
4022 }
4023}
4024
4025
4026static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4027{
4028 struct b43_phy_n *nphy = dev->phy.n;
4029 int i;
4030 u16 scale, entry;
4031
4032 u16 tmp = nphy->txcal_bbmult;
4033 if (core == 0)
4034 tmp >>= 8;
4035 tmp &= 0xff;
4036
4037 for (i = 0; i < 18; i++) {
4038 scale = (ladder_lo[i].percent * tmp) / 100;
4039 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4040 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4041
4042 scale = (ladder_iq[i].percent * tmp) / 100;
4043 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4044 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4045 }
4046}
4047
4048
4049static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4050{
4051 int i;
4052 for (i = 0; i < 15; i++)
4053 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4054 tbl_tx_filter_coef_rev4[2][i]);
4055}
4056
4057
4058static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4059{
4060 int i, j;
4061
4062 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4063
4064 for (i = 0; i < 3; i++)
4065 for (j = 0; j < 15; j++)
4066 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4067 tbl_tx_filter_coef_rev4[i][j]);
4068
4069 if (dev->phy.is_40mhz) {
4070 for (j = 0; j < 15; j++)
4071 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4072 tbl_tx_filter_coef_rev4[3][j]);
4073 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4074 for (j = 0; j < 15; j++)
4075 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4076 tbl_tx_filter_coef_rev4[5][j]);
4077 }
4078
4079 if (dev->phy.channel == 14)
4080 for (j = 0; j < 15; j++)
4081 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4082 tbl_tx_filter_coef_rev4[6][j]);
4083}
4084
4085
4086static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4087{
4088 struct b43_phy_n *nphy = dev->phy.n;
4089
4090 u16 curr_gain[2];
4091 struct nphy_txgains target;
4092 const u32 *table = NULL;
4093
4094 if (!nphy->txpwrctrl) {
4095 int i;
4096
4097 if (nphy->hang_avoid)
4098 b43_nphy_stay_in_carrier_search(dev, true);
4099 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4100 if (nphy->hang_avoid)
4101 b43_nphy_stay_in_carrier_search(dev, false);
4102
4103 for (i = 0; i < 2; ++i) {
4104 if (dev->phy.rev >= 3) {
4105 target.ipa[i] = curr_gain[i] & 0x000F;
4106 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4107 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4108 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4109 } else {
4110 target.ipa[i] = curr_gain[i] & 0x0003;
4111 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4112 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4113 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4114 }
4115 }
4116 } else {
4117 int i;
4118 u16 index[2];
4119 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4120 B43_NPHY_TXPCTL_STAT_BIDX) >>
4121 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4122 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4123 B43_NPHY_TXPCTL_STAT_BIDX) >>
4124 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4125
4126 for (i = 0; i < 2; ++i) {
4127 table = b43_nphy_get_tx_gain_table(dev);
4128 if (dev->phy.rev >= 3) {
4129 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4130 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4131 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4132 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4133 } else {
4134 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4135 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4136 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4137 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4138 }
4139 }
4140 }
4141
4142 return target;
4143}
4144
4145
4146static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4147{
4148 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4149
4150 if (dev->phy.rev >= 3) {
4151 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4152 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4153 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4154 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4155 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4156 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4157 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4158 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4159 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4160 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4161 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4162 b43_nphy_reset_cca(dev);
4163 } else {
4164 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4165 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4166 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4167 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4168 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4169 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4170 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4171 }
4172}
4173
4174
4175static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4176{
4177 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4178 u16 tmp;
4179
4180 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4181 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4182 if (dev->phy.rev >= 3) {
4183 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4184 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4185
4186 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4187 regs[2] = tmp;
4188 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4189
4190 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4191 regs[3] = tmp;
4192 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4193
4194 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4195 b43_phy_mask(dev, B43_NPHY_BBCFG,
4196 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4197
4198 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4199 regs[5] = tmp;
4200 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4201
4202 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4203 regs[6] = tmp;
4204 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4205 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4206 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4207
4208 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4209 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4210 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4211
4212 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4213 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4214 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4215 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4216 } else {
4217 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4218 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4219 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4220 regs[2] = tmp;
4221 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4222 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4223 regs[3] = tmp;
4224 tmp |= 0x2000;
4225 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4226 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4227 regs[4] = tmp;
4228 tmp |= 0x2000;
4229 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4230 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4231 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4232 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4233 tmp = 0x0180;
4234 else
4235 tmp = 0x0120;
4236 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4237 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4238 }
4239}
4240
4241
4242static void b43_nphy_save_cal(struct b43_wldev *dev)
4243{
4244 struct b43_phy_n *nphy = dev->phy.n;
4245
4246 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4247 u16 *txcal_radio_regs = NULL;
4248 struct b43_chanspec *iqcal_chanspec;
4249 u16 *table = NULL;
4250
4251 if (nphy->hang_avoid)
4252 b43_nphy_stay_in_carrier_search(dev, 1);
4253
4254 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4255 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4256 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4257 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4258 table = nphy->cal_cache.txcal_coeffs_2G;
4259 } else {
4260 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4261 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4262 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4263 table = nphy->cal_cache.txcal_coeffs_5G;
4264 }
4265
4266 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4267
4268 if (dev->phy.rev >= 3) {
4269 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4270 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4271 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4272 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4273 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4274 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4275 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4276 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4277 } else {
4278 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4279 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4280 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4281 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4282 }
4283 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4284 iqcal_chanspec->channel_type = dev->phy.channel_type;
4285 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4286
4287 if (nphy->hang_avoid)
4288 b43_nphy_stay_in_carrier_search(dev, 0);
4289}
4290
4291
4292static void b43_nphy_restore_cal(struct b43_wldev *dev)
4293{
4294 struct b43_phy_n *nphy = dev->phy.n;
4295
4296 u16 coef[4];
4297 u16 *loft = NULL;
4298 u16 *table = NULL;
4299
4300 int i;
4301 u16 *txcal_radio_regs = NULL;
4302 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4303
4304 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4305 if (!nphy->iqcal_chanspec_2G.center_freq)
4306 return;
4307 table = nphy->cal_cache.txcal_coeffs_2G;
4308 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4309 } else {
4310 if (!nphy->iqcal_chanspec_5G.center_freq)
4311 return;
4312 table = nphy->cal_cache.txcal_coeffs_5G;
4313 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4314 }
4315
4316 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4317
4318 for (i = 0; i < 4; i++) {
4319 if (dev->phy.rev >= 3)
4320 table[i] = coef[i];
4321 else
4322 coef[i] = 0;
4323 }
4324
4325 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4326 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4327 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4328
4329 if (dev->phy.rev < 2)
4330 b43_nphy_tx_iq_workaround(dev);
4331
4332 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4333 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4334 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4335 } else {
4336 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4337 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4338 }
4339
4340
4341 if (dev->phy.rev >= 3) {
4342 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4343 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4344 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4345 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4346 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4347 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4348 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4349 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4350 } else {
4351 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4352 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4353 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4354 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4355 }
4356 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4357}
4358
4359
4360static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4361 struct nphy_txgains target,
4362 bool full, bool mphase)
4363{
4364 struct b43_phy_n *nphy = dev->phy.n;
4365 int i;
4366 int error = 0;
4367 int freq;
4368 bool avoid = false;
4369 u8 length;
4370 u16 tmp, core, type, count, max, numb, last = 0, cmd;
4371 const u16 *table;
4372 bool phy6or5x;
4373
4374 u16 buffer[11];
4375 u16 diq_start = 0;
4376 u16 save[2];
4377 u16 gain[2];
4378 struct nphy_iqcal_params params[2];
4379 bool updated[2] = { };
4380
4381 b43_nphy_stay_in_carrier_search(dev, true);
4382
4383 if (dev->phy.rev >= 4) {
4384 avoid = nphy->hang_avoid;
4385 nphy->hang_avoid = false;
4386 }
4387
4388 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4389
4390 for (i = 0; i < 2; i++) {
4391 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
4392 gain[i] = params[i].cal_gain;
4393 }
4394
4395 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4396
4397 b43_nphy_tx_cal_radio_setup(dev);
4398 b43_nphy_tx_cal_phy_setup(dev);
4399
4400 phy6or5x = dev->phy.rev >= 6 ||
4401 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4402 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4403 if (phy6or5x) {
4404 if (dev->phy.is_40mhz) {
4405 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4406 tbl_tx_iqlo_cal_loft_ladder_40);
4407 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4408 tbl_tx_iqlo_cal_iqimb_ladder_40);
4409 } else {
4410 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4411 tbl_tx_iqlo_cal_loft_ladder_20);
4412 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4413 tbl_tx_iqlo_cal_iqimb_ladder_20);
4414 }
4415 }
4416
4417 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4418
4419 if (!dev->phy.is_40mhz)
4420 freq = 2500;
4421 else
4422 freq = 5000;
4423
4424 if (nphy->mphase_cal_phase_id > 2)
4425 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4426 0xFFFF, 0, true, false);
4427 else
4428 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4429
4430 if (error == 0) {
4431 if (nphy->mphase_cal_phase_id > 2) {
4432 table = nphy->mphase_txcal_bestcoeffs;
4433 length = 11;
4434 if (dev->phy.rev < 3)
4435 length -= 2;
4436 } else {
4437 if (!full && nphy->txiqlocal_coeffsvalid) {
4438 table = nphy->txiqlocal_bestc;
4439 length = 11;
4440 if (dev->phy.rev < 3)
4441 length -= 2;
4442 } else {
4443 full = true;
4444 if (dev->phy.rev >= 3) {
4445 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4446 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4447 } else {
4448 table = tbl_tx_iqlo_cal_startcoefs;
4449 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4450 }
4451 }
4452 }
4453
4454 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4455
4456 if (full) {
4457 if (dev->phy.rev >= 3)
4458 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4459 else
4460 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4461 } else {
4462 if (dev->phy.rev >= 3)
4463 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4464 else
4465 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4466 }
4467
4468 if (mphase) {
4469 count = nphy->mphase_txcal_cmdidx;
4470 numb = min(max,
4471 (u16)(count + nphy->mphase_txcal_numcmds));
4472 } else {
4473 count = 0;
4474 numb = max;
4475 }
4476
4477 for (; count < numb; count++) {
4478 if (full) {
4479 if (dev->phy.rev >= 3)
4480 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4481 else
4482 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4483 } else {
4484 if (dev->phy.rev >= 3)
4485 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4486 else
4487 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4488 }
4489
4490 core = (cmd & 0x3000) >> 12;
4491 type = (cmd & 0x0F00) >> 8;
4492
4493 if (phy6or5x && updated[core] == 0) {
4494 b43_nphy_update_tx_cal_ladder(dev, core);
4495 updated[core] = true;
4496 }
4497
4498 tmp = (params[core].ncorr[type] << 8) | 0x66;
4499 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4500
4501 if (type == 1 || type == 3 || type == 4) {
4502 buffer[0] = b43_ntab_read(dev,
4503 B43_NTAB16(15, 69 + core));
4504 diq_start = buffer[0];
4505 buffer[0] = 0;
4506 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4507 0);
4508 }
4509
4510 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4511 for (i = 0; i < 2000; i++) {
4512 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4513 if (tmp & 0xC000)
4514 break;
4515 udelay(10);
4516 }
4517
4518 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4519 buffer);
4520 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4521 buffer);
4522
4523 if (type == 1 || type == 3 || type == 4)
4524 buffer[0] = diq_start;
4525 }
4526
4527 if (mphase)
4528 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4529
4530 last = (dev->phy.rev < 3) ? 6 : 7;
4531
4532 if (!mphase || nphy->mphase_cal_phase_id == last) {
4533 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4534 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4535 if (dev->phy.rev < 3) {
4536 buffer[0] = 0;
4537 buffer[1] = 0;
4538 buffer[2] = 0;
4539 buffer[3] = 0;
4540 }
4541 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4542 buffer);
4543 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4544 buffer);
4545 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4546 buffer);
4547 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4548 buffer);
4549 length = 11;
4550 if (dev->phy.rev < 3)
4551 length -= 2;
4552 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4553 nphy->txiqlocal_bestc);
4554 nphy->txiqlocal_coeffsvalid = true;
4555 nphy->txiqlocal_chanspec.center_freq =
4556 dev->phy.channel_freq;
4557 nphy->txiqlocal_chanspec.channel_type =
4558 dev->phy.channel_type;
4559 } else {
4560 length = 11;
4561 if (dev->phy.rev < 3)
4562 length -= 2;
4563 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4564 nphy->mphase_txcal_bestcoeffs);
4565 }
4566
4567 b43_nphy_stop_playback(dev);
4568 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4569 }
4570
4571 b43_nphy_tx_cal_phy_cleanup(dev);
4572 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4573
4574 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4575 b43_nphy_tx_iq_workaround(dev);
4576
4577 if (dev->phy.rev >= 4)
4578 nphy->hang_avoid = avoid;
4579
4580 b43_nphy_stay_in_carrier_search(dev, false);
4581
4582 return error;
4583}
4584
4585
4586static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4587{
4588 struct b43_phy_n *nphy = dev->phy.n;
4589 u8 i;
4590 u16 buffer[7];
4591 bool equal = true;
4592
4593 if (!nphy->txiqlocal_coeffsvalid ||
4594 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4595 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4596 return;
4597
4598 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4599 for (i = 0; i < 4; i++) {
4600 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4601 equal = false;
4602 break;
4603 }
4604 }
4605
4606 if (!equal) {
4607 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4608 nphy->txiqlocal_bestc);
4609 for (i = 0; i < 4; i++)
4610 buffer[i] = 0;
4611 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4612 buffer);
4613 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4614 &nphy->txiqlocal_bestc[5]);
4615 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4616 &nphy->txiqlocal_bestc[5]);
4617 }
4618}
4619
4620
4621static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4622 struct nphy_txgains target, u8 type, bool debug)
4623{
4624 struct b43_phy_n *nphy = dev->phy.n;
4625 int i, j, index;
4626 u8 rfctl[2];
4627 u8 afectl_core;
4628 u16 tmp[6];
4629 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4630 u32 real, imag;
4631 enum ieee80211_band band;
4632
4633 u8 use;
4634 u16 cur_hpf;
4635 u16 lna[3] = { 3, 3, 1 };
4636 u16 hpf1[3] = { 7, 2, 0 };
4637 u16 hpf2[3] = { 2, 0, 0 };
4638 u32 power[3] = { };
4639 u16 gain_save[2];
4640 u16 cal_gain[2];
4641 struct nphy_iqcal_params cal_params[2];
4642 struct nphy_iq_est est;
4643 int ret = 0;
4644 bool playtone = true;
4645 int desired = 13;
4646
4647 b43_nphy_stay_in_carrier_search(dev, 1);
4648
4649 if (dev->phy.rev < 2)
4650 b43_nphy_reapply_tx_cal_coeffs(dev);
4651 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4652 for (i = 0; i < 2; i++) {
4653 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4654 cal_gain[i] = cal_params[i].cal_gain;
4655 }
4656 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4657
4658 for (i = 0; i < 2; i++) {
4659 if (i == 0) {
4660 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4661 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4662 afectl_core = B43_NPHY_AFECTL_C1;
4663 } else {
4664 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4665 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4666 afectl_core = B43_NPHY_AFECTL_C2;
4667 }
4668
4669 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4670 tmp[2] = b43_phy_read(dev, afectl_core);
4671 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4672 tmp[4] = b43_phy_read(dev, rfctl[0]);
4673 tmp[5] = b43_phy_read(dev, rfctl[1]);
4674
4675 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4676 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4677 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4678 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4679 (1 - i));
4680 b43_phy_set(dev, afectl_core, 0x0006);
4681 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4682
4683 band = b43_current_band(dev->wl);
4684
4685 if (nphy->rxcalparams & 0xFF000000) {
4686 if (band == IEEE80211_BAND_5GHZ)
4687 b43_phy_write(dev, rfctl[0], 0x140);
4688 else
4689 b43_phy_write(dev, rfctl[0], 0x110);
4690 } else {
4691 if (band == IEEE80211_BAND_5GHZ)
4692 b43_phy_write(dev, rfctl[0], 0x180);
4693 else
4694 b43_phy_write(dev, rfctl[0], 0x120);
4695 }
4696
4697 if (band == IEEE80211_BAND_5GHZ)
4698 b43_phy_write(dev, rfctl[1], 0x148);
4699 else
4700 b43_phy_write(dev, rfctl[1], 0x114);
4701
4702 if (nphy->rxcalparams & 0x10000) {
4703 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4704 (i + 1));
4705 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4706 (2 - i));
4707 }
4708
4709 for (j = 0; j < 4; j++) {
4710 if (j < 3) {
4711 cur_lna = lna[j];
4712 cur_hpf1 = hpf1[j];
4713 cur_hpf2 = hpf2[j];
4714 } else {
4715 if (power[1] > 10000) {
4716 use = 1;
4717 cur_hpf = cur_hpf1;
4718 index = 2;
4719 } else {
4720 if (power[0] > 10000) {
4721 use = 1;
4722 cur_hpf = cur_hpf1;
4723 index = 1;
4724 } else {
4725 index = 0;
4726 use = 2;
4727 cur_hpf = cur_hpf2;
4728 }
4729 }
4730 cur_lna = lna[index];
4731 cur_hpf1 = hpf1[index];
4732 cur_hpf2 = hpf2[index];
4733 cur_hpf += desired - hweight32(power[index]);
4734 cur_hpf = clamp_val(cur_hpf, 0, 10);
4735 if (use == 1)
4736 cur_hpf1 = cur_hpf;
4737 else
4738 cur_hpf2 = cur_hpf;
4739 }
4740
4741 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4742 (cur_lna << 2));
4743 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
4744 false);
4745 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4746 b43_nphy_stop_playback(dev);
4747
4748 if (playtone) {
4749 ret = b43_nphy_tx_tone(dev, 4000,
4750 (nphy->rxcalparams & 0xFFFF),
4751 false, false);
4752 playtone = false;
4753 } else {
4754 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4755 false, false);
4756 }
4757
4758 if (ret == 0) {
4759 if (j < 3) {
4760 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4761 false);
4762 if (i == 0) {
4763 real = est.i0_pwr;
4764 imag = est.q0_pwr;
4765 } else {
4766 real = est.i1_pwr;
4767 imag = est.q1_pwr;
4768 }
4769 power[i] = ((real + imag) / 1024) + 1;
4770 } else {
4771 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4772 }
4773 b43_nphy_stop_playback(dev);
4774 }
4775
4776 if (ret != 0)
4777 break;
4778 }
4779
4780 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4781 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4782 b43_phy_write(dev, rfctl[1], tmp[5]);
4783 b43_phy_write(dev, rfctl[0], tmp[4]);
4784 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4785 b43_phy_write(dev, afectl_core, tmp[2]);
4786 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4787
4788 if (ret != 0)
4789 break;
4790 }
4791
4792 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
4793 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4794 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4795
4796 b43_nphy_stay_in_carrier_search(dev, 0);
4797
4798 return ret;
4799}
4800
4801static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4802 struct nphy_txgains target, u8 type, bool debug)
4803{
4804 return -1;
4805}
4806
4807
4808static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4809 struct nphy_txgains target, u8 type, bool debug)
4810{
4811 if (dev->phy.rev >= 3)
4812 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4813 else
4814 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4815}
4816
4817
4818static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4819{
4820 struct b43_phy *phy = &dev->phy;
4821 struct b43_phy_n *nphy = phy->n;
4822
4823
4824 nphy->phyrxchain = mask;
4825
4826 if (0 )
4827 return;
4828
4829 b43_mac_suspend(dev);
4830
4831 if (nphy->hang_avoid)
4832 b43_nphy_stay_in_carrier_search(dev, true);
4833
4834 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4835 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4836
4837 if ((mask & 0x3) != 0x3) {
4838 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4839 if (dev->phy.rev >= 3) {
4840
4841 }
4842 } else {
4843 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4844 if (dev->phy.rev >= 3) {
4845
4846 }
4847 }
4848
4849 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4850
4851 if (nphy->hang_avoid)
4852 b43_nphy_stay_in_carrier_search(dev, false);
4853
4854 b43_mac_enable(dev);
4855}
4856
4857
4858
4859
4860
4861
4862static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4863{
4864 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4865
4866 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4867 if (preamble == 1)
4868 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4869 else
4870 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4871
4872 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4873}
4874
4875
4876static void b43_nphy_bphy_init(struct b43_wldev *dev)
4877{
4878 unsigned int i;
4879 u16 val;
4880
4881 val = 0x1E1F;
4882 for (i = 0; i < 16; i++) {
4883 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4884 val -= 0x202;
4885 }
4886 val = 0x3E3F;
4887 for (i = 0; i < 16; i++) {
4888 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4889 val -= 0x202;
4890 }
4891 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4892}
4893
4894
4895static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4896{
4897 if (dev->phy.rev >= 3) {
4898 if (!init)
4899 return;
4900 if (0 ) {
4901 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4902 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4903 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4904 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4905 }
4906 } else {
4907 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4908 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4909
4910 switch (dev->dev->bus_type) {
4911#ifdef CONFIG_B43_BCMA
4912 case B43_BUS_BCMA:
4913 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4914 0xFC00, 0xFC00);
4915 break;
4916#endif
4917#ifdef CONFIG_B43_SSB
4918 case B43_BUS_SSB:
4919 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4920 0xFC00, 0xFC00);
4921 break;
4922#endif
4923 }
4924
4925 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4926 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4927 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4928 0);
4929
4930 if (init) {
4931 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4932 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4933 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4934 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4935 }
4936 }
4937}
4938
4939
4940static int b43_phy_initn(struct b43_wldev *dev)
4941{
4942 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4943 struct b43_phy *phy = &dev->phy;
4944 struct b43_phy_n *nphy = phy->n;
4945 u8 tx_pwr_state;
4946 struct nphy_txgains target;
4947 u16 tmp;
4948 enum ieee80211_band tmp2;
4949 bool do_rssi_cal;
4950
4951 u16 clip[2];
4952 bool do_cal = false;
4953
4954 if ((dev->phy.rev >= 3) &&
4955 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4956 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4957 switch (dev->dev->bus_type) {
4958#ifdef CONFIG_B43_BCMA
4959 case B43_BUS_BCMA:
4960 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4961 BCMA_CC_CHIPCTL, 0x40);
4962 break;
4963#endif
4964#ifdef CONFIG_B43_SSB
4965 case B43_BUS_SSB:
4966 chipco_set32(&dev->dev->sdev->bus->chipco,
4967 SSB_CHIPCO_CHIPCTL, 0x40);
4968 break;
4969#endif
4970 }
4971 }
4972 nphy->deaf_count = 0;
4973 b43_nphy_tables_init(dev);
4974 nphy->crsminpwr_adjusted = false;
4975 nphy->noisevars_adjusted = false;
4976
4977
4978 if (dev->phy.rev >= 3) {
4979 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4980 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4981 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4982 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4983 } else {
4984 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4985 }
4986 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4987 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4988 if (dev->phy.rev < 6) {
4989 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4990 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4991 }
4992 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4993 ~(B43_NPHY_RFSEQMODE_CAOVER |
4994 B43_NPHY_RFSEQMODE_TROVER));
4995 if (dev->phy.rev >= 3)
4996 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4997 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4998
4999 if (dev->phy.rev <= 2) {
5000 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5001 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5002 ~B43_NPHY_BPHY_CTL3_SCALE,
5003 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5004 }
5005 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5006 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5007
5008 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
5009 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5010 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
5011 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5012 else
5013 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5014 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5015 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5016 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
5017
5018 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5019 b43_nphy_update_txrx_chain(dev);
5020
5021 if (phy->rev < 2) {
5022 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5023 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5024 }
5025
5026 tmp2 = b43_current_band(dev->wl);
5027 if (b43_nphy_ipa(dev)) {
5028 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5029 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5030 nphy->papd_epsilon_offset[0] << 7);
5031 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5032 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5033 nphy->papd_epsilon_offset[1] << 7);
5034 b43_nphy_int_pa_set_tx_dig_filters(dev);
5035 } else if (phy->rev >= 5) {
5036 b43_nphy_ext_pa_set_tx_dig_filters(dev);
5037 }
5038
5039 b43_nphy_workarounds(dev);
5040
5041
5042 b43_phy_force_clock(dev, 1);
5043 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5044 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5045 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5046 b43_phy_force_clock(dev, 0);
5047
5048 b43_mac_phy_clock_set(dev, true);
5049
5050 b43_nphy_pa_override(dev, false);
5051 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5052 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5053 b43_nphy_pa_override(dev, true);
5054
5055 b43_nphy_classifier(dev, 0, 0);
5056 b43_nphy_read_clip_detection(dev, clip);
5057 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5058 b43_nphy_bphy_init(dev);
5059
5060 tx_pwr_state = nphy->txpwrctrl;
5061 b43_nphy_tx_power_ctrl(dev, false);
5062 b43_nphy_tx_power_fix(dev);
5063 b43_nphy_tx_power_ctl_idle_tssi(dev);
5064 b43_nphy_tx_power_ctl_setup(dev);
5065 b43_nphy_tx_gain_table_upload(dev);
5066
5067 if (nphy->phyrxchain != 3)
5068 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5069 if (nphy->mphase_cal_phase_id > 0)
5070 ;
5071
5072 do_rssi_cal = false;
5073 if (phy->rev >= 3) {
5074 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5075 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5076 else
5077 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5078
5079 if (do_rssi_cal)
5080 b43_nphy_rssi_cal(dev);
5081 else
5082 b43_nphy_restore_rssi_cal(dev);
5083 } else {
5084 b43_nphy_rssi_cal(dev);
5085 }
5086
5087 if (!((nphy->measure_hold & 0x6) != 0)) {
5088 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5089 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5090 else
5091 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5092
5093 if (nphy->mute)
5094 do_cal = false;
5095
5096 if (do_cal) {
5097 target = b43_nphy_get_tx_gains(dev);
5098
5099 if (nphy->antsel_type == 2)
5100 b43_nphy_superswitch_init(dev, true);
5101 if (nphy->perical != 2) {
5102 b43_nphy_rssi_cal(dev);
5103 if (phy->rev >= 3) {
5104 nphy->cal_orig_pwr_idx[0] =
5105 nphy->txpwrindex[0].index_internal;
5106 nphy->cal_orig_pwr_idx[1] =
5107 nphy->txpwrindex[1].index_internal;
5108
5109 target = b43_nphy_get_tx_gains(dev);
5110 }
5111 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5112 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5113 b43_nphy_save_cal(dev);
5114 } else if (nphy->mphase_cal_phase_id == 0)
5115 ;
5116 } else {
5117 b43_nphy_restore_cal(dev);
5118 }
5119 }
5120
5121 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5122 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5123 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5124 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5125 if (phy->rev >= 3 && phy->rev <= 6)
5126 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
5127 b43_nphy_tx_lp_fbw(dev);
5128 if (phy->rev >= 3)
5129 b43_nphy_spur_workaround(dev);
5130
5131 return 0;
5132}
5133
5134
5135
5136
5137
5138static void b43_chantab_phy_upload(struct b43_wldev *dev,
5139 const struct b43_phy_n_sfo_cfg *e)
5140{
5141 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5142 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5143 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5144 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5145 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5146 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5147}
5148
5149
5150static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5151{
5152 switch (dev->dev->bus_type) {
5153#ifdef CONFIG_B43_BCMA
5154 case B43_BUS_BCMA:
5155 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5156 avoid);
5157 break;
5158#endif
5159#ifdef CONFIG_B43_SSB
5160 case B43_BUS_SSB:
5161 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5162 avoid);
5163 break;
5164#endif
5165 }
5166}
5167
5168
5169static void b43_nphy_channel_setup(struct b43_wldev *dev,
5170 const struct b43_phy_n_sfo_cfg *e,
5171 struct ieee80211_channel *new_channel)
5172{
5173 struct b43_phy *phy = &dev->phy;
5174 struct b43_phy_n *nphy = dev->phy.n;
5175 int ch = new_channel->hw_value;
5176
5177 u16 old_band_5ghz;
5178 u32 tmp32;
5179
5180 old_band_5ghz =
5181 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5182 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5183 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5184 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5185 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5186 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5187 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5188 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5189 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5190 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5191 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5192 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5193 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5194 }
5195
5196 b43_chantab_phy_upload(dev, e);
5197
5198 if (new_channel->hw_value == 14) {
5199 b43_nphy_classifier(dev, 2, 0);
5200 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5201 } else {
5202 b43_nphy_classifier(dev, 2, 2);
5203 if (new_channel->band == IEEE80211_BAND_2GHZ)
5204 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5205 }
5206
5207 if (!nphy->txpwrctrl)
5208 b43_nphy_tx_power_fix(dev);
5209
5210 if (dev->phy.rev < 3)
5211 b43_nphy_adjust_lna_gain_table(dev);
5212
5213 b43_nphy_tx_lp_fbw(dev);
5214
5215 if (dev->phy.rev >= 3 &&
5216 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5217 bool avoid = false;
5218 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5219 avoid = true;
5220 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5221 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5222 avoid = true;
5223 } else {
5224 if (nphy->aband_spurwar_en &&
5225 (ch == 38 || ch == 102 || ch == 118))
5226 avoid = dev->dev->chip_id == 0x4716;
5227 }
5228
5229 b43_nphy_pmu_spur_avoid(dev, avoid);
5230
5231 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5232 dev->dev->chip_id == 43225) {
5233 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5234 avoid ? 0x5341 : 0x8889);
5235 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5236 }
5237
5238 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5239 ;
5240
5241 if (avoid)
5242 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5243 else
5244 b43_phy_mask(dev, B43_NPHY_BBCFG,
5245 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5246
5247 b43_nphy_reset_cca(dev);
5248
5249
5250 }
5251
5252 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5253
5254 if (phy->rev >= 3)
5255 b43_nphy_spur_workaround(dev);
5256}
5257
5258
5259static int b43_nphy_set_channel(struct b43_wldev *dev,
5260 struct ieee80211_channel *channel,
5261 enum nl80211_channel_type channel_type)
5262{
5263 struct b43_phy *phy = &dev->phy;
5264
5265 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5266 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5267
5268 u8 tmp;
5269
5270 if (dev->phy.rev >= 3) {
5271 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5272 channel->center_freq);
5273 if (!tabent_r3)
5274 return -ESRCH;
5275 } else {
5276 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5277 channel->hw_value);
5278 if (!tabent_r2)
5279 return -ESRCH;
5280 }
5281
5282
5283
5284 phy->channel = channel->hw_value;
5285 phy->channel_freq = channel->center_freq;
5286
5287 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5288 b43_channel_type_is_40mhz(channel_type))
5289 ;
5290
5291 if (channel_type == NL80211_CHAN_HT40PLUS)
5292 b43_phy_set(dev, B43_NPHY_RXCTL,
5293 B43_NPHY_RXCTL_BSELU20);
5294 else if (channel_type == NL80211_CHAN_HT40MINUS)
5295 b43_phy_mask(dev, B43_NPHY_RXCTL,
5296 ~B43_NPHY_RXCTL_BSELU20);
5297
5298 if (dev->phy.rev >= 3) {
5299 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5300 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5301 b43_radio_2056_setup(dev, tabent_r3);
5302 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5303 } else {
5304 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5305 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5306 b43_radio_2055_setup(dev, tabent_r2);
5307 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5308 }
5309
5310 return 0;
5311}
5312
5313
5314
5315
5316
5317static int b43_nphy_op_allocate(struct b43_wldev *dev)
5318{
5319 struct b43_phy_n *nphy;
5320
5321 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5322 if (!nphy)
5323 return -ENOMEM;
5324 dev->phy.n = nphy;
5325
5326 return 0;
5327}
5328
5329static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5330{
5331 struct b43_phy *phy = &dev->phy;
5332 struct b43_phy_n *nphy = phy->n;
5333 struct ssb_sprom *sprom = dev->dev->bus_sprom;
5334
5335 memset(nphy, 0, sizeof(*nphy));
5336
5337 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5338 nphy->spur_avoid = (phy->rev >= 3) ?
5339 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5340 nphy->init_por = true;
5341 nphy->gain_boost = true;
5342 nphy->txrx_chain = 2;
5343 nphy->phyrxchain = 3;
5344 nphy->perical = 2;
5345
5346
5347 nphy->tx_pwr_idx[0] = 128;
5348 nphy->tx_pwr_idx[1] = 128;
5349
5350
5351 nphy->txpwrctrl = false;
5352 nphy->pwg_gain_5ghz = false;
5353 if (dev->phy.rev >= 3 ||
5354 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5355 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5356 nphy->txpwrctrl = true;
5357 nphy->pwg_gain_5ghz = true;
5358 } else if (sprom->revision >= 4) {
5359 if (dev->phy.rev >= 2 &&
5360 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5361 nphy->txpwrctrl = true;
5362#ifdef CONFIG_B43_SSB
5363 if (dev->dev->bus_type == B43_BUS_SSB &&
5364 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5365 struct pci_dev *pdev =
5366 dev->dev->sdev->bus->host_pci;
5367 if (pdev->device == 0x4328 ||
5368 pdev->device == 0x432a)
5369 nphy->pwg_gain_5ghz = true;
5370 }
5371#endif
5372 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5373 nphy->pwg_gain_5ghz = true;
5374 }
5375 }
5376
5377 if (dev->phy.rev >= 3) {
5378 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5379 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5380 }
5381
5382 nphy->init_por = true;
5383}
5384
5385static void b43_nphy_op_free(struct b43_wldev *dev)
5386{
5387 struct b43_phy *phy = &dev->phy;
5388 struct b43_phy_n *nphy = phy->n;
5389
5390 kfree(nphy);
5391 phy->n = NULL;
5392}
5393
5394static int b43_nphy_op_init(struct b43_wldev *dev)
5395{
5396 return b43_phy_initn(dev);
5397}
5398
5399static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5400{
5401#if B43_DEBUG
5402 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5403
5404 b43err(dev->wl, "Invalid OFDM PHY access at "
5405 "0x%04X on N-PHY\n", offset);
5406 dump_stack();
5407 }
5408 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5409
5410 b43err(dev->wl, "Invalid EXT-G PHY access at "
5411 "0x%04X on N-PHY\n", offset);
5412 dump_stack();
5413 }
5414#endif
5415}
5416
5417static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5418{
5419 check_phyreg(dev, reg);
5420 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5421 return b43_read16(dev, B43_MMIO_PHY_DATA);
5422}
5423
5424static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5425{
5426 check_phyreg(dev, reg);
5427 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5428 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5429}
5430
5431static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5432 u16 set)
5433{
5434 check_phyreg(dev, reg);
5435 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5436 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5437}
5438
5439static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5440{
5441
5442 B43_WARN_ON(reg == 1);
5443
5444 reg |= 0x100;
5445
5446 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5447 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5448}
5449
5450static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5451{
5452
5453 B43_WARN_ON(reg == 1);
5454
5455 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5456 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5457}
5458
5459
5460static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5461 bool blocked)
5462{
5463 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5464 b43err(dev->wl, "MAC not suspended\n");
5465
5466 if (blocked) {
5467 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5468 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5469 if (dev->phy.rev >= 7) {
5470
5471 } else if (dev->phy.rev >= 3) {
5472 b43_radio_mask(dev, 0x09, ~0x2);
5473
5474 b43_radio_write(dev, 0x204D, 0);
5475 b43_radio_write(dev, 0x2053, 0);
5476 b43_radio_write(dev, 0x2058, 0);
5477 b43_radio_write(dev, 0x205E, 0);
5478 b43_radio_mask(dev, 0x2062, ~0xF0);
5479 b43_radio_write(dev, 0x2064, 0);
5480
5481 b43_radio_write(dev, 0x304D, 0);
5482 b43_radio_write(dev, 0x3053, 0);
5483 b43_radio_write(dev, 0x3058, 0);
5484 b43_radio_write(dev, 0x305E, 0);
5485 b43_radio_mask(dev, 0x3062, ~0xF0);
5486 b43_radio_write(dev, 0x3064, 0);
5487 }
5488 } else {
5489 if (dev->phy.rev >= 7) {
5490 b43_radio_2057_init(dev);
5491 b43_switch_channel(dev, dev->phy.channel);
5492 } else if (dev->phy.rev >= 3) {
5493 b43_radio_init2056(dev);
5494 b43_switch_channel(dev, dev->phy.channel);
5495 } else {
5496 b43_radio_init2055(dev);
5497 }
5498 }
5499}
5500
5501
5502static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5503{
5504 u16 override = on ? 0x0 : 0x7FFF;
5505 u16 core = on ? 0xD : 0x00FD;
5506
5507 if (dev->phy.rev >= 3) {
5508 if (on) {
5509 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5510 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5511 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5512 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5513 } else {
5514 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5515 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5516 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5517 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5518 }
5519 } else {
5520 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5521 }
5522}
5523
5524static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5525 unsigned int new_channel)
5526{
5527 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5528 enum nl80211_channel_type channel_type =
5529 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5530
5531 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5532 if ((new_channel < 1) || (new_channel > 14))
5533 return -EINVAL;
5534 } else {
5535 if (new_channel > 200)
5536 return -EINVAL;
5537 }
5538
5539 return b43_nphy_set_channel(dev, channel, channel_type);
5540}
5541
5542static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5543{
5544 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5545 return 1;
5546 return 36;
5547}
5548
5549const struct b43_phy_operations b43_phyops_n = {
5550 .allocate = b43_nphy_op_allocate,
5551 .free = b43_nphy_op_free,
5552 .prepare_structs = b43_nphy_op_prepare_structs,
5553 .init = b43_nphy_op_init,
5554 .phy_read = b43_nphy_op_read,
5555 .phy_write = b43_nphy_op_write,
5556 .phy_maskset = b43_nphy_op_maskset,
5557 .radio_read = b43_nphy_op_radio_read,
5558 .radio_write = b43_nphy_op_radio_write,
5559 .software_rfkill = b43_nphy_op_software_rfkill,
5560 .switch_analog = b43_nphy_op_switch_analog,
5561 .switch_channel = b43_nphy_op_switch_channel,
5562 .get_default_chan = b43_nphy_op_get_default_chan,
5563 .recalc_txpower = b43_nphy_op_recalc_txpower,
5564 .adjust_txpower = b43_nphy_op_adjust_txpower,
5565};
5566
