LXR linux/drivers/net/wireless/brcm80211/brcmfmac/sdio

   1/*
   2 * Copyright (c) 2011 Broadcom Corporation
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef _BRCMFMAC_SDIO_CHIP_H_
  18#define _BRCMFMAC_SDIO_CHIP_H_
  19
  20/*
  21 * Core reg address translation.
  22 * Both macro's returns a 32 bits byte address on the backplane bus.
  23 */
  24#define CORE_CC_REG(base, field) \
  25                (base + offsetof(struct chipcregs, field))
  26#define CORE_BUS_REG(base, field) \
  27                (base + offsetof(struct sdpcmd_regs, field))
  28#define CORE_SB(base, field) \
  29                (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
  30
  31/* SDIO function 1 register CHIPCLKCSR */
  32/* Force ALP request to backplane */
  33#define SBSDIO_FORCE_ALP                0x01
  34/* Force HT request to backplane */
  35#define SBSDIO_FORCE_HT                 0x02
  36/* Force ILP request to backplane */
  37#define SBSDIO_FORCE_ILP                0x04
  38/* Make ALP ready (power up xtal) */
  39#define SBSDIO_ALP_AVAIL_REQ            0x08
  40/* Make HT ready (power up PLL) */
  41#define SBSDIO_HT_AVAIL_REQ             0x10
  42/* Squelch clock requests from HW */
  43#define SBSDIO_FORCE_HW_CLKREQ_OFF      0x20
  44/* Status: ALP is ready */
  45#define SBSDIO_ALP_AVAIL                0x40
  46/* Status: HT is ready */
  47#define SBSDIO_HT_AVAIL                 0x80
  48#define SBSDIO_AVBITS           (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  49#define SBSDIO_ALPAV(regval)    ((regval) & SBSDIO_AVBITS)
  50#define SBSDIO_HTAV(regval)     (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  51#define SBSDIO_ALPONLY(regval)  (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  52#define SBSDIO_CLKAV(regval, alponly) \
  53        (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
  54
  55#define BRCMF_MAX_CORENUM       6
  56
  57struct chip_core_info {
  58        u16 id;
  59        u16 rev;
  60        u32 base;
  61        u32 wrapbase;
  62        u32 caps;
  63        u32 cib;
  64};
  65
  66struct chip_info {
  67        u32 chip;
  68        u32 chiprev;
  69        u32 socitype;
  70        /* core info */
  71        /* always put chipcommon core at 0, bus core at 1 */
  72        struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
  73        u32 pmurev;
  74        u32 pmucaps;
  75        u32 ramsize;
  76        u32 rambase;
  77        u32 rst_vec;    /* reset vertor for ARM CR4 core */
  78
  79        bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
  80                         u16 coreid);
  81        u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
  82                         u16 coreid);
  83        void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
  84                        struct chip_info *ci, u16 coreid, u32 core_bits);
  85        void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
  86                        struct chip_info *ci, u16 coreid, u32 core_bits);
  87};
  88
  89struct sbconfig {
  90        u32 PAD[2];
  91        u32 sbipsflag;  /* initiator port ocp slave flag */
  92        u32 PAD[3];
  93        u32 sbtpsflag;  /* target port ocp slave flag */
  94        u32 PAD[11];
  95        u32 sbtmerrloga;        /* (sonics >= 2.3) */
  96        u32 PAD;
  97        u32 sbtmerrlog; /* (sonics >= 2.3) */
  98        u32 PAD[3];
  99        u32 sbadmatch3; /* address match3 */
 100        u32 PAD;
 101        u32 sbadmatch2; /* address match2 */
 102        u32 PAD;
 103        u32 sbadmatch1; /* address match1 */
 104        u32 PAD[7];
 105        u32 sbimstate;  /* initiator agent state */
 106        u32 sbintvec;   /* interrupt mask */
 107        u32 sbtmstatelow;       /* target state */
 108        u32 sbtmstatehigh;      /* target state */
 109        u32 sbbwa0;             /* bandwidth allocation table0 */
 110        u32 PAD;
 111        u32 sbimconfiglow;      /* initiator configuration */
 112        u32 sbimconfighigh;     /* initiator configuration */
 113        u32 sbadmatch0; /* address match0 */
 114        u32 PAD;
 115        u32 sbtmconfiglow;      /* target configuration */
 116        u32 sbtmconfighigh;     /* target configuration */
 117        u32 sbbconfig;  /* broadcast configuration */
 118        u32 PAD;
 119        u32 sbbstate;   /* broadcast state */
 120        u32 PAD[3];
 121        u32 sbactcnfg;  /* activate configuration */
 122        u32 PAD[3];
 123        u32 sbflagst;   /* current sbflags */
 124        u32 PAD[3];
 125        u32 sbidlow;            /* identification */
 126        u32 sbidhigh;   /* identification */
 127};
 128
 129/* sdio core registers */
 130struct sdpcmd_regs {
 131        u32 corecontrol;                /* 0x00, rev8 */
 132        u32 corestatus;                 /* rev8 */
 133        u32 PAD[1];
 134        u32 biststatus;                 /* rev8 */
 135
 136        /* PCMCIA access */
 137        u16 pcmciamesportaladdr;        /* 0x010, rev8 */
 138        u16 PAD[1];
 139        u16 pcmciamesportalmask;        /* rev8 */
 140        u16 PAD[1];
 141        u16 pcmciawrframebc;            /* rev8 */
 142        u16 PAD[1];
 143        u16 pcmciaunderflowtimer;       /* rev8 */
 144        u16 PAD[1];
 145
 146        /* interrupt */
 147        u32 intstatus;                  /* 0x020, rev8 */
 148        u32 hostintmask;                /* rev8 */
 149        u32 intmask;                    /* rev8 */
 150        u32 sbintstatus;                /* rev8 */
 151        u32 sbintmask;                  /* rev8 */
 152        u32 funcintmask;                /* rev4 */
 153        u32 PAD[2];
 154        u32 tosbmailbox;                /* 0x040, rev8 */
 155        u32 tohostmailbox;              /* rev8 */
 156        u32 tosbmailboxdata;            /* rev8 */
 157        u32 tohostmailboxdata;          /* rev8 */
 158
 159        /* synchronized access to registers in SDIO clock domain */
 160        u32 sdioaccess;                 /* 0x050, rev8 */
 161        u32 PAD[3];
 162
 163        /* PCMCIA frame control */
 164        u8 pcmciaframectrl;             /* 0x060, rev8 */
 165        u8 PAD[3];
 166        u8 pcmciawatermark;             /* rev8 */
 167        u8 PAD[155];
 168
 169        /* interrupt batching control */
 170        u32 intrcvlazy;                 /* 0x100, rev8 */
 171        u32 PAD[3];
 172
 173        /* counters */
 174        u32 cmd52rd;                    /* 0x110, rev8 */
 175        u32 cmd52wr;                    /* rev8 */
 176        u32 cmd53rd;                    /* rev8 */
 177        u32 cmd53wr;                    /* rev8 */
 178        u32 abort;                      /* rev8 */
 179        u32 datacrcerror;               /* rev8 */
 180        u32 rdoutofsync;                /* rev8 */
 181        u32 wroutofsync;                /* rev8 */
 182        u32 writebusy;                  /* rev8 */
 183        u32 readwait;                   /* rev8 */
 184        u32 readterm;                   /* rev8 */
 185        u32 writeterm;                  /* rev8 */
 186        u32 PAD[40];
 187        u32 clockctlstatus;             /* rev8 */
 188        u32 PAD[7];
 189
 190        u32 PAD[128];                   /* DMA engines */
 191
 192        /* SDIO/PCMCIA CIS region */
 193        char cis[512];                  /* 0x400-0x5ff, rev6 */
 194
 195        /* PCMCIA function control registers */
 196        char pcmciafcr[256];            /* 0x600-6ff, rev6 */
 197        u16 PAD[55];
 198
 199        /* PCMCIA backplane access */
 200        u16 backplanecsr;               /* 0x76E, rev6 */
 201        u16 backplaneaddr0;             /* rev6 */
 202        u16 backplaneaddr1;             /* rev6 */
 203        u16 backplaneaddr2;             /* rev6 */
 204        u16 backplaneaddr3;             /* rev6 */
 205        u16 backplanedata0;             /* rev6 */
 206        u16 backplanedata1;             /* rev6 */
 207        u16 backplanedata2;             /* rev6 */
 208        u16 backplanedata3;             /* rev6 */
 209        u16 PAD[31];
 210
 211        /* sprom "size" & "blank" info */
 212        u16 spromstatus;                /* 0x7BE, rev2 */
 213        u32 PAD[464];
 214
 215        u16 PAD[0x80];
 216};
 217
 218extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
 219                                  struct chip_info **ci_ptr, u32 regs);
 220extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
 221extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
 222                                              struct chip_info *ci,
 223                                              u32 drivestrength);
 224extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
 225extern void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
 226                                           struct chip_info *ci);
 227extern bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
 228                                          struct chip_info *ci, char *nvram_dat,
 229                                          uint nvram_sz);
 230
 231#endif          /* _BRCMFMAC_SDIO_CHIP_H_ */
 232