1#ifndef HOSTAP_WLAN_H
2#define HOSTAP_WLAN_H
3
4#include <linux/interrupt.h>
5#include <linux/wireless.h>
6#include <linux/netdevice.h>
7#include <linux/mutex.h>
8#include <net/iw_handler.h>
9#include <net/ieee80211_radiotap.h>
10#include <net/lib80211.h>
11
12#include "hostap_config.h"
13#include "hostap_common.h"
14
15#define MAX_PARM_DEVICES 8
16#define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
17#define DEF_INTS -1, -1, -1, -1, -1, -1, -1
18#define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
19
20
21
22
23
24
25
26
27#define ETH_P_HOSTAP ETH_P_CONTROL
28
29
30
31struct linux_wlan_ng_val {
32 u32 did;
33 u16 status, len;
34 u32 data;
35} __packed;
36
37struct linux_wlan_ng_prism_hdr {
38 u32 msgcode, msglen;
39 char devname[16];
40 struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal,
41 noise, rate, istx, frmlen;
42} __packed;
43
44struct linux_wlan_ng_cap_hdr {
45 __be32 version;
46 __be32 length;
47 __be64 mactime;
48 __be64 hosttime;
49 __be32 phytype;
50 __be32 channel;
51 __be32 datarate;
52 __be32 antenna;
53 __be32 priority;
54 __be32 ssi_type;
55 __be32 ssi_signal;
56 __be32 ssi_noise;
57 __be32 preamble;
58 __be32 encoding;
59} __packed;
60
61struct hostap_radiotap_rx {
62 struct ieee80211_radiotap_header hdr;
63 __le64 tsft;
64 u8 rate;
65 u8 padding;
66 __le16 chan_freq;
67 __le16 chan_flags;
68 s8 dbm_antsignal;
69 s8 dbm_antnoise;
70} __packed;
71
72#define LWNG_CAP_DID_BASE (4 | (1 << 6))
73#define LWNG_CAPHDR_VERSION 0x80211001
74
75struct hfa384x_rx_frame {
76
77 __le16 status;
78 __le32 time;
79 u8 silence;
80 u8 signal;
81 u8 rate;
82 u8 rxflow;
83 __le32 reserved;
84
85
86 __le16 frame_control;
87 __le16 duration_id;
88 u8 addr1[6];
89 u8 addr2[6];
90 u8 addr3[6];
91 __le16 seq_ctrl;
92 u8 addr4[6];
93 __le16 data_len;
94
95
96 u8 dst_addr[6];
97 u8 src_addr[6];
98 __be16 len;
99
100
101} __packed;
102
103
104struct hfa384x_tx_frame {
105
106 __le16 status;
107 __le16 reserved1;
108 __le16 reserved2;
109 __le32 sw_support;
110 u8 retry_count;
111 u8 tx_rate;
112 __le16 tx_control;
113
114
115 __le16 frame_control;
116 __le16 duration_id;
117 u8 addr1[6];
118 u8 addr2[6];
119 u8 addr3[6];
120 __le16 seq_ctrl;
121 u8 addr4[6];
122 __le16 data_len;
123
124
125 u8 dst_addr[6];
126 u8 src_addr[6];
127 __be16 len;
128
129
130} __packed;
131
132
133struct hfa384x_rid_hdr
134{
135 __le16 len;
136 __le16 rid;
137} __packed;
138
139
140
141
142#define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
143
144#define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100
145
146struct hfa384x_scan_request {
147 __le16 channel_list;
148 __le16 txrate;
149} __packed;
150
151struct hfa384x_hostscan_request {
152 __le16 channel_list;
153 __le16 txrate;
154 __le16 target_ssid_len;
155 u8 target_ssid[32];
156} __packed;
157
158struct hfa384x_join_request {
159 u8 bssid[6];
160 __le16 channel;
161} __packed;
162
163struct hfa384x_info_frame {
164 __le16 len;
165 __le16 type;
166} __packed;
167
168struct hfa384x_comm_tallies {
169 __le16 tx_unicast_frames;
170 __le16 tx_multicast_frames;
171 __le16 tx_fragments;
172 __le16 tx_unicast_octets;
173 __le16 tx_multicast_octets;
174 __le16 tx_deferred_transmissions;
175 __le16 tx_single_retry_frames;
176 __le16 tx_multiple_retry_frames;
177 __le16 tx_retry_limit_exceeded;
178 __le16 tx_discards;
179 __le16 rx_unicast_frames;
180 __le16 rx_multicast_frames;
181 __le16 rx_fragments;
182 __le16 rx_unicast_octets;
183 __le16 rx_multicast_octets;
184 __le16 rx_fcs_errors;
185 __le16 rx_discards_no_buffer;
186 __le16 tx_discards_wrong_sa;
187 __le16 rx_discards_wep_undecryptable;
188 __le16 rx_message_in_msg_fragments;
189 __le16 rx_message_in_bad_msg_fragments;
190} __packed;
191
192struct hfa384x_comm_tallies32 {
193 __le32 tx_unicast_frames;
194 __le32 tx_multicast_frames;
195 __le32 tx_fragments;
196 __le32 tx_unicast_octets;
197 __le32 tx_multicast_octets;
198 __le32 tx_deferred_transmissions;
199 __le32 tx_single_retry_frames;
200 __le32 tx_multiple_retry_frames;
201 __le32 tx_retry_limit_exceeded;
202 __le32 tx_discards;
203 __le32 rx_unicast_frames;
204 __le32 rx_multicast_frames;
205 __le32 rx_fragments;
206 __le32 rx_unicast_octets;
207 __le32 rx_multicast_octets;
208 __le32 rx_fcs_errors;
209 __le32 rx_discards_no_buffer;
210 __le32 tx_discards_wrong_sa;
211 __le32 rx_discards_wep_undecryptable;
212 __le32 rx_message_in_msg_fragments;
213 __le32 rx_message_in_bad_msg_fragments;
214} __packed;
215
216struct hfa384x_scan_result_hdr {
217 __le16 reserved;
218 __le16 scan_reason;
219#define HFA384X_SCAN_IN_PROGRESS 0
220#define HFA384X_SCAN_HOST_INITIATED 1
221#define HFA384X_SCAN_FIRMWARE_INITIATED 2
222#define HFA384X_SCAN_INQUIRY_FROM_HOST 3
223} __packed;
224
225#define HFA384X_SCAN_MAX_RESULTS 32
226
227struct hfa384x_scan_result {
228 __le16 chid;
229 __le16 anl;
230 __le16 sl;
231 u8 bssid[6];
232 __le16 beacon_interval;
233 __le16 capability;
234 __le16 ssid_len;
235 u8 ssid[32];
236 u8 sup_rates[10];
237 __le16 rate;
238} __packed;
239
240struct hfa384x_hostscan_result {
241 __le16 chid;
242 __le16 anl;
243 __le16 sl;
244 u8 bssid[6];
245 __le16 beacon_interval;
246 __le16 capability;
247 __le16 ssid_len;
248 u8 ssid[32];
249 u8 sup_rates[10];
250 __le16 rate;
251 __le16 atim;
252} __packed;
253
254struct comm_tallies_sums {
255 unsigned int tx_unicast_frames;
256 unsigned int tx_multicast_frames;
257 unsigned int tx_fragments;
258 unsigned int tx_unicast_octets;
259 unsigned int tx_multicast_octets;
260 unsigned int tx_deferred_transmissions;
261 unsigned int tx_single_retry_frames;
262 unsigned int tx_multiple_retry_frames;
263 unsigned int tx_retry_limit_exceeded;
264 unsigned int tx_discards;
265 unsigned int rx_unicast_frames;
266 unsigned int rx_multicast_frames;
267 unsigned int rx_fragments;
268 unsigned int rx_unicast_octets;
269 unsigned int rx_multicast_octets;
270 unsigned int rx_fcs_errors;
271 unsigned int rx_discards_no_buffer;
272 unsigned int tx_discards_wrong_sa;
273 unsigned int rx_discards_wep_undecryptable;
274 unsigned int rx_message_in_msg_fragments;
275 unsigned int rx_message_in_bad_msg_fragments;
276};
277
278
279struct hfa384x_regs {
280 u16 cmd;
281 u16 evstat;
282 u16 offset0;
283 u16 offset1;
284 u16 swsupport0;
285};
286
287
288#if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
289
290#define HFA384X_CMD_OFF 0x00
291#define HFA384X_PARAM0_OFF 0x02
292#define HFA384X_PARAM1_OFF 0x04
293#define HFA384X_PARAM2_OFF 0x06
294#define HFA384X_STATUS_OFF 0x08
295#define HFA384X_RESP0_OFF 0x0A
296#define HFA384X_RESP1_OFF 0x0C
297#define HFA384X_RESP2_OFF 0x0E
298#define HFA384X_INFOFID_OFF 0x10
299#define HFA384X_CONTROL_OFF 0x14
300#define HFA384X_SELECT0_OFF 0x18
301#define HFA384X_SELECT1_OFF 0x1A
302#define HFA384X_OFFSET0_OFF 0x1C
303#define HFA384X_OFFSET1_OFF 0x1E
304#define HFA384X_RXFID_OFF 0x20
305#define HFA384X_ALLOCFID_OFF 0x22
306#define HFA384X_TXCOMPLFID_OFF 0x24
307#define HFA384X_SWSUPPORT0_OFF 0x28
308#define HFA384X_SWSUPPORT1_OFF 0x2A
309#define HFA384X_SWSUPPORT2_OFF 0x2C
310#define HFA384X_EVSTAT_OFF 0x30
311#define HFA384X_INTEN_OFF 0x32
312#define HFA384X_EVACK_OFF 0x34
313#define HFA384X_DATA0_OFF 0x36
314#define HFA384X_DATA1_OFF 0x38
315#define HFA384X_AUXPAGE_OFF 0x3A
316#define HFA384X_AUXOFFSET_OFF 0x3C
317#define HFA384X_AUXDATA_OFF 0x3E
318#endif
319
320#ifdef PRISM2_PCI
321
322#define HFA384X_CMD_OFF 0x00
323#define HFA384X_PARAM0_OFF 0x04
324#define HFA384X_PARAM1_OFF 0x08
325#define HFA384X_PARAM2_OFF 0x0C
326#define HFA384X_STATUS_OFF 0x10
327#define HFA384X_RESP0_OFF 0x14
328#define HFA384X_RESP1_OFF 0x18
329#define HFA384X_RESP2_OFF 0x1C
330#define HFA384X_INFOFID_OFF 0x20
331#define HFA384X_CONTROL_OFF 0x28
332#define HFA384X_SELECT0_OFF 0x30
333#define HFA384X_SELECT1_OFF 0x34
334#define HFA384X_OFFSET0_OFF 0x38
335#define HFA384X_OFFSET1_OFF 0x3C
336#define HFA384X_RXFID_OFF 0x40
337#define HFA384X_ALLOCFID_OFF 0x44
338#define HFA384X_TXCOMPLFID_OFF 0x48
339#define HFA384X_PCICOR_OFF 0x4C
340#define HFA384X_SWSUPPORT0_OFF 0x50
341#define HFA384X_SWSUPPORT1_OFF 0x54
342#define HFA384X_SWSUPPORT2_OFF 0x58
343#define HFA384X_PCIHCR_OFF 0x5C
344#define HFA384X_EVSTAT_OFF 0x60
345#define HFA384X_INTEN_OFF 0x64
346#define HFA384X_EVACK_OFF 0x68
347#define HFA384X_DATA0_OFF 0x6C
348#define HFA384X_DATA1_OFF 0x70
349#define HFA384X_AUXPAGE_OFF 0x74
350#define HFA384X_AUXOFFSET_OFF 0x78
351#define HFA384X_AUXDATA_OFF 0x7C
352#define HFA384X_PCI_M0_ADDRH_OFF 0x80
353#define HFA384X_PCI_M0_ADDRL_OFF 0x84
354#define HFA384X_PCI_M0_LEN_OFF 0x88
355#define HFA384X_PCI_M0_CTL_OFF 0x8C
356#define HFA384X_PCI_STATUS_OFF 0x98
357#define HFA384X_PCI_M1_ADDRH_OFF 0xA0
358#define HFA384X_PCI_M1_ADDRL_OFF 0xA4
359#define HFA384X_PCI_M1_LEN_OFF 0xA8
360#define HFA384X_PCI_M1_CTL_OFF 0xAC
361
362
363
364#define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
365#define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
366
367#endif
368
369
370
371#define HFA384X_CMDCODE_INIT 0x00
372#define HFA384X_CMDCODE_ENABLE 0x01
373#define HFA384X_CMDCODE_DISABLE 0x02
374#define HFA384X_CMDCODE_ALLOC 0x0A
375#define HFA384X_CMDCODE_TRANSMIT 0x0B
376#define HFA384X_CMDCODE_INQUIRE 0x11
377#define HFA384X_CMDCODE_ACCESS 0x21
378#define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
379#define HFA384X_CMDCODE_DOWNLOAD 0x22
380#define HFA384X_CMDCODE_READMIF 0x30
381#define HFA384X_CMDCODE_WRITEMIF 0x31
382#define HFA384X_CMDCODE_TEST 0x38
383
384#define HFA384X_CMDCODE_MASK 0x3F
385
386
387#define HFA384X_TEST_CHANGE_CHANNEL 0x08
388#define HFA384X_TEST_MONITOR 0x0B
389#define HFA384X_TEST_STOP 0x0F
390#define HFA384X_TEST_CFG_BITS 0x15
391#define HFA384X_TEST_CFG_BIT_ALC BIT(3)
392
393#define HFA384X_CMD_BUSY BIT(15)
394
395#define HFA384X_CMD_TX_RECLAIM BIT(8)
396
397#define HFA384X_OFFSET_ERR BIT(14)
398#define HFA384X_OFFSET_BUSY BIT(15)
399
400
401
402#define HFA384X_PROGMODE_DISABLE 0
403#define HFA384X_PROGMODE_ENABLE_VOLATILE 1
404#define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
405#define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
406
407#define HFA384X_AUX_MAGIC0 0xfe01
408#define HFA384X_AUX_MAGIC1 0xdc23
409#define HFA384X_AUX_MAGIC2 0xba45
410
411#define HFA384X_AUX_PORT_DISABLED 0
412#define HFA384X_AUX_PORT_DISABLE BIT(14)
413#define HFA384X_AUX_PORT_ENABLE BIT(15)
414#define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
415#define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
416
417#define PRISM2_PDA_SIZE 1024
418
419
420
421#define HFA384X_EV_TICK BIT(15)
422#define HFA384X_EV_WTERR BIT(14)
423#define HFA384X_EV_INFDROP BIT(13)
424#ifdef PRISM2_PCI
425#define HFA384X_EV_PCI_M1 BIT(9)
426#define HFA384X_EV_PCI_M0 BIT(8)
427#endif
428#define HFA384X_EV_INFO BIT(7)
429#define HFA384X_EV_DTIM BIT(5)
430#define HFA384X_EV_CMD BIT(4)
431#define HFA384X_EV_ALLOC BIT(3)
432#define HFA384X_EV_TXEXC BIT(2)
433#define HFA384X_EV_TX BIT(1)
434#define HFA384X_EV_RX BIT(0)
435
436
437
438#define HFA384X_INFO_HANDOVERADDR 0xF000
439#define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001
440#define HFA384X_INFO_COMMTALLIES 0xF100
441#define HFA384X_INFO_SCANRESULTS 0xF101
442#define HFA384X_INFO_CHANNELINFORESULTS 0xF102
443#define HFA384X_INFO_HOSTSCANRESULTS 0xF103
444#define HFA384X_INFO_LINKSTATUS 0xF200
445#define HFA384X_INFO_ASSOCSTATUS 0xF201
446#define HFA384X_INFO_AUTHREQ 0xF202
447#define HFA384X_INFO_PSUSERCNT 0xF203
448#define HFA384X_INFO_KEYIDCHANGED 0xF204
449
450enum { HFA384X_LINKSTATUS_CONNECTED = 1,
451 HFA384X_LINKSTATUS_DISCONNECTED = 2,
452 HFA384X_LINKSTATUS_AP_CHANGE = 3,
453 HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4,
454 HFA384X_LINKSTATUS_AP_IN_RANGE = 5,
455 HFA384X_LINKSTATUS_ASSOC_FAILED = 6 };
456
457enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2,
458 HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0,
459 HFA384X_PORTTYPE_HOSTAP = 6 };
460
461#define HFA384X_RATES_1MBPS BIT(0)
462#define HFA384X_RATES_2MBPS BIT(1)
463#define HFA384X_RATES_5MBPS BIT(2)
464#define HFA384X_RATES_11MBPS BIT(3)
465
466#define HFA384X_ROAMING_FIRMWARE 1
467#define HFA384X_ROAMING_HOST 2
468#define HFA384X_ROAMING_DISABLED 3
469
470#define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
471#define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
472#define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
473#define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
474
475#define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
476#define HFA384X_RX_STATUS_PCF BIT(12)
477#define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
478#define HFA384X_RX_STATUS_UNDECR BIT(1)
479#define HFA384X_RX_STATUS_FCSERR BIT(0)
480
481#define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
482(((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
483#define HFA384X_RX_STATUS_GET_MACPORT(s) \
484(((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
485
486enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1,
487 HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 };
488
489
490#define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
491#define HFA384X_TX_CTRL_802_11 BIT(3)
492#define HFA384X_TX_CTRL_802_3 0
493#define HFA384X_TX_CTRL_TX_EX BIT(2)
494#define HFA384X_TX_CTRL_TX_OK BIT(1)
495
496#define HFA384X_TX_STATUS_RETRYERR BIT(0)
497#define HFA384X_TX_STATUS_AGEDERR BIT(1)
498#define HFA384X_TX_STATUS_DISCON BIT(2)
499#define HFA384X_TX_STATUS_FORMERR BIT(3)
500
501
502#define HFA386X_CR_TX_CONFIGURE 0x12
503#define HFA386X_CR_RX_CONFIGURE 0x14
504#define HFA386X_CR_A_D_TEST_MODES2 0x1A
505#define HFA386X_CR_MANUAL_TX_POWER 0x3E
506#define HFA386X_CR_MEASURED_TX_POWER 0x74
507
508
509#ifdef __KERNEL__
510
511#define PRISM2_TXFID_COUNT 8
512#define PRISM2_DATA_MAXLEN 2304
513#define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
514#define PRISM2_TXFID_EMPTY 0xffff
515#define PRISM2_TXFID_RESERVED 0xfffe
516#define PRISM2_DUMMY_FID 0xffff
517#define MAX_SSID_LEN 32
518#define MAX_NAME_LEN 32
519
520#define PRISM2_DUMP_RX_HDR BIT(0)
521#define PRISM2_DUMP_TX_HDR BIT(1)
522#define PRISM2_DUMP_TXEXC_HDR BIT(2)
523
524struct hostap_tx_callback_info {
525 u16 idx;
526 void (*func)(struct sk_buff *, int ok, void *);
527 void *data;
528 struct hostap_tx_callback_info *next;
529};
530
531
532
533
534
535
536#define PRISM2_FRAG_CACHE_LEN 4
537
538struct prism2_frag_entry {
539 unsigned long first_frag_time;
540 unsigned int seq;
541 unsigned int last_frag;
542 struct sk_buff *skb;
543 u8 src_addr[ETH_ALEN];
544 u8 dst_addr[ETH_ALEN];
545};
546
547
548struct hostap_cmd_queue {
549 struct list_head list;
550 wait_queue_head_t compl;
551 volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type;
552 void (*callback)(struct net_device *dev, long context, u16 resp0,
553 u16 res);
554 long context;
555 u16 cmd, param0, param1;
556 u16 resp0, res;
557 volatile int issued, issuing;
558
559 atomic_t usecnt;
560 int del_req;
561};
562
563
564#define HOSTAP_HW_NO_DISABLE BIT(0)
565#define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
566
567typedef struct local_info local_info_t;
568
569struct prism2_helper_functions {
570
571
572 int (*card_present)(local_info_t *local);
573 void (*cor_sreset)(local_info_t *local);
574 void (*genesis_reset)(local_info_t *local, int hcr);
575
576
577
578
579
580
581
582
583 int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1,
584 u16 *resp0);
585 void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs);
586 int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len,
587 int exact_len);
588 int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len);
589 int (*hw_enable)(struct net_device *dev, int initial);
590 int (*hw_config)(struct net_device *dev, int initial);
591 void (*hw_reset)(struct net_device *dev);
592 void (*hw_shutdown)(struct net_device *dev, int no_disable);
593 int (*reset_port)(struct net_device *dev);
594 void (*schedule_reset)(local_info_t *local);
595 int (*download)(local_info_t *local,
596 struct prism2_download_param *param);
597 int (*tx)(struct sk_buff *skb, struct net_device *dev);
598 int (*set_tim)(struct net_device *dev, int aid, int set);
599 const struct file_operations *read_aux_fops;
600
601 int need_tx_headroom;
602
603 enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI } hw_type;
604};
605
606
607struct prism2_download_data {
608 u32 dl_cmd;
609 u32 start_addr;
610 u32 num_areas;
611 struct prism2_download_data_area {
612 u32 addr;
613 u32 len;
614 u8 *data;
615 } data[0];
616};
617
618
619#define HOSTAP_MAX_BSS_COUNT 64
620#define MAX_WPA_IE_LEN 64
621
622struct hostap_bss_info {
623 struct list_head list;
624 unsigned long last_update;
625 unsigned int count;
626 u8 bssid[ETH_ALEN];
627 u16 capab_info;
628 u8 ssid[32];
629 size_t ssid_len;
630 u8 wpa_ie[MAX_WPA_IE_LEN];
631 size_t wpa_ie_len;
632 u8 rsn_ie[MAX_WPA_IE_LEN];
633 size_t rsn_ie_len;
634 int chan;
635 int included;
636};
637
638
639
640
641
642
643struct local_info {
644 struct module *hw_module;
645 int card_idx;
646 int dev_enabled;
647 int master_dev_auto_open;
648 int num_dev_open;
649 struct net_device *dev;
650 struct net_device *ddev;
651 struct list_head hostap_interfaces;
652
653
654 rwlock_t iface_lock;
655
656
657 spinlock_t cmdlock, baplock, lock, irq_init_lock;
658 struct mutex rid_bap_mtx;
659 u16 infofid;
660
661
662 spinlock_t txfidlock;
663 int txfid_len;
664 u16 txfid[PRISM2_TXFID_COUNT];
665
666
667 u16 intransmitfid[PRISM2_TXFID_COUNT];
668 int next_txfid;
669
670 int next_alloc;
671
672
673
674#define HOSTAP_BITS_TRANSMIT 0
675#define HOSTAP_BITS_BAP_TASKLET 1
676#define HOSTAP_BITS_BAP_TASKLET2 2
677 unsigned long bits;
678
679 struct ap_data *ap;
680
681 char essid[MAX_SSID_LEN + 1];
682 char name[MAX_NAME_LEN + 1];
683 int name_set;
684 u16 channel_mask;
685 u16 scan_channel_mask;
686 struct comm_tallies_sums comm_tallies;
687 struct proc_dir_entry *proc;
688 int iw_mode;
689 int pseudo_adhoc;
690
691 char bssid[ETH_ALEN];
692 int channel;
693 int beacon_int;
694 int dtim_period;
695 int mtu;
696 int frame_dump;
697 int fw_tx_rate_control;
698 u16 tx_rate_control;
699 u16 basic_rates;
700 int hw_resetting;
701 int hw_ready;
702 int hw_reset_tries;
703 int hw_downloading;
704 int shutdown;
705 int pri_only;
706 int no_pri;
707 int sram_type;
708
709 enum {
710 PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
711 PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
712 } txpower_type;
713 int txpower;
714
715
716 struct list_head cmd_queue;
717
718
719
720#define HOSTAP_CMD_QUEUE_MAX_LEN 16
721 int cmd_queue_len;
722
723
724
725 struct work_struct reset_queue;
726
727
728 int is_promisc;
729 struct work_struct set_multicast_list_queue;
730
731 struct work_struct set_tim_queue;
732 struct list_head set_tim_list;
733 spinlock_t set_tim_lock;
734
735 int wds_max_connections;
736 int wds_connections;
737#define HOSTAP_WDS_BROADCAST_RA BIT(0)
738#define HOSTAP_WDS_AP_CLIENT BIT(1)
739#define HOSTAP_WDS_STANDARD_FRAME BIT(2)
740 u32 wds_type;
741 u16 tx_control;
742 int manual_retry_count;
743
744
745 struct iw_statistics wstats;
746 unsigned long scan_timestamp;
747 enum {
748 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
749 PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
750 } monitor_type;
751 int monitor_allow_fcserr;
752
753 int hostapd;
754
755 int hostapd_sta;
756
757 struct net_device *apdev;
758 struct net_device_stats apdevstats;
759
760 char assoc_ap_addr[ETH_ALEN];
761 struct net_device *stadev;
762 struct net_device_stats stadevstats;
763
764#define WEP_KEYS 4
765#define WEP_KEY_LEN 13
766 struct lib80211_crypt_info crypt_info;
767
768 int open_wep;
769 int host_encrypt;
770 int host_decrypt;
771 int privacy_invoked;
772
773 int fw_encrypt_ok;
774
775 int bcrx_sta_key;
776
777
778 struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
779 unsigned int frag_next_idx;
780
781 int ieee_802_1x;
782
783 int antsel_tx, antsel_rx;
784 int rts_threshold;
785 int fragm_threshold;
786 int auth_algs;
787
788 int enh_sec;
789 int tallies32;
790
791 struct prism2_helper_functions *func;
792
793 u8 *pda;
794 int fw_ap;
795#define PRISM2_FW_VER(major, minor, variant) \
796(((major) << 16) | ((minor) << 8) | variant)
797 u32 sta_fw_ver;
798
799
800
801 struct tasklet_struct bap_tasklet;
802
803 struct tasklet_struct info_tasklet;
804 struct sk_buff_head info_list;
805
806
807 struct hostap_tx_callback_info *tx_callback;
808
809
810 struct tasklet_struct rx_tasklet;
811 struct sk_buff_head rx_list;
812
813 struct tasklet_struct sta_tx_exc_tasklet;
814 struct sk_buff_head sta_tx_exc_list;
815
816 int host_roaming;
817 unsigned long last_join_time;
818 struct hfa384x_hostscan_result *last_scan_results;
819 int last_scan_results_count;
820 enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
821 struct work_struct info_queue;
822 unsigned long pending_info;
823#define PRISM2_INFO_PENDING_LINKSTATUS 0
824#define PRISM2_INFO_PENDING_SCANRESULTS 1
825 int prev_link_status;
826 int prev_linkstatus_connected;
827 u8 preferred_ap[6];
828
829#ifdef PRISM2_CALLBACK
830 void *callback_data;
831
832
833#endif
834
835 wait_queue_head_t hostscan_wq;
836
837
838 struct timer_list passive_scan_timer;
839 int passive_scan_interval;
840 int passive_scan_channel;
841 enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
842
843 struct timer_list tick_timer;
844 unsigned long last_tick_timer;
845 unsigned int sw_tick_stuck;
846
847
848
849 unsigned long last_comms_qual_update;
850 int comms_qual;
851 int avg_signal;
852 int avg_noise;
853 struct work_struct comms_qual_update;
854
855
856 int rssi_to_dBm;
857
858
859 struct list_head bss_list;
860 int num_bss_info;
861 int wpa;
862 int tkip_countermeasures;
863 int drop_unencrypted;
864
865
866 u8 *generic_elem;
867 size_t generic_elem_len;
868
869#ifdef PRISM2_DOWNLOAD_SUPPORT
870
871 struct prism2_download_data *dl_pri;
872 struct prism2_download_data *dl_sec;
873#endif
874
875#ifdef PRISM2_IO_DEBUG
876#define PRISM2_IO_DEBUG_SIZE 10000
877 u32 io_debug[PRISM2_IO_DEBUG_SIZE];
878 int io_debug_head;
879 int io_debug_enabled;
880#endif
881
882
883 void *hw_priv;
884};
885
886
887
888
889
890struct hostap_interface {
891 struct list_head list;
892 struct net_device *dev;
893 struct local_info *local;
894 struct net_device_stats stats;
895 struct iw_spy_data spy_data;
896 struct iw_public_data wireless_data;
897
898 enum {
899 HOSTAP_INTERFACE_MASTER,
900 HOSTAP_INTERFACE_MAIN,
901 HOSTAP_INTERFACE_AP,
902 HOSTAP_INTERFACE_STA,
903 HOSTAP_INTERFACE_WDS,
904 } type;
905
906 union {
907 struct hostap_interface_wds {
908 u8 remote_addr[ETH_ALEN];
909 } wds;
910 } u;
911};
912
913
914#define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2
915
916
917
918
919
920
921
922struct hostap_skb_tx_data {
923 unsigned int __padding_for_default_qdiscs;
924 u32 magic;
925 u8 rate;
926#define HOSTAP_TX_FLAGS_WDS BIT(0)
927#define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1)
928#define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2)
929 u8 flags;
930 u16 tx_cb_idx;
931 struct hostap_interface *iface;
932 unsigned long jiffies;
933 unsigned short ethertype;
934};
935
936
937#ifndef PRISM2_NO_DEBUG
938
939#define DEBUG_FID BIT(0)
940#define DEBUG_PS BIT(1)
941#define DEBUG_FLOW BIT(2)
942#define DEBUG_AP BIT(3)
943#define DEBUG_HW BIT(4)
944#define DEBUG_EXTRA BIT(5)
945#define DEBUG_EXTRA2 BIT(6)
946#define DEBUG_PS2 BIT(7)
947#define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
948#define PDEBUG(n, args...) \
949do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
950#define PDEBUG2(n, args...) \
951do { if ((n) & DEBUG_MASK) printk(args); } while (0)
952
953#else
954
955#define PDEBUG(n, args...)
956#define PDEBUG2(n, args...)
957
958#endif
959
960enum { BAP0 = 0, BAP1 = 1 };
961
962#define PRISM2_IO_DEBUG_CMD_INB 0
963#define PRISM2_IO_DEBUG_CMD_INW 1
964#define PRISM2_IO_DEBUG_CMD_INSW 2
965#define PRISM2_IO_DEBUG_CMD_OUTB 3
966#define PRISM2_IO_DEBUG_CMD_OUTW 4
967#define PRISM2_IO_DEBUG_CMD_OUTSW 5
968#define PRISM2_IO_DEBUG_CMD_ERROR 6
969#define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
970
971#ifdef PRISM2_IO_DEBUG
972
973#define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
974(((cmd) << 24) | ((reg) << 16) | value)
975
976static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
977 int reg, int value)
978{
979 struct hostap_interface *iface = netdev_priv(dev);
980 local_info_t *local = iface->local;
981
982 if (!local->io_debug_enabled)
983 return;
984
985 local->io_debug[local->io_debug_head] = jiffies & 0xffffffff;
986 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
987 local->io_debug_head = 0;
988 local->io_debug[local->io_debug_head] =
989 PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
990 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
991 local->io_debug_head = 0;
992}
993
994
995static inline void prism2_io_debug_error(struct net_device *dev, int err)
996{
997 struct hostap_interface *iface = netdev_priv(dev);
998 local_info_t *local = iface->local;
999 unsigned long flags;
1000
1001 if (!local->io_debug_enabled)
1002 return;
1003
1004 spin_lock_irqsave(&local->lock, flags);
1005 prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
1006 if (local->io_debug_enabled == 1) {
1007 local->io_debug_enabled = 0;
1008 printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name);
1009 }
1010 spin_unlock_irqrestore(&local->lock, flags);
1011}
1012
1013#else
1014
1015static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
1016 int reg, int value)
1017{
1018}
1019
1020static inline void prism2_io_debug_error(struct net_device *dev, int err)
1021{
1022}
1023
1024#endif
1025
1026
1027#ifdef PRISM2_CALLBACK
1028enum {
1029
1030 PRISM2_CALLBACK_ENABLE,
1031
1032
1033 PRISM2_CALLBACK_DISABLE,
1034
1035
1036 PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
1037 PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
1038};
1039void prism2_callback(local_info_t *local, int event);
1040#else
1041#define prism2_callback(d, e) do { } while (0)
1042#endif
1043
1044#endif
1045
1046#endif
1047