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30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/ieee80211_radiotap.h>
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl3945"
53
54#include "commands.h"
55#include "common.h"
56#include "3945.h"
57#include "iwl-spectrum.h"
58
59
60
61
62
63#define DRV_DESCRIPTION \
64"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
65
66#ifdef CONFIG_IWLEGACY_DEBUG
67#define VD "d"
68#else
69#define VD
70#endif
71
72
73
74
75
76
77#define DRV_VERSION IWLWIFI_VERSION VD "s"
78#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
79#define DRV_AUTHOR "<ilw@linux.intel.com>"
80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
84MODULE_LICENSE("GPL");
85
86
87struct il_mod_params il3945_mod_params = {
88 .sw_crypto = 1,
89 .restart_fw = 1,
90 .disable_hw_scan = 1,
91
92};
93
94
95
96
97
98
99
100
101
102
103
104
105__le32
106il3945_get_antenna_flags(const struct il_priv *il)
107{
108 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
109
110 switch (il3945_mod_params.antenna) {
111 case IL_ANTENNA_DIVERSITY:
112 return 0;
113
114 case IL_ANTENNA_MAIN:
115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
119 case IL_ANTENNA_AUX:
120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125
126 IL_ERR("Bad antenna selector value (0x%x)\n",
127 il3945_mod_params.antenna);
128
129 return 0;
130}
131
132static int
133il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
134 struct ieee80211_key_conf *keyconf, u8 sta_id)
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
143 if (sta_id == il->hw_params.bcast_id)
144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
149
150 spin_lock_irqsave(&il->sta_lock, flags);
151 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
152 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
153 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
154
155 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
156
157 if ((il->stations[sta_id].sta.key.
158 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
159 il->stations[sta_id].sta.key.key_offset =
160 il_get_free_ucode_key_idx(il);
161
162
163
164 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
165 "no space for a new key");
166
167 il->stations[sta_id].sta.key.key_flags = key_flags;
168 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
169 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
170
171 D_INFO("hwcrypto: modify ucode station key info\n");
172
173 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
174
175 spin_unlock_irqrestore(&il->sta_lock, flags);
176
177 return ret;
178}
179
180static int
181il3945_set_tkip_dynamic_key_info(struct il_priv *il,
182 struct ieee80211_key_conf *keyconf, u8 sta_id)
183{
184 return -EOPNOTSUPP;
185}
186
187static int
188il3945_set_wep_dynamic_key_info(struct il_priv *il,
189 struct ieee80211_key_conf *keyconf, u8 sta_id)
190{
191 return -EOPNOTSUPP;
192}
193
194static int
195il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
196{
197 unsigned long flags;
198 struct il_addsta_cmd sta_cmd;
199
200 spin_lock_irqsave(&il->sta_lock, flags);
201 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
202 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
203 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
204 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
205 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
206 memcpy(&sta_cmd, &il->stations[sta_id].sta,
207 sizeof(struct il_addsta_cmd));
208 spin_unlock_irqrestore(&il->sta_lock, flags);
209
210 D_INFO("hwcrypto: clear ucode station key info\n");
211 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
212}
213
214static int
215il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
216 u8 sta_id)
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->cipher) {
223 case WLAN_CIPHER_SUITE_CCMP:
224 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
225 break;
226 case WLAN_CIPHER_SUITE_TKIP:
227 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
228 break;
229 case WLAN_CIPHER_SUITE_WEP40:
230 case WLAN_CIPHER_SUITE_WEP104:
231 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
232 break;
233 default:
234 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
235 ret = -EINVAL;
236 }
237
238 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
239 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
240
241 return ret;
242}
243
244static int
245il3945_remove_static_key(struct il_priv *il)
246{
247 int ret = -EOPNOTSUPP;
248
249 return ret;
250}
251
252static int
253il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
254{
255 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
256 key->cipher == WLAN_CIPHER_SUITE_WEP104)
257 return -EOPNOTSUPP;
258
259 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
260 return -EINVAL;
261}
262
263static void
264il3945_clear_free_frames(struct il_priv *il)
265{
266 struct list_head *element;
267
268 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
269
270 while (!list_empty(&il->free_frames)) {
271 element = il->free_frames.next;
272 list_del(element);
273 kfree(list_entry(element, struct il3945_frame, list));
274 il->frames_count--;
275 }
276
277 if (il->frames_count) {
278 IL_WARN("%d frames still in use. Did we lose one?\n",
279 il->frames_count);
280 il->frames_count = 0;
281 }
282}
283
284static struct il3945_frame *
285il3945_get_free_frame(struct il_priv *il)
286{
287 struct il3945_frame *frame;
288 struct list_head *element;
289 if (list_empty(&il->free_frames)) {
290 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
291 if (!frame) {
292 IL_ERR("Could not allocate frame!\n");
293 return NULL;
294 }
295
296 il->frames_count++;
297 return frame;
298 }
299
300 element = il->free_frames.next;
301 list_del(element);
302 return list_entry(element, struct il3945_frame, list);
303}
304
305static void
306il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
307{
308 memset(frame, 0, sizeof(*frame));
309 list_add(&frame->list, &il->free_frames);
310}
311
312unsigned int
313il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
314 int left)
315{
316
317 if (!il_is_associated(il) || !il->beacon_skb)
318 return 0;
319
320 if (il->beacon_skb->len > left)
321 return 0;
322
323 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
324
325 return il->beacon_skb->len;
326}
327
328static int
329il3945_send_beacon_cmd(struct il_priv *il)
330{
331 struct il3945_frame *frame;
332 unsigned int frame_size;
333 int rc;
334 u8 rate;
335
336 frame = il3945_get_free_frame(il);
337
338 if (!frame) {
339 IL_ERR("Could not obtain free frame buffer for beacon "
340 "command.\n");
341 return -ENOMEM;
342 }
343
344 rate = il_get_lowest_plcp(il);
345
346 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
347
348 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
349
350 il3945_free_frame(il, frame);
351
352 return rc;
353}
354
355static void
356il3945_unset_hw_params(struct il_priv *il)
357{
358 if (il->_3945.shared_virt)
359 dma_free_coherent(&il->pci_dev->dev,
360 sizeof(struct il3945_shared),
361 il->_3945.shared_virt, il->_3945.shared_phys);
362}
363
364static void
365il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
366 struct il_device_cmd *cmd,
367 struct sk_buff *skb_frag, int sta_id)
368{
369 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
370 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
371
372 tx_cmd->sec_ctl = 0;
373
374 switch (keyinfo->cipher) {
375 case WLAN_CIPHER_SUITE_CCMP:
376 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
377 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
378 D_TX("tx_cmd with AES hwcrypto\n");
379 break;
380
381 case WLAN_CIPHER_SUITE_TKIP:
382 break;
383
384 case WLAN_CIPHER_SUITE_WEP104:
385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
386
387 case WLAN_CIPHER_SUITE_WEP40:
388 tx_cmd->sec_ctl |=
389 TX_CMD_SEC_WEP | (info->control.hw_key->
390 hw_key_idx & TX_CMD_SEC_MSK) <<
391 TX_CMD_SEC_SHIFT;
392
393 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
394
395 D_TX("Configuring packet for WEP encryption " "with key %d\n",
396 info->control.hw_key->hw_key_idx);
397 break;
398
399 default:
400 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
401 break;
402 }
403}
404
405
406
407
408static void
409il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
410 struct ieee80211_tx_info *info,
411 struct ieee80211_hdr *hdr, u8 std_id)
412{
413 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
414 __le32 tx_flags = tx_cmd->tx_flags;
415 __le16 fc = hdr->frame_control;
416
417 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
418 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
419 tx_flags |= TX_CMD_FLG_ACK_MSK;
420 if (ieee80211_is_mgmt(fc))
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 if (ieee80211_is_probe_resp(fc) &&
423 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
424 tx_flags |= TX_CMD_FLG_TSF_MSK;
425 } else {
426 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
427 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
428 }
429
430 tx_cmd->sta_id = std_id;
431 if (ieee80211_has_morefrags(fc))
432 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
433
434 if (ieee80211_is_data_qos(fc)) {
435 u8 *qc = ieee80211_get_qos_ctl(hdr);
436 tx_cmd->tid_tspec = qc[0] & 0xf;
437 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
438 } else {
439 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
440 }
441
442 il_tx_cmd_protection(il, info, fc, &tx_flags);
443
444 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
445 if (ieee80211_is_mgmt(fc)) {
446 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
448 else
449 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
450 } else {
451 tx_cmd->timeout.pm_frame_timeout = 0;
452 }
453
454 tx_cmd->driver_txop = 0;
455 tx_cmd->tx_flags = tx_flags;
456 tx_cmd->next_frame_len = 0;
457}
458
459
460
461
462static int
463il3945_tx_skb(struct il_priv *il,
464 struct ieee80211_sta *sta,
465 struct sk_buff *skb)
466{
467 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
469 struct il3945_tx_cmd *tx_cmd;
470 struct il_tx_queue *txq = NULL;
471 struct il_queue *q = NULL;
472 struct il_device_cmd *out_cmd;
473 struct il_cmd_meta *out_meta;
474 dma_addr_t phys_addr;
475 dma_addr_t txcmd_phys;
476 int txq_id = skb_get_queue_mapping(skb);
477 u16 len, idx, hdr_len;
478 u16 firstlen, secondlen;
479 u8 id;
480 u8 unicast;
481 u8 sta_id;
482 u8 tid = 0;
483 __le16 fc;
484 u8 wait_write_ptr = 0;
485 unsigned long flags;
486
487 spin_lock_irqsave(&il->lock, flags);
488 if (il_is_rfkill(il)) {
489 D_DROP("Dropping - RF KILL\n");
490 goto drop_unlock;
491 }
492
493 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
494 IL_INVALID_RATE) {
495 IL_ERR("ERROR: No TX rate available.\n");
496 goto drop_unlock;
497 }
498
499 unicast = !is_multicast_ether_addr(hdr->addr1);
500 id = 0;
501
502 fc = hdr->frame_control;
503
504#ifdef CONFIG_IWLEGACY_DEBUG
505 if (ieee80211_is_auth(fc))
506 D_TX("Sending AUTH frame\n");
507 else if (ieee80211_is_assoc_req(fc))
508 D_TX("Sending ASSOC frame\n");
509 else if (ieee80211_is_reassoc_req(fc))
510 D_TX("Sending REASSOC frame\n");
511#endif
512
513 spin_unlock_irqrestore(&il->lock, flags);
514
515 hdr_len = ieee80211_hdrlen(fc);
516
517
518 sta_id = il_sta_id_or_broadcast(il, sta);
519 if (sta_id == IL_INVALID_STATION) {
520 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
521 goto drop;
522 }
523
524 D_RATE("station Id %d\n", sta_id);
525
526 if (ieee80211_is_data_qos(fc)) {
527 u8 *qc = ieee80211_get_qos_ctl(hdr);
528 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
529 if (unlikely(tid >= MAX_TID_COUNT))
530 goto drop;
531 }
532
533
534 txq = &il->txq[txq_id];
535 q = &txq->q;
536
537 if ((il_queue_space(q) < q->high_mark))
538 goto drop;
539
540 spin_lock_irqsave(&il->lock, flags);
541
542 idx = il_get_cmd_idx(q, q->write_ptr, 0);
543
544 txq->skbs[q->write_ptr] = skb;
545
546
547 out_cmd = txq->cmd[idx];
548 out_meta = &txq->meta[idx];
549 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
550 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
551 memset(tx_cmd, 0, sizeof(*tx_cmd));
552
553
554
555
556
557
558
559 out_cmd->hdr.cmd = C_TX;
560 out_cmd->hdr.sequence =
561 cpu_to_le16((u16)
562 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
563
564
565 memcpy(tx_cmd->hdr, hdr, hdr_len);
566
567 if (info->control.hw_key)
568 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
569
570
571 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
572
573 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
574
575
576 tx_cmd->len = cpu_to_le16((u16) skb->len);
577
578 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
579 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
580
581
582
583
584
585
586
587
588
589
590 len =
591 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
592 hdr_len;
593 firstlen = (len + 3) & ~3;
594
595
596
597 txcmd_phys =
598 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
599 PCI_DMA_TODEVICE);
600 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
601 goto drop_unlock;
602
603
604
605 secondlen = skb->len - hdr_len;
606 if (secondlen > 0) {
607 phys_addr =
608 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
609 PCI_DMA_TODEVICE);
610 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
611 goto drop_unlock;
612 }
613
614
615
616 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
617 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
618 dma_unmap_len_set(out_meta, len, firstlen);
619 if (secondlen > 0)
620 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
621 U32_PAD(secondlen));
622
623 if (!ieee80211_has_morefrags(hdr->frame_control)) {
624 txq->need_update = 1;
625 } else {
626 wait_write_ptr = 1;
627 txq->need_update = 0;
628 }
629
630 il_update_stats(il, true, fc, skb->len);
631
632 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
633 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
634 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
635 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
636 ieee80211_hdrlen(fc));
637
638
639 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
640 il_txq_update_write_ptr(il, txq);
641 spin_unlock_irqrestore(&il->lock, flags);
642
643 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
644 if (wait_write_ptr) {
645 spin_lock_irqsave(&il->lock, flags);
646 txq->need_update = 1;
647 il_txq_update_write_ptr(il, txq);
648 spin_unlock_irqrestore(&il->lock, flags);
649 }
650
651 il_stop_queue(il, txq);
652 }
653
654 return 0;
655
656drop_unlock:
657 spin_unlock_irqrestore(&il->lock, flags);
658drop:
659 return -1;
660}
661
662static int
663il3945_get_measurement(struct il_priv *il,
664 struct ieee80211_measurement_params *params, u8 type)
665{
666 struct il_spectrum_cmd spectrum;
667 struct il_rx_pkt *pkt;
668 struct il_host_cmd cmd = {
669 .id = C_SPECTRUM_MEASUREMENT,
670 .data = (void *)&spectrum,
671 .flags = CMD_WANT_SKB,
672 };
673 u32 add_time = le64_to_cpu(params->start_time);
674 int rc;
675 int spectrum_resp_status;
676 int duration = le16_to_cpu(params->duration);
677
678 if (il_is_associated(il))
679 add_time =
680 il_usecs_to_beacons(il,
681 le64_to_cpu(params->start_time) -
682 il->_3945.last_tsf,
683 le16_to_cpu(il->timing.beacon_interval));
684
685 memset(&spectrum, 0, sizeof(spectrum));
686
687 spectrum.channel_count = cpu_to_le16(1);
688 spectrum.flags =
689 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
690 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
691 cmd.len = sizeof(spectrum);
692 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
693
694 if (il_is_associated(il))
695 spectrum.start_time =
696 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
697 le16_to_cpu(il->timing.beacon_interval));
698 else
699 spectrum.start_time = 0;
700
701 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
702 spectrum.channels[0].channel = params->channel;
703 spectrum.channels[0].type = type;
704 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
705 spectrum.flags |=
706 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
707 RXON_FLG_TGG_PROTECT_MSK;
708
709 rc = il_send_cmd_sync(il, &cmd);
710 if (rc)
711 return rc;
712
713 pkt = (struct il_rx_pkt *)cmd.reply_page;
714 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
715 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
716 rc = -EIO;
717 }
718
719 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
720 switch (spectrum_resp_status) {
721 case 0:
722 if (pkt->u.spectrum.id != 0xff) {
723 D_INFO("Replaced existing measurement: %d\n",
724 pkt->u.spectrum.id);
725 il->measurement_status &= ~MEASUREMENT_READY;
726 }
727 il->measurement_status |= MEASUREMENT_ACTIVE;
728 rc = 0;
729 break;
730
731 case 1:
732 rc = -EAGAIN;
733 break;
734 }
735
736 il_free_pages(il, cmd.reply_page);
737
738 return rc;
739}
740
741static void
742il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
743{
744 struct il_rx_pkt *pkt = rxb_addr(rxb);
745 struct il_alive_resp *palive;
746 struct delayed_work *pwork;
747
748 palive = &pkt->u.alive_frame;
749
750 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
751 palive->is_valid, palive->ver_type, palive->ver_subtype);
752
753 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
754 D_INFO("Initialization Alive received.\n");
755 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
756 sizeof(struct il_alive_resp));
757 pwork = &il->init_alive_start;
758 } else {
759 D_INFO("Runtime Alive received.\n");
760 memcpy(&il->card_alive, &pkt->u.alive_frame,
761 sizeof(struct il_alive_resp));
762 pwork = &il->alive_start;
763 il3945_disable_events(il);
764 }
765
766
767
768 if (palive->is_valid == UCODE_VALID_OK)
769 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
770 else
771 IL_WARN("uCode did not respond OK.\n");
772}
773
774static void
775il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
776{
777#ifdef CONFIG_IWLEGACY_DEBUG
778 struct il_rx_pkt *pkt = rxb_addr(rxb);
779#endif
780
781 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
782}
783
784static void
785il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
786{
787 struct il_rx_pkt *pkt = rxb_addr(rxb);
788 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
789#ifdef CONFIG_IWLEGACY_DEBUG
790 u8 rate = beacon->beacon_notify_hdr.rate;
791
792 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
793 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
794 beacon->beacon_notify_hdr.failure_frame,
795 le32_to_cpu(beacon->ibss_mgr_status),
796 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
797#endif
798
799 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
800
801}
802
803
804
805static void
806il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
807{
808 struct il_rx_pkt *pkt = rxb_addr(rxb);
809 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
810 unsigned long status = il->status;
811
812 IL_WARN("Card state received: HW:%s SW:%s\n",
813 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
814 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
815
816 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
817
818 if (flags & HW_CARD_DISABLED)
819 set_bit(S_RFKILL, &il->status);
820 else
821 clear_bit(S_RFKILL, &il->status);
822
823 il_scan_cancel(il);
824
825 if ((test_bit(S_RFKILL, &status) !=
826 test_bit(S_RFKILL, &il->status)))
827 wiphy_rfkill_set_hw_state(il->hw->wiphy,
828 test_bit(S_RFKILL, &il->status));
829 else
830 wake_up(&il->wait_command_queue);
831}
832
833
834
835
836
837
838
839
840
841
842static void
843il3945_setup_handlers(struct il_priv *il)
844{
845 il->handlers[N_ALIVE] = il3945_hdl_alive;
846 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
847 il->handlers[N_ERROR] = il_hdl_error;
848 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
849 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
850 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
851 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
852 il->handlers[N_BEACON] = il3945_hdl_beacon;
853
854
855
856
857
858
859 il->handlers[C_STATS] = il3945_hdl_c_stats;
860 il->handlers[N_STATS] = il3945_hdl_stats;
861
862 il_setup_rx_scan_handlers(il);
863 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
864
865
866 il3945_hw_handler_setup(il);
867}
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936static inline __le32
937il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
938{
939 return cpu_to_le32((u32) dma_addr);
940}
941
942
943
944
945
946
947
948
949
950
951
952
953static void
954il3945_rx_queue_restock(struct il_priv *il)
955{
956 struct il_rx_queue *rxq = &il->rxq;
957 struct list_head *element;
958 struct il_rx_buf *rxb;
959 unsigned long flags;
960 int write;
961
962 spin_lock_irqsave(&rxq->lock, flags);
963 write = rxq->write & ~0x7;
964 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
965
966 element = rxq->rx_free.next;
967 rxb = list_entry(element, struct il_rx_buf, list);
968 list_del(element);
969
970
971 rxq->bd[rxq->write] =
972 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
973 rxq->queue[rxq->write] = rxb;
974 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
975 rxq->free_count--;
976 }
977 spin_unlock_irqrestore(&rxq->lock, flags);
978
979
980 if (rxq->free_count <= RX_LOW_WATERMARK)
981 queue_work(il->workqueue, &il->rx_replenish);
982
983
984
985 if (rxq->write_actual != (rxq->write & ~0x7) ||
986 abs(rxq->write - rxq->read) > 7) {
987 spin_lock_irqsave(&rxq->lock, flags);
988 rxq->need_update = 1;
989 spin_unlock_irqrestore(&rxq->lock, flags);
990 il_rx_queue_update_write_ptr(il, rxq);
991 }
992}
993
994
995
996
997
998
999
1000
1001
1002static void
1003il3945_rx_allocate(struct il_priv *il, gfp_t priority)
1004{
1005 struct il_rx_queue *rxq = &il->rxq;
1006 struct list_head *element;
1007 struct il_rx_buf *rxb;
1008 struct page *page;
1009 dma_addr_t page_dma;
1010 unsigned long flags;
1011 gfp_t gfp_mask = priority;
1012
1013 while (1) {
1014 spin_lock_irqsave(&rxq->lock, flags);
1015 if (list_empty(&rxq->rx_used)) {
1016 spin_unlock_irqrestore(&rxq->lock, flags);
1017 return;
1018 }
1019 spin_unlock_irqrestore(&rxq->lock, flags);
1020
1021 if (rxq->free_count > RX_LOW_WATERMARK)
1022 gfp_mask |= __GFP_NOWARN;
1023
1024 if (il->hw_params.rx_page_order > 0)
1025 gfp_mask |= __GFP_COMP;
1026
1027
1028 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1029 if (!page) {
1030 if (net_ratelimit())
1031 D_INFO("Failed to allocate SKB buffer.\n");
1032 if (rxq->free_count <= RX_LOW_WATERMARK &&
1033 net_ratelimit())
1034 IL_ERR("Failed to allocate SKB buffer with %0x."
1035 "Only %u free buffers remaining.\n",
1036 priority, rxq->free_count);
1037
1038
1039
1040 break;
1041 }
1042
1043
1044 page_dma =
1045 pci_map_page(il->pci_dev, page, 0,
1046 PAGE_SIZE << il->hw_params.rx_page_order,
1047 PCI_DMA_FROMDEVICE);
1048
1049 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1050 __free_pages(page, il->hw_params.rx_page_order);
1051 break;
1052 }
1053
1054 spin_lock_irqsave(&rxq->lock, flags);
1055
1056 if (list_empty(&rxq->rx_used)) {
1057 spin_unlock_irqrestore(&rxq->lock, flags);
1058 pci_unmap_page(il->pci_dev, page_dma,
1059 PAGE_SIZE << il->hw_params.rx_page_order,
1060 PCI_DMA_FROMDEVICE);
1061 __free_pages(page, il->hw_params.rx_page_order);
1062 return;
1063 }
1064
1065 element = rxq->rx_used.next;
1066 rxb = list_entry(element, struct il_rx_buf, list);
1067 list_del(element);
1068
1069 rxb->page = page;
1070 rxb->page_dma = page_dma;
1071 list_add_tail(&rxb->list, &rxq->rx_free);
1072 rxq->free_count++;
1073 il->alloc_rxb_page++;
1074
1075 spin_unlock_irqrestore(&rxq->lock, flags);
1076 }
1077}
1078
1079void
1080il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1081{
1082 unsigned long flags;
1083 int i;
1084 spin_lock_irqsave(&rxq->lock, flags);
1085 INIT_LIST_HEAD(&rxq->rx_free);
1086 INIT_LIST_HEAD(&rxq->rx_used);
1087
1088 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1089
1090
1091 if (rxq->pool[i].page != NULL) {
1092 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1093 PAGE_SIZE << il->hw_params.rx_page_order,
1094 PCI_DMA_FROMDEVICE);
1095 __il_free_pages(il, rxq->pool[i].page);
1096 rxq->pool[i].page = NULL;
1097 }
1098 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1099 }
1100
1101
1102
1103 rxq->read = rxq->write = 0;
1104 rxq->write_actual = 0;
1105 rxq->free_count = 0;
1106 spin_unlock_irqrestore(&rxq->lock, flags);
1107}
1108
1109void
1110il3945_rx_replenish(void *data)
1111{
1112 struct il_priv *il = data;
1113 unsigned long flags;
1114
1115 il3945_rx_allocate(il, GFP_KERNEL);
1116
1117 spin_lock_irqsave(&il->lock, flags);
1118 il3945_rx_queue_restock(il);
1119 spin_unlock_irqrestore(&il->lock, flags);
1120}
1121
1122static void
1123il3945_rx_replenish_now(struct il_priv *il)
1124{
1125 il3945_rx_allocate(il, GFP_ATOMIC);
1126
1127 il3945_rx_queue_restock(il);
1128}
1129
1130
1131
1132
1133
1134
1135static void
1136il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1137{
1138 int i;
1139 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1140 if (rxq->pool[i].page != NULL) {
1141 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1142 PAGE_SIZE << il->hw_params.rx_page_order,
1143 PCI_DMA_FROMDEVICE);
1144 __il_free_pages(il, rxq->pool[i].page);
1145 rxq->pool[i].page = NULL;
1146 }
1147 }
1148
1149 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1150 rxq->bd_dma);
1151 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1152 rxq->rb_stts, rxq->rb_stts_dma);
1153 rxq->bd = NULL;
1154 rxq->rb_stts = NULL;
1155}
1156
1157
1158static u8 ratio2dB[100] = {
1159
1160 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
1161 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
1162 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
1163 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
1164 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
1165 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
1166 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
1167 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
1168 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
1169 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
1170};
1171
1172
1173
1174
1175int
1176il3945_calc_db_from_ratio(int sig_ratio)
1177{
1178
1179 if (sig_ratio >= 1000)
1180 return 60;
1181
1182
1183
1184 if (sig_ratio >= 100)
1185 return 20 + (int)ratio2dB[sig_ratio / 10];
1186
1187
1188 if (sig_ratio < 1)
1189 return 0;
1190
1191
1192 return (int)ratio2dB[sig_ratio];
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202static void
1203il3945_rx_handle(struct il_priv *il)
1204{
1205 struct il_rx_buf *rxb;
1206 struct il_rx_pkt *pkt;
1207 struct il_rx_queue *rxq = &il->rxq;
1208 u32 r, i;
1209 int reclaim;
1210 unsigned long flags;
1211 u8 fill_rx = 0;
1212 u32 count = 8;
1213 int total_empty = 0;
1214
1215
1216
1217 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1218 i = rxq->read;
1219
1220
1221 total_empty = r - rxq->write_actual;
1222 if (total_empty < 0)
1223 total_empty += RX_QUEUE_SIZE;
1224
1225 if (total_empty > (RX_QUEUE_SIZE / 2))
1226 fill_rx = 1;
1227
1228 if (i == r)
1229 D_RX("r = %d, i = %d\n", r, i);
1230
1231 while (i != r) {
1232 int len;
1233
1234 rxb = rxq->queue[i];
1235
1236
1237
1238
1239 BUG_ON(rxb == NULL);
1240
1241 rxq->queue[i] = NULL;
1242
1243 pci_unmap_page(il->pci_dev, rxb->page_dma,
1244 PAGE_SIZE << il->hw_params.rx_page_order,
1245 PCI_DMA_FROMDEVICE);
1246 pkt = rxb_addr(rxb);
1247
1248 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
1249 len += sizeof(u32);
1250
1251
1252
1253
1254
1255
1256
1257 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1258 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX;
1259
1260
1261
1262
1263 if (il->handlers[pkt->hdr.cmd]) {
1264 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
1265 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1266 il->isr_stats.handlers[pkt->hdr.cmd]++;
1267 il->handlers[pkt->hdr.cmd] (il, rxb);
1268 } else {
1269
1270 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1271 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1272 }
1273
1274
1275
1276
1277
1278
1279
1280
1281 if (reclaim) {
1282
1283
1284
1285 if (rxb->page)
1286 il_tx_cmd_complete(il, rxb);
1287 else
1288 IL_WARN("Claim null rxb?\n");
1289 }
1290
1291
1292
1293
1294 spin_lock_irqsave(&rxq->lock, flags);
1295 if (rxb->page != NULL) {
1296 rxb->page_dma =
1297 pci_map_page(il->pci_dev, rxb->page, 0,
1298 PAGE_SIZE << il->hw_params.
1299 rx_page_order, PCI_DMA_FROMDEVICE);
1300 if (unlikely(pci_dma_mapping_error(il->pci_dev,
1301 rxb->page_dma))) {
1302 __il_free_pages(il, rxb->page);
1303 rxb->page = NULL;
1304 list_add_tail(&rxb->list, &rxq->rx_used);
1305 } else {
1306 list_add_tail(&rxb->list, &rxq->rx_free);
1307 rxq->free_count++;
1308 }
1309 } else
1310 list_add_tail(&rxb->list, &rxq->rx_used);
1311
1312 spin_unlock_irqrestore(&rxq->lock, flags);
1313
1314 i = (i + 1) & RX_QUEUE_MASK;
1315
1316
1317 if (fill_rx) {
1318 count++;
1319 if (count >= 8) {
1320 rxq->read = i;
1321 il3945_rx_replenish_now(il);
1322 count = 0;
1323 }
1324 }
1325 }
1326
1327
1328 rxq->read = i;
1329 if (fill_rx)
1330 il3945_rx_replenish_now(il);
1331 else
1332 il3945_rx_queue_restock(il);
1333}
1334
1335
1336static inline void
1337il3945_synchronize_irq(struct il_priv *il)
1338{
1339
1340 synchronize_irq(il->pci_dev->irq);
1341 tasklet_kill(&il->irq_tasklet);
1342}
1343
1344static const char *
1345il3945_desc_lookup(int i)
1346{
1347 switch (i) {
1348 case 1:
1349 return "FAIL";
1350 case 2:
1351 return "BAD_PARAM";
1352 case 3:
1353 return "BAD_CHECKSUM";
1354 case 4:
1355 return "NMI_INTERRUPT";
1356 case 5:
1357 return "SYSASSERT";
1358 case 6:
1359 return "FATAL_ERROR";
1360 }
1361
1362 return "UNKNOWN";
1363}
1364
1365#define ERROR_START_OFFSET (1 * sizeof(u32))
1366#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1367
1368void
1369il3945_dump_nic_error_log(struct il_priv *il)
1370{
1371 u32 i;
1372 u32 desc, time, count, base, data1;
1373 u32 blink1, blink2, ilink1, ilink2;
1374
1375 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1376
1377 if (!il3945_hw_valid_rtc_data_addr(base)) {
1378 IL_ERR("Not valid error log pointer 0x%08X\n", base);
1379 return;
1380 }
1381
1382 count = il_read_targ_mem(il, base);
1383
1384 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1385 IL_ERR("Start IWL Error Log Dump:\n");
1386 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1387 }
1388
1389 IL_ERR("Desc Time asrtPC blink2 "
1390 "ilink1 nmiPC Line\n");
1391 for (i = ERROR_START_OFFSET;
1392 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1393 i += ERROR_ELEM_SIZE) {
1394 desc = il_read_targ_mem(il, base + i);
1395 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1396 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1397 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1398 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1399 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1400 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1401
1402 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1403 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1404 ilink1, ilink2, data1);
1405 }
1406}
1407
1408static void
1409il3945_irq_tasklet(struct il_priv *il)
1410{
1411 u32 inta, handled = 0;
1412 u32 inta_fh;
1413 unsigned long flags;
1414#ifdef CONFIG_IWLEGACY_DEBUG
1415 u32 inta_mask;
1416#endif
1417
1418 spin_lock_irqsave(&il->lock, flags);
1419
1420
1421
1422
1423 inta = _il_rd(il, CSR_INT);
1424 _il_wr(il, CSR_INT, inta);
1425
1426
1427
1428
1429 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1430 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1431
1432#ifdef CONFIG_IWLEGACY_DEBUG
1433 if (il_get_debug_level(il) & IL_DL_ISR) {
1434
1435 inta_mask = _il_rd(il, CSR_INT_MASK);
1436 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1437 inta_mask, inta_fh);
1438 }
1439#endif
1440
1441 spin_unlock_irqrestore(&il->lock, flags);
1442
1443
1444
1445
1446
1447 if (inta_fh & CSR39_FH_INT_RX_MASK)
1448 inta |= CSR_INT_BIT_FH_RX;
1449 if (inta_fh & CSR39_FH_INT_TX_MASK)
1450 inta |= CSR_INT_BIT_FH_TX;
1451
1452
1453 if (inta & CSR_INT_BIT_HW_ERR) {
1454 IL_ERR("Hardware error detected. Restarting.\n");
1455
1456
1457 il_disable_interrupts(il);
1458
1459 il->isr_stats.hw++;
1460 il_irq_handle_error(il);
1461
1462 handled |= CSR_INT_BIT_HW_ERR;
1463
1464 return;
1465 }
1466#ifdef CONFIG_IWLEGACY_DEBUG
1467 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1468
1469 if (inta & CSR_INT_BIT_SCD) {
1470 D_ISR("Scheduler finished to transmit "
1471 "the frame/frames.\n");
1472 il->isr_stats.sch++;
1473 }
1474
1475
1476 if (inta & CSR_INT_BIT_ALIVE) {
1477 D_ISR("Alive interrupt\n");
1478 il->isr_stats.alive++;
1479 }
1480 }
1481#endif
1482
1483 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1484
1485
1486 if (inta & CSR_INT_BIT_SW_ERR) {
1487 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1488 inta);
1489 il->isr_stats.sw++;
1490 il_irq_handle_error(il);
1491 handled |= CSR_INT_BIT_SW_ERR;
1492 }
1493
1494
1495 if (inta & CSR_INT_BIT_WAKEUP) {
1496 D_ISR("Wakeup interrupt\n");
1497 il_rx_queue_update_write_ptr(il, &il->rxq);
1498 il_txq_update_write_ptr(il, &il->txq[0]);
1499 il_txq_update_write_ptr(il, &il->txq[1]);
1500 il_txq_update_write_ptr(il, &il->txq[2]);
1501 il_txq_update_write_ptr(il, &il->txq[3]);
1502 il_txq_update_write_ptr(il, &il->txq[4]);
1503 il_txq_update_write_ptr(il, &il->txq[5]);
1504
1505 il->isr_stats.wakeup++;
1506 handled |= CSR_INT_BIT_WAKEUP;
1507 }
1508
1509
1510
1511
1512 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1513 il3945_rx_handle(il);
1514 il->isr_stats.rx++;
1515 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1516 }
1517
1518 if (inta & CSR_INT_BIT_FH_TX) {
1519 D_ISR("Tx interrupt\n");
1520 il->isr_stats.tx++;
1521
1522 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1523 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1524 handled |= CSR_INT_BIT_FH_TX;
1525 }
1526
1527 if (inta & ~handled) {
1528 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1529 il->isr_stats.unhandled++;
1530 }
1531
1532 if (inta & ~il->inta_mask) {
1533 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
1534 inta & ~il->inta_mask);
1535 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
1536 }
1537
1538
1539
1540 if (test_bit(S_INT_ENABLED, &il->status))
1541 il_enable_interrupts(il);
1542
1543#ifdef CONFIG_IWLEGACY_DEBUG
1544 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1545 inta = _il_rd(il, CSR_INT);
1546 inta_mask = _il_rd(il, CSR_INT_MASK);
1547 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1548 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1549 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1550 }
1551#endif
1552}
1553
1554static int
1555il3945_get_channels_for_scan(struct il_priv *il, enum ieee80211_band band,
1556 u8 is_active, u8 n_probes,
1557 struct il3945_scan_channel *scan_ch,
1558 struct ieee80211_vif *vif)
1559{
1560 struct ieee80211_channel *chan;
1561 const struct ieee80211_supported_band *sband;
1562 const struct il_channel_info *ch_info;
1563 u16 passive_dwell = 0;
1564 u16 active_dwell = 0;
1565 int added, i;
1566
1567 sband = il_get_hw_mode(il, band);
1568 if (!sband)
1569 return 0;
1570
1571 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1572 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1573
1574 if (passive_dwell <= active_dwell)
1575 passive_dwell = active_dwell + 1;
1576
1577 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1578 chan = il->scan_request->channels[i];
1579
1580 if (chan->band != band)
1581 continue;
1582
1583 scan_ch->channel = chan->hw_value;
1584
1585 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1586 if (!il_is_channel_valid(ch_info)) {
1587 D_SCAN("Channel %d is INVALID for this band.\n",
1588 scan_ch->channel);
1589 continue;
1590 }
1591
1592 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1593 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1594
1595
1596
1597 if (!is_active || il_is_channel_passive(ch_info) ||
1598 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
1599 scan_ch->type = 0;
1600 if (IL_UCODE_API(il->ucode_ver) == 1)
1601 scan_ch->active_dwell =
1602 cpu_to_le16(passive_dwell - 1);
1603 } else {
1604 scan_ch->type = 1;
1605 }
1606
1607
1608
1609
1610
1611 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1612 if (n_probes)
1613 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1614 } else {
1615
1616
1617 if ((scan_ch->type & 1) && n_probes)
1618 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1619 }
1620
1621
1622 scan_ch->tpc.dsp_atten = 110;
1623
1624
1625
1626 if (band == IEEE80211_BAND_5GHZ)
1627 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1628 else {
1629 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1630
1631
1632
1633
1634 }
1635
1636 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1637 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1638 (scan_ch->type & 1) ? active_dwell : passive_dwell);
1639
1640 scan_ch++;
1641 added++;
1642 }
1643
1644 D_SCAN("total channels to scan %d\n", added);
1645 return added;
1646}
1647
1648static void
1649il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1650{
1651 int i;
1652
1653 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
1654 rates[i].bitrate = il3945_rates[i].ieee * 5;
1655 rates[i].hw_value = i;
1656 rates[i].hw_value_short = i;
1657 rates[i].flags = 0;
1658 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
1659
1660
1661
1662 rates[i].flags |=
1663 (il3945_rates[i].plcp ==
1664 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1665 }
1666 }
1667}
1668
1669
1670
1671
1672
1673
1674
1675static void
1676il3945_dealloc_ucode_pci(struct il_priv *il)
1677{
1678 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1679 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1680 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1681 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1682 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1683 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1684}
1685
1686
1687
1688
1689
1690static int
1691il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1692{
1693 u32 val;
1694 u32 save_len = len;
1695 int rc = 0;
1696 u32 errcnt;
1697
1698 D_INFO("ucode inst image size is %u\n", len);
1699
1700 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1701
1702 errcnt = 0;
1703 for (; len > 0; len -= sizeof(u32), image++) {
1704
1705
1706
1707 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1708 if (val != le32_to_cpu(*image)) {
1709 IL_ERR("uCode INST section is invalid at "
1710 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1711 save_len - len, val, le32_to_cpu(*image));
1712 rc = -EIO;
1713 errcnt++;
1714 if (errcnt >= 20)
1715 break;
1716 }
1717 }
1718
1719 if (!errcnt)
1720 D_INFO("ucode image in INSTRUCTION memory is good\n");
1721
1722 return rc;
1723}
1724
1725
1726
1727
1728
1729
1730static int
1731il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1732{
1733 u32 val;
1734 int rc = 0;
1735 u32 errcnt = 0;
1736 u32 i;
1737
1738 D_INFO("ucode inst image size is %u\n", len);
1739
1740 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
1741
1742
1743
1744 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1745 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1746 if (val != le32_to_cpu(*image)) {
1747#if 0
1748 IL_ERR("uCode INST section is invalid at "
1749 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1750 *image);
1751#endif
1752 rc = -EIO;
1753 errcnt++;
1754 if (errcnt >= 3)
1755 break;
1756 }
1757 }
1758
1759 return rc;
1760}
1761
1762
1763
1764
1765
1766static int
1767il3945_verify_ucode(struct il_priv *il)
1768{
1769 __le32 *image;
1770 u32 len;
1771 int rc = 0;
1772
1773
1774 image = (__le32 *) il->ucode_boot.v_addr;
1775 len = il->ucode_boot.len;
1776 rc = il3945_verify_inst_sparse(il, image, len);
1777 if (rc == 0) {
1778 D_INFO("Bootstrap uCode is good in inst SRAM\n");
1779 return 0;
1780 }
1781
1782
1783 image = (__le32 *) il->ucode_init.v_addr;
1784 len = il->ucode_init.len;
1785 rc = il3945_verify_inst_sparse(il, image, len);
1786 if (rc == 0) {
1787 D_INFO("Initialize uCode is good in inst SRAM\n");
1788 return 0;
1789 }
1790
1791
1792 image = (__le32 *) il->ucode_code.v_addr;
1793 len = il->ucode_code.len;
1794 rc = il3945_verify_inst_sparse(il, image, len);
1795 if (rc == 0) {
1796 D_INFO("Runtime uCode is good in inst SRAM\n");
1797 return 0;
1798 }
1799
1800 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1801
1802
1803
1804
1805 image = (__le32 *) il->ucode_boot.v_addr;
1806 len = il->ucode_boot.len;
1807 rc = il3945_verify_inst_full(il, image, len);
1808
1809 return rc;
1810}
1811
1812static void
1813il3945_nic_start(struct il_priv *il)
1814{
1815
1816 _il_wr(il, CSR_RESET, 0);
1817}
1818
1819#define IL3945_UCODE_GET(item) \
1820static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
1821{ \
1822 return le32_to_cpu(ucode->v1.item); \
1823}
1824
1825static u32
1826il3945_ucode_get_header_size(u32 api_ver)
1827{
1828 return 24;
1829}
1830
1831static u8 *
1832il3945_ucode_get_data(const struct il_ucode_header *ucode)
1833{
1834 return (u8 *) ucode->v1.data;
1835}
1836
1837IL3945_UCODE_GET(inst_size);
1838IL3945_UCODE_GET(data_size);
1839IL3945_UCODE_GET(init_size);
1840IL3945_UCODE_GET(init_data_size);
1841IL3945_UCODE_GET(boot_size);
1842
1843
1844
1845
1846
1847
1848static int
1849il3945_read_ucode(struct il_priv *il)
1850{
1851 const struct il_ucode_header *ucode;
1852 int ret = -EINVAL, idx;
1853 const struct firmware *ucode_raw;
1854
1855 const char *name_pre = il->cfg->fw_name_pre;
1856 const unsigned int api_max = il->cfg->ucode_api_max;
1857 const unsigned int api_min = il->cfg->ucode_api_min;
1858 char buf[25];
1859 u8 *src;
1860 size_t len;
1861 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1862
1863
1864
1865 for (idx = api_max; idx >= api_min; idx--) {
1866 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
1867 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1868 if (ret < 0) {
1869 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
1870 if (ret == -ENOENT)
1871 continue;
1872 else
1873 goto error;
1874 } else {
1875 if (idx < api_max)
1876 IL_ERR("Loaded firmware %s, "
1877 "which is deprecated. "
1878 " Please use API v%u instead.\n", buf,
1879 api_max);
1880 D_INFO("Got firmware '%s' file "
1881 "(%zd bytes) from disk\n", buf, ucode_raw->size);
1882 break;
1883 }
1884 }
1885
1886 if (ret < 0)
1887 goto error;
1888
1889
1890 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
1891 IL_ERR("File size way too small!\n");
1892 ret = -EINVAL;
1893 goto err_release;
1894 }
1895
1896
1897 ucode = (struct il_ucode_header *)ucode_raw->data;
1898
1899 il->ucode_ver = le32_to_cpu(ucode->ver);
1900 api_ver = IL_UCODE_API(il->ucode_ver);
1901 inst_size = il3945_ucode_get_inst_size(ucode);
1902 data_size = il3945_ucode_get_data_size(ucode);
1903 init_size = il3945_ucode_get_init_size(ucode);
1904 init_data_size = il3945_ucode_get_init_data_size(ucode);
1905 boot_size = il3945_ucode_get_boot_size(ucode);
1906 src = il3945_ucode_get_data(ucode);
1907
1908
1909
1910
1911
1912 if (api_ver < api_min || api_ver > api_max) {
1913 IL_ERR("Driver unable to support your firmware API. "
1914 "Driver supports v%u, firmware is v%u.\n", api_max,
1915 api_ver);
1916 il->ucode_ver = 0;
1917 ret = -EINVAL;
1918 goto err_release;
1919 }
1920 if (api_ver != api_max)
1921 IL_ERR("Firmware has old API version. Expected %u, "
1922 "got %u. New firmware can be obtained "
1923 "from http://www.intellinuxwireless.org.\n", api_max,
1924 api_ver);
1925
1926 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1927 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1928 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1929
1930 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1931 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1932 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1933 IL_UCODE_SERIAL(il->ucode_ver));
1934
1935 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1936 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1937 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1938 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1939 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1940 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
1941
1942
1943 if (ucode_raw->size !=
1944 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1945 init_size + init_data_size + boot_size) {
1946
1947 D_INFO("uCode file size %zd does not match expected size\n",
1948 ucode_raw->size);
1949 ret = -EINVAL;
1950 goto err_release;
1951 }
1952
1953
1954 if (inst_size > IL39_MAX_INST_SIZE) {
1955 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
1956 ret = -EINVAL;
1957 goto err_release;
1958 }
1959
1960 if (data_size > IL39_MAX_DATA_SIZE) {
1961 D_INFO("uCode data len %d too large to fit in\n", data_size);
1962 ret = -EINVAL;
1963 goto err_release;
1964 }
1965 if (init_size > IL39_MAX_INST_SIZE) {
1966 D_INFO("uCode init instr len %d too large to fit in\n",
1967 init_size);
1968 ret = -EINVAL;
1969 goto err_release;
1970 }
1971 if (init_data_size > IL39_MAX_DATA_SIZE) {
1972 D_INFO("uCode init data len %d too large to fit in\n",
1973 init_data_size);
1974 ret = -EINVAL;
1975 goto err_release;
1976 }
1977 if (boot_size > IL39_MAX_BSM_SIZE) {
1978 D_INFO("uCode boot instr len %d too large to fit in\n",
1979 boot_size);
1980 ret = -EINVAL;
1981 goto err_release;
1982 }
1983
1984
1985
1986
1987
1988
1989 il->ucode_code.len = inst_size;
1990 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1991
1992 il->ucode_data.len = data_size;
1993 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1994
1995 il->ucode_data_backup.len = data_size;
1996 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1997
1998 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1999 !il->ucode_data_backup.v_addr)
2000 goto err_pci_alloc;
2001
2002
2003 if (init_size && init_data_size) {
2004 il->ucode_init.len = init_size;
2005 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
2006
2007 il->ucode_init_data.len = init_data_size;
2008 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
2009
2010 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
2011 goto err_pci_alloc;
2012 }
2013
2014
2015 if (boot_size) {
2016 il->ucode_boot.len = boot_size;
2017 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
2018
2019 if (!il->ucode_boot.v_addr)
2020 goto err_pci_alloc;
2021 }
2022
2023
2024
2025
2026 len = inst_size;
2027 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
2028 memcpy(il->ucode_code.v_addr, src, len);
2029 src += len;
2030
2031 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2032 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2033
2034
2035
2036 len = data_size;
2037 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
2038 memcpy(il->ucode_data.v_addr, src, len);
2039 memcpy(il->ucode_data_backup.v_addr, src, len);
2040 src += len;
2041
2042
2043 if (init_size) {
2044 len = init_size;
2045 D_INFO("Copying (but not loading) init instr len %zd\n", len);
2046 memcpy(il->ucode_init.v_addr, src, len);
2047 src += len;
2048 }
2049
2050
2051 if (init_data_size) {
2052 len = init_data_size;
2053 D_INFO("Copying (but not loading) init data len %zd\n", len);
2054 memcpy(il->ucode_init_data.v_addr, src, len);
2055 src += len;
2056 }
2057
2058
2059 len = boot_size;
2060 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
2061 memcpy(il->ucode_boot.v_addr, src, len);
2062
2063
2064 release_firmware(ucode_raw);
2065 return 0;
2066
2067err_pci_alloc:
2068 IL_ERR("failed to allocate pci memory\n");
2069 ret = -ENOMEM;
2070 il3945_dealloc_ucode_pci(il);
2071
2072err_release:
2073 release_firmware(ucode_raw);
2074
2075error:
2076 return ret;
2077}
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088static int
2089il3945_set_ucode_ptrs(struct il_priv *il)
2090{
2091 dma_addr_t pinst;
2092 dma_addr_t pdata;
2093
2094
2095 pinst = il->ucode_code.p_addr;
2096 pdata = il->ucode_data_backup.p_addr;
2097
2098
2099 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2100 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2101 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2102
2103
2104
2105 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2106 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2107
2108 D_INFO("Runtime uCode pointers are set.\n");
2109
2110 return 0;
2111}
2112
2113
2114
2115
2116
2117
2118
2119
2120static void
2121il3945_init_alive_start(struct il_priv *il)
2122{
2123
2124 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2125
2126
2127 D_INFO("Initialize Alive failed.\n");
2128 goto restart;
2129 }
2130
2131
2132
2133
2134 if (il3945_verify_ucode(il)) {
2135
2136
2137 D_INFO("Bad \"initialize\" uCode load.\n");
2138 goto restart;
2139 }
2140
2141
2142
2143
2144 D_INFO("Initialization Alive received.\n");
2145 if (il3945_set_ucode_ptrs(il)) {
2146
2147
2148 D_INFO("Couldn't set up uCode pointers.\n");
2149 goto restart;
2150 }
2151 return;
2152
2153restart:
2154 queue_work(il->workqueue, &il->restart);
2155}
2156
2157
2158
2159
2160
2161
2162static void
2163il3945_alive_start(struct il_priv *il)
2164{
2165 int thermal_spin = 0;
2166 u32 rfkill;
2167
2168 D_INFO("Runtime Alive received.\n");
2169
2170 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2171
2172
2173 D_INFO("Alive failed.\n");
2174 goto restart;
2175 }
2176
2177
2178
2179
2180 if (il3945_verify_ucode(il)) {
2181
2182
2183 D_INFO("Bad runtime uCode load.\n");
2184 goto restart;
2185 }
2186
2187 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2188 D_INFO("RFKILL status: 0x%x\n", rfkill);
2189
2190 if (rfkill & 0x1) {
2191 clear_bit(S_RFKILL, &il->status);
2192
2193
2194 while (il3945_hw_get_temperature(il) == 0) {
2195 thermal_spin++;
2196 udelay(10);
2197 }
2198
2199 if (thermal_spin)
2200 D_INFO("Thermal calibration took %dus\n",
2201 thermal_spin * 10);
2202 } else
2203 set_bit(S_RFKILL, &il->status);
2204
2205
2206 set_bit(S_ALIVE, &il->status);
2207
2208
2209 il_setup_watchdog(il);
2210
2211 if (il_is_rfkill(il))
2212 return;
2213
2214 ieee80211_wake_queues(il->hw);
2215
2216 il->active_rate = RATES_MASK_3945;
2217
2218 il_power_update_mode(il, true);
2219
2220 if (il_is_associated(il)) {
2221 struct il3945_rxon_cmd *active_rxon =
2222 (struct il3945_rxon_cmd *)(&il->active);
2223
2224 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2225 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2226 } else {
2227
2228 il_connection_init_rx_config(il);
2229 }
2230
2231
2232 il_send_bt_config(il);
2233
2234 set_bit(S_READY, &il->status);
2235
2236
2237 il3945_commit_rxon(il);
2238
2239 il3945_reg_txpower_periodic(il);
2240
2241 D_INFO("ALIVE processing complete.\n");
2242 wake_up(&il->wait_command_queue);
2243
2244 return;
2245
2246restart:
2247 queue_work(il->workqueue, &il->restart);
2248}
2249
2250static void il3945_cancel_deferred_work(struct il_priv *il);
2251
2252static void
2253__il3945_down(struct il_priv *il)
2254{
2255 unsigned long flags;
2256 int exit_pending;
2257
2258 D_INFO(DRV_NAME " is going down\n");
2259
2260 il_scan_cancel_timeout(il, 200);
2261
2262 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2263
2264
2265
2266 del_timer_sync(&il->watchdog);
2267
2268
2269 il_clear_ucode_stations(il);
2270 il_dealloc_bcast_stations(il);
2271 il_clear_driver_stations(il);
2272
2273
2274 wake_up_all(&il->wait_command_queue);
2275
2276
2277
2278 if (!exit_pending)
2279 clear_bit(S_EXIT_PENDING, &il->status);
2280
2281
2282 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2283
2284
2285 spin_lock_irqsave(&il->lock, flags);
2286 il_disable_interrupts(il);
2287 spin_unlock_irqrestore(&il->lock, flags);
2288 il3945_synchronize_irq(il);
2289
2290 if (il->mac80211_registered)
2291 ieee80211_stop_queues(il->hw);
2292
2293
2294
2295 if (!il_is_init(il)) {
2296 il->status =
2297 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2298 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2299 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2300 goto exit;
2301 }
2302
2303
2304
2305 il->status &=
2306 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2307 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2308 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2309 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2310
2311
2312
2313
2314
2315
2316 spin_lock_irq(&il->reg_lock);
2317
2318
2319 il3945_hw_txq_ctx_stop(il);
2320 il3945_hw_rxq_stop(il);
2321
2322 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2323 udelay(5);
2324
2325 _il_apm_stop(il);
2326
2327 spin_unlock_irq(&il->reg_lock);
2328
2329 il3945_hw_txq_ctx_free(il);
2330exit:
2331 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2332
2333 if (il->beacon_skb)
2334 dev_kfree_skb(il->beacon_skb);
2335 il->beacon_skb = NULL;
2336
2337
2338 il3945_clear_free_frames(il);
2339}
2340
2341static void
2342il3945_down(struct il_priv *il)
2343{
2344 mutex_lock(&il->mutex);
2345 __il3945_down(il);
2346 mutex_unlock(&il->mutex);
2347
2348 il3945_cancel_deferred_work(il);
2349}
2350
2351#define MAX_HW_RESTARTS 5
2352
2353static int
2354il3945_alloc_bcast_station(struct il_priv *il)
2355{
2356 unsigned long flags;
2357 u8 sta_id;
2358
2359 spin_lock_irqsave(&il->sta_lock, flags);
2360 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2361 if (sta_id == IL_INVALID_STATION) {
2362 IL_ERR("Unable to prepare broadcast station\n");
2363 spin_unlock_irqrestore(&il->sta_lock, flags);
2364
2365 return -EINVAL;
2366 }
2367
2368 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2369 il->stations[sta_id].used |= IL_STA_BCAST;
2370 spin_unlock_irqrestore(&il->sta_lock, flags);
2371
2372 return 0;
2373}
2374
2375static int
2376__il3945_up(struct il_priv *il)
2377{
2378 int rc, i;
2379
2380 rc = il3945_alloc_bcast_station(il);
2381 if (rc)
2382 return rc;
2383
2384 if (test_bit(S_EXIT_PENDING, &il->status)) {
2385 IL_WARN("Exit pending; will not bring the NIC up\n");
2386 return -EIO;
2387 }
2388
2389 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2390 IL_ERR("ucode not available for device bring up\n");
2391 return -EIO;
2392 }
2393
2394
2395 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2396 clear_bit(S_RFKILL, &il->status);
2397 else {
2398 set_bit(S_RFKILL, &il->status);
2399 IL_WARN("Radio disabled by HW RF Kill switch\n");
2400 return -ENODEV;
2401 }
2402
2403 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2404
2405 rc = il3945_hw_nic_init(il);
2406 if (rc) {
2407 IL_ERR("Unable to int nic\n");
2408 return rc;
2409 }
2410
2411
2412 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2413 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2414
2415
2416 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2417 il_enable_interrupts(il);
2418
2419
2420 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2421 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2422
2423
2424
2425
2426 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2427 il->ucode_data.len);
2428
2429
2430 if (test_bit(S_RFKILL, &il->status))
2431 return 0;
2432
2433 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2434
2435
2436
2437
2438 rc = il->ops->load_ucode(il);
2439
2440 if (rc) {
2441 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
2442 continue;
2443 }
2444
2445
2446 il3945_nic_start(il);
2447
2448 D_INFO(DRV_NAME " is coming up\n");
2449
2450 return 0;
2451 }
2452
2453 set_bit(S_EXIT_PENDING, &il->status);
2454 __il3945_down(il);
2455 clear_bit(S_EXIT_PENDING, &il->status);
2456
2457
2458
2459 IL_ERR("Unable to initialize device after %d attempts.\n", i);
2460 return -EIO;
2461}
2462
2463
2464
2465
2466
2467
2468
2469static void
2470il3945_bg_init_alive_start(struct work_struct *data)
2471{
2472 struct il_priv *il =
2473 container_of(data, struct il_priv, init_alive_start.work);
2474
2475 mutex_lock(&il->mutex);
2476 if (test_bit(S_EXIT_PENDING, &il->status))
2477 goto out;
2478
2479 il3945_init_alive_start(il);
2480out:
2481 mutex_unlock(&il->mutex);
2482}
2483
2484static void
2485il3945_bg_alive_start(struct work_struct *data)
2486{
2487 struct il_priv *il =
2488 container_of(data, struct il_priv, alive_start.work);
2489
2490 mutex_lock(&il->mutex);
2491 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2492 goto out;
2493
2494 il3945_alive_start(il);
2495out:
2496 mutex_unlock(&il->mutex);
2497}
2498
2499
2500
2501
2502
2503
2504
2505static void
2506il3945_rfkill_poll(struct work_struct *data)
2507{
2508 struct il_priv *il =
2509 container_of(data, struct il_priv, _3945.rfkill_poll.work);
2510 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2511 bool new_rfkill =
2512 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2513
2514 if (new_rfkill != old_rfkill) {
2515 if (new_rfkill)
2516 set_bit(S_RFKILL, &il->status);
2517 else
2518 clear_bit(S_RFKILL, &il->status);
2519
2520 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2521
2522 D_RF_KILL("RF_KILL bit toggled to %s.\n",
2523 new_rfkill ? "disable radio" : "enable radio");
2524 }
2525
2526
2527
2528 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2529 round_jiffies_relative(2 * HZ));
2530
2531}
2532
2533int
2534il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2535{
2536 struct il_host_cmd cmd = {
2537 .id = C_SCAN,
2538 .len = sizeof(struct il3945_scan_cmd),
2539 .flags = CMD_SIZE_HUGE,
2540 };
2541 struct il3945_scan_cmd *scan;
2542 u8 n_probes = 0;
2543 enum ieee80211_band band;
2544 bool is_active = false;
2545 int ret;
2546 u16 len;
2547
2548 lockdep_assert_held(&il->mutex);
2549
2550 if (!il->scan_cmd) {
2551 il->scan_cmd =
2552 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2553 GFP_KERNEL);
2554 if (!il->scan_cmd) {
2555 D_SCAN("Fail to allocate scan memory\n");
2556 return -ENOMEM;
2557 }
2558 }
2559 scan = il->scan_cmd;
2560 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
2561
2562 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2563 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
2564
2565 if (il_is_associated(il)) {
2566 u16 interval;
2567 u32 extra;
2568 u32 suspend_time = 100;
2569 u32 scan_suspend_time = 100;
2570
2571 D_INFO("Scanning while associated...\n");
2572
2573 interval = vif->bss_conf.beacon_int;
2574
2575 scan->suspend_time = 0;
2576 scan->max_out_time = cpu_to_le32(200 * 1024);
2577 if (!interval)
2578 interval = suspend_time;
2579
2580
2581
2582
2583
2584
2585
2586 extra = (suspend_time / interval) << 24;
2587 scan_suspend_time =
2588 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
2589
2590 scan->suspend_time = cpu_to_le32(scan_suspend_time);
2591 D_SCAN("suspend_time 0x%X beacon interval %d\n",
2592 scan_suspend_time, interval);
2593 }
2594
2595 if (il->scan_request->n_ssids) {
2596 int i, p = 0;
2597 D_SCAN("Kicking off active scan\n");
2598 for (i = 0; i < il->scan_request->n_ssids; i++) {
2599
2600 if (!il->scan_request->ssids[i].ssid_len)
2601 continue;
2602 scan->direct_scan[p].id = WLAN_EID_SSID;
2603 scan->direct_scan[p].len =
2604 il->scan_request->ssids[i].ssid_len;
2605 memcpy(scan->direct_scan[p].ssid,
2606 il->scan_request->ssids[i].ssid,
2607 il->scan_request->ssids[i].ssid_len);
2608 n_probes++;
2609 p++;
2610 }
2611 is_active = true;
2612 } else
2613 D_SCAN("Kicking off passive scan.\n");
2614
2615
2616
2617 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2618 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2619 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2620
2621
2622
2623 switch (il->scan_band) {
2624 case IEEE80211_BAND_2GHZ:
2625 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2626 scan->tx_cmd.rate = RATE_1M_PLCP;
2627 band = IEEE80211_BAND_2GHZ;
2628 break;
2629 case IEEE80211_BAND_5GHZ:
2630 scan->tx_cmd.rate = RATE_6M_PLCP;
2631 band = IEEE80211_BAND_5GHZ;
2632 break;
2633 default:
2634 IL_WARN("Invalid scan band\n");
2635 return -EIO;
2636 }
2637
2638
2639
2640
2641
2642
2643 scan->good_CRC_th =
2644 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
2645
2646 len =
2647 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2648 vif->addr, il->scan_request->ie,
2649 il->scan_request->ie_len,
2650 IL_MAX_SCAN_SIZE - sizeof(*scan));
2651 scan->tx_cmd.len = cpu_to_le16(len);
2652
2653
2654 scan->flags |= il3945_get_antenna_flags(il);
2655
2656 scan->channel_count =
2657 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2658 (void *)&scan->data[len], vif);
2659 if (scan->channel_count == 0) {
2660 D_SCAN("channel count %d\n", scan->channel_count);
2661 return -EIO;
2662 }
2663
2664 cmd.len +=
2665 le16_to_cpu(scan->tx_cmd.len) +
2666 scan->channel_count * sizeof(struct il3945_scan_channel);
2667 cmd.data = scan;
2668 scan->len = cpu_to_le16(cmd.len);
2669
2670 set_bit(S_SCAN_HW, &il->status);
2671 ret = il_send_cmd_sync(il, &cmd);
2672 if (ret)
2673 clear_bit(S_SCAN_HW, &il->status);
2674 return ret;
2675}
2676
2677void
2678il3945_post_scan(struct il_priv *il)
2679{
2680
2681
2682
2683
2684 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2685 il3945_commit_rxon(il);
2686}
2687
2688static void
2689il3945_bg_restart(struct work_struct *data)
2690{
2691 struct il_priv *il = container_of(data, struct il_priv, restart);
2692
2693 if (test_bit(S_EXIT_PENDING, &il->status))
2694 return;
2695
2696 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2697 mutex_lock(&il->mutex);
2698 il->is_open = 0;
2699 mutex_unlock(&il->mutex);
2700 il3945_down(il);
2701 ieee80211_restart_hw(il->hw);
2702 } else {
2703 il3945_down(il);
2704
2705 mutex_lock(&il->mutex);
2706 if (test_bit(S_EXIT_PENDING, &il->status)) {
2707 mutex_unlock(&il->mutex);
2708 return;
2709 }
2710
2711 __il3945_up(il);
2712 mutex_unlock(&il->mutex);
2713 }
2714}
2715
2716static void
2717il3945_bg_rx_replenish(struct work_struct *data)
2718{
2719 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2720
2721 mutex_lock(&il->mutex);
2722 if (test_bit(S_EXIT_PENDING, &il->status))
2723 goto out;
2724
2725 il3945_rx_replenish(il);
2726out:
2727 mutex_unlock(&il->mutex);
2728}
2729
2730void
2731il3945_post_associate(struct il_priv *il)
2732{
2733 int rc = 0;
2734 struct ieee80211_conf *conf = NULL;
2735
2736 if (!il->vif || !il->is_open)
2737 return;
2738
2739 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
2740 il->active.bssid_addr);
2741
2742 if (test_bit(S_EXIT_PENDING, &il->status))
2743 return;
2744
2745 il_scan_cancel_timeout(il, 200);
2746
2747 conf = &il->hw->conf;
2748
2749 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2750 il3945_commit_rxon(il);
2751
2752 rc = il_send_rxon_timing(il);
2753 if (rc)
2754 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
2755
2756 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2757
2758 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
2759
2760 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2761 il->vif->bss_conf.beacon_int);
2762
2763 if (il->vif->bss_conf.use_short_preamble)
2764 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2765 else
2766 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2767
2768 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2769 if (il->vif->bss_conf.use_short_slot)
2770 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2771 else
2772 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2773 }
2774
2775 il3945_commit_rxon(il);
2776
2777 switch (il->vif->type) {
2778 case NL80211_IFTYPE_STATION:
2779 il3945_rate_scale_init(il->hw, IL_AP_ID);
2780 break;
2781 case NL80211_IFTYPE_ADHOC:
2782 il3945_send_beacon_cmd(il);
2783 break;
2784 default:
2785 IL_ERR("%s Should not be called in %d mode\n", __func__,
2786 il->vif->type);
2787 break;
2788 }
2789}
2790
2791
2792
2793
2794
2795
2796
2797#define UCODE_READY_TIMEOUT (2 * HZ)
2798
2799static int
2800il3945_mac_start(struct ieee80211_hw *hw)
2801{
2802 struct il_priv *il = hw->priv;
2803 int ret;
2804
2805
2806 mutex_lock(&il->mutex);
2807 D_MAC80211("enter\n");
2808
2809
2810
2811
2812 if (!il->ucode_code.len) {
2813 ret = il3945_read_ucode(il);
2814 if (ret) {
2815 IL_ERR("Could not read microcode: %d\n", ret);
2816 mutex_unlock(&il->mutex);
2817 goto out_release_irq;
2818 }
2819 }
2820
2821 ret = __il3945_up(il);
2822
2823 mutex_unlock(&il->mutex);
2824
2825 if (ret)
2826 goto out_release_irq;
2827
2828 D_INFO("Start UP work.\n");
2829
2830
2831
2832 ret = wait_event_timeout(il->wait_command_queue,
2833 test_bit(S_READY, &il->status),
2834 UCODE_READY_TIMEOUT);
2835 if (!ret) {
2836 if (!test_bit(S_READY, &il->status)) {
2837 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2838 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2839 ret = -ETIMEDOUT;
2840 goto out_release_irq;
2841 }
2842 }
2843
2844
2845
2846 cancel_delayed_work(&il->_3945.rfkill_poll);
2847
2848 il->is_open = 1;
2849 D_MAC80211("leave\n");
2850 return 0;
2851
2852out_release_irq:
2853 il->is_open = 0;
2854 D_MAC80211("leave - failed\n");
2855 return ret;
2856}
2857
2858static void
2859il3945_mac_stop(struct ieee80211_hw *hw)
2860{
2861 struct il_priv *il = hw->priv;
2862
2863 D_MAC80211("enter\n");
2864
2865 if (!il->is_open) {
2866 D_MAC80211("leave - skip\n");
2867 return;
2868 }
2869
2870 il->is_open = 0;
2871
2872 il3945_down(il);
2873
2874 flush_workqueue(il->workqueue);
2875
2876
2877 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2878 round_jiffies_relative(2 * HZ));
2879
2880 D_MAC80211("leave\n");
2881}
2882
2883static void
2884il3945_mac_tx(struct ieee80211_hw *hw,
2885 struct ieee80211_tx_control *control,
2886 struct sk_buff *skb)
2887{
2888 struct il_priv *il = hw->priv;
2889
2890 D_MAC80211("enter\n");
2891
2892 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2893 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2894
2895 if (il3945_tx_skb(il, control->sta, skb))
2896 dev_kfree_skb_any(skb);
2897
2898 D_MAC80211("leave\n");
2899}
2900
2901void
2902il3945_config_ap(struct il_priv *il)
2903{
2904 struct ieee80211_vif *vif = il->vif;
2905 int rc = 0;
2906
2907 if (test_bit(S_EXIT_PENDING, &il->status))
2908 return;
2909
2910
2911 if (!(il_is_associated(il))) {
2912
2913
2914 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2915 il3945_commit_rxon(il);
2916
2917
2918 rc = il_send_rxon_timing(il);
2919 if (rc)
2920 IL_WARN("C_RXON_TIMING failed - "
2921 "Attempting to continue.\n");
2922
2923 il->staging.assoc_id = 0;
2924
2925 if (vif->bss_conf.use_short_preamble)
2926 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2927 else
2928 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2929
2930 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2931 if (vif->bss_conf.use_short_slot)
2932 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2933 else
2934 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2935 }
2936
2937 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2938 il3945_commit_rxon(il);
2939 }
2940 il3945_send_beacon_cmd(il);
2941}
2942
2943static int
2944il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2945 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2946 struct ieee80211_key_conf *key)
2947{
2948 struct il_priv *il = hw->priv;
2949 int ret = 0;
2950 u8 sta_id = IL_INVALID_STATION;
2951 u8 static_key;
2952
2953 D_MAC80211("enter\n");
2954
2955 if (il3945_mod_params.sw_crypto) {
2956 D_MAC80211("leave - hwcrypto disabled\n");
2957 return -EOPNOTSUPP;
2958 }
2959
2960
2961
2962
2963
2964 if (vif->type == NL80211_IFTYPE_ADHOC &&
2965 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2966 D_MAC80211("leave - IBSS RSN\n");
2967 return -EOPNOTSUPP;
2968 }
2969
2970 static_key = !il_is_associated(il);
2971
2972 if (!static_key) {
2973 sta_id = il_sta_id_or_broadcast(il, sta);
2974 if (sta_id == IL_INVALID_STATION) {
2975 D_MAC80211("leave - station not found\n");
2976 return -EINVAL;
2977 }
2978 }
2979
2980 mutex_lock(&il->mutex);
2981 il_scan_cancel_timeout(il, 100);
2982
2983 switch (cmd) {
2984 case SET_KEY:
2985 if (static_key)
2986 ret = il3945_set_static_key(il, key);
2987 else
2988 ret = il3945_set_dynamic_key(il, key, sta_id);
2989 D_MAC80211("enable hwcrypto key\n");
2990 break;
2991 case DISABLE_KEY:
2992 if (static_key)
2993 ret = il3945_remove_static_key(il);
2994 else
2995 ret = il3945_clear_sta_key_info(il, sta_id);
2996 D_MAC80211("disable hwcrypto key\n");
2997 break;
2998 default:
2999 ret = -EINVAL;
3000 }
3001
3002 D_MAC80211("leave ret %d\n", ret);
3003 mutex_unlock(&il->mutex);
3004
3005 return ret;
3006}
3007
3008static int
3009il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3010 struct ieee80211_sta *sta)
3011{
3012 struct il_priv *il = hw->priv;
3013 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
3014 int ret;
3015 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3016 u8 sta_id;
3017
3018 mutex_lock(&il->mutex);
3019 D_INFO("station %pM\n", sta->addr);
3020 sta_priv->common.sta_id = IL_INVALID_STATION;
3021
3022 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
3023 if (ret) {
3024 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
3025
3026 mutex_unlock(&il->mutex);
3027 return ret;
3028 }
3029
3030 sta_priv->common.sta_id = sta_id;
3031
3032
3033 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
3034 il3945_rs_rate_init(il, sta, sta_id);
3035 mutex_unlock(&il->mutex);
3036
3037 return 0;
3038}
3039
3040static void
3041il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3042 unsigned int *total_flags, u64 multicast)
3043{
3044 struct il_priv *il = hw->priv;
3045 __le32 filter_or = 0, filter_nand = 0;
3046
3047#define CHK(test, flag) do { \
3048 if (*total_flags & (test)) \
3049 filter_or |= (flag); \
3050 else \
3051 filter_nand |= (flag); \
3052 } while (0)
3053
3054 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3055 *total_flags);
3056
3057 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3058 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3059 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3060
3061#undef CHK
3062
3063 mutex_lock(&il->mutex);
3064
3065 il->staging.filter_flags &= ~filter_nand;
3066 il->staging.filter_flags |= filter_or;
3067
3068
3069
3070
3071
3072
3073
3074 mutex_unlock(&il->mutex);
3075
3076
3077
3078
3079
3080
3081
3082 *total_flags &=
3083 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3084 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3085}
3086
3087
3088
3089
3090
3091
3092
3093#ifdef CONFIG_IWLEGACY_DEBUG
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106static ssize_t
3107il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3108 char *buf)
3109{
3110 struct il_priv *il = dev_get_drvdata(d);
3111 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3112}
3113
3114static ssize_t
3115il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3116 const char *buf, size_t count)
3117{
3118 struct il_priv *il = dev_get_drvdata(d);
3119 unsigned long val;
3120 int ret;
3121
3122 ret = kstrtoul(buf, 0, &val);
3123 if (ret)
3124 IL_INFO("%s is not in hex or decimal form.\n", buf);
3125 else
3126 il->debug_level = val;
3127
3128 return strnlen(buf, count);
3129}
3130
3131static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il3945_show_debug_level,
3132 il3945_store_debug_level);
3133
3134#endif
3135
3136static ssize_t
3137il3945_show_temperature(struct device *d, struct device_attribute *attr,
3138 char *buf)
3139{
3140 struct il_priv *il = dev_get_drvdata(d);
3141
3142 if (!il_is_alive(il))
3143 return -EAGAIN;
3144
3145 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3146}
3147
3148static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
3149
3150static ssize_t
3151il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
3152{
3153 struct il_priv *il = dev_get_drvdata(d);
3154 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3155}
3156
3157static ssize_t
3158il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3159 const char *buf, size_t count)
3160{
3161 struct il_priv *il = dev_get_drvdata(d);
3162 char *p = (char *)buf;
3163 u32 val;
3164
3165 val = simple_strtoul(p, &p, 10);
3166 if (p == buf)
3167 IL_INFO(": %s is not in decimal form.\n", buf);
3168 else
3169 il3945_hw_reg_set_txpower(il, val);
3170
3171 return count;
3172}
3173
3174static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power,
3175 il3945_store_tx_power);
3176
3177static ssize_t
3178il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
3179{
3180 struct il_priv *il = dev_get_drvdata(d);
3181
3182 return sprintf(buf, "0x%04X\n", il->active.flags);
3183}
3184
3185static ssize_t
3186il3945_store_flags(struct device *d, struct device_attribute *attr,
3187 const char *buf, size_t count)
3188{
3189 struct il_priv *il = dev_get_drvdata(d);
3190 u32 flags = simple_strtoul(buf, NULL, 0);
3191
3192 mutex_lock(&il->mutex);
3193 if (le32_to_cpu(il->staging.flags) != flags) {
3194
3195 if (il_scan_cancel_timeout(il, 100))
3196 IL_WARN("Could not cancel scan.\n");
3197 else {
3198 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
3199 il->staging.flags = cpu_to_le32(flags);
3200 il3945_commit_rxon(il);
3201 }
3202 }
3203 mutex_unlock(&il->mutex);
3204
3205 return count;
3206}
3207
3208static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags,
3209 il3945_store_flags);
3210
3211static ssize_t
3212il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3213 char *buf)
3214{
3215 struct il_priv *il = dev_get_drvdata(d);
3216
3217 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3218}
3219
3220static ssize_t
3221il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3222 const char *buf, size_t count)
3223{
3224 struct il_priv *il = dev_get_drvdata(d);
3225 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3226
3227 mutex_lock(&il->mutex);
3228 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3229
3230 if (il_scan_cancel_timeout(il, 100))
3231 IL_WARN("Could not cancel scan.\n");
3232 else {
3233 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3234 filter_flags);
3235 il->staging.filter_flags = cpu_to_le32(filter_flags);
3236 il3945_commit_rxon(il);
3237 }
3238 }
3239 mutex_unlock(&il->mutex);
3240
3241 return count;
3242}
3243
3244static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
3245 il3945_store_filter_flags);
3246
3247static ssize_t
3248il3945_show_measurement(struct device *d, struct device_attribute *attr,
3249 char *buf)
3250{
3251 struct il_priv *il = dev_get_drvdata(d);
3252 struct il_spectrum_notification measure_report;
3253 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3254 u8 *data = (u8 *) &measure_report;
3255 unsigned long flags;
3256
3257 spin_lock_irqsave(&il->lock, flags);
3258 if (!(il->measurement_status & MEASUREMENT_READY)) {
3259 spin_unlock_irqrestore(&il->lock, flags);
3260 return 0;
3261 }
3262 memcpy(&measure_report, &il->measure_report, size);
3263 il->measurement_status = 0;
3264 spin_unlock_irqrestore(&il->lock, flags);
3265
3266 while (size && PAGE_SIZE - len) {
3267 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3268 PAGE_SIZE - len, 1);
3269 len = strlen(buf);
3270 if (PAGE_SIZE - len)
3271 buf[len++] = '\n';
3272
3273 ofs += 16;
3274 size -= min(size, 16U);
3275 }
3276
3277 return len;
3278}
3279
3280static ssize_t
3281il3945_store_measurement(struct device *d, struct device_attribute *attr,
3282 const char *buf, size_t count)
3283{
3284 struct il_priv *il = dev_get_drvdata(d);
3285 struct ieee80211_measurement_params params = {
3286 .channel = le16_to_cpu(il->active.channel),
3287 .start_time = cpu_to_le64(il->_3945.last_tsf),
3288 .duration = cpu_to_le16(1),
3289 };
3290 u8 type = IL_MEASURE_BASIC;
3291 u8 buffer[32];
3292 u8 channel;
3293
3294 if (count) {
3295 char *p = buffer;
3296 strlcpy(buffer, buf, sizeof(buffer));
3297 channel = simple_strtoul(p, NULL, 0);
3298 if (channel)
3299 params.channel = channel;
3300
3301 p = buffer;
3302 while (*p && *p != ' ')
3303 p++;
3304 if (*p)
3305 type = simple_strtoul(p + 1, NULL, 0);
3306 }
3307
3308 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3309 type, params.channel, buf);
3310 il3945_get_measurement(il, ¶ms, type);
3311
3312 return count;
3313}
3314
3315static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, il3945_show_measurement,
3316 il3945_store_measurement);
3317
3318static ssize_t
3319il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3320 const char *buf, size_t count)
3321{
3322 struct il_priv *il = dev_get_drvdata(d);
3323
3324 il->retry_rate = simple_strtoul(buf, NULL, 0);
3325 if (il->retry_rate <= 0)
3326 il->retry_rate = 1;
3327
3328 return count;
3329}
3330
3331static ssize_t
3332il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3333 char *buf)
3334{
3335 struct il_priv *il = dev_get_drvdata(d);
3336 return sprintf(buf, "%d", il->retry_rate);
3337}
3338
3339static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
3340 il3945_store_retry_rate);
3341
3342static ssize_t
3343il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
3344{
3345
3346 return 0;
3347}
3348
3349static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
3350
3351static ssize_t
3352il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
3353{
3354 struct il_priv *il = dev_get_drvdata(d);
3355
3356 if (!il_is_alive(il))
3357 return -EAGAIN;
3358
3359 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
3360}
3361
3362static ssize_t
3363il3945_store_antenna(struct device *d, struct device_attribute *attr,
3364 const char *buf, size_t count)
3365{
3366 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3367 int ant;
3368
3369 if (count == 0)
3370 return 0;
3371
3372 if (sscanf(buf, "%1i", &ant) != 1) {
3373 D_INFO("not in hex or decimal form.\n");
3374 return count;
3375 }
3376
3377 if (ant >= 0 && ant <= 2) {
3378 D_INFO("Setting antenna select to %d.\n", ant);
3379 il3945_mod_params.antenna = (enum il3945_antenna)ant;
3380 } else
3381 D_INFO("Bad antenna select value %d.\n", ant);
3382
3383 return count;
3384}
3385
3386static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna,
3387 il3945_store_antenna);
3388
3389static ssize_t
3390il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
3391{
3392 struct il_priv *il = dev_get_drvdata(d);
3393 if (!il_is_alive(il))
3394 return -EAGAIN;
3395 return sprintf(buf, "0x%08x\n", (int)il->status);
3396}
3397
3398static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
3399
3400static ssize_t
3401il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3402 const char *buf, size_t count)
3403{
3404 struct il_priv *il = dev_get_drvdata(d);
3405 char *p = (char *)buf;
3406
3407 if (p[0] == '1')
3408 il3945_dump_nic_error_log(il);
3409
3410 return strnlen(buf, count);
3411}
3412
3413static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
3414
3415
3416
3417
3418
3419
3420
3421static void
3422il3945_setup_deferred_work(struct il_priv *il)
3423{
3424 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3425
3426 init_waitqueue_head(&il->wait_command_queue);
3427
3428 INIT_WORK(&il->restart, il3945_bg_restart);
3429 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3430 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3431 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3432 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3433
3434 il_setup_scan_deferred_work(il);
3435
3436 il3945_hw_setup_deferred_work(il);
3437
3438 init_timer(&il->watchdog);
3439 il->watchdog.data = (unsigned long)il;
3440 il->watchdog.function = il_bg_watchdog;
3441
3442 tasklet_init(&il->irq_tasklet,
3443 (void (*)(unsigned long))il3945_irq_tasklet,
3444 (unsigned long)il);
3445}
3446
3447static void
3448il3945_cancel_deferred_work(struct il_priv *il)
3449{
3450 il3945_hw_cancel_deferred_work(il);
3451
3452 cancel_delayed_work_sync(&il->init_alive_start);
3453 cancel_delayed_work(&il->alive_start);
3454
3455 il_cancel_scan_deferred_work(il);
3456}
3457
3458static struct attribute *il3945_sysfs_entries[] = {
3459 &dev_attr_antenna.attr,
3460 &dev_attr_channels.attr,
3461 &dev_attr_dump_errors.attr,
3462 &dev_attr_flags.attr,
3463 &dev_attr_filter_flags.attr,
3464 &dev_attr_measurement.attr,
3465 &dev_attr_retry_rate.attr,
3466 &dev_attr_status.attr,
3467 &dev_attr_temperature.attr,
3468 &dev_attr_tx_power.attr,
3469#ifdef CONFIG_IWLEGACY_DEBUG
3470 &dev_attr_debug_level.attr,
3471#endif
3472 NULL
3473};
3474
3475static struct attribute_group il3945_attribute_group = {
3476 .name = NULL,
3477 .attrs = il3945_sysfs_entries,
3478};
3479
3480static struct ieee80211_ops il3945_mac_ops __read_mostly = {
3481 .tx = il3945_mac_tx,
3482 .start = il3945_mac_start,
3483 .stop = il3945_mac_stop,
3484 .add_interface = il_mac_add_interface,
3485 .remove_interface = il_mac_remove_interface,
3486 .change_interface = il_mac_change_interface,
3487 .config = il_mac_config,
3488 .configure_filter = il3945_configure_filter,
3489 .set_key = il3945_mac_set_key,
3490 .conf_tx = il_mac_conf_tx,
3491 .reset_tsf = il_mac_reset_tsf,
3492 .bss_info_changed = il_mac_bss_info_changed,
3493 .hw_scan = il_mac_hw_scan,
3494 .sta_add = il3945_mac_sta_add,
3495 .sta_remove = il_mac_sta_remove,
3496 .tx_last_beacon = il_mac_tx_last_beacon,
3497 .flush = il_mac_flush,
3498};
3499
3500static int
3501il3945_init_drv(struct il_priv *il)
3502{
3503 int ret;
3504 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3505
3506 il->retry_rate = 1;
3507 il->beacon_skb = NULL;
3508
3509 spin_lock_init(&il->sta_lock);
3510 spin_lock_init(&il->hcmd_lock);
3511
3512 INIT_LIST_HEAD(&il->free_frames);
3513
3514 mutex_init(&il->mutex);
3515
3516 il->ieee_channels = NULL;
3517 il->ieee_rates = NULL;
3518 il->band = IEEE80211_BAND_2GHZ;
3519
3520 il->iw_mode = NL80211_IFTYPE_STATION;
3521 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3522
3523
3524 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3525
3526 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3527 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
3528 eeprom->version);
3529 ret = -EINVAL;
3530 goto err;
3531 }
3532 ret = il_init_channel_map(il);
3533 if (ret) {
3534 IL_ERR("initializing regulatory failed: %d\n", ret);
3535 goto err;
3536 }
3537
3538
3539 if (il3945_txpower_set_from_eeprom(il)) {
3540 ret = -EIO;
3541 goto err_free_channel_map;
3542 }
3543
3544 ret = il_init_geos(il);
3545 if (ret) {
3546 IL_ERR("initializing geos failed: %d\n", ret);
3547 goto err_free_channel_map;
3548 }
3549 il3945_init_hw_rates(il, il->ieee_rates);
3550
3551 return 0;
3552
3553err_free_channel_map:
3554 il_free_channel_map(il);
3555err:
3556 return ret;
3557}
3558
3559#define IL3945_MAX_PROBE_REQUEST 200
3560
3561static int
3562il3945_setup_mac(struct il_priv *il)
3563{
3564 int ret;
3565 struct ieee80211_hw *hw = il->hw;
3566
3567 hw->rate_control_algorithm = "iwl-3945-rs";
3568 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3569 hw->vif_data_size = sizeof(struct il_vif_priv);
3570
3571
3572 hw->flags = IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_SPECTRUM_MGMT |
3573 IEEE80211_HW_SUPPORTS_PS | IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3574
3575 hw->wiphy->interface_modes =
3576 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
3577
3578 hw->wiphy->flags |=
3579 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
3580 WIPHY_FLAG_IBSS_RSN;
3581
3582 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3583
3584 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3585
3586 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
3587
3588
3589 hw->queues = 4;
3590
3591 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
3592 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3593 &il->bands[IEEE80211_BAND_2GHZ];
3594
3595 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
3596 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3597 &il->bands[IEEE80211_BAND_5GHZ];
3598
3599 il_leds_init(il);
3600
3601 ret = ieee80211_register_hw(il->hw);
3602 if (ret) {
3603 IL_ERR("Failed to register hw (error %d)\n", ret);
3604 return ret;
3605 }
3606 il->mac80211_registered = 1;
3607
3608 return 0;
3609}
3610
3611static int
3612il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3613{
3614 int err = 0;
3615 struct il_priv *il;
3616 struct ieee80211_hw *hw;
3617 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3618 struct il3945_eeprom *eeprom;
3619 unsigned long flags;
3620
3621
3622
3623
3624
3625 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3626 if (!hw) {
3627 err = -ENOMEM;
3628 goto out;
3629 }
3630 il = hw->priv;
3631 il->hw = hw;
3632 SET_IEEE80211_DEV(hw, &pdev->dev);
3633
3634 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3635
3636
3637
3638
3639
3640 if (il3945_mod_params.disable_hw_scan) {
3641 D_INFO("Disabling hw_scan\n");
3642 il3945_mac_ops.hw_scan = NULL;
3643 }
3644
3645 D_INFO("*** LOAD DRIVER ***\n");
3646 il->cfg = cfg;
3647 il->ops = &il3945_ops;
3648#ifdef CONFIG_IWLEGACY_DEBUGFS
3649 il->debugfs_ops = &il3945_debugfs_ops;
3650#endif
3651 il->pci_dev = pdev;
3652 il->inta_mask = CSR_INI_SET_MASK;
3653
3654
3655
3656
3657 pci_disable_link_state(pdev,
3658 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3659 PCIE_LINK_STATE_CLKPM);
3660
3661 if (pci_enable_device(pdev)) {
3662 err = -ENODEV;
3663 goto out_ieee80211_free_hw;
3664 }
3665
3666 pci_set_master(pdev);
3667
3668 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3669 if (!err)
3670 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3671 if (err) {
3672 IL_WARN("No suitable DMA available.\n");
3673 goto out_pci_disable_device;
3674 }
3675
3676 pci_set_drvdata(pdev, il);
3677 err = pci_request_regions(pdev, DRV_NAME);
3678 if (err)
3679 goto out_pci_disable_device;
3680
3681
3682
3683
3684 il->hw_base = pci_ioremap_bar(pdev, 0);
3685 if (!il->hw_base) {
3686 err = -ENODEV;
3687 goto out_pci_release_regions;
3688 }
3689
3690 D_INFO("pci_resource_len = 0x%08llx\n",
3691 (unsigned long long)pci_resource_len(pdev, 0));
3692 D_INFO("pci_resource_base = %p\n", il->hw_base);
3693
3694
3695
3696 pci_write_config_byte(pdev, 0x41, 0x00);
3697
3698
3699
3700
3701 spin_lock_init(&il->reg_lock);
3702 spin_lock_init(&il->lock);
3703
3704
3705
3706
3707
3708
3709 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3710
3711
3712
3713
3714
3715
3716 err = il_eeprom_init(il);
3717 if (err) {
3718 IL_ERR("Unable to init EEPROM\n");
3719 goto out_iounmap;
3720 }
3721
3722 eeprom = (struct il3945_eeprom *)il->eeprom;
3723 D_INFO("MAC address: %pM\n", eeprom->mac_address);
3724 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3725
3726
3727
3728
3729
3730 err = il3945_hw_set_hw_params(il);
3731 if (err) {
3732 IL_ERR("failed to set hw settings\n");
3733 goto out_eeprom_free;
3734 }
3735
3736
3737
3738
3739
3740 err = il3945_init_drv(il);
3741 if (err) {
3742 IL_ERR("initializing driver failed\n");
3743 goto out_unset_hw_params;
3744 }
3745
3746 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3747
3748
3749
3750
3751
3752 spin_lock_irqsave(&il->lock, flags);
3753 il_disable_interrupts(il);
3754 spin_unlock_irqrestore(&il->lock, flags);
3755
3756 pci_enable_msi(il->pci_dev);
3757
3758 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3759 if (err) {
3760 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3761 goto out_disable_msi;
3762 }
3763
3764 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
3765 if (err) {
3766 IL_ERR("failed to create sysfs device attributes\n");
3767 goto out_release_irq;
3768 }
3769
3770 il_set_rxon_channel(il, &il->bands[IEEE80211_BAND_2GHZ].channels[5]);
3771 il3945_setup_deferred_work(il);
3772 il3945_setup_handlers(il);
3773 il_power_initialize(il);
3774
3775
3776
3777
3778
3779 il_enable_interrupts(il);
3780
3781 err = il3945_setup_mac(il);
3782 if (err)
3783 goto out_remove_sysfs;
3784
3785 err = il_dbgfs_register(il, DRV_NAME);
3786 if (err)
3787 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
3788 err);
3789
3790
3791 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3792
3793 return 0;
3794
3795out_remove_sysfs:
3796 destroy_workqueue(il->workqueue);
3797 il->workqueue = NULL;
3798 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3799out_release_irq:
3800 free_irq(il->pci_dev->irq, il);
3801out_disable_msi:
3802 pci_disable_msi(il->pci_dev);
3803 il_free_geos(il);
3804 il_free_channel_map(il);
3805out_unset_hw_params:
3806 il3945_unset_hw_params(il);
3807out_eeprom_free:
3808 il_eeprom_free(il);
3809out_iounmap:
3810 iounmap(il->hw_base);
3811out_pci_release_regions:
3812 pci_release_regions(pdev);
3813out_pci_disable_device:
3814 pci_set_drvdata(pdev, NULL);
3815 pci_disable_device(pdev);
3816out_ieee80211_free_hw:
3817 ieee80211_free_hw(il->hw);
3818out:
3819 return err;
3820}
3821
3822static void
3823il3945_pci_remove(struct pci_dev *pdev)
3824{
3825 struct il_priv *il = pci_get_drvdata(pdev);
3826 unsigned long flags;
3827
3828 if (!il)
3829 return;
3830
3831 D_INFO("*** UNLOAD DRIVER ***\n");
3832
3833 il_dbgfs_unregister(il);
3834
3835 set_bit(S_EXIT_PENDING, &il->status);
3836
3837 il_leds_exit(il);
3838
3839 if (il->mac80211_registered) {
3840 ieee80211_unregister_hw(il->hw);
3841 il->mac80211_registered = 0;
3842 } else {
3843 il3945_down(il);
3844 }
3845
3846
3847
3848
3849
3850
3851
3852
3853 il_apm_stop(il);
3854
3855
3856
3857
3858 spin_lock_irqsave(&il->lock, flags);
3859 il_disable_interrupts(il);
3860 spin_unlock_irqrestore(&il->lock, flags);
3861
3862 il3945_synchronize_irq(il);
3863
3864 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3865
3866 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3867
3868 il3945_dealloc_ucode_pci(il);
3869
3870 if (il->rxq.bd)
3871 il3945_rx_queue_free(il, &il->rxq);
3872 il3945_hw_txq_ctx_free(il);
3873
3874 il3945_unset_hw_params(il);
3875
3876
3877 flush_workqueue(il->workqueue);
3878
3879
3880
3881
3882 destroy_workqueue(il->workqueue);
3883 il->workqueue = NULL;
3884
3885 free_irq(pdev->irq, il);
3886 pci_disable_msi(pdev);
3887
3888 iounmap(il->hw_base);
3889 pci_release_regions(pdev);
3890 pci_disable_device(pdev);
3891 pci_set_drvdata(pdev, NULL);
3892
3893 il_free_channel_map(il);
3894 il_free_geos(il);
3895 kfree(il->scan_cmd);
3896 if (il->beacon_skb)
3897 dev_kfree_skb(il->beacon_skb);
3898
3899 ieee80211_free_hw(il->hw);
3900}
3901
3902
3903
3904
3905
3906
3907
3908static struct pci_driver il3945_driver = {
3909 .name = DRV_NAME,
3910 .id_table = il3945_hw_card_ids,
3911 .probe = il3945_pci_probe,
3912 .remove = il3945_pci_remove,
3913 .driver.pm = IL_LEGACY_PM_OPS,
3914};
3915
3916static int __init
3917il3945_init(void)
3918{
3919
3920 int ret;
3921 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3922 pr_info(DRV_COPYRIGHT "\n");
3923
3924 ret = il3945_rate_control_register();
3925 if (ret) {
3926 pr_err("Unable to register rate control algorithm: %d\n", ret);
3927 return ret;
3928 }
3929
3930 ret = pci_register_driver(&il3945_driver);
3931 if (ret) {
3932 pr_err("Unable to initialize PCI module\n");
3933 goto error_register;
3934 }
3935
3936 return ret;
3937
3938error_register:
3939 il3945_rate_control_unregister();
3940 return ret;
3941}
3942
3943static void __exit
3944il3945_exit(void)
3945{
3946 pci_unregister_driver(&il3945_driver);
3947 il3945_rate_control_unregister();
3948}
3949
3950MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
3951
3952module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
3953MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3954module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
3955MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3956module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3957 S_IRUGO);
3958MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
3959#ifdef CONFIG_IWLEGACY_DEBUG
3960module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
3961MODULE_PARM_DESC(debug, "debug output mask");
3962#endif
3963module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
3964MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3965
3966module_exit(il3945_exit);
3967module_init(il3945_init);
3968