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69#ifndef __iwl_commands_h__
70#define __iwl_commands_h__
71
72#include <linux/ieee80211.h>
73#include <linux/types.h>
74
75
76enum {
77 REPLY_ALIVE = 0x1,
78 REPLY_ERROR = 0x2,
79 REPLY_ECHO = 0x3,
80
81
82 REPLY_RXON = 0x10,
83 REPLY_RXON_ASSOC = 0x11,
84 REPLY_QOS_PARAM = 0x13,
85 REPLY_RXON_TIMING = 0x14,
86
87
88 REPLY_ADD_STA = 0x18,
89 REPLY_REMOVE_STA = 0x19,
90 REPLY_REMOVE_ALL_STA = 0x1a,
91 REPLY_TXFIFO_FLUSH = 0x1e,
92
93
94 REPLY_WEPKEY = 0x20,
95
96
97 REPLY_TX = 0x1c,
98 REPLY_LEDS_CMD = 0x48,
99 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
100
101
102 COEX_PRIORITY_TABLE_CMD = 0x5a,
103 COEX_MEDIUM_NOTIFICATION = 0x5b,
104 COEX_EVENT_CMD = 0x5c,
105
106
107 TEMPERATURE_NOTIFICATION = 0x62,
108 CALIBRATION_CFG_CMD = 0x65,
109 CALIBRATION_RES_NOTIFICATION = 0x66,
110 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
111
112
113 REPLY_QUIET_CMD = 0x71,
114 REPLY_CHANNEL_SWITCH = 0x72,
115 CHANNEL_SWITCH_NOTIFICATION = 0x73,
116 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
117 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
118
119
120 POWER_TABLE_CMD = 0x77,
121 PM_SLEEP_NOTIFICATION = 0x7A,
122 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
123
124
125 REPLY_SCAN_CMD = 0x80,
126 REPLY_SCAN_ABORT_CMD = 0x81,
127 SCAN_START_NOTIFICATION = 0x82,
128 SCAN_RESULTS_NOTIFICATION = 0x83,
129 SCAN_COMPLETE_NOTIFICATION = 0x84,
130
131
132 BEACON_NOTIFICATION = 0x90,
133 REPLY_TX_BEACON = 0x91,
134 WHO_IS_AWAKE_NOTIFICATION = 0x94,
135
136
137 REPLY_TX_POWER_DBM_CMD = 0x95,
138 QUIET_NOTIFICATION = 0x96,
139 REPLY_TX_PWR_TABLE_CMD = 0x97,
140 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
141 TX_ANT_CONFIGURATION_CMD = 0x98,
142 MEASURE_ABORT_NOTIFICATION = 0x99,
143
144
145 REPLY_BT_CONFIG = 0x9b,
146
147
148 REPLY_STATISTICS_CMD = 0x9c,
149 STATISTICS_NOTIFICATION = 0x9d,
150
151
152 REPLY_CARD_STATE_CMD = 0xa0,
153 CARD_STATE_NOTIFICATION = 0xa1,
154
155
156 MISSED_BEACONS_NOTIFICATION = 0xa2,
157
158 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
159 SENSITIVITY_CMD = 0xa8,
160 REPLY_PHY_CALIBRATION_CMD = 0xb0,
161 REPLY_RX_PHY_CMD = 0xc0,
162 REPLY_RX_MPDU_CMD = 0xc1,
163 REPLY_RX = 0xc3,
164 REPLY_COMPRESSED_BA = 0xc5,
165
166
167 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
168 REPLY_BT_COEX_PROT_ENV = 0xcd,
169 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
170
171
172 REPLY_WIPAN_PARAMS = 0xb2,
173 REPLY_WIPAN_RXON = 0xb3,
174 REPLY_WIPAN_RXON_TIMING = 0xb4,
175 REPLY_WIPAN_RXON_ASSOC = 0xb6,
176 REPLY_WIPAN_QOS_PARAM = 0xb7,
177 REPLY_WIPAN_WEPKEY = 0xb8,
178 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
179 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
180 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
181
182 REPLY_WOWLAN_PATTERNS = 0xe0,
183 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
184 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
185 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
186 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
187 REPLY_WOWLAN_GET_STATUS = 0xe5,
188 REPLY_D3_CONFIG = 0xd3,
189
190 REPLY_MAX = 0xff
191};
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200
201
202#define IWL_MIN_NUM_QUEUES 11
203
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206
207#define IWL_DEFAULT_CMD_QUEUE_NUM 4
208#define IWL_IPAN_CMD_QUEUE_NUM 9
209
210#define IWL_TX_FIFO_BK 0
211#define IWL_TX_FIFO_BE 1
212#define IWL_TX_FIFO_VI 2
213#define IWL_TX_FIFO_VO 3
214#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
215#define IWL_TX_FIFO_BE_IPAN 4
216#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
217#define IWL_TX_FIFO_VO_IPAN 5
218
219#define IWL_TX_FIFO_AUX 5
220#define IWL_TX_FIFO_UNUSED 255
221
222#define IWLAGN_CMD_FIFO_NUM 7
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228
229#define IWL_IPAN_MCAST_QUEUE 8
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279#define RATE_MCS_CODE_MSK 0x7
280#define RATE_MCS_SPATIAL_POS 3
281#define RATE_MCS_SPATIAL_MSK 0x18
282#define RATE_MCS_HT_DUP_POS 5
283#define RATE_MCS_HT_DUP_MSK 0x20
284
285#define RATE_MCS_RATE_MSK 0xff
286
287
288#define RATE_MCS_FLAGS_POS 8
289#define RATE_MCS_HT_POS 8
290#define RATE_MCS_HT_MSK 0x100
291
292
293#define RATE_MCS_CCK_POS 9
294#define RATE_MCS_CCK_MSK 0x200
295
296
297#define RATE_MCS_GF_POS 10
298#define RATE_MCS_GF_MSK 0x400
299
300
301#define RATE_MCS_HT40_POS 11
302#define RATE_MCS_HT40_MSK 0x800
303
304
305#define RATE_MCS_DUP_POS 12
306#define RATE_MCS_DUP_MSK 0x1000
307
308
309#define RATE_MCS_SGI_POS 13
310#define RATE_MCS_SGI_MSK 0x2000
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321#define RATE_MCS_ANT_POS 14
322#define RATE_MCS_ANT_A_MSK 0x04000
323#define RATE_MCS_ANT_B_MSK 0x08000
324#define RATE_MCS_ANT_C_MSK 0x10000
325#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
326#define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
327#define RATE_ANT_NUM 3
328
329#define POWER_TABLE_NUM_ENTRIES 33
330#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
331#define POWER_TABLE_CCK_ENTRY 32
332
333#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
334#define IWL_PWR_CCK_ENTRIES 2
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342
343struct tx_power_dual_stream {
344 __le32 dw;
345} __packed;
346
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349
350
351#define IWLAGN_TX_POWER_AUTO 0x7f
352#define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
353
354struct iwlagn_tx_power_dbm_cmd {
355 s8 global_lmt;
356 u8 flags;
357 s8 srv_chan_lmt;
358 u8 reserved;
359} __packed;
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367struct iwl_tx_ant_config_cmd {
368 __le32 valid;
369} __packed;
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376
377#define UCODE_VALID_OK cpu_to_le32(0x1)
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425struct iwl_error_event_table {
426 u32 valid;
427 u32 error_id;
428 u32 pc;
429 u32 blink1;
430 u32 blink2;
431 u32 ilink1;
432 u32 ilink2;
433 u32 data1;
434 u32 data2;
435 u32 line;
436 u32 bcon_time;
437 u32 tsf_low;
438 u32 tsf_hi;
439 u32 gp1;
440 u32 gp2;
441 u32 gp3;
442 u32 ucode_ver;
443 u32 hw_ver;
444 u32 brd_ver;
445 u32 log_pc;
446 u32 frame_ptr;
447 u32 stack_ptr;
448 u32 hcmd;
449 u32 isr0;
450
451 u32 isr1;
452
453 u32 isr2;
454
455 u32 isr3;
456
457 u32 isr4;
458
459 u32 isr_pref;
460 u32 wait_event;
461 u32 l2p_control;
462 u32 l2p_duration;
463 u32 l2p_mhvalid;
464 u32 l2p_addr_match;
465 u32 lmpm_pmg_sel;
466
467 u32 u_timestamp;
468
469 u32 flow_handler;
470} __packed;
471
472struct iwl_alive_resp {
473 u8 ucode_minor;
474 u8 ucode_major;
475 __le16 reserved1;
476 u8 sw_rev[8];
477 u8 ver_type;
478 u8 ver_subtype;
479 __le16 reserved2;
480 __le32 log_event_table_ptr;
481 __le32 error_event_table_ptr;
482 __le32 timestamp;
483 __le32 is_valid;
484} __packed;
485
486
487
488
489struct iwl_error_resp {
490 __le32 error_type;
491 u8 cmd_id;
492 u8 reserved1;
493 __le16 bad_cmd_seq_num;
494 __le32 error_info;
495 __le64 timestamp;
496} __packed;
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507
508enum {
509 RXON_DEV_TYPE_AP = 1,
510 RXON_DEV_TYPE_ESS = 3,
511 RXON_DEV_TYPE_IBSS = 4,
512 RXON_DEV_TYPE_SNIFFER = 6,
513 RXON_DEV_TYPE_CP = 7,
514 RXON_DEV_TYPE_2STA = 8,
515 RXON_DEV_TYPE_P2P = 9,
516};
517
518
519#define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
520#define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
521#define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
522#define RXON_RX_CHAIN_VALID_POS (1)
523#define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
524#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
525#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
526#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
527#define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
528#define RXON_RX_CHAIN_CNT_POS (10)
529#define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
530#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
531#define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
532#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
533
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535
536#define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
537#define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
538
539#define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
540
541#define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
542
543#define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
544#define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
545
546#define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
547#define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
548#define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
549#define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
550
551#define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
552#define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
553
554
555#define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
556
557
558
559#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
560#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
561
562#define RXON_FLG_HT_OPERATING_MODE_POS (23)
563
564#define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
565#define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
566
567#define RXON_FLG_CHANNEL_MODE_POS (25)
568#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
569
570
571enum {
572 CHANNEL_MODE_LEGACY = 0,
573 CHANNEL_MODE_PURE_40 = 1,
574 CHANNEL_MODE_MIXED = 2,
575 CHANNEL_MODE_RESERVED = 3,
576};
577#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
578#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
579#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
580
581
582#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
583
584
585
586#define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
587
588#define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
589
590#define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
591
592#define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
593
594#define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
595
596#define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
597
598#define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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618struct iwl_rxon_cmd {
619 u8 node_addr[6];
620 __le16 reserved1;
621 u8 bssid_addr[6];
622 __le16 reserved2;
623 u8 wlap_bssid_addr[6];
624 __le16 reserved3;
625 u8 dev_type;
626 u8 air_propagation;
627 __le16 rx_chain;
628 u8 ofdm_basic_rates;
629 u8 cck_basic_rates;
630 __le16 assoc_id;
631 __le32 flags;
632 __le32 filter_flags;
633 __le16 channel;
634 u8 ofdm_ht_single_stream_basic_rates;
635 u8 ofdm_ht_dual_stream_basic_rates;
636 u8 ofdm_ht_triple_stream_basic_rates;
637 u8 reserved5;
638 __le16 acquisition_data;
639 __le16 reserved6;
640} __packed;
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644
645struct iwl_rxon_assoc_cmd {
646 __le32 flags;
647 __le32 filter_flags;
648 u8 ofdm_basic_rates;
649 u8 cck_basic_rates;
650 __le16 reserved1;
651 u8 ofdm_ht_single_stream_basic_rates;
652 u8 ofdm_ht_dual_stream_basic_rates;
653 u8 ofdm_ht_triple_stream_basic_rates;
654 u8 reserved2;
655 __le16 rx_chain_select_flags;
656 __le16 acquisition_data;
657 __le32 reserved3;
658} __packed;
659
660#define IWL_CONN_MAX_LISTEN_INTERVAL 10
661#define IWL_MAX_UCODE_BEACON_INTERVAL 4
662
663
664
665
666struct iwl_rxon_time_cmd {
667 __le64 timestamp;
668 __le16 beacon_interval;
669 __le16 atim_window;
670 __le32 beacon_init_val;
671 __le16 listen_interval;
672 u8 dtim_period;
673 u8 delta_cp_bss_tbtts;
674} __packed;
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690struct iwl5000_channel_switch_cmd {
691 u8 band;
692 u8 expect_beacon;
693 __le16 channel;
694 __le32 rxon_flags;
695 __le32 rxon_filter_flags;
696 __le32 switch_time;
697 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
698} __packed;
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711struct iwl6000_channel_switch_cmd {
712 u8 band;
713 u8 expect_beacon;
714 __le16 channel;
715 __le32 rxon_flags;
716 __le32 rxon_filter_flags;
717 __le32 switch_time;
718 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
719} __packed;
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724struct iwl_csa_notification {
725 __le16 band;
726 __le16 channel;
727 __le32 status;
728} __packed;
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752struct iwl_ac_qos {
753 __le16 cw_min;
754 __le16 cw_max;
755 u8 aifsn;
756 u8 reserved1;
757 __le16 edca_txop;
758} __packed;
759
760
761#define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
762#define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
763#define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
764
765
766#define AC_NUM 4
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774struct iwl_qosparam_cmd {
775 __le32 qos_flags;
776 struct iwl_ac_qos ac[AC_NUM];
777} __packed;
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789#define IWL_AP_ID 0
790#define IWL_AP_ID_PAN 1
791#define IWL_STA_ID 2
792#define IWLAGN_PAN_BCAST_ID 14
793#define IWLAGN_BROADCAST_ID 15
794#define IWLAGN_STATION_COUNT 16
795
796#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
797
798#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
799#define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
800#define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
801#define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
802#define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
803#define STA_FLG_MAX_AGG_SIZE_POS (19)
804#define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
805#define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
806#define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
807#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
808#define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
809
810
811#define STA_CONTROL_MODIFY_MSK 0x01
812
813
814#define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
815#define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
816#define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
817#define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
818#define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
819
820#define STA_KEY_FLG_KEYID_POS 8
821#define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
822
823#define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
824
825
826#define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
827#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
828#define STA_KEY_MAX_NUM 8
829#define STA_KEY_MAX_NUM_PAN 16
830
831#define IWLAGN_HW_KEY_DEFAULT 0xfe
832
833
834#define STA_MODIFY_KEY_MASK 0x01
835#define STA_MODIFY_TID_DISABLE_TX 0x02
836#define STA_MODIFY_TX_RATE_MSK 0x04
837#define STA_MODIFY_ADDBA_TID_MSK 0x08
838#define STA_MODIFY_DELBA_TID_MSK 0x10
839#define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
840
841
842struct iwl_keyinfo {
843 __le16 key_flags;
844 u8 tkip_rx_tsc_byte2;
845 u8 reserved1;
846 __le16 tkip_rx_ttak[5];
847 u8 key_offset;
848 u8 reserved2;
849 u8 key[16];
850 __le64 tx_secur_seq_cnt;
851 __le64 hw_tkip_mic_rx_key;
852 __le64 hw_tkip_mic_tx_key;
853} __packed;
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867struct sta_id_modify {
868 u8 addr[ETH_ALEN];
869 __le16 reserved1;
870 u8 sta_id;
871 u8 modify_mask;
872 __le16 reserved2;
873} __packed;
874
875
876
877
878
879
880
881
882
883
884
885
886
887
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889
890
891
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894
895
896
897
898
899
900
901struct iwl_addsta_cmd {
902 u8 mode;
903 u8 reserved[3];
904 struct sta_id_modify sta;
905 struct iwl_keyinfo key;
906 __le32 station_flags;
907 __le32 station_flags_msk;
908
909
910
911
912 __le16 tid_disable_tx;
913 __le16 legacy_reserved;
914
915
916
917 u8 add_immediate_ba_tid;
918
919
920
921 u8 remove_immediate_ba_tid;
922
923
924
925 __le16 add_immediate_ba_ssn;
926
927
928
929
930
931
932 __le16 sleep_tx_count;
933
934 __le16 reserved2;
935} __packed;
936
937
938#define ADD_STA_SUCCESS_MSK 0x1
939#define ADD_STA_NO_ROOM_IN_TABLE 0x2
940#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
941#define ADD_STA_MODIFY_NON_EXIST_STA 0x8
942
943
944
945struct iwl_add_sta_resp {
946 u8 status;
947} __packed;
948
949#define REM_STA_SUCCESS_MSK 0x1
950
951
952
953struct iwl_rem_sta_resp {
954 u8 status;
955} __packed;
956
957
958
959
960struct iwl_rem_sta_cmd {
961 u8 num_sta;
962 u8 reserved[3];
963 u8 addr[ETH_ALEN];
964 u8 reserved2[2];
965} __packed;
966
967
968
969#define IWL_SCD_BK_MSK cpu_to_le32(BIT(0))
970#define IWL_SCD_BE_MSK cpu_to_le32(BIT(1))
971#define IWL_SCD_VI_MSK cpu_to_le32(BIT(2))
972#define IWL_SCD_VO_MSK cpu_to_le32(BIT(3))
973#define IWL_SCD_MGMT_MSK cpu_to_le32(BIT(3))
974
975
976#define IWL_PAN_SCD_BK_MSK cpu_to_le32(BIT(4))
977#define IWL_PAN_SCD_BE_MSK cpu_to_le32(BIT(5))
978#define IWL_PAN_SCD_VI_MSK cpu_to_le32(BIT(6))
979#define IWL_PAN_SCD_VO_MSK cpu_to_le32(BIT(7))
980#define IWL_PAN_SCD_MGMT_MSK cpu_to_le32(BIT(7))
981#define IWL_PAN_SCD_MULTICAST_MSK cpu_to_le32(BIT(8))
982
983#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
984
985#define IWL_DROP_ALL BIT(1)
986
987
988
989
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995
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1007
1008struct iwl_txfifo_flush_cmd {
1009 __le32 queue_control;
1010 __le16 flush_control;
1011 __le16 reserved;
1012} __packed;
1013
1014
1015
1016
1017struct iwl_wep_key {
1018 u8 key_index;
1019 u8 key_offset;
1020 u8 reserved1[2];
1021 u8 key_size;
1022 u8 reserved2[3];
1023 u8 key[16];
1024} __packed;
1025
1026struct iwl_wep_cmd {
1027 u8 num_keys;
1028 u8 global_key_type;
1029 u8 flags;
1030 u8 reserved;
1031 struct iwl_wep_key key[0];
1032} __packed;
1033
1034#define WEP_KEY_WEP_TYPE 1
1035#define WEP_KEYS_MAX 4
1036#define WEP_INVALID_OFFSET 0xff
1037#define WEP_KEY_LEN_64 5
1038#define WEP_KEY_LEN_128 13
1039
1040
1041
1042
1043
1044
1045
1046#define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1047#define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1048
1049#define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1050#define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1051#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1052#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1053#define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1054#define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1055#define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1056
1057#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1058#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1059#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1060#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1061#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1062#define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1063
1064#define RX_RES_STATUS_STATION_FOUND (1<<6)
1065#define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1066
1067#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1068#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1069#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1070#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1071#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1072
1073#define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1074#define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1075#define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1076#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1077
1078
1079#define IWLAGN_RX_RES_PHY_CNT 8
1080#define IWLAGN_RX_RES_AGC_IDX 1
1081#define IWLAGN_RX_RES_RSSI_AB_IDX 2
1082#define IWLAGN_RX_RES_RSSI_C_IDX 3
1083#define IWLAGN_OFDM_AGC_MSK 0xfe00
1084#define IWLAGN_OFDM_AGC_BIT_POS 9
1085#define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1086#define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1087#define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1088#define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1089#define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1090#define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1091#define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1092#define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1093#define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1094
1095struct iwlagn_non_cfg_phy {
1096 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1097} __packed;
1098
1099
1100
1101
1102
1103
1104struct iwl_rx_phy_res {
1105 u8 non_cfg_phy_cnt;
1106 u8 cfg_phy_cnt;
1107 u8 stat_id;
1108 u8 reserved1;
1109 __le64 timestamp;
1110 __le32 beacon_time_stamp;
1111 __le16 phy_flags;
1112 __le16 channel;
1113 u8 non_cfg_phy_buf[32];
1114 __le32 rate_n_flags;
1115 __le16 byte_count;
1116 __le16 frame_time;
1117} __packed;
1118
1119struct iwl_rx_mpdu_res_start {
1120 __le16 byte_count;
1121 __le16 reserved;
1122} __packed;
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
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1134
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1150
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1152
1153
1154
1155
1156#define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1157
1158
1159
1160
1161#define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1162
1163
1164
1165
1166
1167
1168
1169#define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1170
1171
1172
1173#define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1174
1175
1176#define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1177
1178
1179
1180#define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1181
1182
1183
1184
1185
1186#define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1187
1188
1189
1190#define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1191
1192
1193
1194
1195#define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1196
1197
1198
1199
1200
1201
1202
1203#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1204
1205
1206
1207#define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1208
1209
1210#define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1211
1212
1213
1214
1215
1216#define TX_CMD_SEC_WEP 0x01
1217#define TX_CMD_SEC_CCM 0x02
1218#define TX_CMD_SEC_TKIP 0x03
1219#define TX_CMD_SEC_MSK 0x03
1220#define TX_CMD_SEC_SHIFT 6
1221#define TX_CMD_SEC_KEY128 0x08
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232struct iwl_dram_scratch {
1233 u8 try_cnt;
1234 u8 bt_kill_cnt;
1235 __le16 reserved;
1236} __packed;
1237
1238struct iwl_tx_cmd {
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249 __le16 len;
1250
1251
1252
1253
1254
1255
1256 __le16 next_frame_len;
1257
1258 __le32 tx_flags;
1259
1260
1261
1262 struct iwl_dram_scratch scratch;
1263
1264
1265 __le32 rate_n_flags;
1266
1267
1268 u8 sta_id;
1269
1270
1271 u8 sec_ctl;
1272
1273
1274
1275
1276
1277
1278
1279
1280 u8 initial_rate_index;
1281 u8 reserved;
1282 u8 key[16];
1283 __le16 next_frame_flags;
1284 __le16 reserved2;
1285 union {
1286 __le32 life_time;
1287 __le32 attempt;
1288 } stop_time;
1289
1290
1291
1292 __le32 dram_lsb_ptr;
1293 u8 dram_msb_ptr;
1294
1295 u8 rts_retry_limit;
1296 u8 data_retry_limit;
1297 u8 tid_tspec;
1298 union {
1299 __le16 pm_frame_timeout;
1300 __le16 attempt_duration;
1301 } timeout;
1302
1303
1304
1305
1306
1307 __le16 driver_txop;
1308
1309
1310
1311
1312
1313 u8 payload[0];
1314 struct ieee80211_hdr hdr[0];
1315} __packed;
1316
1317
1318
1319
1320
1321
1322
1323
1324enum {
1325 TX_STATUS_SUCCESS = 0x01,
1326 TX_STATUS_DIRECT_DONE = 0x02,
1327
1328 TX_STATUS_POSTPONE_DELAY = 0x40,
1329 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1330 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1331 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1332 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1333
1334 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1335 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1336 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1337 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1338 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1339 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1340 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1341 TX_STATUS_FAIL_DEST_PS = 0x88,
1342 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1343 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1344 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1345 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1346 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1347 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1348 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1349 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1350 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1351};
1352
1353#define TX_PACKET_MODE_REGULAR 0x0000
1354#define TX_PACKET_MODE_BURST_SEQ 0x0100
1355#define TX_PACKET_MODE_BURST_FIRST 0x0200
1356
1357enum {
1358 TX_POWER_PA_NOT_ACTIVE = 0x0,
1359};
1360
1361enum {
1362 TX_STATUS_MSK = 0x000000ff,
1363 TX_STATUS_DELAY_MSK = 0x00000040,
1364 TX_STATUS_ABORT_MSK = 0x00000080,
1365 TX_PACKET_MODE_MSK = 0x0000ff00,
1366 TX_FIFO_NUMBER_MSK = 0x00070000,
1367 TX_RESERVED = 0x00780000,
1368 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1369 TX_ABORT_REQUIRED_MSK = 0x80000000,
1370};
1371
1372
1373
1374
1375
1376enum {
1377 AGG_TX_STATE_TRANSMITTED = 0x00,
1378 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1379 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1380 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1381 AGG_TX_STATE_ABORT_MSK = 0x08,
1382 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1383 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1384 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1385 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1386 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1387 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1388 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1389 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1390};
1391
1392#define AGG_TX_STATUS_MSK 0x00000fff
1393#define AGG_TX_TRY_MSK 0x0000f000
1394#define AGG_TX_TRY_POS 12
1395
1396#define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1397 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1398 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1399
1400
1401#define AGG_TX_STATE_TRY_CNT_POS 12
1402#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1403
1404
1405#define AGG_TX_STATE_SEQ_NUM_POS 16
1406#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1407
1408
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1429
1430struct agg_tx_status {
1431 __le16 status;
1432 __le16 sequence;
1433} __packed;
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445#define IWL50_TX_RES_INIT_RATE_INDEX_POS 0
1446#define IWL50_TX_RES_INIT_RATE_INDEX_MSK 0x0f
1447#define IWL50_TX_RES_RATE_TABLE_COLOR_POS 4
1448#define IWL50_TX_RES_RATE_TABLE_COLOR_MSK 0x70
1449#define IWL50_TX_RES_INV_RATE_INDEX_MSK 0x80
1450
1451
1452#define IWLAGN_TX_RES_TID_POS 0
1453#define IWLAGN_TX_RES_TID_MSK 0x0f
1454#define IWLAGN_TX_RES_RA_POS 4
1455#define IWLAGN_TX_RES_RA_MSK 0xf0
1456
1457struct iwlagn_tx_resp {
1458 u8 frame_count;
1459 u8 bt_kill_count;
1460 u8 failure_rts;
1461 u8 failure_frame;
1462
1463
1464
1465 __le32 rate_n_flags;
1466
1467
1468
1469 __le16 wireless_media_time;
1470
1471 u8 pa_status;
1472 u8 pa_integ_res_a[3];
1473 u8 pa_integ_res_b[3];
1474 u8 pa_integ_res_C[3];
1475
1476 __le32 tfd_info;
1477 __le16 seq_ctl;
1478 __le16 byte_cnt;
1479 u8 tlc_info;
1480 u8 ra_tid;
1481 __le16 frame_ctrl;
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495 struct agg_tx_status status;
1496
1497} __packed;
1498
1499
1500
1501
1502
1503struct iwl_compressed_ba_resp {
1504 __le32 sta_addr_lo32;
1505 __le16 sta_addr_hi16;
1506 __le16 reserved;
1507
1508
1509 u8 sta_id;
1510 u8 tid;
1511 __le16 seq_ctl;
1512 __le64 bitmap;
1513 __le16 scd_flow;
1514 __le16 scd_ssn;
1515 u8 txed;
1516 u8 txed_2_done;
1517 __le16 reserved1;
1518} __packed;
1519
1520
1521
1522
1523
1524
1525
1526#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1527
1528
1529#define LINK_QUAL_AC_NUM AC_NUM
1530
1531
1532#define LINK_QUAL_MAX_RETRY_NUM 16
1533
1534
1535#define LINK_QUAL_ANT_A_MSK (1 << 0)
1536#define LINK_QUAL_ANT_B_MSK (1 << 1)
1537#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1538
1539
1540
1541
1542
1543
1544
1545struct iwl_link_qual_general_params {
1546 u8 flags;
1547
1548
1549 u8 mimo_delimiter;
1550
1551
1552 u8 single_stream_ant_msk;
1553
1554
1555 u8 dual_stream_ant_msk;
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568 u8 start_rate_index[LINK_QUAL_AC_NUM];
1569} __packed;
1570
1571#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1572#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1573#define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1574
1575#define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1576#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1577#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1578
1579#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1580#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1581#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1582
1583
1584
1585
1586
1587
1588struct iwl_link_qual_agg_params {
1589
1590
1591
1592
1593
1594 __le16 agg_time_limit;
1595
1596
1597
1598
1599
1600
1601
1602 u8 agg_dis_start_th;
1603
1604
1605
1606
1607
1608
1609 u8 agg_frame_cnt_limit;
1610
1611 __le32 reserved;
1612} __packed;
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1800
1801
1802struct iwl_link_quality_cmd {
1803
1804
1805 u8 sta_id;
1806 u8 reserved1;
1807 __le16 control;
1808 struct iwl_link_qual_general_params general_params;
1809 struct iwl_link_qual_agg_params agg_params;
1810
1811
1812
1813
1814
1815
1816 struct {
1817 __le32 rate_n_flags;
1818 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1819 __le32 reserved2;
1820} __packed;
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831#define BT_COEX_DISABLE (0x0)
1832#define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1833#define BT_ENABLE_PRIORITY BIT(1)
1834#define BT_ENABLE_2_WIRE BIT(2)
1835
1836#define BT_COEX_DISABLE (0x0)
1837#define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1838
1839#define BT_LEAD_TIME_MIN (0x0)
1840#define BT_LEAD_TIME_DEF (0x1E)
1841#define BT_LEAD_TIME_MAX (0xFF)
1842
1843#define BT_MAX_KILL_MIN (0x1)
1844#define BT_MAX_KILL_DEF (0x5)
1845#define BT_MAX_KILL_MAX (0xFF)
1846
1847#define BT_DURATION_LIMIT_DEF 625
1848#define BT_DURATION_LIMIT_MAX 1250
1849#define BT_DURATION_LIMIT_MIN 625
1850
1851#define BT_ON_THRESHOLD_DEF 4
1852#define BT_ON_THRESHOLD_MAX 1000
1853#define BT_ON_THRESHOLD_MIN 1
1854
1855#define BT_FRAG_THRESHOLD_DEF 0
1856#define BT_FRAG_THRESHOLD_MAX 0
1857#define BT_FRAG_THRESHOLD_MIN 0
1858
1859#define BT_AGG_THRESHOLD_DEF 1200
1860#define BT_AGG_THRESHOLD_MAX 8000
1861#define BT_AGG_THRESHOLD_MIN 400
1862
1863
1864
1865
1866
1867
1868
1869
1870struct iwl_bt_cmd {
1871 u8 flags;
1872 u8 lead_time;
1873 u8 max_kill;
1874 u8 reserved;
1875 __le32 kill_ack_mask;
1876 __le32 kill_cts_mask;
1877} __packed;
1878
1879#define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1880
1881#define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1882#define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1883#define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1884#define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1885#define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1886#define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1887
1888#define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1889
1890#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1891
1892#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1893#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1894
1895#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1896#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1897#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1898#define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1899
1900#define IWLAGN_BT_MAX_KILL_DEFAULT 5
1901
1902#define IWLAGN_BT3_T7_DEFAULT 1
1903
1904enum iwl_bt_kill_idx {
1905 IWL_BT_KILL_DEFAULT = 0,
1906 IWL_BT_KILL_OVERRIDE = 1,
1907 IWL_BT_KILL_REDUCE = 2,
1908};
1909
1910#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1911#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1912#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1913#define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1914
1915#define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1916
1917#define IWLAGN_BT3_T2_DEFAULT 0xc
1918
1919#define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1920#define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1921#define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1922#define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1923#define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1924#define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1925#define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1926#define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1927
1928#define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1929 IWLAGN_BT_VALID_BOOST | \
1930 IWLAGN_BT_VALID_MAX_KILL | \
1931 IWLAGN_BT_VALID_3W_TIMERS | \
1932 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1933 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1934 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1935 IWLAGN_BT_VALID_3W_LUT)
1936
1937#define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1938
1939#define IWLAGN_BT_DECISION_LUT_SIZE 12
1940
1941struct iwl_basic_bt_cmd {
1942 u8 flags;
1943 u8 ledtime;
1944 u8 max_kill;
1945 u8 bt3_timer_t7_value;
1946 __le32 kill_ack_mask;
1947 __le32 kill_cts_mask;
1948 u8 bt3_prio_sample_time;
1949 u8 bt3_timer_t2_value;
1950 __le16 bt4_reaction_time;
1951 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1952
1953
1954
1955
1956 u8 reduce_txpower;
1957 u8 reserved;
1958 __le16 valid;
1959};
1960
1961struct iwl_bt_cmd_v1 {
1962 struct iwl_basic_bt_cmd basic;
1963 u8 prio_boost;
1964
1965
1966
1967
1968 u8 tx_prio_boost;
1969 __le16 rx_prio_boost;
1970};
1971
1972struct iwl_bt_cmd_v2 {
1973 struct iwl_basic_bt_cmd basic;
1974 __le32 prio_boost;
1975
1976
1977
1978
1979 u8 reserved;
1980 u8 tx_prio_boost;
1981 __le16 rx_prio_boost;
1982};
1983
1984#define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1985
1986struct iwlagn_bt_sco_cmd {
1987 __le32 flags;
1988};
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
2000 RXON_FILTER_CTL2HOST_MSK | \
2001 RXON_FILTER_ACCEPT_GRP_MSK | \
2002 RXON_FILTER_DIS_DECRYPT_MSK | \
2003 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
2004 RXON_FILTER_ASSOC_MSK | \
2005 RXON_FILTER_BCON_AWARE_MSK)
2006
2007struct iwl_measure_channel {
2008 __le32 duration;
2009
2010 u8 channel;
2011 u8 type;
2012 __le16 reserved;
2013} __packed;
2014
2015
2016
2017
2018struct iwl_spectrum_cmd {
2019 __le16 len;
2020 u8 token;
2021 u8 id;
2022 u8 origin;
2023 u8 periodic;
2024 __le16 path_loss_timeout;
2025 __le32 start_time;
2026 __le32 reserved2;
2027 __le32 flags;
2028 __le32 filter_flags;
2029 __le16 channel_count;
2030 __le16 reserved3;
2031 struct iwl_measure_channel channels[10];
2032} __packed;
2033
2034
2035
2036
2037struct iwl_spectrum_resp {
2038 u8 token;
2039 u8 id;
2040 __le16 status;
2041
2042
2043} __packed;
2044
2045enum iwl_measurement_state {
2046 IWL_MEASUREMENT_START = 0,
2047 IWL_MEASUREMENT_STOP = 1,
2048};
2049
2050enum iwl_measurement_status {
2051 IWL_MEASUREMENT_OK = 0,
2052 IWL_MEASUREMENT_CONCURRENT = 1,
2053 IWL_MEASUREMENT_CSA_CONFLICT = 2,
2054 IWL_MEASUREMENT_TGH_CONFLICT = 3,
2055
2056 IWL_MEASUREMENT_STOPPED = 6,
2057 IWL_MEASUREMENT_TIMEOUT = 7,
2058 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
2059};
2060
2061#define NUM_ELEMENTS_IN_HISTOGRAM 8
2062
2063struct iwl_measurement_histogram {
2064 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
2065 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
2066} __packed;
2067
2068
2069struct iwl_measurement_cca_counters {
2070 __le32 ofdm;
2071 __le32 cck;
2072} __packed;
2073
2074enum iwl_measure_type {
2075 IWL_MEASURE_BASIC = (1 << 0),
2076 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2077 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2078 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2079 IWL_MEASURE_FRAME = (1 << 4),
2080
2081 IWL_MEASURE_IDLE = (1 << 7),
2082};
2083
2084
2085
2086
2087struct iwl_spectrum_notification {
2088 u8 id;
2089 u8 token;
2090 u8 channel_index;
2091 u8 state;
2092 __le32 start_time;
2093 u8 band;
2094 u8 channel;
2095 u8 type;
2096 u8 reserved1;
2097
2098
2099 __le32 cca_ofdm;
2100 __le32 cca_cck;
2101 __le32 cca_time;
2102 u8 basic_type;
2103
2104 u8 reserved2[3];
2105 struct iwl_measurement_histogram histogram;
2106 __le32 stop_time;
2107 __le32 status;
2108} __packed;
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151#define IWL_POWER_VEC_SIZE 5
2152
2153#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2154#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2155#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2156#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2157#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2158#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2159#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2160#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2161#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2162#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2163#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2164
2165struct iwl_powertable_cmd {
2166 __le16 flags;
2167 u8 keep_alive_seconds;
2168 u8 debug_flags;
2169 __le32 rx_data_timeout;
2170 __le32 tx_data_timeout;
2171 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2172 __le32 keep_alive_beacons;
2173} __packed;
2174
2175
2176
2177
2178
2179struct iwl_sleep_notification {
2180 u8 pm_sleep_mode;
2181 u8 pm_wakeup_src;
2182 __le16 reserved;
2183 __le32 sleep_time;
2184 __le32 tsf_low;
2185 __le32 bcon_timer;
2186} __packed;
2187
2188
2189enum {
2190 IWL_PM_NO_SLEEP = 0,
2191 IWL_PM_SLP_MAC = 1,
2192 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2193 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2194 IWL_PM_SLP_PHY = 4,
2195 IWL_PM_SLP_REPENT = 5,
2196 IWL_PM_WAKEUP_BY_TIMER = 6,
2197 IWL_PM_WAKEUP_BY_DRIVER = 7,
2198 IWL_PM_WAKEUP_BY_RFKILL = 8,
2199
2200 IWL_PM_NUM_OF_MODES = 12,
2201};
2202
2203
2204
2205
2206#define CARD_STATE_CMD_DISABLE 0x00
2207#define CARD_STATE_CMD_ENABLE 0x01
2208#define CARD_STATE_CMD_HALT 0x02
2209struct iwl_card_state_cmd {
2210 __le32 status;
2211} __packed;
2212
2213
2214
2215
2216struct iwl_card_state_notif {
2217 __le32 flags;
2218} __packed;
2219
2220#define HW_CARD_DISABLED 0x01
2221#define SW_CARD_DISABLED 0x02
2222#define CT_CARD_DISABLED 0x04
2223#define RXON_CARD_DISABLED 0x10
2224
2225struct iwl_ct_kill_config {
2226 __le32 reserved;
2227 __le32 critical_temperature_M;
2228 __le32 critical_temperature_R;
2229} __packed;
2230
2231
2232struct iwl_ct_kill_throttling_config {
2233 __le32 critical_temperature_exit;
2234 __le32 reserved;
2235 __le32 critical_temperature_enter;
2236} __packed;
2237
2238
2239
2240
2241
2242
2243
2244#define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2245#define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267struct iwl_scan_channel {
2268
2269
2270
2271
2272
2273
2274
2275 __le32 type;
2276 __le16 channel;
2277 u8 tx_gain;
2278 u8 dsp_atten;
2279 __le16 active_dwell;
2280 __le16 passive_dwell;
2281} __packed;
2282
2283
2284#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294struct iwl_ssid_ie {
2295 u8 id;
2296 u8 len;
2297 u8 ssid[32];
2298} __packed;
2299
2300#define PROBE_OPTION_MAX 20
2301#define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2302#define IWL_GOOD_CRC_TH_DISABLED 0
2303#define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2304#define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2305#define IWL_MAX_CMD_SIZE 4096
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360enum iwl_scan_flags {
2361
2362 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2363
2364};
2365
2366struct iwl_scan_cmd {
2367 __le16 len;
2368 u8 scan_flags;
2369 u8 channel_count;
2370 __le16 quiet_time;
2371
2372 __le16 quiet_plcp_th;
2373 __le16 good_CRC_th;
2374 __le16 rx_chain;
2375 __le32 max_out_time;
2376
2377 __le32 suspend_time;
2378
2379
2380 __le32 flags;
2381 __le32 filter_flags;
2382
2383
2384
2385 struct iwl_tx_cmd tx_cmd;
2386
2387
2388 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405 u8 data[0];
2406} __packed;
2407
2408
2409#define CAN_ABORT_STATUS cpu_to_le32(0x1)
2410
2411#define ABORT_STATUS 0x2
2412
2413
2414
2415
2416struct iwl_scanreq_notification {
2417 __le32 status;
2418} __packed;
2419
2420
2421
2422
2423struct iwl_scanstart_notification {
2424 __le32 tsf_low;
2425 __le32 tsf_high;
2426 __le32 beacon_timer;
2427 u8 channel;
2428 u8 band;
2429 u8 reserved[2];
2430 __le32 status;
2431} __packed;
2432
2433#define SCAN_OWNER_STATUS 0x1
2434#define MEASURE_OWNER_STATUS 0x2
2435
2436#define IWL_PROBE_STATUS_OK 0
2437#define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2438
2439#define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2440#define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2441
2442#define NUMBER_OF_STATISTICS 1
2443
2444
2445
2446struct iwl_scanresults_notification {
2447 u8 channel;
2448 u8 band;
2449 u8 probe_status;
2450 u8 num_probe_not_sent;
2451 __le32 tsf_low;
2452 __le32 tsf_high;
2453 __le32 statistics[NUMBER_OF_STATISTICS];
2454} __packed;
2455
2456
2457
2458
2459struct iwl_scancomplete_notification {
2460 u8 scanned_channels;
2461 u8 status;
2462 u8 bt_status;
2463 u8 last_channel;
2464 __le32 tsf_low;
2465 __le32 tsf_high;
2466} __packed;
2467
2468
2469
2470
2471
2472
2473
2474
2475enum iwl_ibss_manager {
2476 IWL_NOT_IBSS_MANAGER = 0,
2477 IWL_IBSS_MANAGER = 1,
2478};
2479
2480
2481
2482
2483
2484struct iwlagn_beacon_notif {
2485 struct iwlagn_tx_resp beacon_notify_hdr;
2486 __le32 low_tsf;
2487 __le32 high_tsf;
2488 __le32 ibss_mgr_status;
2489} __packed;
2490
2491
2492
2493
2494
2495struct iwl_tx_beacon_cmd {
2496 struct iwl_tx_cmd tx;
2497 __le16 tim_idx;
2498 u8 tim_size;
2499 u8 reserved1;
2500 struct ieee80211_hdr frame[0];
2501} __packed;
2502
2503
2504
2505
2506
2507
2508
2509#define IWL_TEMP_CONVERT 260
2510
2511#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2512#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2513#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2514
2515
2516struct rate_histogram {
2517 union {
2518 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2519 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2520 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2521 } success;
2522 union {
2523 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2524 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2525 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2526 } failed;
2527} __packed;
2528
2529
2530
2531struct statistics_dbg {
2532 __le32 burst_check;
2533 __le32 burst_count;
2534 __le32 wait_for_silence_timeout_cnt;
2535 __le32 reserved[3];
2536} __packed;
2537
2538struct statistics_rx_phy {
2539 __le32 ina_cnt;
2540 __le32 fina_cnt;
2541 __le32 plcp_err;
2542 __le32 crc32_err;
2543 __le32 overrun_err;
2544 __le32 early_overrun_err;
2545 __le32 crc32_good;
2546 __le32 false_alarm_cnt;
2547 __le32 fina_sync_err_cnt;
2548 __le32 sfd_timeout;
2549 __le32 fina_timeout;
2550 __le32 unresponded_rts;
2551 __le32 rxe_frame_limit_overrun;
2552 __le32 sent_ack_cnt;
2553 __le32 sent_cts_cnt;
2554 __le32 sent_ba_rsp_cnt;
2555 __le32 dsp_self_kill;
2556 __le32 mh_format_err;
2557 __le32 re_acq_main_rssi_sum;
2558 __le32 reserved3;
2559} __packed;
2560
2561struct statistics_rx_ht_phy {
2562 __le32 plcp_err;
2563 __le32 overrun_err;
2564 __le32 early_overrun_err;
2565 __le32 crc32_good;
2566 __le32 crc32_err;
2567 __le32 mh_format_err;
2568 __le32 agg_crc32_good;
2569 __le32 agg_mpdu_cnt;
2570 __le32 agg_cnt;
2571 __le32 unsupport_mcs;
2572} __packed;
2573
2574#define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2575
2576struct statistics_rx_non_phy {
2577 __le32 bogus_cts;
2578 __le32 bogus_ack;
2579 __le32 non_bssid_frames;
2580
2581 __le32 filtered_frames;
2582
2583 __le32 non_channel_beacons;
2584
2585 __le32 channel_beacons;
2586
2587 __le32 num_missed_bcon;
2588 __le32 adc_rx_saturation_time;
2589
2590 __le32 ina_detection_search_time;
2591
2592 __le32 beacon_silence_rssi_a;
2593 __le32 beacon_silence_rssi_b;
2594 __le32 beacon_silence_rssi_c;
2595 __le32 interference_data_flag;
2596
2597
2598 __le32 channel_load;
2599 __le32 dsp_false_alarms;
2600
2601 __le32 beacon_rssi_a;
2602 __le32 beacon_rssi_b;
2603 __le32 beacon_rssi_c;
2604 __le32 beacon_energy_a;
2605 __le32 beacon_energy_b;
2606 __le32 beacon_energy_c;
2607} __packed;
2608
2609struct statistics_rx_non_phy_bt {
2610 struct statistics_rx_non_phy common;
2611
2612 __le32 num_bt_kills;
2613 __le32 reserved[2];
2614} __packed;
2615
2616struct statistics_rx {
2617 struct statistics_rx_phy ofdm;
2618 struct statistics_rx_phy cck;
2619 struct statistics_rx_non_phy general;
2620 struct statistics_rx_ht_phy ofdm_ht;
2621} __packed;
2622
2623struct statistics_rx_bt {
2624 struct statistics_rx_phy ofdm;
2625 struct statistics_rx_phy cck;
2626 struct statistics_rx_non_phy_bt general;
2627 struct statistics_rx_ht_phy ofdm_ht;
2628} __packed;
2629
2630
2631
2632
2633
2634
2635
2636
2637struct statistics_tx_power {
2638 u8 ant_a;
2639 u8 ant_b;
2640 u8 ant_c;
2641 u8 reserved;
2642} __packed;
2643
2644struct statistics_tx_non_phy_agg {
2645 __le32 ba_timeout;
2646 __le32 ba_reschedule_frames;
2647 __le32 scd_query_agg_frame_cnt;
2648 __le32 scd_query_no_agg;
2649 __le32 scd_query_agg;
2650 __le32 scd_query_mismatch;
2651 __le32 frame_not_ready;
2652 __le32 underrun;
2653 __le32 bt_prio_kill;
2654 __le32 rx_ba_rsp_cnt;
2655} __packed;
2656
2657struct statistics_tx {
2658 __le32 preamble_cnt;
2659 __le32 rx_detected_cnt;
2660 __le32 bt_prio_defer_cnt;
2661 __le32 bt_prio_kill_cnt;
2662 __le32 few_bytes_cnt;
2663 __le32 cts_timeout;
2664 __le32 ack_timeout;
2665 __le32 expected_ack_cnt;
2666 __le32 actual_ack_cnt;
2667 __le32 dump_msdu_cnt;
2668 __le32 burst_abort_next_frame_mismatch_cnt;
2669 __le32 burst_abort_missing_next_frame_cnt;
2670 __le32 cts_timeout_collision;
2671 __le32 ack_or_ba_timeout_collision;
2672 struct statistics_tx_non_phy_agg agg;
2673
2674
2675
2676
2677
2678 struct statistics_tx_power tx_power;
2679 __le32 reserved1;
2680} __packed;
2681
2682
2683struct statistics_div {
2684 __le32 tx_on_a;
2685 __le32 tx_on_b;
2686 __le32 exec_time;
2687 __le32 probe_time;
2688 __le32 reserved1;
2689 __le32 reserved2;
2690} __packed;
2691
2692struct statistics_general_common {
2693 __le32 temperature;
2694 __le32 temperature_m;
2695 struct statistics_dbg dbg;
2696 __le32 sleep_time;
2697 __le32 slots_out;
2698 __le32 slots_idle;
2699 __le32 ttl_timestamp;
2700 struct statistics_div div;
2701 __le32 rx_enable_counter;
2702
2703
2704
2705
2706
2707 __le32 num_of_sos_states;
2708} __packed;
2709
2710struct statistics_bt_activity {
2711
2712 __le32 hi_priority_tx_req_cnt;
2713 __le32 hi_priority_tx_denied_cnt;
2714 __le32 lo_priority_tx_req_cnt;
2715 __le32 lo_priority_tx_denied_cnt;
2716
2717 __le32 hi_priority_rx_req_cnt;
2718 __le32 hi_priority_rx_denied_cnt;
2719 __le32 lo_priority_rx_req_cnt;
2720 __le32 lo_priority_rx_denied_cnt;
2721} __packed;
2722
2723struct statistics_general {
2724 struct statistics_general_common common;
2725 __le32 reserved2;
2726 __le32 reserved3;
2727} __packed;
2728
2729struct statistics_general_bt {
2730 struct statistics_general_common common;
2731 struct statistics_bt_activity activity;
2732 __le32 reserved2;
2733 __le32 reserved3;
2734} __packed;
2735
2736#define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2737#define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2738#define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755#define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2756#define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2757struct iwl_statistics_cmd {
2758 __le32 configuration_flags;
2759} __packed;
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2777#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2778
2779struct iwl_notif_statistics {
2780 __le32 flag;
2781 struct statistics_rx rx;
2782 struct statistics_tx tx;
2783 struct statistics_general general;
2784} __packed;
2785
2786struct iwl_bt_notif_statistics {
2787 __le32 flag;
2788 struct statistics_rx_bt rx;
2789 struct statistics_tx tx;
2790 struct statistics_general_bt general;
2791} __packed;
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813#define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2814#define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2815#define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2816
2817struct iwl_missed_beacon_notif {
2818 __le32 consecutive_missed_beacons;
2819 __le32 total_missed_becons;
2820 __le32 num_expected_beacons;
2821 __le32 num_recvd_beacons;
2822} __packed;
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
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2867
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2872
2873
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2883
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2893
2894
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2896
2897
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2900
2901
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2903
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2913
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2952
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2959
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2966
2967
2968
2969
2970
2971
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2973
2974
2975
2976
2977
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2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997#define HD_TABLE_SIZE (11)
2998#define HD_MIN_ENERGY_CCK_DET_INDEX (0)
2999#define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
3000#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
3001#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
3002#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
3003#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
3004#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
3005#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
3006#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
3007#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
3008#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
3009
3010
3011
3012
3013#define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
3014#define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
3015#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
3016#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
3017#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
3018#define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
3019#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
3020#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
3021#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3022#define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3023#define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3024#define HD_RESERVED (22)
3025
3026
3027#define ENHANCE_HD_TABLE_SIZE (23)
3028
3029
3030#define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3031
3032#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3033#define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3034#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3035#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3036#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3037#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3038#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3039#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3040#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3041#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3042#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3043
3044#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3045#define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3046#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3047#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3048#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3049#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3050#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3051#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3052#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3053#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3054#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3055
3056
3057
3058#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3059#define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3060
3061
3062
3063
3064
3065
3066
3067
3068struct iwl_sensitivity_cmd {
3069 __le16 control;
3070 __le16 table[HD_TABLE_SIZE];
3071} __packed;
3072
3073
3074
3075
3076struct iwl_enhance_sensitivity_cmd {
3077 __le16 control;
3078 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3079} __packed;
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138enum {
3139 IWL_PHY_CALIBRATE_DC_CMD = 8,
3140 IWL_PHY_CALIBRATE_LO_CMD = 9,
3141 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3142 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3143 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3144 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3145 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3146};
3147
3148
3149
3150
3151enum iwl_ucode_calib_cfg {
3152 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3153 IWL_CALIB_CFG_DC_IDX = BIT(1),
3154 IWL_CALIB_CFG_LO_IDX = BIT(2),
3155 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3156 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3157 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3158 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3159 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3160 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3161 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3162 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3163};
3164
3165#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3166 IWL_CALIB_CFG_DC_IDX | \
3167 IWL_CALIB_CFG_LO_IDX | \
3168 IWL_CALIB_CFG_TX_IQ_IDX | \
3169 IWL_CALIB_CFG_RX_IQ_IDX | \
3170 IWL_CALIB_CFG_CRYSTAL_IDX)
3171
3172#define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3173 IWL_CALIB_CFG_DC_IDX | \
3174 IWL_CALIB_CFG_LO_IDX | \
3175 IWL_CALIB_CFG_TX_IQ_IDX | \
3176 IWL_CALIB_CFG_RX_IQ_IDX | \
3177 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3178 IWL_CALIB_CFG_PAPD_IDX | \
3179 IWL_CALIB_CFG_TX_PWR_IDX | \
3180 IWL_CALIB_CFG_CRYSTAL_IDX)
3181
3182#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3183
3184struct iwl_calib_cfg_elmnt_s {
3185 __le32 is_enable;
3186 __le32 start;
3187 __le32 send_res;
3188 __le32 apply_res;
3189 __le32 reserved;
3190} __packed;
3191
3192struct iwl_calib_cfg_status_s {
3193 struct iwl_calib_cfg_elmnt_s once;
3194 struct iwl_calib_cfg_elmnt_s perd;
3195 __le32 flags;
3196} __packed;
3197
3198struct iwl_calib_cfg_cmd {
3199 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3200 struct iwl_calib_cfg_status_s drv_calib_cfg;
3201 __le32 reserved1;
3202} __packed;
3203
3204struct iwl_calib_hdr {
3205 u8 op_code;
3206 u8 first_group;
3207 u8 groups_num;
3208 u8 data_valid;
3209} __packed;
3210
3211struct iwl_calib_cmd {
3212 struct iwl_calib_hdr hdr;
3213 u8 data[0];
3214} __packed;
3215
3216struct iwl_calib_xtal_freq_cmd {
3217 struct iwl_calib_hdr hdr;
3218 u8 cap_pin1;
3219 u8 cap_pin2;
3220 u8 pad[2];
3221} __packed;
3222
3223#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3224struct iwl_calib_temperature_offset_cmd {
3225 struct iwl_calib_hdr hdr;
3226 __le16 radio_sensor_offset;
3227 __le16 reserved;
3228} __packed;
3229
3230struct iwl_calib_temperature_offset_v2_cmd {
3231 struct iwl_calib_hdr hdr;
3232 __le16 radio_sensor_offset_high;
3233 __le16 radio_sensor_offset_low;
3234 __le16 burntVoltageRef;
3235 __le16 reserved;
3236} __packed;
3237
3238
3239struct iwl_calib_chain_noise_reset_cmd {
3240 struct iwl_calib_hdr hdr;
3241 u8 data[0];
3242};
3243
3244
3245struct iwl_calib_chain_noise_gain_cmd {
3246 struct iwl_calib_hdr hdr;
3247 u8 delta_gain_1;
3248 u8 delta_gain_2;
3249 u8 pad[2];
3250} __packed;
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265struct iwl_led_cmd {
3266 __le32 interval;
3267 u8 id;
3268 u8 off;
3269
3270 u8 on;
3271
3272 u8 reserved;
3273} __packed;
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3287#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3288#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3289
3290#define COEX_CU_UNASSOC_IDLE_RP 4
3291#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3292#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3293#define COEX_CU_CALIBRATION_RP 4
3294#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3295#define COEX_CU_CONNECTION_ESTAB_RP 4
3296#define COEX_CU_ASSOCIATED_IDLE_RP 4
3297#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3298#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3299#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3300#define COEX_CU_RF_ON_RP 6
3301#define COEX_CU_RF_OFF_RP 4
3302#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3303#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3304#define COEX_CU_RSRVD1_RP 4
3305#define COEX_CU_RSRVD2_RP 4
3306
3307#define COEX_CU_UNASSOC_IDLE_WP 3
3308#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3309#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3310#define COEX_CU_CALIBRATION_WP 3
3311#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3312#define COEX_CU_CONNECTION_ESTAB_WP 3
3313#define COEX_CU_ASSOCIATED_IDLE_WP 3
3314#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3315#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3316#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3317#define COEX_CU_RF_ON_WP 3
3318#define COEX_CU_RF_OFF_WP 3
3319#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3320#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3321#define COEX_CU_RSRVD1_WP 3
3322#define COEX_CU_RSRVD2_WP 3
3323
3324#define COEX_UNASSOC_IDLE_FLAGS 0
3325#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3326 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3327 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3328#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3329 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3330 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3331#define COEX_CALIBRATION_FLAGS \
3332 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3333 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3334#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3335
3336
3337
3338
3339#define COEX_CONNECTION_ESTAB_FLAGS \
3340 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3341 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3342 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3343#define COEX_ASSOCIATED_IDLE_FLAGS 0
3344#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3345 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3346 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3347#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3348 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3349 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3350#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3351#define COEX_RF_ON_FLAGS 0
3352#define COEX_RF_OFF_FLAGS 0
3353#define COEX_STAND_ALONE_DEBUG_FLAGS \
3354 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3355 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3356#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3357 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3358 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3359 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3360#define COEX_RSRVD1_FLAGS 0
3361#define COEX_RSRVD2_FLAGS 0
3362
3363
3364
3365
3366#define COEX_CU_RF_ON_FLAGS \
3367 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3368 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3369 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3370
3371
3372enum {
3373
3374 COEX_UNASSOC_IDLE = 0,
3375 COEX_UNASSOC_MANUAL_SCAN = 1,
3376 COEX_UNASSOC_AUTO_SCAN = 2,
3377
3378 COEX_CALIBRATION = 3,
3379 COEX_PERIODIC_CALIBRATION = 4,
3380
3381 COEX_CONNECTION_ESTAB = 5,
3382
3383 COEX_ASSOCIATED_IDLE = 6,
3384 COEX_ASSOC_MANUAL_SCAN = 7,
3385 COEX_ASSOC_AUTO_SCAN = 8,
3386 COEX_ASSOC_ACTIVE_LEVEL = 9,
3387
3388 COEX_RF_ON = 10,
3389 COEX_RF_OFF = 11,
3390 COEX_STAND_ALONE_DEBUG = 12,
3391
3392 COEX_IPAN_ASSOC_LEVEL = 13,
3393
3394 COEX_RSRVD1 = 14,
3395 COEX_RSRVD2 = 15,
3396 COEX_NUM_OF_EVENTS = 16
3397};
3398
3399
3400
3401
3402
3403
3404struct iwl_wimax_coex_event_entry {
3405 u8 request_prio;
3406 u8 win_medium_prio;
3407 u8 reserved;
3408 u8 flags;
3409} __packed;
3410
3411
3412
3413
3414#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3415
3416#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3417
3418#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3419
3420#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3421
3422struct iwl_wimax_coex_cmd {
3423 u8 flags;
3424 u8 reserved[3];
3425 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3426} __packed;
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442#define COEX_MEDIUM_BUSY (0x0)
3443#define COEX_MEDIUM_ACTIVE (0x1)
3444#define COEX_MEDIUM_PRE_RELEASE (0x2)
3445#define COEX_MEDIUM_MSK (0x7)
3446
3447
3448#define COEX_MEDIUM_CHANGED (0x8)
3449#define COEX_MEDIUM_CHANGED_MSK (0x8)
3450#define COEX_MEDIUM_SHIFT (3)
3451
3452struct iwl_coex_medium_notification {
3453 __le32 status;
3454 __le32 events;
3455} __packed;
3456
3457
3458
3459
3460
3461
3462
3463
3464#define COEX_EVENT_REQUEST_MSK (0x1)
3465
3466struct iwl_coex_event_cmd {
3467 u8 flags;
3468 u8 event;
3469 __le16 reserved;
3470} __packed;
3471
3472struct iwl_coex_event_resp {
3473 __le32 status;
3474} __packed;
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486enum iwl_bt_coex_profile_traffic_load {
3487 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3488 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3489 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3490 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3491
3492
3493
3494
3495};
3496
3497#define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3498#define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3499
3500
3501#define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3502#define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3503 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3504#define BT_UART_MSG_FRAME1SSN_POS (3)
3505#define BT_UART_MSG_FRAME1SSN_MSK \
3506 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3507#define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3508#define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3509 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3510#define BT_UART_MSG_FRAME1RESERVED_POS (6)
3511#define BT_UART_MSG_FRAME1RESERVED_MSK \
3512 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3513
3514#define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3515#define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3516 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3517#define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3518#define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3519 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3520#define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3521#define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3522 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3523#define BT_UART_MSG_FRAME2INBAND_POS (5)
3524#define BT_UART_MSG_FRAME2INBAND_MSK \
3525 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3526#define BT_UART_MSG_FRAME2RESERVED_POS (6)
3527#define BT_UART_MSG_FRAME2RESERVED_MSK \
3528 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3529
3530#define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3531#define BT_UART_MSG_FRAME3SCOESCO_MSK \
3532 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3533#define BT_UART_MSG_FRAME3SNIFF_POS (1)
3534#define BT_UART_MSG_FRAME3SNIFF_MSK \
3535 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3536#define BT_UART_MSG_FRAME3A2DP_POS (2)
3537#define BT_UART_MSG_FRAME3A2DP_MSK \
3538 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3539#define BT_UART_MSG_FRAME3ACL_POS (3)
3540#define BT_UART_MSG_FRAME3ACL_MSK \
3541 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3542#define BT_UART_MSG_FRAME3MASTER_POS (4)
3543#define BT_UART_MSG_FRAME3MASTER_MSK \
3544 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3545#define BT_UART_MSG_FRAME3OBEX_POS (5)
3546#define BT_UART_MSG_FRAME3OBEX_MSK \
3547 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3548#define BT_UART_MSG_FRAME3RESERVED_POS (6)
3549#define BT_UART_MSG_FRAME3RESERVED_MSK \
3550 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3551
3552#define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3553#define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3554 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3555#define BT_UART_MSG_FRAME4RESERVED_POS (6)
3556#define BT_UART_MSG_FRAME4RESERVED_MSK \
3557 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3558
3559#define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3560#define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3561 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3562#define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3563#define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3564 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3565#define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3566#define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3567 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3568#define BT_UART_MSG_FRAME5RESERVED_POS (6)
3569#define BT_UART_MSG_FRAME5RESERVED_MSK \
3570 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3571
3572#define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3573#define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3574 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3575#define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3576#define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3577 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3578#define BT_UART_MSG_FRAME6RESERVED_POS (6)
3579#define BT_UART_MSG_FRAME6RESERVED_MSK \
3580 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3581
3582#define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3583#define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3584 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3585#define BT_UART_MSG_FRAME7PAGE_POS (3)
3586#define BT_UART_MSG_FRAME7PAGE_MSK \
3587 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3588#define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3589#define BT_UART_MSG_FRAME7INQUIRY_MSK \
3590 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3591#define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3592#define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3593 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3594#define BT_UART_MSG_FRAME7RESERVED_POS (6)
3595#define BT_UART_MSG_FRAME7RESERVED_MSK \
3596 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3597
3598
3599#define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3600#define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3601 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3602#define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3603#define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3604 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3605
3606#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3607#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3608 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3609#define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3610#define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3611 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3612
3613#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3614#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3615 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3616#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3617#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3618 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3619#define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3620#define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3621 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3622#define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3623#define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3624 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3625
3626#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3627#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3628 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3629#define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3630#define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3631 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3632#define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3633#define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3634 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3635
3636#define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3637#define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3638 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3639#define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3640#define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3641 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3642#define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3643#define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3644 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3645#define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3646#define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3647 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3648
3649#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3650#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3651 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3652#define BT_UART_MSG_2_FRAME6RFU_POS (5)
3653#define BT_UART_MSG_2_FRAME6RFU_MSK \
3654 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3655#define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3656#define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3657 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3658
3659#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3660#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3661 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3662#define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3663#define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3664 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3665#define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3666#define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3667 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3668#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3669#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3670 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3671#define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3672#define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3673 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3674
3675
3676#define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3677#define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3678
3679struct iwl_bt_uart_msg {
3680 u8 header;
3681 u8 frame1;
3682 u8 frame2;
3683 u8 frame3;
3684 u8 frame4;
3685 u8 frame5;
3686 u8 frame6;
3687 u8 frame7;
3688} __packed;
3689
3690struct iwl_bt_coex_profile_notif {
3691 struct iwl_bt_uart_msg last_bt_uart_msg;
3692 u8 bt_status;
3693 u8 bt_traffic_load;
3694 u8 bt_ci_compliance;
3695 u8 reserved;
3696} __packed;
3697
3698#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3699#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3700#define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3701#define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3702#define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3703#define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3704#define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3705
3706
3707
3708
3709
3710enum bt_coex_prio_table_events {
3711 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3712 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3713 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3714 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3715 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3716 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3717 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3718 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3719 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3720 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3721 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3722 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3723 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3724 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3725 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3726 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3727
3728 BT_COEX_PRIO_TBL_EVT_MAX,
3729};
3730
3731enum bt_coex_prio_table_priorities {
3732 BT_COEX_PRIO_TBL_DISABLED = 0,
3733 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3734 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3735 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3736 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3737 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3738 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3739 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3740 BT_COEX_PRIO_TBL_MAX,
3741};
3742
3743struct iwl_bt_coex_prio_table_cmd {
3744 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3745} __packed;
3746
3747#define IWL_BT_COEX_ENV_CLOSE 0
3748#define IWL_BT_COEX_ENV_OPEN 1
3749
3750
3751
3752
3753struct iwl_bt_coex_prot_env_cmd {
3754 u8 action;
3755 u8 type;
3756 u8 reserved[2];
3757} __packed;
3758
3759
3760
3761
3762enum iwlagn_d3_wakeup_filters {
3763 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3764 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3765};
3766
3767struct iwlagn_d3_config_cmd {
3768 __le32 min_sleep_time;
3769 __le32 wakeup_flags;
3770} __packed;
3771
3772
3773
3774
3775#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3776#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3777
3778struct iwlagn_wowlan_pattern {
3779 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3780 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3781 u8 mask_size;
3782 u8 pattern_size;
3783 __le16 reserved;
3784} __packed;
3785
3786#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3787
3788struct iwlagn_wowlan_patterns_cmd {
3789 __le32 n_patterns;
3790 struct iwlagn_wowlan_pattern patterns[];
3791} __packed;
3792
3793
3794
3795
3796enum iwlagn_wowlan_wakeup_filters {
3797 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3798 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3799 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3800 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3801 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3802 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3803 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3804 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3805 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3806};
3807
3808struct iwlagn_wowlan_wakeup_filter_cmd {
3809 __le32 enabled;
3810 __le16 non_qos_seq;
3811 __le16 reserved;
3812 __le16 qos_seq[8];
3813};
3814
3815
3816
3817
3818#define IWLAGN_NUM_RSC 16
3819
3820struct tkip_sc {
3821 __le16 iv16;
3822 __le16 pad;
3823 __le32 iv32;
3824} __packed;
3825
3826struct iwlagn_tkip_rsc_tsc {
3827 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3828 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3829 struct tkip_sc tsc;
3830} __packed;
3831
3832struct aes_sc {
3833 __le64 pn;
3834} __packed;
3835
3836struct iwlagn_aes_rsc_tsc {
3837 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3838 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3839 struct aes_sc tsc;
3840} __packed;
3841
3842union iwlagn_all_tsc_rsc {
3843 struct iwlagn_tkip_rsc_tsc tkip;
3844 struct iwlagn_aes_rsc_tsc aes;
3845};
3846
3847struct iwlagn_wowlan_rsc_tsc_params_cmd {
3848 union iwlagn_all_tsc_rsc all_tsc_rsc;
3849} __packed;
3850
3851
3852
3853
3854#define IWLAGN_MIC_KEY_SIZE 8
3855#define IWLAGN_P1K_SIZE 5
3856struct iwlagn_mic_keys {
3857 u8 tx[IWLAGN_MIC_KEY_SIZE];
3858 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3859 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3860} __packed;
3861
3862struct iwlagn_p1k_cache {
3863 __le16 p1k[IWLAGN_P1K_SIZE];
3864} __packed;
3865
3866#define IWLAGN_NUM_RX_P1K_CACHE 2
3867
3868struct iwlagn_wowlan_tkip_params_cmd {
3869 struct iwlagn_mic_keys mic_keys;
3870 struct iwlagn_p1k_cache tx;
3871 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3872 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3873} __packed;
3874
3875
3876
3877
3878
3879#define IWLAGN_KCK_MAX_SIZE 32
3880#define IWLAGN_KEK_MAX_SIZE 32
3881
3882struct iwlagn_wowlan_kek_kck_material_cmd {
3883 u8 kck[IWLAGN_KCK_MAX_SIZE];
3884 u8 kek[IWLAGN_KEK_MAX_SIZE];
3885 __le16 kck_len;
3886 __le16 kek_len;
3887 __le64 replay_ctr;
3888} __packed;
3889
3890#define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3891
3892
3893
3894
3895struct iwlagn_wowlan_status {
3896 __le64 replay_ctr;
3897 __le32 rekey_status;
3898 __le32 wakeup_reason;
3899 u8 pattern_number;
3900 u8 reserved1;
3901 __le16 qos_seq_ctr[8];
3902 __le16 non_qos_seq_ctr;
3903 __le16 reserved2;
3904 union iwlagn_all_tsc_rsc tsc_rsc;
3905 __le16 reserved3;
3906} __packed;
3907
3908
3909
3910
3911
3912
3913
3914
3915#define IWL_MIN_SLOT_TIME 20
3916
3917
3918
3919
3920
3921
3922
3923
3924struct iwl_wipan_slot {
3925 __le16 width;
3926 u8 type;
3927 u8 reserved;
3928} __packed;
3929
3930#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3931#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3932#define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3933#define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3934#define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951struct iwl_wipan_params_cmd {
3952 __le16 flags;
3953 u8 reserved;
3954 u8 num_slots;
3955 struct iwl_wipan_slot slots[10];
3956} __packed;
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966struct iwl_wipan_p2p_channel_switch_cmd {
3967 __le16 channel;
3968 __le16 reserved;
3969};
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982struct iwl_wipan_noa_descriptor {
3983 u8 count;
3984 __le32 duration;
3985 __le32 interval;
3986 __le32 starttime;
3987} __packed;
3988
3989struct iwl_wipan_noa_attribute {
3990 u8 id;
3991 __le16 length;
3992 u8 index;
3993 u8 ct_window;
3994 struct iwl_wipan_noa_descriptor descr0, descr1;
3995 u8 reserved;
3996} __packed;
3997
3998struct iwl_wipan_noa_notification {
3999 u32 noa_active;
4000 struct iwl_wipan_noa_attribute noa_attribute;
4001} __packed;
4002
4003#endif
4004