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64#ifndef __fw_api_h__
65#define __fw_api_h__
66
67#include "fw-api-rs.h"
68#include "fw-api-tx.h"
69#include "fw-api-sta.h"
70#include "fw-api-mac.h"
71#include "fw-api-power.h"
72#include "fw-api-d3.h"
73#include "fw-api-bt-coex.h"
74
75
76enum {
77 IWL_MVM_OFFCHANNEL_QUEUE = 8,
78 IWL_MVM_CMD_QUEUE = 9,
79 IWL_MVM_AUX_QUEUE = 15,
80 IWL_MVM_FIRST_AGG_QUEUE = 16,
81 IWL_MVM_NUM_QUEUES = 20,
82 IWL_MVM_LAST_AGG_QUEUE = IWL_MVM_NUM_QUEUES - 1,
83 IWL_MVM_CMD_FIFO = 7
84};
85
86#define IWL_MVM_STATION_COUNT 16
87
88
89enum {
90 MVM_ALIVE = 0x1,
91 REPLY_ERROR = 0x2,
92
93 INIT_COMPLETE_NOTIF = 0x4,
94
95
96 PHY_CONTEXT_CMD = 0x8,
97 DBG_CFG = 0x9,
98
99
100 ADD_STA = 0x18,
101 REMOVE_STA = 0x19,
102
103
104 TX_CMD = 0x1c,
105 TXPATH_FLUSH = 0x1e,
106 MGMT_MCAST_KEY = 0x1f,
107
108
109 WEP_KEY = 0x20,
110
111
112 MAC_CONTEXT_CMD = 0x28,
113 TIME_EVENT_CMD = 0x29,
114 TIME_EVENT_NOTIFICATION = 0x2a,
115 BINDING_CONTEXT_CMD = 0x2b,
116 TIME_QUOTA_CMD = 0x2c,
117
118 LQ_CMD = 0x4e,
119
120
121 TEMPERATURE_NOTIFICATION = 0x62,
122 CALIBRATION_CFG_CMD = 0x65,
123 CALIBRATION_RES_NOTIFICATION = 0x66,
124 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
125 RADIO_VERSION_NOTIFICATION = 0x68,
126
127
128 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
129 SCAN_OFFLOAD_ABORT_CMD = 0x52,
130 SCAN_OFFLOAD_COMPLETE = 0x6D,
131 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
132 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
133
134
135 PHY_CONFIGURATION_CMD = 0x6a,
136 CALIB_RES_NOTIF_PHY_DB = 0x6b,
137
138
139
140 POWER_TABLE_CMD = 0x77,
141
142
143 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
144
145
146 SCAN_REQUEST_CMD = 0x80,
147 SCAN_ABORT_CMD = 0x81,
148 SCAN_START_NOTIFICATION = 0x82,
149 SCAN_RESULTS_NOTIFICATION = 0x83,
150 SCAN_COMPLETE_NOTIFICATION = 0x84,
151
152
153 NVM_ACCESS_CMD = 0x88,
154
155 SET_CALIB_DEFAULT_CMD = 0x8e,
156
157 BEACON_NOTIFICATION = 0x90,
158 BEACON_TEMPLATE_CMD = 0x91,
159 TX_ANT_CONFIGURATION_CMD = 0x98,
160 BT_CONFIG = 0x9b,
161 STATISTICS_NOTIFICATION = 0x9d,
162
163
164 CARD_STATE_CMD = 0xa0,
165 CARD_STATE_NOTIFICATION = 0xa1,
166
167 MISSED_BEACONS_NOTIFICATION = 0xa2,
168
169 REPLY_RX_PHY_CMD = 0xc0,
170 REPLY_RX_MPDU_CMD = 0xc1,
171 BA_NOTIF = 0xc5,
172
173
174 BT_COEX_PRIO_TABLE = 0xcc,
175 BT_COEX_PROT_ENV = 0xcd,
176 BT_PROFILE_NOTIFICATION = 0xce,
177
178 REPLY_BEACON_FILTERING_CMD = 0xd2,
179
180 REPLY_DEBUG_CMD = 0xf0,
181 DEBUG_LOG_MSG = 0xf7,
182
183 MCAST_FILTER_CMD = 0xd0,
184
185
186 D3_CONFIG_CMD = 0xd3,
187 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
188 OFFLOADS_QUERY_CMD = 0xd5,
189 REMOTE_WAKE_CONFIG_CMD = 0xd6,
190
191
192 WOWLAN_PATTERNS = 0xe0,
193 WOWLAN_CONFIGURATION = 0xe1,
194 WOWLAN_TSC_RSC_PARAM = 0xe2,
195 WOWLAN_TKIP_PARAM = 0xe3,
196 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
197 WOWLAN_GET_STATUSES = 0xe5,
198 WOWLAN_TX_POWER_PER_DB = 0xe6,
199
200
201 NET_DETECT_CONFIG_CMD = 0x54,
202 NET_DETECT_PROFILES_QUERY_CMD = 0x56,
203 NET_DETECT_PROFILES_CMD = 0x57,
204 NET_DETECT_HOTSPOTS_CMD = 0x58,
205 NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
206
207 REPLY_MAX = 0xff,
208};
209
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213
214struct iwl_cmd_response {
215 __le32 status;
216};
217
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221
222struct iwl_tx_ant_cfg_cmd {
223 __le32 valid;
224} __packed;
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233
234struct iwl_calib_ctrl {
235 __le32 flow_trigger;
236 __le32 event_trigger;
237} __packed;
238
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240
241
242enum iwl_calib_cfg {
243 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
244 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
245 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
246 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
247 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
248 IWL_CALIB_CFG_DC_IDX = BIT(5),
249 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
250 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
251 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
252 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
253 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
254 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
255 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
256 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
257 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
258 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
259 IWL_CALIB_CFG_DAC_IDX = BIT(16),
260 IWL_CALIB_CFG_ABS_IDX = BIT(17),
261 IWL_CALIB_CFG_AGC_IDX = BIT(18),
262};
263
264
265
266
267struct iwl_phy_cfg_cmd {
268 __le32 phy_cfg;
269 struct iwl_calib_ctrl calib_control;
270} __packed;
271
272#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
273#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
274#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
275#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
276#define PHY_CFG_TX_CHAIN_A BIT(8)
277#define PHY_CFG_TX_CHAIN_B BIT(9)
278#define PHY_CFG_TX_CHAIN_C BIT(10)
279#define PHY_CFG_RX_CHAIN_A BIT(12)
280#define PHY_CFG_RX_CHAIN_B BIT(13)
281#define PHY_CFG_RX_CHAIN_C BIT(14)
282
283
284
285enum {
286 NVM_ACCESS_TARGET_CACHE = 0,
287 NVM_ACCESS_TARGET_OTP = 1,
288 NVM_ACCESS_TARGET_EEPROM = 2,
289};
290
291
292enum {
293 NVM_SECTION_TYPE_HW = 0,
294 NVM_SECTION_TYPE_SW,
295 NVM_SECTION_TYPE_PAPD,
296 NVM_SECTION_TYPE_BT,
297 NVM_SECTION_TYPE_CALIBRATION,
298 NVM_SECTION_TYPE_PRODUCTION,
299 NVM_SECTION_TYPE_POST_FCS_CALIB,
300 NVM_NUM_OF_SECTIONS,
301};
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312struct iwl_nvm_access_cmd {
313 u8 op_code;
314 u8 target;
315 __le16 type;
316 __le16 offset;
317 __le16 length;
318 u8 data[];
319} __packed;
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329struct iwl_nvm_access_resp {
330 __le16 offset;
331 __le16 length;
332 __le16 type;
333 __le16 status;
334 u8 data[];
335} __packed;
336
337
338
339
340#define ALIVE_RESP_UCODE_OK BIT(0)
341#define ALIVE_RESP_RFKILL BIT(1)
342
343
344enum {
345 FW_TYPE_HW = 0,
346 FW_TYPE_PROT = 1,
347 FW_TYPE_AP = 2,
348 FW_TYPE_WOWLAN = 3,
349 FW_TYPE_TIMING = 4,
350 FW_TYPE_WIPAN = 5
351};
352
353
354enum {
355 FW_SUBTYPE_FULL_FEATURE = 0,
356 FW_SUBTYPE_BOOTSRAP = 1,
357 FW_SUBTYPE_REDUCED = 2,
358 FW_SUBTYPE_ALIVE_ONLY = 3,
359 FW_SUBTYPE_WOWLAN = 4,
360 FW_SUBTYPE_AP_SUBTYPE = 5,
361 FW_SUBTYPE_WIPAN = 6,
362 FW_SUBTYPE_INITIALIZE = 9
363};
364
365#define IWL_ALIVE_STATUS_ERR 0xDEAD
366#define IWL_ALIVE_STATUS_OK 0xCAFE
367
368#define IWL_ALIVE_FLG_RFKILL BIT(0)
369
370struct mvm_alive_resp {
371 __le16 status;
372 __le16 flags;
373 u8 ucode_minor;
374 u8 ucode_major;
375 __le16 id;
376 u8 api_minor;
377 u8 api_major;
378 u8 ver_subtype;
379 u8 ver_type;
380 u8 mac;
381 u8 opt;
382 __le16 reserved2;
383 __le32 timestamp;
384 __le32 error_event_table_ptr;
385 __le32 log_event_table_ptr;
386 __le32 cpu_register_ptr;
387 __le32 dbgm_config_ptr;
388 __le32 alive_counter_ptr;
389 __le32 scd_base_ptr;
390} __packed;
391
392
393enum {
394 FW_ERR_UNKNOWN_CMD = 0x0,
395 FW_ERR_INVALID_CMD_PARAM = 0x1,
396 FW_ERR_SERVICE = 0x2,
397 FW_ERR_ARC_MEMORY = 0x3,
398 FW_ERR_ARC_CODE = 0x4,
399 FW_ERR_WATCH_DOG = 0x5,
400 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
401 FW_ERR_WEP_KEY_SIZE = 0x11,
402 FW_ERR_OBSOLETE_FUNC = 0x12,
403 FW_ERR_UNEXPECTED = 0xFE,
404 FW_ERR_FATAL = 0xFF
405};
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416
417struct iwl_error_resp {
418 __le32 error_type;
419 u8 cmd_id;
420 u8 reserved1;
421 __le16 bad_cmd_seq_num;
422 __le32 error_service;
423 __le64 timestamp;
424} __packed;
425
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427
428
429#define MAX_MACS_IN_BINDING (3)
430#define MAX_BINDINGS (4)
431#define AUX_BINDING_INDEX (3)
432#define MAX_PHYS (4)
433
434
435#define FW_CTXT_ID_POS (0)
436#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
437#define FW_CTXT_COLOR_POS (8)
438#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
439#define FW_CTXT_INVALID (0xffffffff)
440
441#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
442 (_color << FW_CTXT_COLOR_POS))
443
444
445enum {
446 FW_CTXT_ACTION_STUB = 0,
447 FW_CTXT_ACTION_ADD,
448 FW_CTXT_ACTION_MODIFY,
449 FW_CTXT_ACTION_REMOVE,
450 FW_CTXT_ACTION_NUM
451};
452
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455
456enum iwl_time_event_type {
457
458 TE_BSS_STA_AGGRESSIVE_ASSOC,
459 TE_BSS_STA_ASSOC,
460 TE_BSS_EAP_DHCP_PROT,
461 TE_BSS_QUIET_PERIOD,
462
463
464 TE_P2P_DEVICE_DISCOVERABLE,
465 TE_P2P_DEVICE_LISTEN,
466 TE_P2P_DEVICE_ACTION_SCAN,
467 TE_P2P_DEVICE_FULL_SCAN,
468
469
470 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
471 TE_P2P_CLIENT_ASSOC,
472 TE_P2P_CLIENT_QUIET_PERIOD,
473
474
475 TE_P2P_GO_ASSOC_PROT,
476 TE_P2P_GO_REPETITIVE_NOA,
477 TE_P2P_GO_CT_WINDOW,
478
479
480 TE_WIDI_TX_SYNC,
481
482 TE_MAX
483};
484
485
486enum {
487 TE_INDEPENDENT = 0,
488 TE_DEP_OTHER = 1,
489 TE_DEP_TSF = 2,
490 TE_EVENT_SOCIOPATHIC = 4,
491};
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509enum {
510 TE_NOTIF_NONE = 0,
511 TE_NOTIF_HOST_EVENT_START = 0x1,
512 TE_NOTIF_HOST_EVENT_END = 0x2,
513 TE_NOTIF_INTERNAL_EVENT_START = 0x4,
514 TE_NOTIF_INTERNAL_EVENT_END = 0x8,
515 TE_NOTIF_HOST_FRAG_START = 0x10,
516 TE_NOTIF_HOST_FRAG_END = 0x20,
517 TE_NOTIF_INTERNAL_FRAG_START = 0x40,
518 TE_NOTIF_INTERNAL_FRAG_END = 0x80
519};
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534enum {
535 TE_FRAG_NONE = 0,
536 TE_FRAG_SINGLE = 1,
537 TE_FRAG_DUAL = 2,
538 TE_FRAG_ENDLESS = 0xffffffff
539};
540
541
542#define TE_REPEAT_ENDLESS (0xffffffff)
543
544#define TE_REPEAT_MAX_MSK (0x0fffffff)
545
546#define TE_FRAG_MAX_MSK (0x0fffffff)
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569struct iwl_time_event_cmd {
570
571 __le32 id_and_color;
572 __le32 action;
573 __le32 id;
574
575 __le32 apply_time;
576 __le32 max_delay;
577 __le32 dep_policy;
578 __le32 depends_on;
579 __le32 is_present;
580 __le32 max_frags;
581 __le32 interval;
582 __le32 interval_reciprocal;
583 __le32 duration;
584 __le32 repeat;
585 __le32 notify;
586} __packed;
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595struct iwl_time_event_resp {
596 __le32 status;
597 __le32 id;
598 __le32 unique_id;
599 __le32 id_and_color;
600} __packed;
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611
612struct iwl_time_event_notif {
613 __le32 timestamp;
614 __le32 session_id;
615 __le32 unique_id;
616 __le32 id_and_color;
617 __le32 action;
618 __le32 status;
619} __packed;
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632struct iwl_binding_cmd {
633
634 __le32 id_and_color;
635 __le32 action;
636
637 __le32 macs[MAX_MACS_IN_BINDING];
638 __le32 phy;
639} __packed;
640
641
642#define IWL_MVM_MAX_QUOTA 128
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651struct iwl_time_quota_data {
652 __le32 id_and_color;
653 __le32 quota;
654 __le32 max_duration;
655} __packed;
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662struct iwl_time_quota_cmd {
663 struct iwl_time_quota_data quotas[MAX_BINDINGS];
664} __packed;
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669
670#define PHY_BAND_5 (0)
671#define PHY_BAND_24 (1)
672
673
674#define PHY_VHT_CHANNEL_MODE20 (0x0)
675#define PHY_VHT_CHANNEL_MODE40 (0x1)
676#define PHY_VHT_CHANNEL_MODE80 (0x2)
677#define PHY_VHT_CHANNEL_MODE160 (0x3)
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691#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
692#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
693#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
694#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
695#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
696#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
697#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
698#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
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706struct iwl_fw_channel_info {
707 u8 band;
708 u8 channel;
709 u8 width;
710 u8 ctrl_pos;
711} __packed;
712
713#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
714#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
715 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
716#define PHY_RX_CHAIN_VALID_POS (1)
717#define PHY_RX_CHAIN_VALID_MSK \
718 (0x7 << PHY_RX_CHAIN_VALID_POS)
719#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
720#define PHY_RX_CHAIN_FORCE_SEL_MSK \
721 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
722#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
723#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
724 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
725#define PHY_RX_CHAIN_CNT_POS (10)
726#define PHY_RX_CHAIN_CNT_MSK \
727 (0x3 << PHY_RX_CHAIN_CNT_POS)
728#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
729#define PHY_RX_CHAIN_MIMO_CNT_MSK \
730 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
731#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
732#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
733 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
734
735
736#define NUM_PHY_CTX 3
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753struct iwl_phy_context_cmd {
754
755 __le32 id_and_color;
756 __le32 action;
757
758 __le32 apply_time;
759 __le32 tx_param_color;
760 struct iwl_fw_channel_info ci;
761 __le32 txchain_info;
762 __le32 rxchain_info;
763 __le32 acquisition_data;
764 __le32 dsp_cfg_flags;
765} __packed;
766
767#define IWL_RX_INFO_PHY_CNT 8
768#define IWL_RX_INFO_AGC_IDX 1
769#define IWL_RX_INFO_RSSI_AB_IDX 2
770#define IWL_OFDM_AGC_A_MSK 0x0000007f
771#define IWL_OFDM_AGC_A_POS 0
772#define IWL_OFDM_AGC_B_MSK 0x00003f80
773#define IWL_OFDM_AGC_B_POS 7
774#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
775#define IWL_OFDM_AGC_CODE_POS 20
776#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
777#define IWL_OFDM_RSSI_A_POS 0
778#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
779#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
780#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
781#define IWL_OFDM_RSSI_B_POS 16
782#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
783#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
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807struct iwl_rx_phy_info {
808 u8 non_cfg_phy_cnt;
809 u8 cfg_phy_cnt;
810 u8 stat_id;
811 u8 reserved1;
812 __le32 system_timestamp;
813 __le64 timestamp;
814 __le32 beacon_time_stamp;
815 __le16 phy_flags;
816 __le16 channel;
817 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
818 __le32 rate_n_flags;
819 __le32 byte_count;
820 __le16 mac_active_msk;
821 __le16 frame_time;
822} __packed;
823
824struct iwl_rx_mpdu_res_start {
825 __le16 byte_count;
826 __le16 reserved;
827} __packed;
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841enum iwl_rx_phy_flags {
842 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
843 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
844 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
845 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
846 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
847 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
848 RX_RES_PHY_FLAGS_AGG = BIT(7),
849 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
850 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
851 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
852};
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886enum iwl_mvm_rx_status {
887 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
888 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
889 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
890 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
891 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
892 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
893 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
894 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
895 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
896 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
897 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
898 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
899 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
900 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
901 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
902 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
903 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
904 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
905 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
906 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
907 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
908 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
909 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
910 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
911 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
912 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
913};
914
915
916
917
918
919
920
921
922struct iwl_radio_version_notif {
923 __le32 radio_flavor;
924 __le32 radio_step;
925 __le32 radio_dash;
926} __packed;
927
928enum iwl_card_state_flags {
929 CARD_ENABLED = 0x00,
930 HW_CARD_DISABLED = 0x01,
931 SW_CARD_DISABLED = 0x02,
932 CT_KILL_CARD_DISABLED = 0x04,
933 HALT_CARD_DISABLED = 0x08,
934 CARD_DISABLED_MSK = 0x0f,
935 CARD_IS_RX_ON = 0x10,
936};
937
938
939
940
941
942
943struct iwl_card_state_notif {
944 __le32 flags;
945} __packed;
946
947
948
949
950
951
952
953
954
955
956
957struct iwl_missed_beacons_notif {
958 __le32 mac_id;
959 __le32 consec_missed_beacons_since_last_rx;
960 __le32 consec_missed_beacons;
961 __le32 num_expected_beacons;
962 __le32 num_recvd_beacons;
963} __packed;
964
965
966
967
968
969
970
971
972struct iwl_set_calib_default_cmd {
973 __le16 calib_index;
974 __le16 length;
975 u8 data[0];
976} __packed;
977
978#define MAX_PORT_ID_NUM 2
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993struct iwl_mcast_filter_cmd {
994 u8 filter_own;
995 u8 port_id;
996 u8 count;
997 u8 pass_all;
998 u8 bssid[6];
999 u8 reserved[2];
1000 u8 addr_list[0];
1001} __packed;
1002
1003struct mvm_statistics_dbg {
1004 __le32 burst_check;
1005 __le32 burst_count;
1006 __le32 wait_for_silence_timeout_cnt;
1007 __le32 reserved[3];
1008} __packed;
1009
1010struct mvm_statistics_div {
1011 __le32 tx_on_a;
1012 __le32 tx_on_b;
1013 __le32 exec_time;
1014 __le32 probe_time;
1015 __le32 rssi_ant;
1016 __le32 reserved2;
1017} __packed;
1018
1019struct mvm_statistics_general_common {
1020 __le32 temperature;
1021 __le32 temperature_m;
1022 struct mvm_statistics_dbg dbg;
1023 __le32 sleep_time;
1024 __le32 slots_out;
1025 __le32 slots_idle;
1026 __le32 ttl_timestamp;
1027 struct mvm_statistics_div div;
1028 __le32 rx_enable_counter;
1029
1030
1031
1032
1033
1034 __le32 num_of_sos_states;
1035} __packed;
1036
1037struct mvm_statistics_rx_non_phy {
1038 __le32 bogus_cts;
1039 __le32 bogus_ack;
1040 __le32 non_bssid_frames;
1041
1042 __le32 filtered_frames;
1043
1044 __le32 non_channel_beacons;
1045
1046 __le32 channel_beacons;
1047
1048 __le32 num_missed_bcon;
1049 __le32 adc_rx_saturation_time;
1050
1051 __le32 ina_detection_search_time;
1052
1053 __le32 beacon_silence_rssi_a;
1054 __le32 beacon_silence_rssi_b;
1055 __le32 beacon_silence_rssi_c;
1056 __le32 interference_data_flag;
1057
1058
1059 __le32 channel_load;
1060 __le32 dsp_false_alarms;
1061
1062 __le32 beacon_rssi_a;
1063 __le32 beacon_rssi_b;
1064 __le32 beacon_rssi_c;
1065 __le32 beacon_energy_a;
1066 __le32 beacon_energy_b;
1067 __le32 beacon_energy_c;
1068 __le32 num_bt_kills;
1069 __le32 mac_id;
1070 __le32 directed_data_mpdu;
1071} __packed;
1072
1073struct mvm_statistics_rx_phy {
1074 __le32 ina_cnt;
1075 __le32 fina_cnt;
1076 __le32 plcp_err;
1077 __le32 crc32_err;
1078 __le32 overrun_err;
1079 __le32 early_overrun_err;
1080 __le32 crc32_good;
1081 __le32 false_alarm_cnt;
1082 __le32 fina_sync_err_cnt;
1083 __le32 sfd_timeout;
1084 __le32 fina_timeout;
1085 __le32 unresponded_rts;
1086 __le32 rxe_frame_limit_overrun;
1087 __le32 sent_ack_cnt;
1088 __le32 sent_cts_cnt;
1089 __le32 sent_ba_rsp_cnt;
1090 __le32 dsp_self_kill;
1091 __le32 mh_format_err;
1092 __le32 re_acq_main_rssi_sum;
1093 __le32 reserved;
1094} __packed;
1095
1096struct mvm_statistics_rx_ht_phy {
1097 __le32 plcp_err;
1098 __le32 overrun_err;
1099 __le32 early_overrun_err;
1100 __le32 crc32_good;
1101 __le32 crc32_err;
1102 __le32 mh_format_err;
1103 __le32 agg_crc32_good;
1104 __le32 agg_mpdu_cnt;
1105 __le32 agg_cnt;
1106 __le32 unsupport_mcs;
1107} __packed;
1108
1109#define MAX_CHAINS 3
1110
1111struct mvm_statistics_tx_non_phy_agg {
1112 __le32 ba_timeout;
1113 __le32 ba_reschedule_frames;
1114 __le32 scd_query_agg_frame_cnt;
1115 __le32 scd_query_no_agg;
1116 __le32 scd_query_agg;
1117 __le32 scd_query_mismatch;
1118 __le32 frame_not_ready;
1119 __le32 underrun;
1120 __le32 bt_prio_kill;
1121 __le32 rx_ba_rsp_cnt;
1122 __s8 txpower[MAX_CHAINS];
1123 __s8 reserved;
1124 __le32 reserved2;
1125} __packed;
1126
1127struct mvm_statistics_tx_channel_width {
1128 __le32 ext_cca_narrow_ch20[1];
1129 __le32 ext_cca_narrow_ch40[2];
1130 __le32 ext_cca_narrow_ch80[3];
1131 __le32 ext_cca_narrow_ch160[4];
1132 __le32 last_tx_ch_width_indx;
1133 __le32 rx_detected_per_ch_width[4];
1134 __le32 success_per_ch_width[4];
1135 __le32 fail_per_ch_width[4];
1136};
1137
1138struct mvm_statistics_tx {
1139 __le32 preamble_cnt;
1140 __le32 rx_detected_cnt;
1141 __le32 bt_prio_defer_cnt;
1142 __le32 bt_prio_kill_cnt;
1143 __le32 few_bytes_cnt;
1144 __le32 cts_timeout;
1145 __le32 ack_timeout;
1146 __le32 expected_ack_cnt;
1147 __le32 actual_ack_cnt;
1148 __le32 dump_msdu_cnt;
1149 __le32 burst_abort_next_frame_mismatch_cnt;
1150 __le32 burst_abort_missing_next_frame_cnt;
1151 __le32 cts_timeout_collision;
1152 __le32 ack_or_ba_timeout_collision;
1153 struct mvm_statistics_tx_non_phy_agg agg;
1154 struct mvm_statistics_tx_channel_width channel_width;
1155} __packed;
1156
1157
1158struct mvm_statistics_bt_activity {
1159 __le32 hi_priority_tx_req_cnt;
1160 __le32 hi_priority_tx_denied_cnt;
1161 __le32 lo_priority_tx_req_cnt;
1162 __le32 lo_priority_tx_denied_cnt;
1163 __le32 hi_priority_rx_req_cnt;
1164 __le32 hi_priority_rx_denied_cnt;
1165 __le32 lo_priority_rx_req_cnt;
1166 __le32 lo_priority_rx_denied_cnt;
1167} __packed;
1168
1169struct mvm_statistics_general {
1170 struct mvm_statistics_general_common common;
1171 __le32 beacon_filtered;
1172 __le32 missed_beacons;
1173 __s8 beacon_filter_everage_energy;
1174 __s8 beacon_filter_reason;
1175 __s8 beacon_filter_current_energy;
1176 __s8 beacon_filter_reserved;
1177 __le32 beacon_filter_delta_time;
1178 struct mvm_statistics_bt_activity bt_activity;
1179} __packed;
1180
1181struct mvm_statistics_rx {
1182 struct mvm_statistics_rx_phy ofdm;
1183 struct mvm_statistics_rx_phy cck;
1184 struct mvm_statistics_rx_non_phy general;
1185 struct mvm_statistics_rx_ht_phy ofdm_ht;
1186} __packed;
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204struct iwl_notif_statistics {
1205 __le32 flag;
1206 struct mvm_statistics_rx rx;
1207 struct mvm_statistics_tx tx;
1208 struct mvm_statistics_general general;
1209} __packed;
1210
1211#endif
1212