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30#ifndef __RTL92C_DEF_H__
31#define __RTL92C_DEF_H__
32
33#define HAL_RETRY_LIMIT_INFRA 48
34#define HAL_RETRY_LIMIT_AP_ADHOC 7
35
36#define PHY_RSSI_SLID_WIN_MAX 100
37#define PHY_LINKQUALITY_SLID_WIN_MAX 20
38#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
39
40#define RESET_DELAY_8185 20
41
42#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
43#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
44
45#define NUM_OF_FIRMWARE_QUEUE 10
46#define NUM_OF_PAGES_IN_FW 0x100
47#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
48#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
49#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
50#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
51#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
52#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
53#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
54#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
55#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
56#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
57
58#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
59#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
60#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
61#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
62#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
63
64#define MAX_LINES_HWCONFIG_TXT 1000
65#define MAX_BYTES_LINE_HWCONFIG_TXT 256
66
67#define SW_THREE_WIRE 0
68#define HW_THREE_WIRE 2
69
70#define BT_DEMO_BOARD 0
71#define BT_QA_BOARD 1
72#define BT_FPGA 2
73
74#define RX_SMOOTH_FACTOR 20
75
76#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
77#define HAL_PRIME_CHNL_OFFSET_LOWER 1
78#define HAL_PRIME_CHNL_OFFSET_UPPER 2
79
80#define MAX_H2C_QUEUE_NUM 10
81
82#define RX_MPDU_QUEUE 0
83#define RX_CMD_QUEUE 1
84#define RX_MAX_QUEUE 2
85#define AC2QUEUEID(_AC) (_AC)
86
87#define C2H_RX_CMD_HDR_LEN 8
88#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
89 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
90#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
91 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
92#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
93 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
94#define GET_C2H_CMD_CONTINUE(__prxhdr) \
95 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
96#define GET_C2H_CMD_CONTENT(__prxhdr) \
97 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
98
99#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
101#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
103#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
105#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
107#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
108 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
109#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
110 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
111#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
112 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
113#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
114 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
115#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
116 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
117
118#define CHIP_VER_B BIT(4)
119#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
120#define CHIP_BONDING_92C_1T2R 0x1
121#define RF_TYPE_1T2R BIT(1)
122#define CHIP_92C_BITMASK BIT(0)
123#define CHIP_UNKNOWN BIT(7)
124#define CHIP_92C_1T2R 0x03
125#define CHIP_92C 0x01
126#define CHIP_88C 0x00
127
128enum version_8192c {
129 VERSION_A_CHIP_92C = 0x01,
130 VERSION_A_CHIP_88C = 0x00,
131 VERSION_B_CHIP_92C = 0x11,
132 VERSION_B_CHIP_88C = 0x10,
133 VERSION_TEST_CHIP_88C = 0x00,
134 VERSION_TEST_CHIP_92C = 0x01,
135 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
136 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
137 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
138 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
139 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
140 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
141 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
142 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
143 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
144 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
145 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
146 VERSION_UNKNOWN = 0x88,
147};
148
149#define CUT_VERSION_MASK (BIT(6)|BIT(7))
150#define CHIP_VENDOR_UMC BIT(5)
151#define CHIP_VENDOR_UMC_B_CUT BIT(6)
152#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
153 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
154#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
155#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
156 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
157#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
158#define IS_CHIP_VENDOR_UMC(version) \
159 ((version & CHIP_VENDOR_UMC) ? true : false)
160#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
161#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
162 ((IS_CHIP_VENDOR_UMC(version)) ? \
163 ((GET_CVID_CUT_VERSION(version) == CHIP_VENDOR_UMC_B_CUT) ? \
164 true : false) : false)
165
166enum rtl819x_loopback_e {
167 RTL819X_NO_LOOPBACK = 0,
168 RTL819X_MAC_LOOPBACK = 1,
169 RTL819X_DMA_LOOPBACK = 2,
170 RTL819X_CCK_LOOPBACK = 3,
171};
172
173enum rf_optype {
174 RF_OP_BY_SW_3WIRE = 0,
175 RF_OP_BY_FW,
176 RF_OP_MAX
177};
178
179enum rf_power_state {
180 RF_ON,
181 RF_OFF,
182 RF_SLEEP,
183 RF_SHUT_DOWN,
184};
185
186enum power_save_mode {
187 POWER_SAVE_MODE_ACTIVE,
188 POWER_SAVE_MODE_SAVE,
189};
190
191enum power_polocy_config {
192 POWERCFG_MAX_POWER_SAVINGS,
193 POWERCFG_GLOBAL_POWER_SAVINGS,
194 POWERCFG_LOCAL_POWER_SAVINGS,
195 POWERCFG_LENOVO,
196};
197
198enum interface_select_pci {
199 INTF_SEL1_MINICARD = 0,
200 INTF_SEL0_PCIE = 1,
201 INTF_SEL2_RSV = 2,
202 INTF_SEL3_RSV = 3,
203};
204
205enum hal_fw_c2h_cmd_id {
206 HAL_FW_C2H_CMD_Read_MACREG = 0,
207 HAL_FW_C2H_CMD_Read_BBREG = 1,
208 HAL_FW_C2H_CMD_Read_RFREG = 2,
209 HAL_FW_C2H_CMD_Read_EEPROM = 3,
210 HAL_FW_C2H_CMD_Read_EFUSE = 4,
211 HAL_FW_C2H_CMD_Read_CAM = 5,
212 HAL_FW_C2H_CMD_Get_BasicRate = 6,
213 HAL_FW_C2H_CMD_Get_DataRate = 7,
214 HAL_FW_C2H_CMD_Survey = 8,
215 HAL_FW_C2H_CMD_SurveyDone = 9,
216 HAL_FW_C2H_CMD_JoinBss = 10,
217 HAL_FW_C2H_CMD_AddSTA = 11,
218 HAL_FW_C2H_CMD_DelSTA = 12,
219 HAL_FW_C2H_CMD_AtimDone = 13,
220 HAL_FW_C2H_CMD_TX_Report = 14,
221 HAL_FW_C2H_CMD_CCX_Report = 15,
222 HAL_FW_C2H_CMD_DTM_Report = 16,
223 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
224 HAL_FW_C2H_CMD_C2HLBK = 18,
225 HAL_FW_C2H_CMD_C2HDBG = 19,
226 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
227 HAL_FW_C2H_CMD_MAX
228};
229
230enum rtl_desc_qsel {
231 QSLT_BK = 0x2,
232 QSLT_BE = 0x0,
233 QSLT_VI = 0x5,
234 QSLT_VO = 0x7,
235 QSLT_BEACON = 0x10,
236 QSLT_HIGH = 0x11,
237 QSLT_MGNT = 0x12,
238 QSLT_CMD = 0x13,
239};
240
241struct phy_sts_cck_8192s_t {
242 u8 adc_pwdb_X[4];
243 u8 sq_rpt;
244 u8 cck_agc_rpt;
245};
246
247struct h2c_cmd_8192c {
248 u8 element_id;
249 u32 cmd_len;
250 u8 *p_cmdbuffer;
251};
252
253#endif
254
