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30#include "../wifi.h"
31#include "../core.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "hw.h"
38#include "sw.h"
39#include "trx.h"
40#include "led.h"
41
42#include <linux/module.h>
43
44static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
45{
46 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
47
48
49 rtlpci->const_amdpci_aspm = 0;
50
51
52
53
54
55
56
57
58
59
60 rtlpci->const_pci_aspm = 3;
61
62
63 rtlpci->const_devicepci_aspm_setting = 0x03;
64
65
66 rtlpci->const_hostpci_aspm_setting = 0x02;
67
68
69
70
71
72
73
74
75
76 rtlpci->const_hwsw_rfoff_d3 = 0;
77
78
79
80
81
82
83
84
85 rtlpci->const_support_pciaspm = 1;
86}
87
88static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
89{
90 int err;
91 u8 tid;
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94
95 rtlpriv->dm.dm_initialgain_enable = true;
96 rtlpriv->dm.dm_flag = 0;
97 rtlpriv->dm.disable_framebursting = false;
98 rtlpriv->dm.thermalvalue = 0;
99 rtlpriv->dm.useramask = true;
100
101
102 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
103 rtlpriv->phy.current_channel = 36;
104 else
105 rtlpriv->phy.current_channel = 1;
106
107 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
108 rtlpriv->rtlhal.disable_amsdu_8k = true;
109
110 rtlpci->rxbuffersize = 4096;
111 }
112
113 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
114
115 rtlpci->receive_config = (
116 RCR_APPFCS
117 | RCR_AMF
118 | RCR_ADF
119 | RCR_APP_MIC
120 | RCR_APP_ICV
121 | RCR_AICV
122 | RCR_ACRC32
123 | RCR_AB
124 | RCR_AM
125 | RCR_APM
126 | RCR_APP_PHYST_RXFF
127 | RCR_HTC_LOC_CTRL
128 );
129
130 rtlpci->irq_mask[0] = (u32) (
131 IMR_ROK
132 | IMR_VODOK
133 | IMR_VIDOK
134 | IMR_BEDOK
135 | IMR_BKDOK
136 | IMR_MGNTDOK
137 | IMR_HIGHDOK
138 | IMR_BDOK
139 | IMR_RDU
140 | IMR_RXFOVW
141 );
142
143 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
144
145
146 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
147
148 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
149 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
150 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
151 if (!rtlpriv->psc.inactiveps)
152 pr_info("Power Save off (module option)\n");
153 if (!rtlpriv->psc.fwctrl_lps)
154 pr_info("FW Power Save off (module option)\n");
155 rtlpriv->psc.reg_fwctrl_lps = 3;
156 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
157
158
159 rtl92d_init_aspm_vars(hw);
160
161 if (rtlpriv->psc.reg_fwctrl_lps == 1)
162 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
163 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
164 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
165 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
166 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
167
168
169 rtlpriv->rtlhal.earlymode_enable = false;
170 for (tid = 0; tid < 8; tid++)
171 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
172
173
174 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
175 if (!rtlpriv->rtlhal.pfirmware) {
176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
177 "Can't alloc buffer for fw\n");
178 return 1;
179 }
180
181 rtlpriv->max_fw_size = 0x8000;
182 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
183 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
184
185
186 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
187 rtlpriv->io.dev, GFP_KERNEL, hw,
188 rtl_fw_cb);
189 if (err) {
190 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
191 "Failed to request firmware!\n");
192 return 1;
193 }
194
195 return 0;
196}
197
198static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
199{
200 struct rtl_priv *rtlpriv = rtl_priv(hw);
201 u8 tid;
202
203 if (rtlpriv->rtlhal.pfirmware) {
204 vfree(rtlpriv->rtlhal.pfirmware);
205 rtlpriv->rtlhal.pfirmware = NULL;
206 }
207 for (tid = 0; tid < 8; tid++)
208 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
209}
210
211static struct rtl_hal_ops rtl8192de_hal_ops = {
212 .init_sw_vars = rtl92d_init_sw_vars,
213 .deinit_sw_vars = rtl92d_deinit_sw_vars,
214 .read_eeprom_info = rtl92de_read_eeprom_info,
215 .interrupt_recognized = rtl92de_interrupt_recognized,
216 .hw_init = rtl92de_hw_init,
217 .hw_disable = rtl92de_card_disable,
218 .hw_suspend = rtl92de_suspend,
219 .hw_resume = rtl92de_resume,
220 .enable_interrupt = rtl92de_enable_interrupt,
221 .disable_interrupt = rtl92de_disable_interrupt,
222 .set_network_type = rtl92de_set_network_type,
223 .set_chk_bssid = rtl92de_set_check_bssid,
224 .set_qos = rtl92de_set_qos,
225 .set_bcn_reg = rtl92de_set_beacon_related_registers,
226 .set_bcn_intv = rtl92de_set_beacon_interval,
227 .update_interrupt_mask = rtl92de_update_interrupt_mask,
228 .get_hw_reg = rtl92de_get_hw_reg,
229 .set_hw_reg = rtl92de_set_hw_reg,
230 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
231 .fill_tx_desc = rtl92de_tx_fill_desc,
232 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
233 .query_rx_desc = rtl92de_rx_query_desc,
234 .set_channel_access = rtl92de_update_channel_access_setting,
235 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
236 .set_bw_mode = rtl92d_phy_set_bw_mode,
237 .switch_channel = rtl92d_phy_sw_chnl,
238 .dm_watchdog = rtl92d_dm_watchdog,
239 .scan_operation_backup = rtl92d_phy_scan_operation_backup,
240 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
241 .led_control = rtl92de_led_control,
242 .set_desc = rtl92de_set_desc,
243 .get_desc = rtl92de_get_desc,
244 .tx_polling = rtl92de_tx_polling,
245 .enable_hw_sec = rtl92de_enable_hw_security_config,
246 .set_key = rtl92de_set_key,
247 .init_sw_leds = rtl92de_init_sw_leds,
248 .get_bbreg = rtl92d_phy_query_bb_reg,
249 .set_bbreg = rtl92d_phy_set_bb_reg,
250 .get_rfreg = rtl92d_phy_query_rf_reg,
251 .set_rfreg = rtl92d_phy_set_rf_reg,
252 .linked_set_reg = rtl92d_linked_set_reg,
253};
254
255static struct rtl_mod_params rtl92de_mod_params = {
256 .sw_crypto = false,
257 .inactiveps = true,
258 .swctrl_lps = true,
259 .fwctrl_lps = false,
260 .debug = DBG_EMERG,
261};
262
263static struct rtl_hal_cfg rtl92de_hal_cfg = {
264 .bar_id = 2,
265 .write_readback = true,
266 .name = "rtl8192de",
267 .fw_name = "rtlwifi/rtl8192defw.bin",
268 .ops = &rtl8192de_hal_ops,
269 .mod_params = &rtl92de_mod_params,
270
271 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
272 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
273 .maps[SYS_CLK] = REG_SYS_CLKR,
274 .maps[MAC_RCR_AM] = RCR_AM,
275 .maps[MAC_RCR_AB] = RCR_AB,
276 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
277 .maps[MAC_RCR_ACF] = RCR_ACF,
278 .maps[MAC_RCR_AAP] = RCR_AAP,
279
280 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
281 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
282 .maps[EFUSE_CLK] = 0,
283 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
284 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
285 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
286 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
287 .maps[EFUSE_ANA8M] = 0,
288 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
289 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
290 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
291
292 .maps[RWCAM] = REG_CAMCMD,
293 .maps[WCAMI] = REG_CAMWRITE,
294 .maps[RCAMO] = REG_CAMREAD,
295 .maps[CAMDBG] = REG_CAMDBG,
296 .maps[SECR] = REG_SECCFG,
297 .maps[SEC_CAM_NONE] = CAM_NONE,
298 .maps[SEC_CAM_WEP40] = CAM_WEP40,
299 .maps[SEC_CAM_TKIP] = CAM_TKIP,
300 .maps[SEC_CAM_AES] = CAM_AES,
301 .maps[SEC_CAM_WEP104] = CAM_WEP104,
302
303 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
304 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
305 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
306 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
307 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
308 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
309 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
310 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
311 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
312 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
313 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
314 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
315 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
316 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
317 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
318 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
319
320 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
321 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
322 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
323 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
324 .maps[RTL_IMR_RDU] = IMR_RDU,
325 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
326 .maps[RTL_IMR_BDOK] = IMR_BDOK,
327 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
328 .maps[RTL_IMR_TBDER] = IMR_TBDER,
329 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
330 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
331 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
332 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
333 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
334 .maps[RTL_IMR_VODOK] = IMR_VODOK,
335 .maps[RTL_IMR_ROK] = IMR_ROK,
336 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
337
338 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
339 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
340 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
341 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
342 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
343 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
344 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
345 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
346 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
347 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
348 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
349 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
350
351 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
352 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
353};
354
355static struct pci_device_id rtl92de_pci_ids[] = {
356 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
357 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
358 {},
359};
360
361MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
362
363MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
364MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
365MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
366MODULE_LICENSE("GPL");
367MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
368MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
369
370module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
371module_param_named(debug, rtl92de_mod_params.debug, int, 0444);
372module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
373module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
374module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
375MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
376MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
377MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
378MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
379MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
380
381static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
382
383static struct pci_driver rtl92de_driver = {
384 .name = KBUILD_MODNAME,
385 .id_table = rtl92de_pci_ids,
386 .probe = rtl_pci_probe,
387 .remove = rtl_pci_disconnect,
388 .driver.pm = &rtlwifi_pm_ops,
389};
390
391
392
393spinlock_t globalmutex_power;
394spinlock_t globalmutex_for_fwdownload;
395spinlock_t globalmutex_for_power_and_efuse;
396
397static int __init rtl92de_module_init(void)
398{
399 int ret = 0;
400
401 spin_lock_init(&globalmutex_power);
402 spin_lock_init(&globalmutex_for_fwdownload);
403 spin_lock_init(&globalmutex_for_power_and_efuse);
404
405 ret = pci_register_driver(&rtl92de_driver);
406 if (ret)
407 RT_ASSERT(false, "No device found\n");
408 return ret;
409}
410
411static void __exit rtl92de_module_exit(void)
412{
413 pci_unregister_driver(&rtl92de_driver);
414}
415
416module_init(rtl92de_module_init);
417module_exit(rtl92de_module_exit);
418
