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30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36#include "fw.h"
37
38static const u32 edca_setting_dl[PEER_MAX] = {
39 0xa44f,
40 0x5ea44f,
41 0x5ea44f,
42 0xa630,
43 0xa44f,
44 0xa630,
45 0xa630,
46 0xa42b,
47};
48
49static const u32 edca_setting_dl_gmode[PEER_MAX] = {
50 0x4322,
51 0xa44f,
52 0x5ea44f,
53 0xa42b,
54 0x5e4322,
55 0x4322,
56 0xa430,
57 0x5ea44f,
58};
59
60static const u32 edca_setting_ul[PEER_MAX] = {
61 0x5e4322,
62 0xa44f,
63 0x5ea44f,
64 0x5ea322,
65 0x5ea422,
66 0x5ea322,
67 0x3ea44f,
68 0x5ea44f,
69};
70
71static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
75
76 static u64 last_txok_cnt;
77 static u64 last_rxok_cnt;
78 u64 cur_txok_cnt = 0;
79 u64 cur_rxok_cnt = 0;
80
81 u32 edca_be_ul = edca_setting_ul[mac->vendor];
82 u32 edca_be_dl = edca_setting_dl[mac->vendor];
83 u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
84
85 if (mac->link_state != MAC80211_LINKED) {
86 rtlpriv->dm.current_turbo_edca = false;
87 goto dm_checkedcaturbo_exit;
88 }
89
90 if ((!rtlpriv->dm.is_any_nonbepkts) &&
91 (!rtlpriv->dm.disable_framebursting)) {
92 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
93 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
94
95 if (rtlpriv->phy.rf_type == RF_1T2R) {
96 if (cur_txok_cnt > 4 * cur_rxok_cnt) {
97
98 if (rtlpriv->dm.is_cur_rdlstate ||
99 !rtlpriv->dm.current_turbo_edca) {
100 rtl_write_dword(rtlpriv, EDCAPARA_BE,
101 edca_be_ul);
102 rtlpriv->dm.is_cur_rdlstate = false;
103 }
104 } else {
105 if (!rtlpriv->dm.is_cur_rdlstate ||
106 !rtlpriv->dm.current_turbo_edca) {
107 if (mac->mode == WIRELESS_MODE_G ||
108 mac->mode == WIRELESS_MODE_B)
109 rtl_write_dword(rtlpriv,
110 EDCAPARA_BE,
111 edca_gmode);
112 else
113 rtl_write_dword(rtlpriv,
114 EDCAPARA_BE,
115 edca_be_dl);
116 rtlpriv->dm.is_cur_rdlstate = true;
117 }
118 }
119 rtlpriv->dm.current_turbo_edca = true;
120 } else {
121 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
122 if (!rtlpriv->dm.is_cur_rdlstate ||
123 !rtlpriv->dm.current_turbo_edca) {
124 if (mac->mode == WIRELESS_MODE_G ||
125 mac->mode == WIRELESS_MODE_B)
126 rtl_write_dword(rtlpriv,
127 EDCAPARA_BE,
128 edca_gmode);
129 else
130 rtl_write_dword(rtlpriv,
131 EDCAPARA_BE,
132 edca_be_dl);
133 rtlpriv->dm.is_cur_rdlstate = true;
134 }
135 } else {
136 if (rtlpriv->dm.is_cur_rdlstate ||
137 !rtlpriv->dm.current_turbo_edca) {
138 rtl_write_dword(rtlpriv, EDCAPARA_BE,
139 edca_be_ul);
140 rtlpriv->dm.is_cur_rdlstate = false;
141 }
142 }
143 rtlpriv->dm.current_turbo_edca = true;
144 }
145 } else {
146 if (rtlpriv->dm.current_turbo_edca) {
147 u8 tmp = AC0_BE;
148 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
149 &tmp);
150 rtlpriv->dm.current_turbo_edca = false;
151 }
152 }
153
154dm_checkedcaturbo_exit:
155 rtlpriv->dm.is_any_nonbepkts = false;
156 last_txok_cnt = rtlpriv->stats.txbytesunicast;
157 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
158}
159
160static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
161 struct ieee80211_hw *hw)
162{
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
165 u8 thermalvalue = 0;
166 u32 fw_cmd = 0;
167
168 rtlpriv->dm.txpower_trackinginit = true;
169
170 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
171
172 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
173 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermal meter 0x%x\n",
174 thermalvalue,
175 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
176
177 if (thermalvalue) {
178 rtlpriv->dm.thermalvalue = thermalvalue;
179 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
180 rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
181 } else {
182 fw_cmd = (FW_TXPWR_TRACK_THERMAL |
183 (rtlpriv->efuse.thermalmeter[0] << 8) |
184 (thermalvalue << 16));
185
186 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
187 "Write to FW Thermal Val = 0x%x\n", fw_cmd);
188
189 rtl_write_dword(rtlpriv, WFM5, fw_cmd);
190 rtl92s_phy_chk_fwcmd_iodone(hw);
191 }
192 }
193
194 rtlpriv->dm.txpowercount = 0;
195}
196
197static void _rtl92s_dm_check_txpowertracking_thermalmeter(
198 struct ieee80211_hw *hw)
199{
200 struct rtl_priv *rtlpriv = rtl_priv(hw);
201 struct rtl_phy *rtlphy = &(rtlpriv->phy);
202 static u8 tm_trigger;
203 u8 tx_power_checkcnt = 5;
204
205
206 if (rtlphy->rf_type == RF_2T2R)
207 return;
208
209 if (!rtlpriv->dm.txpower_tracking)
210 return;
211
212 if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
213 rtlpriv->dm.txpowercount++;
214 return;
215 }
216
217 if (!tm_trigger) {
218 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
219 RFREG_OFFSET_MASK, 0x60);
220 tm_trigger = 1;
221 } else {
222 _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
223 tm_trigger = 0;
224 }
225}
226
227static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
228{
229 struct rtl_priv *rtlpriv = rtl_priv(hw);
230 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
231 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
232 struct rate_adaptive *ra = &(rtlpriv->ra);
233 struct ieee80211_sta *sta = NULL;
234 u32 low_rssi_thresh = 0;
235 u32 middle_rssi_thresh = 0;
236 u32 high_rssi_thresh = 0;
237
238 if (is_hal_stop(rtlhal))
239 return;
240
241 if (!rtlpriv->dm.useramask)
242 return;
243
244 if (hal_get_firmwareversion(rtlpriv) >= 61 &&
245 !rtlpriv->dm.inform_fw_driverctrldm) {
246 rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
247 rtlpriv->dm.inform_fw_driverctrldm = true;
248 }
249
250 if ((mac->link_state == MAC80211_LINKED) &&
251 (mac->opmode == NL80211_IFTYPE_STATION)) {
252 switch (ra->pre_ratr_state) {
253 case DM_RATR_STA_HIGH:
254 high_rssi_thresh = 40;
255 middle_rssi_thresh = 30;
256 low_rssi_thresh = 20;
257 break;
258 case DM_RATR_STA_MIDDLE:
259 high_rssi_thresh = 44;
260 middle_rssi_thresh = 30;
261 low_rssi_thresh = 20;
262 break;
263 case DM_RATR_STA_LOW:
264 high_rssi_thresh = 44;
265 middle_rssi_thresh = 34;
266 low_rssi_thresh = 20;
267 break;
268 case DM_RATR_STA_ULTRALOW:
269 high_rssi_thresh = 44;
270 middle_rssi_thresh = 34;
271 low_rssi_thresh = 24;
272 break;
273 default:
274 high_rssi_thresh = 44;
275 middle_rssi_thresh = 34;
276 low_rssi_thresh = 24;
277 break;
278 }
279
280 if (rtlpriv->dm.undec_sm_pwdb > (long)high_rssi_thresh) {
281 ra->ratr_state = DM_RATR_STA_HIGH;
282 } else if (rtlpriv->dm.undec_sm_pwdb >
283 (long)middle_rssi_thresh) {
284 ra->ratr_state = DM_RATR_STA_LOW;
285 } else if (rtlpriv->dm.undec_sm_pwdb >
286 (long)low_rssi_thresh) {
287 ra->ratr_state = DM_RATR_STA_LOW;
288 } else {
289 ra->ratr_state = DM_RATR_STA_ULTRALOW;
290 }
291
292 if (ra->pre_ratr_state != ra->ratr_state) {
293 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
294 "RSSI = %ld RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
295 rtlpriv->dm.undec_sm_pwdb, ra->ratr_state,
296 ra->pre_ratr_state, ra->ratr_state);
297
298 rcu_read_lock();
299 sta = rtl_find_sta(hw, mac->bssid);
300 if (sta)
301 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
302 ra->ratr_state);
303 rcu_read_unlock();
304
305 ra->pre_ratr_state = ra->ratr_state;
306 }
307 }
308}
309
310static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
311{
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
314 struct rtl_phy *rtlphy = &(rtlpriv->phy);
315 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
316 bool current_mrc;
317 bool enable_mrc = true;
318 long tmpentry_maxpwdb = 0;
319 u8 rssi_a = 0;
320 u8 rssi_b = 0;
321
322 if (is_hal_stop(rtlhal))
323 return;
324
325 if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
326 return;
327
328 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(¤t_mrc));
329
330 if (mac->link_state >= MAC80211_LINKED) {
331 if (rtlpriv->dm.undec_sm_pwdb > tmpentry_maxpwdb) {
332 rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
333 rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
334 }
335 }
336
337
338 if (mac->mode != WIRELESS_MODE_B) {
339 if ((rssi_a == 0) && (rssi_b == 0)) {
340 enable_mrc = true;
341 } else if (rssi_b > 30) {
342
343 enable_mrc = true;
344 } else if (rssi_b < 5) {
345
346 enable_mrc = false;
347
348 } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
349 if ((rssi_a - rssi_b) > 15)
350
351 enable_mrc = false;
352 else if ((rssi_a - rssi_b) < 10)
353
354 enable_mrc = true;
355 else
356 enable_mrc = current_mrc;
357 } else {
358
359 enable_mrc = true;
360 }
361 }
362
363
364 if (enable_mrc != current_mrc)
365 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
366 (u8 *)&enable_mrc);
367
368}
369
370void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
371{
372 struct rtl_priv *rtlpriv = rtl_priv(hw);
373
374 rtlpriv->dm.current_turbo_edca = false;
375 rtlpriv->dm.is_any_nonbepkts = false;
376 rtlpriv->dm.is_cur_rdlstate = false;
377}
378
379static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
380{
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rate_adaptive *ra = &(rtlpriv->ra);
383
384 ra->ratr_state = DM_RATR_STA_MAX;
385 ra->pre_ratr_state = DM_RATR_STA_MAX;
386
387 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER &&
388 hal_get_firmwareversion(rtlpriv) >= 60)
389 rtlpriv->dm.useramask = true;
390 else
391 rtlpriv->dm.useramask = false;
392
393 rtlpriv->dm.useramask = false;
394 rtlpriv->dm.inform_fw_driverctrldm = false;
395}
396
397static void _rtl92s_dm_init_txpowertracking_thermalmeter(
398 struct ieee80211_hw *hw)
399{
400 struct rtl_priv *rtlpriv = rtl_priv(hw);
401
402 rtlpriv->dm.txpower_tracking = true;
403 rtlpriv->dm.txpowercount = 0;
404 rtlpriv->dm.txpower_trackinginit = false;
405}
406
407static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
408{
409 struct rtl_priv *rtlpriv = rtl_priv(hw);
410 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
411 u32 ret_value;
412
413 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
414 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
415
416 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
417 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
418 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
419 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
420 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
421
422 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
423 falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
424 falsealm_cnt->cnt_mcs_fail;
425
426
427 ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
428 falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
429 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
430 falsealm_cnt->cnt_cck_fail;
431}
432
433static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct dig_t *digtable = &rtlpriv->dm_digtable;
437 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
438
439 if (falsealm_cnt->cnt_all > digtable->fa_highthresh) {
440 if ((digtable->back_val - 6) <
441 digtable->backoffval_range_min)
442 digtable->back_val = digtable->backoffval_range_min;
443 else
444 digtable->back_val -= 6;
445 } else if (falsealm_cnt->cnt_all < digtable->fa_lowthresh) {
446 if ((digtable->back_val + 6) >
447 digtable->backoffval_range_max)
448 digtable->back_val =
449 digtable->backoffval_range_max;
450 else
451 digtable->back_val += 6;
452 }
453}
454
455static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
456{
457 struct rtl_priv *rtlpriv = rtl_priv(hw);
458 struct dig_t *digtable = &rtlpriv->dm_digtable;
459 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
460 static u8 initialized, force_write;
461 u8 initial_gain = 0;
462
463 if ((digtable->pre_sta_cstate == digtable->cur_sta_cstate) ||
464 (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT)) {
465 if (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) {
466 if (rtlpriv->psc.rfpwr_state != ERFON)
467 return;
468
469 if (digtable->backoff_enable_flag)
470 rtl92s_backoff_enable_flag(hw);
471 else
472 digtable->back_val = DM_DIG_BACKOFF;
473
474 if ((digtable->rssi_val + 10 - digtable->back_val) >
475 digtable->rx_gain_max)
476 digtable->cur_igvalue =
477 digtable->rx_gain_max;
478 else if ((digtable->rssi_val + 10 - digtable->back_val)
479 < digtable->rx_gain_min)
480 digtable->cur_igvalue =
481 digtable->rx_gain_min;
482 else
483 digtable->cur_igvalue = digtable->rssi_val + 10
484 - digtable->back_val;
485
486 if (falsealm_cnt->cnt_all > 10000)
487 digtable->cur_igvalue =
488 (digtable->cur_igvalue > 0x33) ?
489 digtable->cur_igvalue : 0x33;
490
491 if (falsealm_cnt->cnt_all > 16000)
492 digtable->cur_igvalue =
493 digtable->rx_gain_max;
494
495 } else {
496
497 return;
498 }
499
500
501 } else {
502
503 digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
504 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
505
506 digtable->back_val = DM_DIG_BACKOFF;
507 digtable->cur_igvalue = rtlpriv->phy.default_initialgain[0];
508 digtable->pre_igvalue = 0;
509 return;
510 }
511
512
513 if (digtable->pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
514 MASKBYTE0))
515 force_write = 1;
516
517 if ((digtable->pre_igvalue != digtable->cur_igvalue) ||
518 !initialized || force_write) {
519
520 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
521
522 initial_gain = (u8)digtable->cur_igvalue;
523
524
525 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
526 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
527 digtable->pre_igvalue = digtable->cur_igvalue;
528 initialized = 1;
529 force_write = 0;
530 }
531}
532
533static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
534{
535 struct rtl_priv *rtlpriv = rtl_priv(hw);
536 struct dig_t *dig = &rtlpriv->dm_digtable;
537
538 if (rtlpriv->mac80211.act_scanning)
539 return;
540
541
542 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
543 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
544 dig->cur_sta_cstate = DIG_STA_CONNECT;
545 else
546 dig->cur_sta_cstate = DIG_STA_DISCONNECT;
547
548 dig->rssi_val = rtlpriv->dm.undec_sm_pwdb;
549
550
551 if (dig->cur_sta_cstate != DIG_STA_DISCONNECT) {
552 if (dig->dig_twoport_algorithm ==
553 DIG_TWO_PORT_ALGO_FALSE_ALARM) {
554 dig->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
555 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
556 }
557 }
558
559 _rtl92s_dm_false_alarm_counter_statistics(hw);
560 _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
561
562 dig->pre_sta_cstate = dig->cur_sta_cstate;
563}
564
565static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
566{
567 struct rtl_priv *rtlpriv = rtl_priv(hw);
568 struct rtl_phy *rtlphy = &(rtlpriv->phy);
569 struct dig_t *digtable = &rtlpriv->dm_digtable;
570
571
572 if (rtlphy->rf_type == RF_2T2R)
573 return;
574
575 if (!rtlpriv->dm.dm_initialgain_enable)
576 return;
577
578 if (digtable->dig_enable_flag == false)
579 return;
580
581 _rtl92s_dm_ctrl_initgain_bytwoport(hw);
582}
583
584static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
585{
586 struct rtl_priv *rtlpriv = rtl_priv(hw);
587 struct rtl_phy *rtlphy = &(rtlpriv->phy);
588 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
589 long undec_sm_pwdb;
590 long txpwr_threshold_lv1, txpwr_threshold_lv2;
591
592
593 if (rtlphy->rf_type == RF_2T2R)
594 return;
595
596 if (!rtlpriv->dm.dynamic_txpower_enable ||
597 rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
598 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
599 return;
600 }
601
602 if ((mac->link_state < MAC80211_LINKED) &&
603 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
604 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
605 "Not connected to any\n");
606
607 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
608
609 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
610 return;
611 }
612
613 if (mac->link_state >= MAC80211_LINKED) {
614 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
615 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
616 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
617 "AP Client PWDB = 0x%lx\n",
618 undec_sm_pwdb);
619 } else {
620 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
621 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
622 "STA Default Port PWDB = 0x%lx\n",
623 undec_sm_pwdb);
624 }
625 } else {
626 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
627
628 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
629 "AP Ext Port PWDB = 0x%lx\n",
630 undec_sm_pwdb);
631 }
632
633 txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
634 txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
635
636 if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
637 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
638 else if (undec_sm_pwdb >= txpwr_threshold_lv2)
639 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
640 else if ((undec_sm_pwdb < (txpwr_threshold_lv2 - 3)) &&
641 (undec_sm_pwdb >= txpwr_threshold_lv1))
642 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
643 else if (undec_sm_pwdb < (txpwr_threshold_lv1 - 3))
644 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
645
646 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
647 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
648
649 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
650}
651
652static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
653{
654 struct rtl_priv *rtlpriv = rtl_priv(hw);
655 struct dig_t *digtable = &rtlpriv->dm_digtable;
656
657
658 digtable->dig_enable_flag = true;
659 digtable->backoff_enable_flag = true;
660
661 if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
662 (hal_get_firmwareversion(rtlpriv) >= 0x3c))
663 digtable->dig_algorithm = DIG_ALGO_BY_TOW_PORT;
664 else
665 digtable->dig_algorithm =
666 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
667
668 digtable->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
669 digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
670
671 digtable->dig_dbgmode = DM_DBG_OFF;
672 digtable->dig_slgorithm_switch = 0;
673
674
675 digtable->dig_state = DM_STA_DIG_MAX;
676 digtable->dig_highpwrstate = DM_STA_DIG_MAX;
677
678 digtable->cur_sta_cstate = DIG_STA_DISCONNECT;
679 digtable->pre_sta_cstate = DIG_STA_DISCONNECT;
680 digtable->cur_ap_cstate = DIG_AP_DISCONNECT;
681 digtable->pre_ap_cstate = DIG_AP_DISCONNECT;
682
683 digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
684 digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
685
686 digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
687 digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
688
689 digtable->rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
690 digtable->rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
691
692
693 digtable->rssi_val = 50;
694 digtable->back_val = DM_DIG_BACKOFF;
695 digtable->rx_gain_max = DM_DIG_MAX;
696
697 digtable->rx_gain_min = DM_DIG_MIN;
698
699 digtable->backoffval_range_max = DM_DIG_BACKOFF_MAX;
700 digtable->backoffval_range_min = DM_DIG_BACKOFF_MIN;
701}
702
703static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706
707 if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
708 (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
709 rtlpriv->dm.dynamic_txpower_enable = true;
710 else
711 rtlpriv->dm.dynamic_txpower_enable = false;
712
713 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
714 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
715}
716
717void rtl92s_dm_init(struct ieee80211_hw *hw)
718{
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
720
721 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
722 rtlpriv->dm.undec_sm_pwdb = -1;
723
724 _rtl92s_dm_init_dynamic_txpower(hw);
725 rtl92s_dm_init_edca_turbo(hw);
726 _rtl92s_dm_init_rate_adaptive_mask(hw);
727 _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
728 _rtl92s_dm_init_dig(hw);
729
730 rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
731}
732
733void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
734{
735 _rtl92s_dm_check_edca_turbo(hw);
736 _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
737 _rtl92s_dm_ctrl_initgain_byrssi(hw);
738 _rtl92s_dm_dynamic_txpower(hw);
739 _rtl92s_dm_refresh_rateadaptive_mask(hw);
740 _rtl92s_dm_switch_baseband_mrc(hw);
741}
742
743
