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29#ifndef __REALTEK_FIRMWARE92S_H__
30#define __REALTEK_FIRMWARE92S_H__
31
32#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
33#define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE 90000
34#define RTL8190_CPU_START_OFFSET 0x80
35
36#define MAX_FIRMWARE_CODE_SIZE 0xFF00
37
38#define RT_8192S_FIRMWARE_HDR_SIZE 80
39#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
40
41
42#define MAX_DEV_ADDR_SIZE 8
43#define MAX_FIRMWARE_INFORMATION_SIZE 32
44#define MAX_802_11_HEADER_LENGTH (40 + \
45 MAX_FIRMWARE_INFORMATION_SIZE)
46#define ENCRYPTION_MAX_OVERHEAD 128
47#define MAX_FRAGMENT_COUNT 8
48#define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
49 (MAX_802_11_HEADER_LENGTH + \
50 ENCRYPTION_MAX_OVERHEAD) *\
51 MAX_FRAGMENT_COUNT)
52
53#define H2C_TX_CMD_HDR_LEN 8
54
55
56#define FW_DIG_ENABLE_CTL BIT(0)
57#define FW_HIGH_PWR_ENABLE_CTL BIT(1)
58#define FW_SS_CTL BIT(2)
59#define FW_RA_INIT_CTL BIT(3)
60#define FW_RA_BG_CTL BIT(4)
61#define FW_RA_N_CTL BIT(5)
62#define FW_PWR_TRK_CTL BIT(6)
63#define FW_IQK_CTL BIT(7)
64#define FW_FA_CTL BIT(8)
65#define FW_DRIVER_CTRL_DM_CTL BIT(9)
66#define FW_PAPE_CTL_BY_SW_HW BIT(10)
67#define FW_DISABLE_ALL_DM 0
68#define FW_PWR_TRK_PARAM_CLR 0x0000ffff
69#define FW_RA_PARAM_CLR 0xffff0000
70
71enum desc_packet_type {
72 DESC_PACKET_TYPE_INIT = 0,
73 DESC_PACKET_TYPE_NORMAL = 1,
74};
75
76
77struct fw_priv {
78
79
80 u8 signature_0;
81
82 u8 signature_1;
83
84
85 u8 hci_sel;
86
87 u8 chip_version;
88
89 u8 customer_id_0;
90
91 u8 customer_id_1;
92
93
94 u8 rf_config;
95
96 u8 usb_ep_num;
97
98
99
100 u8 regulatory_class_0;
101
102 u8 regulatory_class_1;
103
104 u8 regulatory_class_2;
105
106 u8 regulatory_class_3;
107
108 u8 rfintfs;
109 u8 def_nettype;
110 u8 rsvd010;
111 u8 rsvd011;
112
113
114
115 u8 lbk_mode;
116
117
118 u8 mp_mode;
119 u8 rsvd020;
120 u8 rsvd021;
121 u8 rsvd022;
122 u8 rsvd023;
123 u8 rsvd024;
124 u8 rsvd025;
125
126
127
128 u8 qos_en;
129
130
131 u8 bw_40mhz_en;
132 u8 amsdu2ampdu_en;
133
134 u8 ampdu_en;
135
136 u8 rate_control_offload;
137
138 u8 aggregation_offload;
139 u8 rsvd030;
140 u8 rsvd031;
141
142
143
144 u8 beacon_offload;
145
146 u8 mlme_offload;
147
148 u8 hwpc_offload;
149
150 u8 tcp_checksum_offload;
151
152 u8 tcp_offload;
153
154 u8 ps_control_offload;
155
156 u8 wwlan_offload;
157 u8 rsvd040;
158
159
160
161 u8 tcp_tx_frame_len_L;
162
163 u8 tcp_tx_frame_len_H;
164
165 u8 tcp_rx_frame_len_L;
166
167 u8 tcp_rx_frame_len_H;
168 u8 rsvd050;
169 u8 rsvd051;
170 u8 rsvd052;
171 u8 rsvd053;
172};
173
174
175struct fw_hdr {
176
177
178 u16 signature;
179
180
181 u16 version;
182
183 u32 dmem_size;
184
185
186
187
188 u32 img_imem_size;
189
190 u32 img_sram_size;
191
192
193
194 u32 fw_priv_size;
195 u32 rsvd0;
196
197
198 u32 rsvd1;
199 u32 rsvd2;
200
201 struct fw_priv fwpriv;
202
203} ;
204
205enum fw_status {
206 FW_STATUS_INIT = 0,
207 FW_STATUS_LOAD_IMEM = 1,
208 FW_STATUS_LOAD_EMEM = 2,
209 FW_STATUS_LOAD_DMEM = 3,
210 FW_STATUS_READY = 4,
211};
212
213struct rt_firmware {
214 struct fw_hdr *pfwheader;
215 enum fw_status fwstatus;
216 u16 firmwareversion;
217 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
218 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
219 u32 fw_imem_len;
220 u32 fw_emem_len;
221 u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE];
222 u32 sz_fw_tmpbufferlen;
223 u16 cmdpacket_fragthresold;
224};
225
226struct h2c_set_pwrmode_parm {
227 u8 mode;
228 u8 flag_low_traffic_en;
229 u8 flag_lpnav_en;
230 u8 flag_rf_low_snr_en;
231
232 u8 flag_dps_en;
233 u8 bcn_rx_en;
234 u8 bcn_pass_cnt;
235
236 u8 bcn_to;
237 u16 bcn_itv;
238
239 u8 app_itv;
240 u8 awake_bcn_itvl;
241 u8 smart_ps;
242
243 u8 bcn_pass_period;
244};
245
246struct h2c_joinbss_rpt_parm {
247 u8 opmode;
248 u8 ps_qos_info;
249 u8 bssid[6];
250 u16 bcnitv;
251 u16 aid;
252} ;
253
254struct h2c_wpa_ptk {
255
256 u8 kck[16];
257
258 u8 kek[16];
259
260 u8 tk1[16];
261 union {
262
263 u8 tk2[16];
264 struct {
265 u8 tx_mic_key[8];
266 u8 rx_mic_key[8];
267 } athu;
268 } u;
269};
270
271struct h2c_wpa_two_way_parm {
272
273 u8 pairwise_en_alg;
274 u8 group_en_alg;
275 struct h2c_wpa_ptk wpa_ptk_value;
276} ;
277
278enum h2c_cmd {
279 FW_H2C_SETPWRMODE = 0,
280 FW_H2C_JOINBSSRPT = 1,
281 FW_H2C_WOWLAN_UPDATE_GTK = 2,
282 FW_H2C_WOWLAN_UPDATE_IV = 3,
283 FW_H2C_WOWLAN_OFFLOAD = 4,
284};
285
286enum fw_h2c_cmd {
287 H2C_READ_MACREG_CMD,
288 H2C_WRITE_MACREG_CMD,
289 H2C_READBB_CMD,
290 H2C_WRITEBB_CMD,
291 H2C_READRF_CMD,
292 H2C_WRITERF_CMD,
293 H2C_READ_EEPROM_CMD,
294 H2C_WRITE_EEPROM_CMD,
295 H2C_READ_EFUSE_CMD,
296 H2C_WRITE_EFUSE_CMD,
297 H2C_READ_CAM_CMD,
298 H2C_WRITE_CAM_CMD,
299 H2C_SETBCNITV_CMD,
300 H2C_SETMBIDCFG_CMD,
301 H2C_JOINBSS_CMD,
302 H2C_DISCONNECT_CMD,
303 H2C_CREATEBSS_CMD,
304 H2C_SETOPMode_CMD,
305 H2C_SITESURVEY_CMD,
306 H2C_SETAUTH_CMD,
307 H2C_SETKEY_CMD,
308 H2C_SETSTAKEY_CMD,
309 H2C_SETASSOCSTA_CMD,
310 H2C_DELASSOCSTA_CMD,
311 H2C_SETSTAPWRSTATE_CMD,
312 H2C_SETBASICRATE_CMD,
313 H2C_GETBASICRATE_CMD,
314 H2C_SETDATARATE_CMD,
315 H2C_GETDATARATE_CMD,
316 H2C_SETPHYINFO_CMD,
317 H2C_GETPHYINFO_CMD,
318 H2C_SETPHY_CMD,
319 H2C_GETPHY_CMD,
320 H2C_READRSSI_CMD,
321 H2C_READGAIN_CMD,
322 H2C_SETATIM_CMD,
323 H2C_SETPWRMODE_CMD,
324 H2C_JOINBSSRPT_CMD,
325 H2C_SETRATABLE_CMD,
326 H2C_GETRATABLE_CMD,
327 H2C_GETCCXREPORT_CMD,
328 H2C_GETDTMREPORT_CMD,
329 H2C_GETTXRATESTATICS_CMD,
330 H2C_SETUSBSUSPEND_CMD,
331 H2C_SETH2CLBK_CMD,
332 H2C_TMP1,
333 H2C_WOWLAN_UPDATE_GTK_CMD,
334 H2C_WOWLAN_FW_OFFLOAD,
335 H2C_TMP2,
336 H2C_TMP3,
337 H2C_WOWLAN_UPDATE_IV_CMD,
338 H2C_TMP4,
339 MAX_H2CCMD
340};
341
342
343
344#define FW_CMD_IO_CLR(rtlpriv, _Bit) \
345 do { \
346 udelay(1000); \
347 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
348 } while (0)
349
350#define FW_CMD_IO_UPDATE(rtlpriv, _val) \
351 rtlpriv->rtlhal.fwcmd_iomap = _val;
352
353#define FW_CMD_IO_SET(rtlpriv, _val) \
354 do { \
355 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
356 FW_CMD_IO_UPDATE(rtlpriv, _val); \
357 } while (0)
358
359#define FW_CMD_PARA_SET(rtlpriv, _val) \
360 do { \
361 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
362 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
363 } while (0)
364
365#define FW_CMD_IO_QUERY(rtlpriv) \
366 (u16)(rtlpriv->rtlhal.fwcmd_iomap)
367#define FW_CMD_IO_PARA_QUERY(rtlpriv) \
368 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
369
370int rtl92s_download_fw(struct ieee80211_hw *hw);
371void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
372void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
373 u8 mstatus, u8 ps_qosinfo);
374
375#endif
376
377