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22#ifndef __WLCORE_H__
23#define __WLCORE_H__
24
25#include <linux/platform_device.h>
26
27#include "wlcore_i.h"
28#include "event.h"
29#include "boot.h"
30
31
32#define WLCORE_MAX_TX_DESCRIPTORS 32
33
34
35
36
37
38#define WLCORE_NUM_MAC_ADDRESSES 3
39
40
41#define WLCORE_MAX_TXPWR 25
42
43
44struct wl1271_tx_hw_descr;
45enum wl_rx_buf_align;
46struct wl1271_rx_descriptor;
47
48struct wlcore_ops {
49 int (*setup)(struct wl1271 *wl);
50 int (*identify_chip)(struct wl1271 *wl);
51 int (*identify_fw)(struct wl1271 *wl);
52 int (*boot)(struct wl1271 *wl);
53 int (*plt_init)(struct wl1271 *wl);
54 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
55 void *buf, size_t len);
56 int (*ack_event)(struct wl1271 *wl);
57 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
58 bool *timeout);
59 int (*process_mailbox_events)(struct wl1271 *wl);
60 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
61 void (*set_tx_desc_blocks)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
63 u32 blks, u32 spare_blks);
64 void (*set_tx_desc_data_len)(struct wl1271 *wl,
65 struct wl1271_tx_hw_descr *desc,
66 struct sk_buff *skb);
67 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
68 u32 rx_desc);
69 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
70 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
71 u32 data_len);
72 int (*tx_delayed_compl)(struct wl1271 *wl);
73 void (*tx_immediate_compl)(struct wl1271 *wl);
74 int (*hw_init)(struct wl1271 *wl);
75 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
76 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
77 struct wl12xx_vif *wlvif);
78 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
79 int (*get_mac)(struct wl1271 *wl);
80 void (*set_tx_desc_csum)(struct wl1271 *wl,
81 struct wl1271_tx_hw_descr *desc,
82 struct sk_buff *skb);
83 void (*set_rx_csum)(struct wl1271 *wl,
84 struct wl1271_rx_descriptor *desc,
85 struct sk_buff *skb);
86 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
87 struct wl12xx_vif *wlvif);
88 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
89 int (*handle_static_data)(struct wl1271 *wl,
90 struct wl1271_static_data *static_data);
91 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
92 struct cfg80211_scan_request *req);
93 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
94 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
95 struct cfg80211_sched_scan_request *req,
96 struct ieee80211_sched_scan_ies *ies);
97 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
98 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
99 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
100 struct ieee80211_vif *vif,
101 struct ieee80211_sta *sta,
102 struct ieee80211_key_conf *key_conf);
103 int (*channel_switch)(struct wl1271 *wl,
104 struct wl12xx_vif *wlvif,
105 struct ieee80211_channel_switch *ch_switch);
106 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
107 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
108 struct ieee80211_sta *sta, u32 changed);
109 int (*set_peer_cap)(struct wl1271 *wl,
110 struct ieee80211_sta_ht_cap *ht_cap,
111 bool allow_ht_operation,
112 u32 rate_set, u8 hlid);
113 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
114 struct wl1271_link *lnk);
115 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
116 struct wl1271_link *lnk);
117};
118
119enum wlcore_partitions {
120 PART_DOWN,
121 PART_WORK,
122 PART_BOOT,
123 PART_DRPW,
124 PART_TOP_PRCM_ELP_SOC,
125 PART_PHY_INIT,
126
127 PART_TABLE_LEN,
128};
129
130struct wlcore_partition {
131 u32 size;
132 u32 start;
133};
134
135struct wlcore_partition_set {
136 struct wlcore_partition mem;
137 struct wlcore_partition reg;
138 struct wlcore_partition mem2;
139 struct wlcore_partition mem3;
140};
141
142enum wlcore_registers {
143
144 REG_ECPU_CONTROL,
145 REG_INTERRUPT_NO_CLEAR,
146 REG_INTERRUPT_ACK,
147 REG_COMMAND_MAILBOX_PTR,
148 REG_EVENT_MAILBOX_PTR,
149 REG_INTERRUPT_TRIG,
150 REG_INTERRUPT_MASK,
151 REG_PC_ON_RECOVERY,
152 REG_CHIP_ID_B,
153 REG_CMD_MBOX_ADDRESS,
154
155
156 REG_SLV_MEM_DATA,
157 REG_SLV_REG_DATA,
158
159
160 REG_RAW_FW_STATUS_ADDR,
161
162 REG_TABLE_LEN,
163};
164
165struct wl1271_stats {
166 void *fw_stats;
167 unsigned long fw_stats_update;
168 size_t fw_stats_len;
169
170 unsigned int retry_count;
171 unsigned int excessive_retries;
172};
173
174struct wl1271 {
175 bool initialized;
176 struct ieee80211_hw *hw;
177 bool mac80211_registered;
178
179 struct device *dev;
180 struct platform_device *pdev;
181
182 void *if_priv;
183
184 struct wl1271_if_operations *if_ops;
185
186 int irq;
187
188 spinlock_t wl_lock;
189
190 enum wlcore_state state;
191 enum wl12xx_fw_type fw_type;
192 bool plt;
193 enum plt_mode plt_mode;
194 u8 fem_manuf;
195 u8 last_vif_count;
196 struct mutex mutex;
197
198 unsigned long flags;
199
200 struct wlcore_partition_set curr_part;
201
202 struct wl1271_chip chip;
203
204 int cmd_box_addr;
205
206 u8 *fw;
207 size_t fw_len;
208 void *nvs;
209 size_t nvs_len;
210
211 s8 hw_pg_ver;
212
213
214 u32 fuse_oui_addr;
215 u32 fuse_nic_addr;
216
217
218 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
219 int channel;
220 u8 system_hlid;
221
222 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
223 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
224 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
225 unsigned long rate_policies_map[
226 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
227 unsigned long klv_templates_map[
228 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
229
230 u8 session_ids[WL12XX_MAX_LINKS];
231
232 struct list_head wlvif_list;
233
234 u8 sta_count;
235 u8 ap_count;
236
237 struct wl1271_acx_mem_map *target_mem_map;
238
239
240 u32 tx_blocks_freed;
241 u32 tx_blocks_available;
242 u32 tx_allocated_blocks;
243 u32 tx_results_count;
244
245
246 u32 tx_pkts_freed[NUM_TX_QUEUES];
247 u32 tx_allocated_pkts[NUM_TX_QUEUES];
248
249
250 u32 tx_packets_count;
251
252
253 s64 time_offset;
254
255
256 int tx_queue_count[NUM_TX_QUEUES];
257 unsigned long queue_stop_reasons[
258 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
259
260
261 struct sk_buff_head deferred_rx_queue;
262
263
264 struct sk_buff_head deferred_tx_queue;
265
266 struct work_struct tx_work;
267 struct workqueue_struct *freezable_wq;
268
269
270 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
271 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
272 int tx_frames_cnt;
273
274
275 u32 rx_counter;
276
277
278 u8 *aggr_buf;
279 u32 aggr_buf_size;
280
281
282 struct sk_buff *dummy_packet;
283
284
285 struct work_struct netstack_work;
286
287
288 u8 *fwlog;
289
290
291 ssize_t fwlog_size;
292
293
294 wait_queue_head_t fwlog_waitq;
295
296
297 struct work_struct recovery_work;
298 bool watchdog_recovery;
299
300
301 u32 reg_ch_conf_last[2];
302
303 u32 reg_ch_conf_pending[2];
304
305
306 void *mbox;
307
308
309 u32 event_mask;
310
311
312 u32 mbox_size;
313 u32 mbox_ptr[2];
314
315
316 struct wl12xx_vif *scan_wlvif;
317 struct wl1271_scan scan;
318 struct delayed_work scan_complete_work;
319
320 struct ieee80211_vif *roc_vif;
321 struct delayed_work roc_complete_work;
322
323 struct wl12xx_vif *sched_vif;
324
325
326 enum ieee80211_band band;
327
328 struct completion *elp_compl;
329 struct delayed_work elp_work;
330
331
332 int power_level;
333
334 struct wl1271_stats stats;
335
336 __le32 *buffer_32;
337 u32 buffer_cmd;
338 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
339
340 struct wl_fw_status_1 *fw_status_1;
341 struct wl_fw_status_2 *fw_status_2;
342 struct wl1271_tx_hw_res_if *tx_res_if;
343
344
345 struct wlcore_conf conf;
346
347 bool sg_enabled;
348
349 bool enable_11a;
350
351 int recovery_count;
352
353
354 s8 noise;
355
356
357 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
358
359
360
361
362
363 bool wow_enabled;
364 bool irq_wake_enabled;
365
366
367
368
369
370 struct wl1271_link links[WL12XX_MAX_LINKS];
371
372
373 int active_link_count;
374
375
376 u32 fw_fast_lnk_map;
377
378
379 u32 ap_fw_ps_map;
380
381
382 unsigned long ap_ps_map;
383
384
385 unsigned int quirks;
386
387
388 unsigned int platform_quirks;
389
390
391 int ba_rx_session_count;
392
393
394 int ba_rx_session_count_max;
395
396
397 int active_sta_count;
398
399
400 struct wl12xx_vif *last_wlvif;
401
402
403 struct delayed_work tx_watchdog_work;
404
405 struct wlcore_ops *ops;
406
407 const struct wlcore_partition_set *ptable;
408
409 const int *rtable;
410
411 const char *plt_fw_name;
412 const char *sr_fw_name;
413 const char *mr_fw_name;
414
415 u8 scan_templ_id_2_4;
416 u8 scan_templ_id_5;
417 u8 sched_scan_templ_id_2_4;
418 u8 sched_scan_templ_id_5;
419 u8 max_channels_5;
420
421
422 void *priv;
423
424
425 u32 num_tx_desc;
426
427 u32 num_rx_desc;
428
429
430 const u8 **band_rate_to_idx;
431
432
433 u8 hw_tx_rate_tbl_size;
434
435
436 u8 hw_min_ht_rate;
437
438
439 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
440
441
442 size_t fw_status_priv_len;
443
444
445 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
446
447
448 size_t static_data_priv_len;
449
450
451 enum nl80211_channel_type channel_type;
452
453
454 struct mutex flush_mutex;
455
456
457 int sleep_auth;
458
459
460 int num_mac_addr;
461
462
463 unsigned int min_sr_fw_ver[NUM_FW_VER];
464
465
466 unsigned int min_mr_fw_ver[NUM_FW_VER];
467
468 struct completion nvs_loading_complete;
469
470
471 u32 num_channels;
472};
473
474int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
475int wlcore_remove(struct platform_device *pdev);
476struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
477 u32 mbox_size);
478int wlcore_free_hw(struct wl1271 *wl);
479int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
480 struct ieee80211_vif *vif,
481 struct ieee80211_sta *sta,
482 struct ieee80211_key_conf *key_conf);
483void wlcore_regdomain_config(struct wl1271 *wl);
484
485static inline void
486wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
487 struct ieee80211_sta_ht_cap *ht_cap)
488{
489 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
490}
491
492
493#define WLCORE_FW_VER_IGNORE -1
494
495static inline void
496wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
497 unsigned int iftype_sr, unsigned int major_sr,
498 unsigned int subtype_sr, unsigned int minor_sr,
499 unsigned int iftype_mr, unsigned int major_mr,
500 unsigned int subtype_mr, unsigned int minor_mr)
501{
502 wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
503 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
504 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
505 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
506 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
507
508 wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
509 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
510 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
511 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
512 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
513}
514
515
516#define CHUNK_SIZE 16384
517
518
519
520
521#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
522
523
524#define WLCORE_QUIRK_START_STA_FAILS BIT(1)
525
526
527#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
528
529
530#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
531
532
533#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
534
535
536#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
537
538
539#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
540
541
542#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
543
544
545#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
546
547
548#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
549
550
551#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
552
553
554#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12)
555
556
557#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
558
559
560#define ELPCTRL_WAKE_UP 0x1
561#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
562#define ELPCTRL_SLEEP 0x0
563
564#define ELPCTRL_WLAN_READY 0x2
565
566
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576
577
578
579#define INTR_TRIG_TX_PROC0 BIT(2)
580
581
582
583
584
585
586#define INTR_TRIG_RX_PROC0 BIT(3)
587
588#define INTR_TRIG_DEBUG_ACK BIT(4)
589
590#define INTR_TRIG_STATE_CHANGED BIT(5)
591
592
593
594
595
596
597
598
599#define INTR_TRIG_RX_PROC1 BIT(17)
600
601
602
603
604
605
606#define INTR_TRIG_TX_PROC1 BIT(18)
607
608#define ACX_SLV_SOFT_RESET_BIT BIT(1)
609#define SOFT_RESET_MAX_TIME 1000000
610#define SOFT_RESET_STALL_TIME 1000
611
612#define ECPU_CONTROL_HALT 0x00000101
613
614#define WELP_ARM_COMMAND_VAL 0x4
615
616#endif
617