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10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/log2.h>
20#include <linux/pci-aspm.h>
21#include <linux/pm_wakeup.h>
22#include <linux/interrupt.h>
23#include <linux/device.h>
24#include <linux/pm_runtime.h>
25#include <asm-generic/pci-bridge.h>
26#include <asm/setup.h>
27#include "pci.h"
28
29const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31};
32EXPORT_SYMBOL_GPL(pci_power_names);
33
34int isa_dma_bridge_buggy;
35EXPORT_SYMBOL(isa_dma_bridge_buggy);
36
37int pci_pci_problems;
38EXPORT_SYMBOL(pci_pci_problems);
39
40unsigned int pci_pm_d3_delay;
41
42static void pci_pme_list_scan(struct work_struct *work);
43
44static LIST_HEAD(pci_pme_list);
45static DEFINE_MUTEX(pci_pme_list_mutex);
46static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47
48struct pci_pme_device {
49 struct list_head list;
50 struct pci_dev *dev;
51};
52
53#define PME_TIMEOUT 1000
54
55static void pci_dev_d3_sleep(struct pci_dev *dev)
56{
57 unsigned int delay = dev->d3_delay;
58
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
61
62 msleep(delay);
63}
64
65#ifdef CONFIG_PCI_DOMAINS
66int pci_domains_supported = 1;
67#endif
68
69#define DEFAULT_CARDBUS_IO_SIZE (256)
70#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71
72unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74
75#define DEFAULT_HOTPLUG_IO_SIZE (256)
76#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77
78unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80
81enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
82
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86
87
88
89u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
90u8 pci_cache_line_size;
91
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93
94
95
96unsigned int pcibios_max_latency = 255;
97
98
99static bool pcie_ari_disabled;
100
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107
108unsigned char pci_bus_max_busnr(struct pci_bus* bus)
109{
110 struct list_head *tmp;
111 unsigned char max, n;
112
113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max)
117 max = n;
118 }
119 return max;
120}
121EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
122
123#ifdef CONFIG_HAS_IOMEM
124void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
125{
126
127
128
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
130 WARN_ON(1);
131 return NULL;
132 }
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
135}
136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif
138
139#define PCI_FIND_CAP_TTL 48
140
141static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
143{
144 u8 id;
145
146 while ((*ttl)--) {
147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
148 if (pos < 0x40)
149 break;
150 pos &= ~3;
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
152 &id);
153 if (id == 0xff)
154 break;
155 if (id == cap)
156 return pos;
157 pos += PCI_CAP_LIST_NEXT;
158 }
159 return 0;
160}
161
162static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
163 u8 pos, int cap)
164{
165 int ttl = PCI_FIND_CAP_TTL;
166
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
168}
169
170int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
171{
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
174}
175EXPORT_SYMBOL_GPL(pci_find_next_capability);
176
177static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
179{
180 u16 status;
181
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
184 return 0;
185
186 switch (hdr_type) {
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
189 return PCI_CAPABILITY_LIST;
190 case PCI_HEADER_TYPE_CARDBUS:
191 return PCI_CB_CAPABILITY_LIST;
192 default:
193 return 0;
194 }
195
196 return 0;
197}
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217
218int pci_find_capability(struct pci_dev *dev, int cap)
219{
220 int pos;
221
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
223 if (pos)
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
225
226 return pos;
227}
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241
242int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
243{
244 int pos;
245 u8 hdr_type;
246
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
248
249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
250 if (pos)
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
252
253 return pos;
254}
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266
267int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
268{
269 u32 header;
270 int ttl;
271 int pos = PCI_CFG_SPACE_SIZE;
272
273
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
275
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
277 return 0;
278
279 if (start)
280 pos = start;
281
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
283 return 0;
284
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287
288
289 if (header == 0)
290 return 0;
291
292 while (ttl-- > 0) {
293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
294 return pos;
295
296 pos = PCI_EXT_CAP_NEXT(header);
297 if (pos < PCI_CFG_SPACE_SIZE)
298 break;
299
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
301 break;
302 }
303
304 return 0;
305}
306EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
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321
322int pci_find_ext_capability(struct pci_dev *dev, int cap)
323{
324 return pci_find_next_ext_capability(dev, 0, cap);
325}
326EXPORT_SYMBOL_GPL(pci_find_ext_capability);
327
328static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
329{
330 int rc, ttl = PCI_FIND_CAP_TTL;
331 u8 cap, mask;
332
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
335 else
336 mask = HT_5BIT_CAP_MASK;
337
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
340 while (pos) {
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
343 return 0;
344
345 if ((cap & mask) == ht_cap)
346 return pos;
347
348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
350 PCI_CAP_ID_HT, &ttl);
351 }
352
353 return 0;
354}
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367
368int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
369{
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
371}
372EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
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385int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
386{
387 int pos;
388
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
390 if (pos)
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
392
393 return pos;
394}
395EXPORT_SYMBOL_GPL(pci_find_ht_capability);
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404
405
406struct resource *
407pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
408{
409 const struct pci_bus *bus = dev->bus;
410 int i;
411 struct resource *best = NULL, *r;
412
413 pci_bus_for_each_resource(bus, r, i) {
414 if (!r)
415 continue;
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue;
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue;
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r;
422
423 if (r->flags & IORESOURCE_PREFETCH)
424 continue;
425
426 if (!best)
427 best = r;
428 }
429 return best;
430}
431
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438
439static void
440pci_restore_bars(struct pci_dev *dev)
441{
442 int i;
443
444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
445 pci_update_resource(dev, i);
446}
447
448static struct pci_platform_pm_ops *pci_platform_pm;
449
450int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
451{
452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
453 || !ops->sleep_wake)
454 return -EINVAL;
455 pci_platform_pm = ops;
456 return 0;
457}
458
459static inline bool platform_pci_power_manageable(struct pci_dev *dev)
460{
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
462}
463
464static inline int platform_pci_set_power_state(struct pci_dev *dev,
465 pci_power_t t)
466{
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
468}
469
470static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
471{
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
474}
475
476static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
477{
478 return pci_platform_pm ?
479 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
480}
481
482static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
483{
484 return pci_platform_pm ?
485 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
486}
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500
501static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
502{
503 u16 pmcsr;
504 bool need_restore = false;
505
506
507 if (dev->current_state == state)
508 return 0;
509
510 if (!dev->pm_cap)
511 return -EIO;
512
513 if (state < PCI_D0 || state > PCI_D3hot)
514 return -EINVAL;
515
516
517
518
519
520 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
521 && dev->current_state > state) {
522 dev_err(&dev->dev, "invalid power transition "
523 "(from state %d to %d)\n", dev->current_state, state);
524 return -EINVAL;
525 }
526
527
528 if ((state == PCI_D1 && !dev->d1_support)
529 || (state == PCI_D2 && !dev->d2_support))
530 return -EIO;
531
532 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
533
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537
538 switch (dev->current_state) {
539 case PCI_D0:
540 case PCI_D1:
541 case PCI_D2:
542 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
543 pmcsr |= state;
544 break;
545 case PCI_D3hot:
546 case PCI_D3cold:
547 case PCI_UNKNOWN:
548 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
549 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
550 need_restore = true;
551
552 default:
553 pmcsr = 0;
554 break;
555 }
556
557
558 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
559
560
561
562 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
563 pci_dev_d3_sleep(dev);
564 else if (state == PCI_D2 || dev->current_state == PCI_D2)
565 udelay(PCI_PM_D2_DELAY);
566
567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
569 if (dev->current_state != state && printk_ratelimit())
570 dev_info(&dev->dev, "Refused to change power state, "
571 "currently in D%d\n", dev->current_state);
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586 if (need_restore)
587 pci_restore_bars(dev);
588
589 if (dev->bus->self)
590 pcie_aspm_pm_state_change(dev->bus->self);
591
592 return 0;
593}
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599
600
601void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
602{
603 if (dev->pm_cap) {
604 u16 pmcsr;
605
606
607
608
609
610 if (dev->current_state == PCI_D3cold)
611 return;
612 if (state == PCI_D3cold) {
613 dev->current_state = PCI_D3cold;
614 return;
615 }
616 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
617 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
618 } else {
619 dev->current_state = state;
620 }
621}
622
623
624
625
626
627void pci_power_up(struct pci_dev *dev)
628{
629 if (platform_pci_power_manageable(dev))
630 platform_pci_set_power_state(dev, PCI_D0);
631
632 pci_raw_set_power_state(dev, PCI_D0);
633 pci_update_current_state(dev, PCI_D0);
634}
635
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639
640
641static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
642{
643 int error;
644
645 if (platform_pci_power_manageable(dev)) {
646 error = platform_pci_set_power_state(dev, state);
647 if (!error)
648 pci_update_current_state(dev, state);
649 } else
650 error = -ENODEV;
651
652 if (error && !dev->pm_cap)
653 dev->current_state = PCI_D0;
654
655 return error;
656}
657
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661
662
663static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
664{
665 if (state == PCI_D0) {
666 pci_platform_power_transition(dev, PCI_D0);
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668
669
670
671
672
673
674 if (dev->runtime_d3cold) {
675 msleep(dev->d3cold_delay);
676
677
678
679
680
681
682 pci_wakeup_bus(dev->subordinate);
683 }
684 }
685}
686
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690
691
692static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
693{
694 pci_power_t state = *(pci_power_t *)data;
695
696 dev->current_state = state;
697 return 0;
698}
699
700
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703
704
705static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
706{
707 if (bus)
708 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
709}
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716
717
718int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
719{
720 int ret;
721
722 if (state <= PCI_D0)
723 return -EINVAL;
724 ret = pci_platform_power_transition(dev, state);
725
726 if (!ret && state == PCI_D3cold)
727 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
728 return ret;
729}
730EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
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745
746
747int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
748{
749 int error;
750
751
752 if (state > PCI_D3cold)
753 state = PCI_D3cold;
754 else if (state < PCI_D0)
755 state = PCI_D0;
756 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
757
758
759
760
761
762 return 0;
763
764
765 if (dev->current_state == state)
766 return 0;
767
768 __pci_start_power_transition(dev, state);
769
770
771
772 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
773 return 0;
774
775
776
777
778
779 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
780 PCI_D3hot : state);
781
782 if (!__pci_complete_power_transition(dev, state))
783 error = 0;
784
785
786
787
788 if (!error && dev->bus->self)
789 pcie_aspm_powersave_config_link(dev->bus->self);
790
791 return error;
792}
793
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803
804pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
805{
806 pci_power_t ret;
807
808 if (!dev->pm_cap)
809 return PCI_D0;
810
811 ret = platform_pci_choose_state(dev);
812 if (ret != PCI_POWER_ERROR)
813 return ret;
814
815 switch (state.event) {
816 case PM_EVENT_ON:
817 return PCI_D0;
818 case PM_EVENT_FREEZE:
819 case PM_EVENT_PRETHAW:
820
821 case PM_EVENT_SUSPEND:
822 case PM_EVENT_HIBERNATE:
823 return PCI_D3hot;
824 default:
825 dev_info(&dev->dev, "unrecognized suspend event %d\n",
826 state.event);
827 BUG();
828 }
829 return PCI_D0;
830}
831
832EXPORT_SYMBOL(pci_choose_state);
833
834#define PCI_EXP_SAVE_REGS 7
835
836
837static struct pci_cap_saved_state *pci_find_saved_cap(
838 struct pci_dev *pci_dev, char cap)
839{
840 struct pci_cap_saved_state *tmp;
841
842 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
843 if (tmp->cap.cap_nr == cap)
844 return tmp;
845 }
846 return NULL;
847}
848
849static int pci_save_pcie_state(struct pci_dev *dev)
850{
851 int i = 0;
852 struct pci_cap_saved_state *save_state;
853 u16 *cap;
854
855 if (!pci_is_pcie(dev))
856 return 0;
857
858 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
859 if (!save_state) {
860 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
861 return -ENOMEM;
862 }
863
864 cap = (u16 *)&save_state->cap.data[0];
865 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
866 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
872
873 return 0;
874}
875
876static void pci_restore_pcie_state(struct pci_dev *dev)
877{
878 int i = 0;
879 struct pci_cap_saved_state *save_state;
880 u16 *cap;
881
882 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
883 if (!save_state)
884 return;
885
886 cap = (u16 *)&save_state->cap.data[0];
887 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
888 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
894}
895
896
897static int pci_save_pcix_state(struct pci_dev *dev)
898{
899 int pos;
900 struct pci_cap_saved_state *save_state;
901
902 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
903 if (pos <= 0)
904 return 0;
905
906 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
907 if (!save_state) {
908 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
909 return -ENOMEM;
910 }
911
912 pci_read_config_word(dev, pos + PCI_X_CMD,
913 (u16 *)save_state->cap.data);
914
915 return 0;
916}
917
918static void pci_restore_pcix_state(struct pci_dev *dev)
919{
920 int i = 0, pos;
921 struct pci_cap_saved_state *save_state;
922 u16 *cap;
923
924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
925 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
926 if (!save_state || pos <= 0)
927 return;
928 cap = (u16 *)&save_state->cap.data[0];
929
930 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
931}
932
933
934
935
936
937
938int
939pci_save_state(struct pci_dev *dev)
940{
941 int i;
942
943 for (i = 0; i < 16; i++)
944 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
945 dev->state_saved = true;
946 if ((i = pci_save_pcie_state(dev)) != 0)
947 return i;
948 if ((i = pci_save_pcix_state(dev)) != 0)
949 return i;
950 return 0;
951}
952
953static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
954 u32 saved_val, int retry)
955{
956 u32 val;
957
958 pci_read_config_dword(pdev, offset, &val);
959 if (val == saved_val)
960 return;
961
962 for (;;) {
963 dev_dbg(&pdev->dev, "restoring config space at offset "
964 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
965 pci_write_config_dword(pdev, offset, saved_val);
966 if (retry-- <= 0)
967 return;
968
969 pci_read_config_dword(pdev, offset, &val);
970 if (val == saved_val)
971 return;
972
973 mdelay(1);
974 }
975}
976
977static void pci_restore_config_space_range(struct pci_dev *pdev,
978 int start, int end, int retry)
979{
980 int index;
981
982 for (index = end; index >= start; index--)
983 pci_restore_config_dword(pdev, 4 * index,
984 pdev->saved_config_space[index],
985 retry);
986}
987
988static void pci_restore_config_space(struct pci_dev *pdev)
989{
990 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
991 pci_restore_config_space_range(pdev, 10, 15, 0);
992
993 pci_restore_config_space_range(pdev, 4, 9, 10);
994 pci_restore_config_space_range(pdev, 0, 3, 0);
995 } else {
996 pci_restore_config_space_range(pdev, 0, 15, 0);
997 }
998}
999
1000
1001
1002
1003
1004void pci_restore_state(struct pci_dev *dev)
1005{
1006 if (!dev->state_saved)
1007 return;
1008
1009
1010 pci_restore_pcie_state(dev);
1011 pci_restore_ats_state(dev);
1012
1013 pci_restore_config_space(dev);
1014
1015 pci_restore_pcix_state(dev);
1016 pci_restore_msi_state(dev);
1017 pci_restore_iov_state(dev);
1018
1019 dev->state_saved = false;
1020}
1021
1022struct pci_saved_state {
1023 u32 config_space[16];
1024 struct pci_cap_saved_data cap[0];
1025};
1026
1027
1028
1029
1030
1031
1032
1033
1034struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1035{
1036 struct pci_saved_state *state;
1037 struct pci_cap_saved_state *tmp;
1038 struct pci_cap_saved_data *cap;
1039 size_t size;
1040
1041 if (!dev->state_saved)
1042 return NULL;
1043
1044 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1045
1046 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1047 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1048
1049 state = kzalloc(size, GFP_KERNEL);
1050 if (!state)
1051 return NULL;
1052
1053 memcpy(state->config_space, dev->saved_config_space,
1054 sizeof(state->config_space));
1055
1056 cap = state->cap;
1057 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1058 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1059 memcpy(cap, &tmp->cap, len);
1060 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1061 }
1062
1063
1064 return state;
1065}
1066EXPORT_SYMBOL_GPL(pci_store_saved_state);
1067
1068
1069
1070
1071
1072
1073int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1074{
1075 struct pci_cap_saved_data *cap;
1076
1077 dev->state_saved = false;
1078
1079 if (!state)
1080 return 0;
1081
1082 memcpy(dev->saved_config_space, state->config_space,
1083 sizeof(state->config_space));
1084
1085 cap = state->cap;
1086 while (cap->size) {
1087 struct pci_cap_saved_state *tmp;
1088
1089 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1090 if (!tmp || tmp->cap.size != cap->size)
1091 return -EINVAL;
1092
1093 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1094 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1095 sizeof(struct pci_cap_saved_data) + cap->size);
1096 }
1097
1098 dev->state_saved = true;
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(pci_load_saved_state);
1102
1103
1104
1105
1106
1107
1108
1109int pci_load_and_free_saved_state(struct pci_dev *dev,
1110 struct pci_saved_state **state)
1111{
1112 int ret = pci_load_saved_state(dev, *state);
1113 kfree(*state);
1114 *state = NULL;
1115 return ret;
1116}
1117EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1118
1119static int do_pci_enable_device(struct pci_dev *dev, int bars)
1120{
1121 int err;
1122
1123 err = pci_set_power_state(dev, PCI_D0);
1124 if (err < 0 && err != -EIO)
1125 return err;
1126 err = pcibios_enable_device(dev, bars);
1127 if (err < 0)
1128 return err;
1129 pci_fixup_device(pci_fixup_enable, dev);
1130
1131 return 0;
1132}
1133
1134
1135
1136
1137
1138
1139
1140
1141int pci_reenable_device(struct pci_dev *dev)
1142{
1143 if (pci_is_enabled(dev))
1144 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1145 return 0;
1146}
1147
1148static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1149{
1150 int err;
1151 int i, bars = 0;
1152
1153
1154
1155
1156
1157
1158
1159 if (dev->pm_cap) {
1160 u16 pmcsr;
1161 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1162 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1163 }
1164
1165 if (atomic_inc_return(&dev->enable_cnt) > 1)
1166 return 0;
1167
1168
1169 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1170 if (dev->resource[i].flags & flags)
1171 bars |= (1 << i);
1172 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1173 if (dev->resource[i].flags & flags)
1174 bars |= (1 << i);
1175
1176 err = do_pci_enable_device(dev, bars);
1177 if (err < 0)
1178 atomic_dec(&dev->enable_cnt);
1179 return err;
1180}
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190int pci_enable_device_io(struct pci_dev *dev)
1191{
1192 return pci_enable_device_flags(dev, IORESOURCE_IO);
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203int pci_enable_device_mem(struct pci_dev *dev)
1204{
1205 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1206}
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219int pci_enable_device(struct pci_dev *dev)
1220{
1221 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1222}
1223
1224
1225
1226
1227
1228
1229
1230struct pci_devres {
1231 unsigned int enabled:1;
1232 unsigned int pinned:1;
1233 unsigned int orig_intx:1;
1234 unsigned int restore_intx:1;
1235 u32 region_mask;
1236};
1237
1238static void pcim_release(struct device *gendev, void *res)
1239{
1240 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1241 struct pci_devres *this = res;
1242 int i;
1243
1244 if (dev->msi_enabled)
1245 pci_disable_msi(dev);
1246 if (dev->msix_enabled)
1247 pci_disable_msix(dev);
1248
1249 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1250 if (this->region_mask & (1 << i))
1251 pci_release_region(dev, i);
1252
1253 if (this->restore_intx)
1254 pci_intx(dev, this->orig_intx);
1255
1256 if (this->enabled && !this->pinned)
1257 pci_disable_device(dev);
1258}
1259
1260static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1261{
1262 struct pci_devres *dr, *new_dr;
1263
1264 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1265 if (dr)
1266 return dr;
1267
1268 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1269 if (!new_dr)
1270 return NULL;
1271 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1272}
1273
1274static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1275{
1276 if (pci_is_managed(pdev))
1277 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1278 return NULL;
1279}
1280
1281
1282
1283
1284
1285
1286
1287int pcim_enable_device(struct pci_dev *pdev)
1288{
1289 struct pci_devres *dr;
1290 int rc;
1291
1292 dr = get_pci_dr(pdev);
1293 if (unlikely(!dr))
1294 return -ENOMEM;
1295 if (dr->enabled)
1296 return 0;
1297
1298 rc = pci_enable_device(pdev);
1299 if (!rc) {
1300 pdev->is_managed = 1;
1301 dr->enabled = 1;
1302 }
1303 return rc;
1304}
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314void pcim_pin_device(struct pci_dev *pdev)
1315{
1316 struct pci_devres *dr;
1317
1318 dr = find_pci_dr(pdev);
1319 WARN_ON(!dr || !dr->enabled);
1320 if (dr)
1321 dr->pinned = 1;
1322}
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332int __weak pcibios_add_device (struct pci_dev *dev)
1333{
1334 return 0;
1335}
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345void __weak pcibios_release_device(struct pci_dev *dev) {}
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355void __weak pcibios_disable_device (struct pci_dev *dev) {}
1356
1357static void do_pci_disable_device(struct pci_dev *dev)
1358{
1359 u16 pci_command;
1360
1361 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1362 if (pci_command & PCI_COMMAND_MASTER) {
1363 pci_command &= ~PCI_COMMAND_MASTER;
1364 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1365 }
1366
1367 pcibios_disable_device(dev);
1368}
1369
1370
1371
1372
1373
1374
1375
1376
1377void pci_disable_enabled_device(struct pci_dev *dev)
1378{
1379 if (pci_is_enabled(dev))
1380 do_pci_disable_device(dev);
1381}
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393void
1394pci_disable_device(struct pci_dev *dev)
1395{
1396 struct pci_devres *dr;
1397
1398 dr = find_pci_dr(dev);
1399 if (dr)
1400 dr->enabled = 0;
1401
1402 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1403 "disabling already-disabled device");
1404
1405 if (atomic_dec_return(&dev->enable_cnt) != 0)
1406 return;
1407
1408 do_pci_disable_device(dev);
1409
1410 dev->is_busmaster = 0;
1411}
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1423 enum pcie_reset_state state)
1424{
1425 return -EINVAL;
1426}
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1437{
1438 return pcibios_set_pcie_reset_state(dev, state);
1439}
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449bool pci_check_pme_status(struct pci_dev *dev)
1450{
1451 int pmcsr_pos;
1452 u16 pmcsr;
1453 bool ret = false;
1454
1455 if (!dev->pm_cap)
1456 return false;
1457
1458 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1459 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1460 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1461 return false;
1462
1463
1464 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1465 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1466
1467 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1468 ret = true;
1469 }
1470
1471 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1472
1473 return ret;
1474}
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1485{
1486 if (pme_poll_reset && dev->pme_poll)
1487 dev->pme_poll = false;
1488
1489 if (pci_check_pme_status(dev)) {
1490 pci_wakeup_event(dev);
1491 pm_request_resume(&dev->dev);
1492 }
1493 return 0;
1494}
1495
1496
1497
1498
1499
1500void pci_pme_wakeup_bus(struct pci_bus *bus)
1501{
1502 if (bus)
1503 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1504}
1505
1506
1507
1508
1509
1510
1511static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1512{
1513 pci_wakeup_event(pci_dev);
1514 pm_request_resume(&pci_dev->dev);
1515 return 0;
1516}
1517
1518
1519
1520
1521
1522void pci_wakeup_bus(struct pci_bus *bus)
1523{
1524 if (bus)
1525 pci_walk_bus(bus, pci_wakeup, NULL);
1526}
1527
1528
1529
1530
1531
1532
1533bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1534{
1535 if (!dev->pm_cap)
1536 return false;
1537
1538 return !!(dev->pme_support & (1 << state));
1539}
1540
1541static void pci_pme_list_scan(struct work_struct *work)
1542{
1543 struct pci_pme_device *pme_dev, *n;
1544
1545 mutex_lock(&pci_pme_list_mutex);
1546 if (!list_empty(&pci_pme_list)) {
1547 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1548 if (pme_dev->dev->pme_poll) {
1549 struct pci_dev *bridge;
1550
1551 bridge = pme_dev->dev->bus->self;
1552
1553
1554
1555
1556
1557 if (bridge && bridge->current_state != PCI_D0)
1558 continue;
1559 pci_pme_wakeup(pme_dev->dev, NULL);
1560 } else {
1561 list_del(&pme_dev->list);
1562 kfree(pme_dev);
1563 }
1564 }
1565 if (!list_empty(&pci_pme_list))
1566 schedule_delayed_work(&pci_pme_work,
1567 msecs_to_jiffies(PME_TIMEOUT));
1568 }
1569 mutex_unlock(&pci_pme_list_mutex);
1570}
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580void pci_pme_active(struct pci_dev *dev, bool enable)
1581{
1582 u16 pmcsr;
1583
1584 if (!dev->pme_support)
1585 return;
1586
1587 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1588
1589 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1590 if (!enable)
1591 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1592
1593 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615 if (dev->pme_poll) {
1616 struct pci_pme_device *pme_dev;
1617 if (enable) {
1618 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1619 GFP_KERNEL);
1620 if (!pme_dev)
1621 goto out;
1622 pme_dev->dev = dev;
1623 mutex_lock(&pci_pme_list_mutex);
1624 list_add(&pme_dev->list, &pci_pme_list);
1625 if (list_is_singular(&pci_pme_list))
1626 schedule_delayed_work(&pci_pme_work,
1627 msecs_to_jiffies(PME_TIMEOUT));
1628 mutex_unlock(&pci_pme_list_mutex);
1629 } else {
1630 mutex_lock(&pci_pme_list_mutex);
1631 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1632 if (pme_dev->dev == dev) {
1633 list_del(&pme_dev->list);
1634 kfree(pme_dev);
1635 break;
1636 }
1637 }
1638 mutex_unlock(&pci_pme_list_mutex);
1639 }
1640 }
1641
1642out:
1643 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1644}
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1667 bool runtime, bool enable)
1668{
1669 int ret = 0;
1670
1671 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1672 return -EINVAL;
1673
1674
1675 if (!!enable == !!dev->wakeup_prepared)
1676 return 0;
1677
1678
1679
1680
1681
1682
1683
1684 if (enable) {
1685 int error;
1686
1687 if (pci_pme_capable(dev, state))
1688 pci_pme_active(dev, true);
1689 else
1690 ret = 1;
1691 error = runtime ? platform_pci_run_wake(dev, true) :
1692 platform_pci_sleep_wake(dev, true);
1693 if (ret)
1694 ret = error;
1695 if (!ret)
1696 dev->wakeup_prepared = true;
1697 } else {
1698 if (runtime)
1699 platform_pci_run_wake(dev, false);
1700 else
1701 platform_pci_sleep_wake(dev, false);
1702 pci_pme_active(dev, false);
1703 dev->wakeup_prepared = false;
1704 }
1705
1706 return ret;
1707}
1708EXPORT_SYMBOL(__pci_enable_wake);
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1725{
1726 return pci_pme_capable(dev, PCI_D3cold) ?
1727 pci_enable_wake(dev, PCI_D3cold, enable) :
1728 pci_enable_wake(dev, PCI_D3hot, enable);
1729}
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739pci_power_t pci_target_state(struct pci_dev *dev)
1740{
1741 pci_power_t target_state = PCI_D3hot;
1742
1743 if (platform_pci_power_manageable(dev)) {
1744
1745
1746
1747
1748 pci_power_t state = platform_pci_choose_state(dev);
1749
1750 switch (state) {
1751 case PCI_POWER_ERROR:
1752 case PCI_UNKNOWN:
1753 break;
1754 case PCI_D1:
1755 case PCI_D2:
1756 if (pci_no_d1d2(dev))
1757 break;
1758 default:
1759 target_state = state;
1760 }
1761 } else if (!dev->pm_cap) {
1762 target_state = PCI_D0;
1763 } else if (device_may_wakeup(&dev->dev)) {
1764
1765
1766
1767
1768
1769 if (dev->pme_support) {
1770 while (target_state
1771 && !(dev->pme_support & (1 << target_state)))
1772 target_state--;
1773 }
1774 }
1775
1776 return target_state;
1777}
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787int pci_prepare_to_sleep(struct pci_dev *dev)
1788{
1789 pci_power_t target_state = pci_target_state(dev);
1790 int error;
1791
1792 if (target_state == PCI_POWER_ERROR)
1793 return -EIO;
1794
1795
1796 if (target_state > PCI_D3hot)
1797 target_state = PCI_D3hot;
1798
1799 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1800
1801 error = pci_set_power_state(dev, target_state);
1802
1803 if (error)
1804 pci_enable_wake(dev, target_state, false);
1805
1806 return error;
1807}
1808
1809
1810
1811
1812
1813
1814
1815int pci_back_from_sleep(struct pci_dev *dev)
1816{
1817 pci_enable_wake(dev, PCI_D0, false);
1818 return pci_set_power_state(dev, PCI_D0);
1819}
1820
1821
1822
1823
1824
1825
1826
1827
1828int pci_finish_runtime_suspend(struct pci_dev *dev)
1829{
1830 pci_power_t target_state = pci_target_state(dev);
1831 int error;
1832
1833 if (target_state == PCI_POWER_ERROR)
1834 return -EIO;
1835
1836 dev->runtime_d3cold = target_state == PCI_D3cold;
1837
1838 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1839
1840 error = pci_set_power_state(dev, target_state);
1841
1842 if (error) {
1843 __pci_enable_wake(dev, target_state, true, false);
1844 dev->runtime_d3cold = false;
1845 }
1846
1847 return error;
1848}
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858bool pci_dev_run_wake(struct pci_dev *dev)
1859{
1860 struct pci_bus *bus = dev->bus;
1861
1862 if (device_run_wake(&dev->dev))
1863 return true;
1864
1865 if (!dev->pme_support)
1866 return false;
1867
1868 while (bus->parent) {
1869 struct pci_dev *bridge = bus->self;
1870
1871 if (device_run_wake(&bridge->dev))
1872 return true;
1873
1874 bus = bus->parent;
1875 }
1876
1877
1878 if (bus->bridge)
1879 return device_run_wake(bus->bridge);
1880
1881 return false;
1882}
1883EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1884
1885void pci_config_pm_runtime_get(struct pci_dev *pdev)
1886{
1887 struct device *dev = &pdev->dev;
1888 struct device *parent = dev->parent;
1889
1890 if (parent)
1891 pm_runtime_get_sync(parent);
1892 pm_runtime_get_noresume(dev);
1893
1894
1895
1896
1897 pm_runtime_barrier(dev);
1898
1899
1900
1901
1902
1903 if (pdev->current_state == PCI_D3cold)
1904 pm_runtime_resume(dev);
1905}
1906
1907void pci_config_pm_runtime_put(struct pci_dev *pdev)
1908{
1909 struct device *dev = &pdev->dev;
1910 struct device *parent = dev->parent;
1911
1912 pm_runtime_put(dev);
1913 if (parent)
1914 pm_runtime_put_sync(parent);
1915}
1916
1917
1918
1919
1920
1921void pci_pm_init(struct pci_dev *dev)
1922{
1923 int pm;
1924 u16 pmc;
1925
1926 pm_runtime_forbid(&dev->dev);
1927 pm_runtime_set_active(&dev->dev);
1928 pm_runtime_enable(&dev->dev);
1929 device_enable_async_suspend(&dev->dev);
1930 dev->wakeup_prepared = false;
1931
1932 dev->pm_cap = 0;
1933 dev->pme_support = 0;
1934
1935
1936 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1937 if (!pm)
1938 return;
1939
1940 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1941
1942 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1943 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1944 pmc & PCI_PM_CAP_VER_MASK);
1945 return;
1946 }
1947
1948 dev->pm_cap = pm;
1949 dev->d3_delay = PCI_PM_D3_WAIT;
1950 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1951 dev->d3cold_allowed = true;
1952
1953 dev->d1_support = false;
1954 dev->d2_support = false;
1955 if (!pci_no_d1d2(dev)) {
1956 if (pmc & PCI_PM_CAP_D1)
1957 dev->d1_support = true;
1958 if (pmc & PCI_PM_CAP_D2)
1959 dev->d2_support = true;
1960
1961 if (dev->d1_support || dev->d2_support)
1962 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1963 dev->d1_support ? " D1" : "",
1964 dev->d2_support ? " D2" : "");
1965 }
1966
1967 pmc &= PCI_PM_CAP_PME_MASK;
1968 if (pmc) {
1969 dev_printk(KERN_DEBUG, &dev->dev,
1970 "PME# supported from%s%s%s%s%s\n",
1971 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1972 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1973 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1974 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1975 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1976 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1977 dev->pme_poll = true;
1978
1979
1980
1981
1982 device_set_wakeup_capable(&dev->dev, true);
1983
1984 pci_pme_active(dev, false);
1985 }
1986}
1987
1988static void pci_add_saved_cap(struct pci_dev *pci_dev,
1989 struct pci_cap_saved_state *new_cap)
1990{
1991 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1992}
1993
1994
1995
1996
1997
1998
1999
2000static int pci_add_cap_save_buffer(
2001 struct pci_dev *dev, char cap, unsigned int size)
2002{
2003 int pos;
2004 struct pci_cap_saved_state *save_state;
2005
2006 pos = pci_find_capability(dev, cap);
2007 if (pos <= 0)
2008 return 0;
2009
2010 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2011 if (!save_state)
2012 return -ENOMEM;
2013
2014 save_state->cap.cap_nr = cap;
2015 save_state->cap.size = size;
2016 pci_add_saved_cap(dev, save_state);
2017
2018 return 0;
2019}
2020
2021
2022
2023
2024
2025void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2026{
2027 int error;
2028
2029 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2030 PCI_EXP_SAVE_REGS * sizeof(u16));
2031 if (error)
2032 dev_err(&dev->dev,
2033 "unable to preallocate PCI Express save buffer\n");
2034
2035 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2036 if (error)
2037 dev_err(&dev->dev,
2038 "unable to preallocate PCI-X save buffer\n");
2039}
2040
2041void pci_free_cap_save_buffers(struct pci_dev *dev)
2042{
2043 struct pci_cap_saved_state *tmp;
2044 struct hlist_node *n;
2045
2046 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2047 kfree(tmp);
2048}
2049
2050
2051
2052
2053
2054
2055
2056
2057void pci_configure_ari(struct pci_dev *dev)
2058{
2059 u32 cap;
2060 struct pci_dev *bridge;
2061
2062 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2063 return;
2064
2065 bridge = dev->bus->self;
2066 if (!bridge)
2067 return;
2068
2069 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2070 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2071 return;
2072
2073 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2074 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2075 PCI_EXP_DEVCTL2_ARI);
2076 bridge->ari_enabled = 1;
2077 } else {
2078 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2079 PCI_EXP_DEVCTL2_ARI);
2080 bridge->ari_enabled = 0;
2081 }
2082}
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2094{
2095 u16 ctrl = 0;
2096
2097 if (type & PCI_EXP_IDO_REQUEST)
2098 ctrl |= PCI_EXP_IDO_REQ_EN;
2099 if (type & PCI_EXP_IDO_COMPLETION)
2100 ctrl |= PCI_EXP_IDO_CMP_EN;
2101 if (ctrl)
2102 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2103}
2104EXPORT_SYMBOL(pci_enable_ido);
2105
2106
2107
2108
2109
2110
2111void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2112{
2113 u16 ctrl = 0;
2114
2115 if (type & PCI_EXP_IDO_REQUEST)
2116 ctrl |= PCI_EXP_IDO_REQ_EN;
2117 if (type & PCI_EXP_IDO_COMPLETION)
2118 ctrl |= PCI_EXP_IDO_CMP_EN;
2119 if (ctrl)
2120 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2121}
2122EXPORT_SYMBOL(pci_disable_ido);
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2144{
2145 u32 cap;
2146 u16 ctrl;
2147 int ret;
2148
2149 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2150 if (!(cap & PCI_EXP_OBFF_MASK))
2151 return -ENOTSUPP;
2152
2153
2154 if (dev->bus->self) {
2155 ret = pci_enable_obff(dev->bus->self, type);
2156 if (ret)
2157 return ret;
2158 }
2159
2160 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2161 if (cap & PCI_EXP_OBFF_WAKE)
2162 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2163 else {
2164 switch (type) {
2165 case PCI_EXP_OBFF_SIGNAL_L0:
2166 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2167 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2168 break;
2169 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2170 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2171 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2172 break;
2173 default:
2174 WARN(1, "bad OBFF signal type\n");
2175 return -ENOTSUPP;
2176 }
2177 }
2178 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2179
2180 return 0;
2181}
2182EXPORT_SYMBOL(pci_enable_obff);
2183
2184
2185
2186
2187
2188
2189
2190void pci_disable_obff(struct pci_dev *dev)
2191{
2192 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2193}
2194EXPORT_SYMBOL(pci_disable_obff);
2195
2196
2197
2198
2199
2200
2201
2202
2203static bool pci_ltr_supported(struct pci_dev *dev)
2204{
2205 u32 cap;
2206
2207 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2208
2209 return cap & PCI_EXP_DEVCAP2_LTR;
2210}
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222int pci_enable_ltr(struct pci_dev *dev)
2223{
2224 int ret;
2225
2226
2227 if (PCI_FUNC(dev->devfn) != 0)
2228 return -EINVAL;
2229
2230 if (!pci_ltr_supported(dev))
2231 return -ENOTSUPP;
2232
2233
2234 if (dev->bus->self) {
2235 ret = pci_enable_ltr(dev->bus->self);
2236 if (ret)
2237 return ret;
2238 }
2239
2240 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2241}
2242EXPORT_SYMBOL(pci_enable_ltr);
2243
2244
2245
2246
2247
2248void pci_disable_ltr(struct pci_dev *dev)
2249{
2250
2251 if (PCI_FUNC(dev->devfn) != 0)
2252 return;
2253
2254 if (!pci_ltr_supported(dev))
2255 return;
2256
2257 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2258}
2259EXPORT_SYMBOL(pci_disable_ltr);
2260
2261static int __pci_ltr_scale(int *val)
2262{
2263 int scale = 0;
2264
2265 while (*val > 1023) {
2266 *val = (*val + 31) / 32;
2267 scale++;
2268 }
2269 return scale;
2270}
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2281{
2282 int pos, ret, snoop_scale, nosnoop_scale;
2283 u16 val;
2284
2285 if (!pci_ltr_supported(dev))
2286 return -ENOTSUPP;
2287
2288 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2289 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2290
2291 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2292 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2293 return -EINVAL;
2294
2295 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2296 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2297 return -EINVAL;
2298
2299 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2300 if (!pos)
2301 return -ENOTSUPP;
2302
2303 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2304 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2305 if (ret != 4)
2306 return -EIO;
2307
2308 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2309 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2310 if (ret != 4)
2311 return -EIO;
2312
2313 return 0;
2314}
2315EXPORT_SYMBOL(pci_set_ltr);
2316
2317static int pci_acs_enable;
2318
2319
2320
2321
2322void pci_request_acs(void)
2323{
2324 pci_acs_enable = 1;
2325}
2326
2327
2328
2329
2330
2331void pci_enable_acs(struct pci_dev *dev)
2332{
2333 int pos;
2334 u16 cap;
2335 u16 ctrl;
2336
2337 if (!pci_acs_enable)
2338 return;
2339
2340 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2341 if (!pos)
2342 return;
2343
2344 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2345 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2346
2347
2348 ctrl |= (cap & PCI_ACS_SV);
2349
2350
2351 ctrl |= (cap & PCI_ACS_RR);
2352
2353
2354 ctrl |= (cap & PCI_ACS_CR);
2355
2356
2357 ctrl |= (cap & PCI_ACS_UF);
2358
2359 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2360}
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2371{
2372 int pos, ret;
2373 u16 ctrl;
2374
2375 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2376 if (ret >= 0)
2377 return ret > 0;
2378
2379 if (!pci_is_pcie(pdev))
2380 return false;
2381
2382
2383 if (pdev->multifunction)
2384 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2385 PCI_ACS_EC | PCI_ACS_DT);
2386
2387 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2388 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2389 pdev->multifunction) {
2390 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2391 if (!pos)
2392 return false;
2393
2394 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2395 if ((ctrl & acs_flags) != acs_flags)
2396 return false;
2397 }
2398
2399 return true;
2400}
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411bool pci_acs_path_enabled(struct pci_dev *start,
2412 struct pci_dev *end, u16 acs_flags)
2413{
2414 struct pci_dev *pdev, *parent = start;
2415
2416 do {
2417 pdev = parent;
2418
2419 if (!pci_acs_enabled(pdev, acs_flags))
2420 return false;
2421
2422 if (pci_is_root_bus(pdev->bus))
2423 return (end == NULL);
2424
2425 parent = pdev->bus->self;
2426 } while (pdev != end);
2427
2428 return true;
2429}
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2443{
2444 int slot;
2445
2446 if (pci_ari_enabled(dev->bus))
2447 slot = 0;
2448 else
2449 slot = PCI_SLOT(dev->devfn);
2450
2451 return (((pin - 1) + slot) % 4) + 1;
2452}
2453
2454int
2455pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2456{
2457 u8 pin;
2458
2459 pin = dev->pin;
2460 if (!pin)
2461 return -1;
2462
2463 while (!pci_is_root_bus(dev->bus)) {
2464 pin = pci_swizzle_interrupt_pin(dev, pin);
2465 dev = dev->bus->self;
2466 }
2467 *bridge = dev;
2468 return pin;
2469}
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2480{
2481 u8 pin = *pinp;
2482
2483 while (!pci_is_root_bus(dev->bus)) {
2484 pin = pci_swizzle_interrupt_pin(dev, pin);
2485 dev = dev->bus->self;
2486 }
2487 *pinp = pin;
2488 return PCI_SLOT(dev->devfn);
2489}
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500void pci_release_region(struct pci_dev *pdev, int bar)
2501{
2502 struct pci_devres *dr;
2503
2504 if (pci_resource_len(pdev, bar) == 0)
2505 return;
2506 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2507 release_region(pci_resource_start(pdev, bar),
2508 pci_resource_len(pdev, bar));
2509 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2510 release_mem_region(pci_resource_start(pdev, bar),
2511 pci_resource_len(pdev, bar));
2512
2513 dr = find_pci_dr(pdev);
2514 if (dr)
2515 dr->region_mask &= ~(1 << bar);
2516}
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2538 int exclusive)
2539{
2540 struct pci_devres *dr;
2541
2542 if (pci_resource_len(pdev, bar) == 0)
2543 return 0;
2544
2545 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2546 if (!request_region(pci_resource_start(pdev, bar),
2547 pci_resource_len(pdev, bar), res_name))
2548 goto err_out;
2549 }
2550 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2551 if (!__request_mem_region(pci_resource_start(pdev, bar),
2552 pci_resource_len(pdev, bar), res_name,
2553 exclusive))
2554 goto err_out;
2555 }
2556
2557 dr = find_pci_dr(pdev);
2558 if (dr)
2559 dr->region_mask |= 1 << bar;
2560
2561 return 0;
2562
2563err_out:
2564 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2565 &pdev->resource[bar]);
2566 return -EBUSY;
2567}
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2584{
2585 return __pci_request_region(pdev, bar, res_name, 0);
2586}
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2607{
2608 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2609}
2610
2611
2612
2613
2614
2615
2616
2617
2618void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2619{
2620 int i;
2621
2622 for (i = 0; i < 6; i++)
2623 if (bars & (1 << i))
2624 pci_release_region(pdev, i);
2625}
2626
2627static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2628 const char *res_name, int excl)
2629{
2630 int i;
2631
2632 for (i = 0; i < 6; i++)
2633 if (bars & (1 << i))
2634 if (__pci_request_region(pdev, i, res_name, excl))
2635 goto err_out;
2636 return 0;
2637
2638err_out:
2639 while(--i >= 0)
2640 if (bars & (1 << i))
2641 pci_release_region(pdev, i);
2642
2643 return -EBUSY;
2644}
2645
2646
2647
2648
2649
2650
2651
2652
2653int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2654 const char *res_name)
2655{
2656 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2657}
2658
2659int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2660 int bars, const char *res_name)
2661{
2662 return __pci_request_selected_regions(pdev, bars, res_name,
2663 IORESOURCE_EXCLUSIVE);
2664}
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675void pci_release_regions(struct pci_dev *pdev)
2676{
2677 pci_release_selected_regions(pdev, (1 << 6) - 1);
2678}
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2694{
2695 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2696}
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2715{
2716 return pci_request_selected_regions_exclusive(pdev,
2717 ((1 << 6) - 1), res_name);
2718}
2719
2720static void __pci_set_master(struct pci_dev *dev, bool enable)
2721{
2722 u16 old_cmd, cmd;
2723
2724 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2725 if (enable)
2726 cmd = old_cmd | PCI_COMMAND_MASTER;
2727 else
2728 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2729 if (cmd != old_cmd) {
2730 dev_dbg(&dev->dev, "%s bus mastering\n",
2731 enable ? "enabling" : "disabling");
2732 pci_write_config_word(dev, PCI_COMMAND, cmd);
2733 }
2734 dev->is_busmaster = enable;
2735}
2736
2737
2738
2739
2740
2741
2742
2743
2744char * __weak __init pcibios_setup(char *str)
2745{
2746 return str;
2747}
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757void __weak pcibios_set_master(struct pci_dev *dev)
2758{
2759 u8 lat;
2760
2761
2762 if (pci_is_pcie(dev))
2763 return;
2764
2765 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2766 if (lat < 16)
2767 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2768 else if (lat > pcibios_max_latency)
2769 lat = pcibios_max_latency;
2770 else
2771 return;
2772 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2773 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2774}
2775
2776
2777
2778
2779
2780
2781
2782
2783void pci_set_master(struct pci_dev *dev)
2784{
2785 __pci_set_master(dev, true);
2786 pcibios_set_master(dev);
2787}
2788
2789
2790
2791
2792
2793void pci_clear_master(struct pci_dev *dev)
2794{
2795 __pci_set_master(dev, false);
2796}
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808int pci_set_cacheline_size(struct pci_dev *dev)
2809{
2810 u8 cacheline_size;
2811
2812 if (!pci_cache_line_size)
2813 return -EINVAL;
2814
2815
2816
2817 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2818 if (cacheline_size >= pci_cache_line_size &&
2819 (cacheline_size % pci_cache_line_size) == 0)
2820 return 0;
2821
2822
2823 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2824
2825 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2826 if (cacheline_size == pci_cache_line_size)
2827 return 0;
2828
2829 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2830 "supported\n", pci_cache_line_size << 2);
2831
2832 return -EINVAL;
2833}
2834EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2835
2836#ifdef PCI_DISABLE_MWI
2837int pci_set_mwi(struct pci_dev *dev)
2838{
2839 return 0;
2840}
2841
2842int pci_try_set_mwi(struct pci_dev *dev)
2843{
2844 return 0;
2845}
2846
2847void pci_clear_mwi(struct pci_dev *dev)
2848{
2849}
2850
2851#else
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861int
2862pci_set_mwi(struct pci_dev *dev)
2863{
2864 int rc;
2865 u16 cmd;
2866
2867 rc = pci_set_cacheline_size(dev);
2868 if (rc)
2869 return rc;
2870
2871 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2872 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2873 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2874 cmd |= PCI_COMMAND_INVALIDATE;
2875 pci_write_config_word(dev, PCI_COMMAND, cmd);
2876 }
2877
2878 return 0;
2879}
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890int pci_try_set_mwi(struct pci_dev *dev)
2891{
2892 int rc = pci_set_mwi(dev);
2893 return rc;
2894}
2895
2896
2897
2898
2899
2900
2901
2902void
2903pci_clear_mwi(struct pci_dev *dev)
2904{
2905 u16 cmd;
2906
2907 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2908 if (cmd & PCI_COMMAND_INVALIDATE) {
2909 cmd &= ~PCI_COMMAND_INVALIDATE;
2910 pci_write_config_word(dev, PCI_COMMAND, cmd);
2911 }
2912}
2913#endif
2914
2915
2916
2917
2918
2919
2920
2921
2922void
2923pci_intx(struct pci_dev *pdev, int enable)
2924{
2925 u16 pci_command, new;
2926
2927 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2928
2929 if (enable) {
2930 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2931 } else {
2932 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2933 }
2934
2935 if (new != pci_command) {
2936 struct pci_devres *dr;
2937
2938 pci_write_config_word(pdev, PCI_COMMAND, new);
2939
2940 dr = find_pci_dr(pdev);
2941 if (dr && !dr->restore_intx) {
2942 dr->restore_intx = 1;
2943 dr->orig_intx = !enable;
2944 }
2945 }
2946}
2947
2948
2949
2950
2951
2952
2953
2954
2955bool pci_intx_mask_supported(struct pci_dev *dev)
2956{
2957 bool mask_supported = false;
2958 u16 orig, new;
2959
2960 if (dev->broken_intx_masking)
2961 return false;
2962
2963 pci_cfg_access_lock(dev);
2964
2965 pci_read_config_word(dev, PCI_COMMAND, &orig);
2966 pci_write_config_word(dev, PCI_COMMAND,
2967 orig ^ PCI_COMMAND_INTX_DISABLE);
2968 pci_read_config_word(dev, PCI_COMMAND, &new);
2969
2970
2971
2972
2973
2974
2975 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2976 dev_err(&dev->dev, "Command register changed from "
2977 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2978 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2979 mask_supported = true;
2980 pci_write_config_word(dev, PCI_COMMAND, orig);
2981 }
2982
2983 pci_cfg_access_unlock(dev);
2984 return mask_supported;
2985}
2986EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2987
2988static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2989{
2990 struct pci_bus *bus = dev->bus;
2991 bool mask_updated = true;
2992 u32 cmd_status_dword;
2993 u16 origcmd, newcmd;
2994 unsigned long flags;
2995 bool irq_pending;
2996
2997
2998
2999
3000
3001 BUILD_BUG_ON(PCI_COMMAND % 4);
3002 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3003
3004 raw_spin_lock_irqsave(&pci_lock, flags);
3005
3006 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3007
3008 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3009
3010
3011
3012
3013
3014
3015 if (mask != irq_pending) {
3016 mask_updated = false;
3017 goto done;
3018 }
3019
3020 origcmd = cmd_status_dword;
3021 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3022 if (mask)
3023 newcmd |= PCI_COMMAND_INTX_DISABLE;
3024 if (newcmd != origcmd)
3025 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3026
3027done:
3028 raw_spin_unlock_irqrestore(&pci_lock, flags);
3029
3030 return mask_updated;
3031}
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041bool pci_check_and_mask_intx(struct pci_dev *dev)
3042{
3043 return pci_check_and_set_intx_mask(dev, true);
3044}
3045EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055bool pci_check_and_unmask_intx(struct pci_dev *dev)
3056{
3057 return pci_check_and_set_intx_mask(dev, false);
3058}
3059EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069void pci_msi_off(struct pci_dev *dev)
3070{
3071 int pos;
3072 u16 control;
3073
3074 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3075 if (pos) {
3076 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3077 control &= ~PCI_MSI_FLAGS_ENABLE;
3078 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3079 }
3080 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3081 if (pos) {
3082 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3083 control &= ~PCI_MSIX_FLAGS_ENABLE;
3084 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3085 }
3086}
3087EXPORT_SYMBOL_GPL(pci_msi_off);
3088
3089int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3090{
3091 return dma_set_max_seg_size(&dev->dev, size);
3092}
3093EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3094
3095int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3096{
3097 return dma_set_seg_boundary(&dev->dev, mask);
3098}
3099EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3100
3101static int pcie_flr(struct pci_dev *dev, int probe)
3102{
3103 int i;
3104 u32 cap;
3105 u16 status;
3106
3107 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3108 if (!(cap & PCI_EXP_DEVCAP_FLR))
3109 return -ENOTTY;
3110
3111 if (probe)
3112 return 0;
3113
3114
3115 for (i = 0; i < 4; i++) {
3116 if (i)
3117 msleep((1 << (i - 1)) * 100);
3118
3119 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3120 if (!(status & PCI_EXP_DEVSTA_TRPND))
3121 goto clear;
3122 }
3123
3124 dev_err(&dev->dev, "transaction is not cleared; "
3125 "proceeding with reset anyway\n");
3126
3127clear:
3128 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3129
3130 msleep(100);
3131
3132 return 0;
3133}
3134
3135static int pci_af_flr(struct pci_dev *dev, int probe)
3136{
3137 int i;
3138 int pos;
3139 u8 cap;
3140 u8 status;
3141
3142 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3143 if (!pos)
3144 return -ENOTTY;
3145
3146 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3147 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3148 return -ENOTTY;
3149
3150 if (probe)
3151 return 0;
3152
3153
3154 for (i = 0; i < 4; i++) {
3155 if (i)
3156 msleep((1 << (i - 1)) * 100);
3157
3158 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3159 if (!(status & PCI_AF_STATUS_TP))
3160 goto clear;
3161 }
3162
3163 dev_err(&dev->dev, "transaction is not cleared; "
3164 "proceeding with reset anyway\n");
3165
3166clear:
3167 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3168 msleep(100);
3169
3170 return 0;
3171}
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188static int pci_pm_reset(struct pci_dev *dev, int probe)
3189{
3190 u16 csr;
3191
3192 if (!dev->pm_cap)
3193 return -ENOTTY;
3194
3195 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3196 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3197 return -ENOTTY;
3198
3199 if (probe)
3200 return 0;
3201
3202 if (dev->current_state != PCI_D0)
3203 return -EINVAL;
3204
3205 csr &= ~PCI_PM_CTRL_STATE_MASK;
3206 csr |= PCI_D3hot;
3207 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3208 pci_dev_d3_sleep(dev);
3209
3210 csr &= ~PCI_PM_CTRL_STATE_MASK;
3211 csr |= PCI_D0;
3212 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3213 pci_dev_d3_sleep(dev);
3214
3215 return 0;
3216}
3217
3218static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3219{
3220 u16 ctrl;
3221 struct pci_dev *pdev;
3222
3223 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3224 return -ENOTTY;
3225
3226 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3227 if (pdev != dev)
3228 return -ENOTTY;
3229
3230 if (probe)
3231 return 0;
3232
3233 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3234 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3235 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3236 msleep(100);
3237
3238 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3239 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3240 msleep(100);
3241
3242 return 0;
3243}
3244
3245static int __pci_dev_reset(struct pci_dev *dev, int probe)
3246{
3247 int rc;
3248
3249 might_sleep();
3250
3251 rc = pci_dev_specific_reset(dev, probe);
3252 if (rc != -ENOTTY)
3253 goto done;
3254
3255 rc = pcie_flr(dev, probe);
3256 if (rc != -ENOTTY)
3257 goto done;
3258
3259 rc = pci_af_flr(dev, probe);
3260 if (rc != -ENOTTY)
3261 goto done;
3262
3263 rc = pci_pm_reset(dev, probe);
3264 if (rc != -ENOTTY)
3265 goto done;
3266
3267 rc = pci_parent_bus_reset(dev, probe);
3268done:
3269 return rc;
3270}
3271
3272static int pci_dev_reset(struct pci_dev *dev, int probe)
3273{
3274 int rc;
3275
3276 if (!probe) {
3277 pci_cfg_access_lock(dev);
3278
3279 device_lock(&dev->dev);
3280 }
3281
3282 rc = __pci_dev_reset(dev, probe);
3283
3284 if (!probe) {
3285 device_unlock(&dev->dev);
3286 pci_cfg_access_unlock(dev);
3287 }
3288 return rc;
3289}
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307int __pci_reset_function(struct pci_dev *dev)
3308{
3309 return pci_dev_reset(dev, 0);
3310}
3311EXPORT_SYMBOL_GPL(__pci_reset_function);
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332int __pci_reset_function_locked(struct pci_dev *dev)
3333{
3334 return __pci_dev_reset(dev, 0);
3335}
3336EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349int pci_probe_reset_function(struct pci_dev *dev)
3350{
3351 return pci_dev_reset(dev, 1);
3352}
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370int pci_reset_function(struct pci_dev *dev)
3371{
3372 int rc;
3373
3374 rc = pci_dev_reset(dev, 1);
3375 if (rc)
3376 return rc;
3377
3378 pci_save_state(dev);
3379
3380
3381
3382
3383
3384 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3385
3386 rc = pci_dev_reset(dev, 0);
3387
3388 pci_restore_state(dev);
3389
3390 return rc;
3391}
3392EXPORT_SYMBOL_GPL(pci_reset_function);
3393
3394
3395
3396
3397
3398
3399
3400
3401int pcix_get_max_mmrbc(struct pci_dev *dev)
3402{
3403 int cap;
3404 u32 stat;
3405
3406 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3407 if (!cap)
3408 return -EINVAL;
3409
3410 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3411 return -EINVAL;
3412
3413 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3414}
3415EXPORT_SYMBOL(pcix_get_max_mmrbc);
3416
3417
3418
3419
3420
3421
3422
3423
3424int pcix_get_mmrbc(struct pci_dev *dev)
3425{
3426 int cap;
3427 u16 cmd;
3428
3429 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3430 if (!cap)
3431 return -EINVAL;
3432
3433 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3434 return -EINVAL;
3435
3436 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3437}
3438EXPORT_SYMBOL(pcix_get_mmrbc);
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3450{
3451 int cap;
3452 u32 stat, v, o;
3453 u16 cmd;
3454
3455 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3456 return -EINVAL;
3457
3458 v = ffs(mmrbc) - 10;
3459
3460 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3461 if (!cap)
3462 return -EINVAL;
3463
3464 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3465 return -EINVAL;
3466
3467 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3468 return -E2BIG;
3469
3470 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3471 return -EINVAL;
3472
3473 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3474 if (o != v) {
3475 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3476 return -EIO;
3477
3478 cmd &= ~PCI_X_CMD_MAX_READ;
3479 cmd |= v << 2;
3480 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3481 return -EIO;
3482 }
3483 return 0;
3484}
3485EXPORT_SYMBOL(pcix_set_mmrbc);
3486
3487
3488
3489
3490
3491
3492
3493
3494int pcie_get_readrq(struct pci_dev *dev)
3495{
3496 u16 ctl;
3497
3498 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3499
3500 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3501}
3502EXPORT_SYMBOL(pcie_get_readrq);
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512int pcie_set_readrq(struct pci_dev *dev, int rq)
3513{
3514 u16 v;
3515
3516 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3517 return -EINVAL;
3518
3519
3520
3521
3522
3523
3524
3525 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3526 int mps = pcie_get_mps(dev);
3527
3528 if (mps < 0)
3529 return mps;
3530 if (mps < rq)
3531 rq = mps;
3532 }
3533
3534 v = (ffs(rq) - 8) << 12;
3535
3536 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3537 PCI_EXP_DEVCTL_READRQ, v);
3538}
3539EXPORT_SYMBOL(pcie_set_readrq);
3540
3541
3542
3543
3544
3545
3546
3547
3548int pcie_get_mps(struct pci_dev *dev)
3549{
3550 u16 ctl;
3551
3552 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3553
3554 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3555}
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565int pcie_set_mps(struct pci_dev *dev, int mps)
3566{
3567 u16 v;
3568
3569 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3570 return -EINVAL;
3571
3572 v = ffs(mps) - 8;
3573 if (v > dev->pcie_mpss)
3574 return -EINVAL;
3575 v <<= 5;
3576
3577 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3578 PCI_EXP_DEVCTL_PAYLOAD, v);
3579}
3580
3581
3582
3583
3584
3585
3586
3587
3588int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3589{
3590 int i, bars = 0;
3591 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3592 if (pci_resource_flags(dev, i) & flags)
3593 bars |= (1 << i);
3594 return bars;
3595}
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3606{
3607 int reg;
3608
3609 if (resno < PCI_ROM_RESOURCE) {
3610 *type = pci_bar_unknown;
3611 return PCI_BASE_ADDRESS_0 + 4 * resno;
3612 } else if (resno == PCI_ROM_RESOURCE) {
3613 *type = pci_bar_mem32;
3614 return dev->rom_base_reg;
3615 } else if (resno < PCI_BRIDGE_RESOURCES) {
3616
3617 reg = pci_iov_resource_bar(dev, resno, type);
3618 if (reg)
3619 return reg;
3620 }
3621
3622 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3623 return 0;
3624}
3625
3626
3627static arch_set_vga_state_t arch_set_vga_state;
3628
3629void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3630{
3631 arch_set_vga_state = func;
3632}
3633
3634static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3635 unsigned int command_bits, u32 flags)
3636{
3637 if (arch_set_vga_state)
3638 return arch_set_vga_state(dev, decode, command_bits,
3639 flags);
3640 return 0;
3641}
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651int pci_set_vga_state(struct pci_dev *dev, bool decode,
3652 unsigned int command_bits, u32 flags)
3653{
3654 struct pci_bus *bus;
3655 struct pci_dev *bridge;
3656 u16 cmd;
3657 int rc;
3658
3659 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3660
3661
3662 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3663 if (rc)
3664 return rc;
3665
3666 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3667 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3668 if (decode == true)
3669 cmd |= command_bits;
3670 else
3671 cmd &= ~command_bits;
3672 pci_write_config_word(dev, PCI_COMMAND, cmd);
3673 }
3674
3675 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3676 return 0;
3677
3678 bus = dev->bus;
3679 while (bus) {
3680 bridge = bus->self;
3681 if (bridge) {
3682 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3683 &cmd);
3684 if (decode == true)
3685 cmd |= PCI_BRIDGE_CTL_VGA;
3686 else
3687 cmd &= ~PCI_BRIDGE_CTL_VGA;
3688 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3689 cmd);
3690 }
3691 bus = bus->parent;
3692 }
3693 return 0;
3694}
3695
3696#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3697static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3698static DEFINE_SPINLOCK(resource_alignment_lock);
3699
3700
3701
3702
3703
3704
3705
3706
3707static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3708{
3709 int seg, bus, slot, func, align_order, count;
3710 resource_size_t align = 0;
3711 char *p;
3712
3713 spin_lock(&resource_alignment_lock);
3714 p = resource_alignment_param;
3715 while (*p) {
3716 count = 0;
3717 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3718 p[count] == '@') {
3719 p += count + 1;
3720 } else {
3721 align_order = -1;
3722 }
3723 if (sscanf(p, "%x:%x:%x.%x%n",
3724 &seg, &bus, &slot, &func, &count) != 4) {
3725 seg = 0;
3726 if (sscanf(p, "%x:%x.%x%n",
3727 &bus, &slot, &func, &count) != 3) {
3728
3729 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3730 p);
3731 break;
3732 }
3733 }
3734 p += count;
3735 if (seg == pci_domain_nr(dev->bus) &&
3736 bus == dev->bus->number &&
3737 slot == PCI_SLOT(dev->devfn) &&
3738 func == PCI_FUNC(dev->devfn)) {
3739 if (align_order == -1) {
3740 align = PAGE_SIZE;
3741 } else {
3742 align = 1 << align_order;
3743 }
3744
3745 break;
3746 }
3747 if (*p != ';' && *p != ',') {
3748
3749 break;
3750 }
3751 p++;
3752 }
3753 spin_unlock(&resource_alignment_lock);
3754 return align;
3755}
3756
3757
3758
3759
3760
3761
3762
3763
3764void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3765{
3766 int i;
3767 struct resource *r;
3768 resource_size_t align, size;
3769 u16 command;
3770
3771
3772 align = pci_specified_resource_alignment(dev);
3773 if (!align)
3774 return;
3775
3776 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3777 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3778 dev_warn(&dev->dev,
3779 "Can't reassign resources to host bridge.\n");
3780 return;
3781 }
3782
3783 dev_info(&dev->dev,
3784 "Disabling memory decoding and releasing memory resources.\n");
3785 pci_read_config_word(dev, PCI_COMMAND, &command);
3786 command &= ~PCI_COMMAND_MEMORY;
3787 pci_write_config_word(dev, PCI_COMMAND, command);
3788
3789 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3790 r = &dev->resource[i];
3791 if (!(r->flags & IORESOURCE_MEM))
3792 continue;
3793 size = resource_size(r);
3794 if (size < align) {
3795 size = align;
3796 dev_info(&dev->dev,
3797 "Rounding up size of resource #%d to %#llx.\n",
3798 i, (unsigned long long)size);
3799 }
3800 r->end = size - 1;
3801 r->start = 0;
3802 }
3803
3804
3805
3806
3807 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3808 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3809 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3810 r = &dev->resource[i];
3811 if (!(r->flags & IORESOURCE_MEM))
3812 continue;
3813 r->end = resource_size(r) - 1;
3814 r->start = 0;
3815 }
3816 pci_disable_bridge_window(dev);
3817 }
3818}
3819
3820static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3821{
3822 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3823 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3824 spin_lock(&resource_alignment_lock);
3825 strncpy(resource_alignment_param, buf, count);
3826 resource_alignment_param[count] = '\0';
3827 spin_unlock(&resource_alignment_lock);
3828 return count;
3829}
3830
3831static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3832{
3833 size_t count;
3834 spin_lock(&resource_alignment_lock);
3835 count = snprintf(buf, size, "%s", resource_alignment_param);
3836 spin_unlock(&resource_alignment_lock);
3837 return count;
3838}
3839
3840static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3841{
3842 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3843}
3844
3845static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3846 const char *buf, size_t count)
3847{
3848 return pci_set_resource_alignment_param(buf, count);
3849}
3850
3851BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3852 pci_resource_alignment_store);
3853
3854static int __init pci_resource_alignment_sysfs_init(void)
3855{
3856 return bus_create_file(&pci_bus_type,
3857 &bus_attr_resource_alignment);
3858}
3859
3860late_initcall(pci_resource_alignment_sysfs_init);
3861
3862static void pci_no_domains(void)
3863{
3864#ifdef CONFIG_PCI_DOMAINS
3865 pci_domains_supported = 0;
3866#endif
3867}
3868
3869
3870
3871
3872
3873
3874
3875
3876int __weak pci_ext_cfg_avail(void)
3877{
3878 return 1;
3879}
3880
3881void __weak pci_fixup_cardbus(struct pci_bus *bus)
3882{
3883}
3884EXPORT_SYMBOL(pci_fixup_cardbus);
3885
3886static int __init pci_setup(char *str)
3887{
3888 while (str) {
3889 char *k = strchr(str, ',');
3890 if (k)
3891 *k++ = 0;
3892 if (*str && (str = pcibios_setup(str)) && *str) {
3893 if (!strcmp(str, "nomsi")) {
3894 pci_no_msi();
3895 } else if (!strcmp(str, "noaer")) {
3896 pci_no_aer();
3897 } else if (!strncmp(str, "realloc=", 8)) {
3898 pci_realloc_get_opt(str + 8);
3899 } else if (!strncmp(str, "realloc", 7)) {
3900 pci_realloc_get_opt("on");
3901 } else if (!strcmp(str, "nodomains")) {
3902 pci_no_domains();
3903 } else if (!strncmp(str, "noari", 5)) {
3904 pcie_ari_disabled = true;
3905 } else if (!strncmp(str, "cbiosize=", 9)) {
3906 pci_cardbus_io_size = memparse(str + 9, &str);
3907 } else if (!strncmp(str, "cbmemsize=", 10)) {
3908 pci_cardbus_mem_size = memparse(str + 10, &str);
3909 } else if (!strncmp(str, "resource_alignment=", 19)) {
3910 pci_set_resource_alignment_param(str + 19,
3911 strlen(str + 19));
3912 } else if (!strncmp(str, "ecrc=", 5)) {
3913 pcie_ecrc_get_policy(str + 5);
3914 } else if (!strncmp(str, "hpiosize=", 9)) {
3915 pci_hotplug_io_size = memparse(str + 9, &str);
3916 } else if (!strncmp(str, "hpmemsize=", 10)) {
3917 pci_hotplug_mem_size = memparse(str + 10, &str);
3918 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3919 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3920 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3921 pcie_bus_config = PCIE_BUS_SAFE;
3922 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3923 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3924 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3925 pcie_bus_config = PCIE_BUS_PEER2PEER;
3926 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3927 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
3928 } else {
3929 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3930 str);
3931 }
3932 }
3933 str = k;
3934 }
3935 return 0;
3936}
3937early_param("pci", pci_setup);
3938
3939EXPORT_SYMBOL(pci_reenable_device);
3940EXPORT_SYMBOL(pci_enable_device_io);
3941EXPORT_SYMBOL(pci_enable_device_mem);
3942EXPORT_SYMBOL(pci_enable_device);
3943EXPORT_SYMBOL(pcim_enable_device);
3944EXPORT_SYMBOL(pcim_pin_device);
3945EXPORT_SYMBOL(pci_disable_device);
3946EXPORT_SYMBOL(pci_find_capability);
3947EXPORT_SYMBOL(pci_bus_find_capability);
3948EXPORT_SYMBOL(pci_release_regions);
3949EXPORT_SYMBOL(pci_request_regions);
3950EXPORT_SYMBOL(pci_request_regions_exclusive);
3951EXPORT_SYMBOL(pci_release_region);
3952EXPORT_SYMBOL(pci_request_region);
3953EXPORT_SYMBOL(pci_request_region_exclusive);
3954EXPORT_SYMBOL(pci_release_selected_regions);
3955EXPORT_SYMBOL(pci_request_selected_regions);
3956EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3957EXPORT_SYMBOL(pci_set_master);
3958EXPORT_SYMBOL(pci_clear_master);
3959EXPORT_SYMBOL(pci_set_mwi);
3960EXPORT_SYMBOL(pci_try_set_mwi);
3961EXPORT_SYMBOL(pci_clear_mwi);
3962EXPORT_SYMBOL_GPL(pci_intx);
3963EXPORT_SYMBOL(pci_assign_resource);
3964EXPORT_SYMBOL(pci_find_parent_resource);
3965EXPORT_SYMBOL(pci_select_bars);
3966
3967EXPORT_SYMBOL(pci_set_power_state);
3968EXPORT_SYMBOL(pci_save_state);
3969EXPORT_SYMBOL(pci_restore_state);
3970EXPORT_SYMBOL(pci_pme_capable);
3971EXPORT_SYMBOL(pci_pme_active);
3972EXPORT_SYMBOL(pci_wake_from_d3);
3973EXPORT_SYMBOL(pci_target_state);
3974EXPORT_SYMBOL(pci_prepare_to_sleep);
3975EXPORT_SYMBOL(pci_back_from_sleep);
3976EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
3977